-Department of Electrical & Electronic Engineering

Bangladesh University of Engineering & Technology

EEE458 VLSI II Laboratory

Laboratory Module 1:
ASIC Front End Design: RTL design of a digital sub-system and System level
validation using CADENCE IUS

Objectives:
Almost all the digital ICs are designed and manufactured by semi-custom IC methodologies.
Typically it refers to Hardware Description Language (HDL) based IC design with automatic
synthesis-place and route by Electronic Design Automation (EDA) tools. Semi-custom IC design
methodology has 3 major categories - (i) Standard cell based Application Specific Integrated
Circuit (ASIC) design (ii) Gate arrays and (iii) FPGA. In ASIC design pre-designed library cells
(preferably tested with Design For Manufacturing (DFM) are used but designer has flexibility in
placement of the cells & routing.
This and the following two labs are basic introduction of ASIC design using CADENCE digital
Front End (FE) and Back End (BE) tools. In top-down ASIC design flow, system level
specification is obtained first from which a high-level behavioral abstraction is created. The
behavioral abstraction is then used as a reference to create and refine a synthesizable register
transfer level (RTL) abstraction that captures the desired functionality required by the design
specification. RTL design is simulated extensively for system level validation of the design.
This lab will use CADENCE Incisive Unified Simulator (IUS) environment for RTL design. It will
also give you an example of a Verilog test bench, so that you can test your design and can go more
easily through the other labs and your project.

The following Cadence CAD tools will be used in this lab:

 NC-Sim for simulation.

 Sim Vision for visualization.

Lab 1-1.Setting up the working directory and running a Directed Testing.

Please login to EDA playground. Choose language as Verilog/SystemVerilog

and tool as Cadence Xcelium 20.09

Place your mux code in the right side of the window which is the design window. Now play the
testbench code on the left side of the window which is the test window. Select EPwave after run
with tick mark.

// your design code

module mux21 (input a,b,s,
output y);
assign y=~s & a | s & b;
endmodule

// your testbench code

©ABM H. Rashid, Dept. of EEE, BUET Page 1 21/11/2021

// or browse Examples
module testbench2( ); // No in, out
reg a,b,s; // inst. In dut
wire y;

// instantiate DUT
mux21 dut (
.a (a),
.b (b),
.s (s),
.y (y));
// apply inputs one at a time
initial begin
//sequential block
a = 0; b = 0; s = 0; #10; //apply inputs, wait 10ns
s = 1; #10;
b = 1; s = 0; #10;
s = 1; #10;
end
// Waveform dumping
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule
After your run is completed you will see the following wavform. Verify your design here.

Lab 1-2. Flat Testbench with Self Checking MUX.

module testbench2( ); // No in, out

reg a,b,s; // inst. In dut
wire y;

// instantiate DUT
mux21 dut (
.a (a),
.b (b),
.s (s),
.y (y));
// apply inputs one at a time
initial begin
//sequential block

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 a = 0; b = 0; s = 0; #10;
//apply inputs, wait 10ns
if (y !== 0) $display("000 failed.");
else
$display("000 Correct.");
s = 1; #10;
if (y !== 0) $display("001 failed.");
else
$display("001 Correct.");
a = 1; s = 0; #10;
if (y !== 1) $display("100 failed.");
else
$display("001 Correct.");
a = 1; s = 0; #10;
if (y !== 1) $display("100 failed.");
else
$display("100 Correct.");
a = 1; s = 1; #10;
if (y !== 0) $display("101 failed.");
else
$display("101 Correct.");
end
endmodule

You will get the following response.

xcelium> run
000 Correct.
001 Correct.
001 Correct.
100 Correct.
101 Correct.
xmsim: *W,RNQUIE: Simulation is complete.
xcelium> exit
TOOL: xrun 20.09-s003: Exiting on Nov 20, 2021 at 23:44:14 EST (total: 00:00:02)

Lab 1-3. Flat Testbench with Self Checking ALU in a flat testbench.

In this section we have to design an ALU with the following function:

OP FUNCTIONALITY OP FUNCTIONALITY
CODE CODE
0 Addition 8 Bitwise Negation
1 Subtraction 9 Bitwise AND
2 Multiplication 10 Bitwise OR
3 Division 11 Bitwise XOR
4 Modulo Division 12 Left Shift
5 Logical AND 13 Right Shift
6 Logical OR 14 Increment
7 Logical Negation 15 Decrement

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The alu code can be as follows:

// Code your design here

module alu (out,a,b,s,clk);
input clk;
input [7:0]a,b;
input [3:0]s;
output [15:0] out;
reg [15:0] out;

always@(posedge clk) begin

case(s)
4'b0000: out=a+b; //8-bit addition
4'b0001: out=a-b; //8-bit subtraction
4'b0010: out=a*b; //8-bit multiplication
4'b0011: out=a/b; //8-bit division
4'b0100: out=a%b; //8-bit modulo division
4'b0101: out=a&&b; //8-bit logical and
4'b0110: out=a||b; //8-bit logical or
4'b0111: out=!a; //8-bit logical negation
4'b1000: out=~a; //8-bit bitwise negation
4'b1001:out=a&b; //8-bit bitwise and
4'b1010: out=a|b; //8-bit bitwise or
4'b1011: out=a^b; //8-bit bitwise xor
4'b1100: out=a<<1; //left shift
4'b1101: out=a>>1; //right shift
4'b1110: out=a+1; //increment
4'b1111: out=a-1; //decrement
endcase
end
endmodule

// Code your testbench here

// or browse Examples
module testbench;
reg clk;
reg [7:0] a,b;
reg [3:0] s;

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 wire [15:0] out;

// Clock generation
initial
forever #5 clk = ~clk;

// Module instantiation
alu DUT( .clk (clk),
.a (a),
.b (b),
.s (s),
.out (out)
);

initial begin
clk = 1'b0;
a = $random;
b = $random;
s = 4'bx;
#30
s = 0;
#10
result_checker(s,a,b,out);
#10
s = 14;
#10
result_checker(s,a,b,out);
#10
s = $random;
#10
result_checker(s,a,b,out);
$finish;
end
// Task : result_checker
// Task : result_checker
task result_checker(input [3:0] s,input [7:0] a,b,input [15:0]resulted_out);
reg [15:0] expected_out;
begin

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 if(s==0) expected_out=a + b;
else if(s==1) expected_out=a - b;
else if(s==2) expected_out=a * b;
else if(s==3) expected_out=a / b;
else if(s==4) expected_out=a % b;
else if(s==5) expected_out=a && b;
else if(s==6) expected_out=a || b;
else if(s==7) expected_out=!a;
else if(s==8) expected_out=~a;
else if(s==9) expected_out=a & b;
else if(s==10) expected_out=a | b;
else if(s==11) expected_out=a ^ b;
else if(s==12) expected_out=a << 1;
else if(s==13) expected_out=a >> 1;
else if(s==14) expected_out=a + 1;
else if(s==15) expected_out=a - 1;

if(resulted_out == expected_out)
$display("Passed : a=%d, b=%d, s=%d, resulted_out=%d, expected_out=%d",
a,b,s,resulted_out,expected_out);
else
$display("Failed : a=%d, b=%d, s=%d, resulted_out=%d, expected_out=%d",
a,b,s,resulted_out,expected_out);
end
endtask

// Waveform dumping
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

After your run you will get the following output. Check the expected result.

xcelium> run

Passed : a= 36, b=129, s= 0, resulted_out= 165, expected_out= 165

Passed : a= 36, b=129, s=14, resulted_out= 37, expected_out= 37

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Passed : a= 36, b=129, s= 9, resulted_out= 0, expected_out= 0

Simulation complete via $finish(1) at time 80 NS + 0

./testbench.sv:38 $finish;

xcelium> exit

TOOL: xrun 20.09-s003: Exiting on Nov 21, 2021 at 00:01:32 EST

(total: 00:00:01)

Finding VCD file...

./dump.vcd

[2021-11-21 00:01:32 EST] Opening EPWave...

Done

EPWave will show the following window. Verify the result.

Lab 1-4. Flat testbench with testvector in a separate testvector file : MUX Example.

// your design code

module mux21 (input a,b,s,
output y);
assign y=~s & a | s & b;
endmodule

// your testbench code

// Code your testbench here

// or browse Examples
module testbench3( ); // Testbench has no inputs, outputs,
reg clk, reset; // clk and rest are internal
reg a, b, s, yexpected; //values from testvectors
wire y;
reg [31:0] vectornum, errors; //bookkeeping variables
reg [3:0] testvectors[10000:0]; //array of testvectros
// instantiate device under test
mux21 dut (
.a (a),

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 .b (b),
.s (s),
.y (y));
// generate clock
always //no sensitivity list, so it always executes
begin
clk = 1; #5; clk = 0; #5; //10ns period
end
//at start of test, load vectors and pulse reset
initial
begin
$readmemb("testvectormux.tv", testvectors); //read vec
vectornum = 0; errors = 0;
reset =1; #27; reset = 0; //apply reset wait
end
// apply test vectors on rising edge of clk
always@(posedge clk)
begin
#1; {a, b, s, yexpected} = testvectors[vectornum];
end
// check results on falling edge of clk
always@(negedge clk)
if (~reset)
begin
if (y !== yexpected)
begin
$display("Error: inputs = %b", {a,b,s});
$display("Outputs = %b (%b exp)", y, yexpected);
errors = errors + 1;
end
// increment array index and read next testvector
vectornum = vectornum + 1;
if (testvectors[vectornum] === 4'bx)
begin
$display("%d tests completed with %d errors", vectornum, errors);
$finish;
end
end

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endmodule

The following result is obtained.

[2021-11-21 00:25:34 EST] xrun -Q -unbuffered '-timescale' '1ns/1ns' '-sysv' '-access'

'+rw' design.sv testbench.sv

TOOL: xrun 20.09-s003: Started on Nov 21, 2021 at 00:25:34 EST

xrun: 20.09-s003: (c) Copyright 1995-2020 Cadence Design Systems, Inc.

Top level design units:

testbench3

xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009

SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009

simulation semantics.

$readmemb("testvectormux.tv", testvectors); //read vec

xmelab: *W,MEMODR (./testbench.sv,23|41): $readmem default memory order incompatible

with IEEE1364.

Loading snapshot worklib.testbench3:sv .................... Done

xmsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009

SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009

simulation semantics.

xcelium> source /xcelium20.09/tools/xcelium/files/xmsimrc

xcelium> run

xmsim: *W,RMEMNOF: $readmem error: open failed on file "testvectormux.tv".

File: ./testbench.sv, line = 23, pos = 41

Scope: testbench3

Time: 0 FS + 0

1 tests completed with 0 errors

Simulation complete via $finish(1) at time 35 NS + 0

./testbench.sv:47 $finish;

xcelium> exit

TOOL: xrun 20.09-s003: Exiting on Nov 21, 2021 at 00:25:35 EST

(total: 00:00:01)

Done

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Lab 1-5. Finite State Machine Design
Now we will design a simple finite state machine (FSMs) and simulate it with IUS. There are two
types of finite state machines. In Mealy machines the output is a function of the current state and
inputs. In Moore machines the output is a function of only the current state.
FSMs are modelled in Verilog with an always block defining the state registers and combinational
logic defining the next state and output logic.
The simple finite state machine considered here is a divide-by-3 counter which has one output and
one input. The output should be asserted every three clock cycles. The state transition diagram for a
Moore machine is shown in figure below. The output value is labelled in each state because the
output is only a function of the state.

S0
Out=0

S2 S1
Out=1 Out=0

Divide by 3 counter state transition

diagram

The verilog code for the FSM is as below:

Module divideby3FSM ( input clk,

Input reset
Output out);
Reg [2:0] state, nextstate;

parameter S0 = 2’b00;
parameter S1 = 2’b01;
parameter S2 = 2’b10;

//state register
always @posedge clk, reset)
if (reset) state <=S0;
else state <=nextstate;
//next state logic
always @ (*)
case (state)

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 S0: nextstate <= S1;
S1: nextstate <= S2;
S2: nextstate <= S0;
default: nextstate <= S0;
endcase;
//output logic
assign out = (state ==S2);
endmodule

Now write also a state bench code and then follow the procedure described above and simulate
the FSM test bench and verify its functionality.

Report :
1. Provide the circuit diagram and performance curves of both the above circuits
2. Compare in a table the design specifications with the simulated specifications.
3. Discuss about the discrepancy between the design specifications and the simulated
specifications.
4. Now write behavioural verilog code of your assigned project and Verify its functionality
using IUS. After successful debug show the code and the simulation output and explain
your architecture in the report of the assignment.

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