LB 820-3302 Schematic Diagram - LSS

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
D7 MLB
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2012-01-12
LAST_MODIFIED=Thu Jan 12 10:24:09 2012

( csa) Date ( csa) Date
D Page Contents Sync Page Contents Sync D

1 11/30/2011 54 11/30/2011
1 Table of Contents K70 MLB 49 I and V Sense(Development) K70 MLB
2 11/30/2011 55 12/13/2011
2 System Block Diagram K70 MLB 50 Temperature Sensors D7 DOUG
3 01/03/2012 56 11/30/2011
3 Power Block Diagram D7 NICK 51 System Fan K70 MLB
4 12/13/2011 61 01/03/2012
4 BOM Configuration D7 NICK 52 AUDIO: CODEC/REGULATORS D7 BREECE
5 11/30/2011 62 01/03/2012
5 DEBUG LEDS K70 MLB 53 AUDIO: HEADPHONE AMP D7 BREECE
6 01/11/2012 63 01/03/2012
6 Power Connectors/Aliases D7 NICK 54 AUDIO: LEFT SPKR AMP D7 BREECE
7 11/30/2011 64 01/03/2012
7 Holes/PD parts K70 MLB 55 AUDIO: RIGHT SPKR AMP D7 BREECE
8 11/30/2011 65 01/03/2012
8 Unused Signal Aliases K70 MLB 56 AUDIO: Jack, Mikey, CHS Switch D7 BREECE
9 11/30/2011 66 01/03/2012
9 Signal Aliases K70 MLB 57 Audio: Spkr/Mic Conn. D7 BREECE
10 11/30/2011 67 01/03/2012
10 CPU DMI/PEG/FDI/RSVD K70 MLB 58 AUDIO: Detects/Grounding D7 BREECE
11 11/30/2011 68 01/03/2012
11 CPU CLOCK/MISC/JTAG K70 MLB 59 AUDIO: Speaker ID D7 BREECE
12 11/30/2011 69 12/13/2011
12 CPU DDR3 INTERFACES K70 MLB 60 PM Regulator Enables D7 NICK
13 11/30/2011 70 12/13/2011
13 CPU POWER K70 MLB 61 PM Power Good D7 NICK
14 11/30/2011 71 01/04/2012
14 CPU GROUNDS K70 MLB 62 VReg CPU Core/AXG Cntl D7 NICK
15 01/11/2012 72 01/04/2012
15 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU D7 TONY 63 VReg CPU Core Phases D7 NICK
16 11/30/2011 73 01/04/2012
16 CPU NON-GFX DECOUPLING K70 MLB 64 VReg CPU AXG Phases D7 NICK
17 11/30/2011 74 01/04/2012
17 GFX DECOUPLING & PCH PWR ALIAS 65 VReg CPU/PCH 1.05V S0
C 18
18
PCH SATA/PCIE/CLK/LPC/SPI
K70 MLB
K70 MLB
11/30/2011
66
75
VReg CPU VccSA S0
D7 NICK
D7 NICK
01/04/2012 C
19 11/30/2011 76 01/04/2012
19 PCH DMI/FDI/GRAPHICS K70 MLB 67 VReg 3.3V S5/5V S4 D7 NICK
20 11/30/2011 77 01/04/2012
20 PCH PCI/USB K70 MLB 68 VReg VDDQ and 1.8V S0 D7 NICK
21 01/11/2012 78 01/04/2012
21 PCH MISC D7 TONY 69 VReg G3Hot D7 NICK
22 11/30/2011 79 01/04/2012
22 PCH POWER K70 MLB 70 FET-Controlled S0 and S4 D7 NICK
23 11/30/2011 80 01/10/2012
23 PCH GROUNDS K70 MLB 71 KEPLER PCI-E D7 TONY
24 11/30/2011 81 01/10/2012
24 PCH DECOUPLING K70 MLB 72 KEPLER CORE/FB POWER D7 TONY
25 11/30/2011 82 01/10/2012
25 CPU and PCH XDP K70 MLB 73 KEPLER FRAME BUFFER I/F D7 TONY
26 11/30/2011 83 01/03/2012
26 CHIPSET SUPPORT K70 MLB 74 1V05 GPU POWER SUPPLY D7 NICK
27 12/13/2011 84 12/13/2011
27 USB HUB D7 NICK 75 GDDR5 Frame Buffer A D7 TONY
28 11/30/2011 85 12/13/2011
28 CPU Memory S3 Support K70 MLB 76 GDDR5 Frame Buffer B D7 TONY
29 11/30/2011 86 12/13/2011
29 DDR3 SO-DIMM Connector A K70 MLB 77 KEPLER EDP/DP/GPIO D7 TONY
31 11/30/2011 87 01/10/2012
30 DDR3 SO-DIMM CONNECTOR B K70 MLB 78 KEPLER GPIOS,CLK & STRAPS D7 TONY
33 11/30/2011 88 01/10/2012
31 DDR3 ALIASES AND BITSWAPS K70 MLB 79 KEPLER PEX PWR/GNDS D7 TONY
34 11/30/2011 89 01/03/2012
32 DDR3/FRAMEBUF VREF MARGINING K70 MLB 80 VReg GPU Core D7 NICK
35 12/13/2011 91 11/30/2011
33 AIRPORT/BT D7 NICK 81 Internal DP Support K70 MLB
36 01/11/2012 92 12/14/2011
34 Thunderbolt Host (1 of 2) D7 DOUG 82 Internal DP MUXing D7 NICK
37 01/11/2012 93 12/15/2011
B 35
38
Thunderbolt Host (2 of 2) D7 DOUG
01/11/2012
83
94
TBT DDC Crossbar D7 DOUG
12/15/2011
B
36 Thunderbolt Power Support D7 DOUG 84 Thunderbolt Connector A D7 DOUG
39 01/12/2012 96 12/15/2011
37 ETHERNET PHY (CAESAR IV) D7 NICK 85 Thunderbolt Connector B D7 DOUG
40 01/12/2012 97 01/03/2012
38 Ethernet Support & Connector D7 NICK 86 LCD Backlight Driver (LP8545) D7 NICK
41 01/12/2012 100 12/12/2011
39 SD READER CONNECTOR D7 NICK 87 K70 Rule Definitions D7 DAVE
42 01/11/2012 101 12/12/2011
40 Camera Controller D7 TONY 88 DDR3 Constraints D7 DAVE
45 12/16/2011 102 12/12/2011
41 SATA Connectors D7 NICK 89 CPU PCIe Constraints D7 DAVE
46 01/04/2012 103 12/12/2011
42 EXTERNAL USB PORTS A & B D7 NICK 90 PCH PCIe/DMI Constaints D7 DAVE
47 01/04/2012 104 12/12/2011
43 EXTERNAL USB PORTS C & D D7 NICK 91 SATA/FDI/XDP Constraints D7 DAVE
49 01/11/2012 105 12/12/2011
44 SMC D7 DOUG 92 PCH and BR Constraints D7 DAVE
50 01/11/2012 106 12/12/2011
45 SMC Support D7 DOUG 93 USB/Ethernet/SD Constraints D7 DAVE
51 12/13/2011 107 01/03/2012
46 SPI and Debug Connector D7 NICK 94 SMBus/Sensor Constraints D7 DOUG
52 01/03/2012 108 12/12/2011
47 SMBus Connections D7 DOUG 95 VReg Constraints D7 DAVE
53 01/06/2012 109 12/12/2011
48 I and V Sense(Production) D7 DOUG 96 CPU VReg Constraints D7 DAVE
110 12/12/2011
97 Platform VReg Constraints D7 DAVE
111 12/13/2011
98 TBT/DP Constraints D7 NICK
112 12/12/2011
99 GDDR5/GPU Constraints D7 DAVE
113 12/12/2011
A 100 BLC Constraints D7 DAVE

A
DRAWING TITLE
Schematic / PCB #’s SCH,D7,MLB

DRAWING NUMBER SIZE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION Apple Inc. 051-9509 D
REVISION
R
051-9509 1 SCH,MLB,D7 SCH CRITICAL 4.2.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
820-3302 1 PCBF,MLB,D7 PCB CRITICAL
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=D7
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 113
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST MODIFIED=Thu Jan 12 10 24 09 2012 IV ALL RIGHTS REDRAWING
E VE 1 OF 100
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D D
System Block diagram can be found on Kismet

PATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram
C C
B B
A SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A

PAGE TITLE
System Block Diagram

DRAWING NUMBER SIZE
Apple Inc. 051-9509 D

REVISION
R
4.2.0
2 OF 113
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 100
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Supply Module
AC/DC
PP12V_S0_FET PP12V_S0_GPUCORE
D Reg G3H 12V
PP12V ACDC
I
PP12V G3H
I D
PP12V_S0_GPUUNCORE
I
PP12V_S5
U7100
U7800
Regulator
Regulator Vin
PPCPUCORE_S0
Vin en S0 Reg S0 Core CPU
U7600
PP3V42_G3H
en G3H Reg G3H
SMC, RTC, BT
Regulator PPCPUAXG_S0
Reg S0 AXG CPU
Vin
PP5V_S5_LDO
en S5 LDO S5 5V SMC AVref
PP3V3_S5
Reg S5 3.3V Bootrom, PCH
U7400
PP3V3_S4_AP_FET Regulator
AirPort
PP3V3_ENET
Vin
Ethernet PP1V05_S0_REG
en S0 Reg S0 VccIO CPU, PCH
PP3V3_S0_SSD PPSSD_S0
SSD
C PP3V3_S0
I PP1V05_TBTLC
Thunderbolt C
Audio, LCD, PCH, Camera, GPU
PP1V05_TBTCIO
Thunderbolt
PP3V3_TBTLC
Thunderbolt
U7500
PP3V3_S0_SW_SD_PWR
SD Card Regulator
PP5V_S4
en S4 Reg S4 5V USB ports Vin
PPVCCSA_S0_REG
PP5V_S0 en S0 Reg S0 VccSA CPU
Audio, PCH, Camera
PPHDD_S0
I HDD
U7700
Regulator
Vin
PPVDDQ S3 PPVDDQ_S3_DDR
en S3 Reg S3 VDDQ I SO-DIMMs Loads
PP1V5_S0
Fan
Audio, CPU
Internal display
PPDDRVTT_S3 Speaker amps
LDO S3 VTT S0-DIMMs
B B
PPDDRVTT_S0
en S0 LDO S0 VTT SO-DIMMs
U8900
Regulator
PP12V_S0_GPUCORE
Vin
Loads PPVCORE_S0_GPU
en S0 Reg S0 Core GPU
Thunderbolt
U8350
Regulator
U7750 PP12V_S0_GPUUNCORE
Regulator Vin
PPVDDQ_S0_GPU
PP5V_S0_FET en S0 Reg S0 GPUVDDQ GPU FB
Vin
PP1V8_S0_REG
en S0 Reg S0 1.8V CPU PLL, GPU PLL
A U8300 SYNC MASTER=D7 NICK SYNC DATE=01/03/2012 A
Regulator PAGE TITLE
Power Block Diagram

Vin DRAWING NUMBER SIZE
en S0 Reg S0 IOVDD PP1V05_S0_GPU

GPU Apple Inc. 051-9509 D
REVISION
R
4.2.0
3 OF 113
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Main BOM Variants
Alternates
BOM NUMBER BOM NAME BOM OPTIONS
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
085-4441 PCBA,MLB,DEV,D7 DEVELOPMENT,D7_DEVEL PART NUMBER
639-3566 PCBA,MLB,D7,GSA,GOOD D7_COMMON,CPU:GOOD,GPU:GSA,GS,FBA,SSD:N,EEEE:DF98 377S0107 377S0126 ALL USB diodes

639-3668 PCBA,MLB,D7,GSB,GOOD D7_COMMON,CPU:GOOD,GPU:GSB,GS,FBB,SSD:N,EEEE:F117 157S0055 157S0058 ALL Enet magnetics
639-3567 PCBA,MLB,D7,GTX,BETTER D7_COMMON,CPU:BETTER,GPU:107GTX,FBA,FBB,SSD:Y,EEEE:DT42 376S1081 376S0975 ALL P/NCh dual FET
639-3665 PCBA,MLB,D7,GTX,CTO D7_COMMON,CPU:CTO,GPU:107GTX,FBA,FBB,SSD:Y,EEEE:F116 341S3486 341S3487 ALL P/NCh dual FET
D D
CPU Socket
Bar Code Labels / EEEE #’s PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
511S0073 1 SOCKET,MOLEX,LGA1155,CPU-LF U1000 CRITICAL

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
825-7122 1 MLB LABEL,48.0X4.8 EEEE_DF98 CRITICAL EEEE:DF98

825-7122 1 MLB LABEL,48.0X4.8 EEEE_DT42 CRITICAL EEEE:DT42
CPU Socket Alternates
825-7122 1 MLB LABEL,48.0X4.8 EEEE_F116 CRITICAL EEEE:F116
825-7122 1 MLB LABEL,48.0X4.8 EEEE_F117 CRITICAL EEEE:F117 PART NUMBER
511S0071 511S0073 ALL TYCO SOCKET

511S0072 511S0073 ALL FOXCONN SOCKET
BOM Groups
BOM GROUP BOM OPTIONS
D7_COMMON COMMON,ALTERNATE,D7_COMMON1,D7_COMMON2,D7_PROGPARTS
VRAM BOM Variants
D7_COMMON1 XDP,RSMRST:SMC,SPEAKERID,TBTHV:P12V BOM NUMBER BOM NAME BOM OPTIONS
D7_COMMON2 SNS_CPUCORE:3PHASE,CPUCOREDRV:ISL6612,IG:N,GPU_ROM:YES,SNS_GPUS0:K70,SNS_VDDQS3_DDR:Y 607-9432 K70,GDDR5,SAMSUNG FB:BOTH_SAMSUNG
Add ’K70_PRODUCTION’ at RevA release 607-9435 K70,GDDR5,HYNIX FB:BOTH_HYNIX

D7_PROGPARTS SMC:PROTO1,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG
D7_DEVEL XDP_CONN,LPCPLUS,VREFMRGN:EXT,BKLT_PWM,DEVEL_SENSORS,DEVEL_AUDIO 607-9433 K70,GDDR5,SAMSUNG_CH1 FB:CH1_SAMSUNG
C DEVEL_SENSORS SNS_VDDQS0_GPU:Y,SNS_VDDQS3:Y,TEMPSNSDEV 607-9436 K70,GDDR5,HYNIX_CH1 FB:CH1_HYNIX

C
D7_PRODUCTION SNS_VDDQS0_GPU:N,SNS_VDDQS3:N,VREFMRGN:N 607-9434 K70,GDDR5,SAMSUNG_CH2 FB:CH2_SAMSUNG
607-9437 K70,GDDR5,HYNIX_CH2 FB:CH2_HYNIX
CPUs
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION VRAM Module Parts
337S4240 1 IVB QC13 QS E0 2 8G 65W 4+1 1 10 6M LGA CPU CRITICAL CPU:GOOD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
337S4258 1 IVB QC48 QS E1 2 9G 65W 4+2 1 10 6M LGA CPU CRITICAL CPU:BETTER Replace with 65W part 333S0619 4 IC SGRAM GDDR5 32MX32 1 5GHz G DIE HF U8400,U8450,U8500,U8550 CRITICAL FB:BOTH_SAMSUNG
337S4246 1 IVB SR0PN PRQ E1 3 1G 65W 4+2 1 15 8M LG CPU CRITICAL CPU:CTO 333S0620 4 IC GDDR5 32MX32 1 5GHZ VEGA 44NM B DIE U8400,U8450,U8500,U8550 CRITICAL FB:BOTH_HYNIX
333S0631 2 IC SGRAM GDDR5 64MX32 4 2GBPS D DIE HF U8400,U8450 CRITICAL FB:CH1_SAMSUNG
333S0630 2 U8400,U8450 CRITICAL FB:CH1_HYNIX

Module Parts IC GDDR5 2GB M DIE 170B FBGA
333S0631 2 IC SGRAM GDDR5 64MX32 4 2GBPS D DIE HF U8500,U8550 CRITICAL FB:CH2_SAMSUNG

333S0630 2 IC GDDR5 2GB M DIE 170B FBGA U8500,U8550 CRITICAL FB:CH2_HYNIX
337S4234 1 IC PCH PPT DT Z77 QS C1 U1800 CRITICAL
338S1047 1 IC TBT CR 4C ES1 288 FCBGA 12X12MM U3600 CRITICAL
337S4221 1 IC,GPU,NV,GK107-GS-2/1-QS-A U8000 CRITICAL GPU:GSA
337S4220 1 IC,GPU,NV,GK107-GS-2/1-QS-A U8000 CRITICAL GPU:GSB

VRAM Alternates
1 U8000
B 337S4239
343S0592 1
IC,GPU,NV,GK107-GTX-QS-A2
IC,BCM57766,CIV+,A0,8X8 U3900
CRITICAL
CRITICAL
GPU:107GTX
607-9435
PART NUMBER
607-9432 VRAM GDDR5_BOTH

B
607-9432 1 K70,GDDR5,SAMSUNG VRAM CRITICAL GPU:107GTX 607-9436 607-9433 GPU:GSA VRAM GDDR5_CH1
607-9437 607-9434 GPU:GSB VRAM GDDR5_CH2
Programmable Parts
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION GPU Module Parts
341S3493 1 IC,CR,V24.2,D7/D7I U3690 CRITICAL T29ROM:PROG
335S0865 1 IC,EEPROM,SERIAL,256KB,MLP8 U3690 CRITICAL T29ROM:BLANK
607-9433 1 K70 GDDR5 SAMSUNG CH1 VRAM CRITICAL GPU:GSA
335S0807 1 IC,64 MBIT SPI SERIAL FLASH U5110 CRITICAL BOOTROM:BLANK Alternate: 335S0812
607-9434 1 K70 GDDR5 SAMSUNG CH2 VRAM CRITICAL GPU:GSB
341S3480 1 IC,PROGRMD,EFI ROM,K70 U5110 CRITICAL BOOTROM:PROG
335S0862 1 IC SERIAL FLASH 2MBIT 2 7V REV F U3990 CRITICAL CIVROM:BLANK Alternate: 335S0854
341S3487 1 IC,ENET 1MBITFLASH,CIV,PVT,J40 U3990 CRITICAL CIVROM:PROG

338S1098 1 IC,SMC12-A3,BLANK,D7 U4900 CRITICAL SMC:BLANK
341S3484 1 IC,SMC,PROGRMD,PROTO1,D7 U4900 CRITICAL SMC:PROTO1
341S3388 1 IC,SMC,PROGRMD,EVT,D7 U4900 CRITICAL SMC:EVT
341S3389 1 IC,SMC,PROGRMD,DVT,D7 U4900 CRITICAL SMC:DVT
Programmable Parts (unused)
A 341S3390 1 IC,SMC,PROGRMD,PVT,D7 U4900 CRITICAL SMC:PVT
SYNC MASTER=D7 NICK SYNC DATE=12/13/2011 A
341S3409 1 IC,SMC,PROGRMD,PROD,D7 U4900 CRITICAL SMC:PROD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PAGE TITLE
341S3453 1 IC,CAMERA FLASH,K70/K72 U4202 CRITICAL CAMROM:PROG 335S0724 1 IC,1 MBIT SERIAL FLASH U8701 CRITICAL GPUROM:BLANK
BOM Configuration
DRAWING NUMBER SIZE
335S0852 1 IC,FLASH,SPI,1MBIT,3V3 U4202 CRITICAL CAMROM:BLANK
REVISION
R
4.2.0
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GPU GOOD Led VIDEO ON Led

S5 Led ALL_SYS_PWRGD Led =PP3V3_S0_LED
D =PP3V3 S4 LED
6 5
6 5 =PP3V3_S0_LED
D
6 =PP3V3_S5_LED
6
1
R502 R503
1
1K
R504
1
1K
1
R501
1K 5%
1K
1/16W
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5% MF-LF 2 402 2 402
1/16W 2 402 GPU_PRESENT_R
MF-LF
2 402
CORE_VOLTAGES_ON_R LCD_SHOULD_ON_R
A SILK_PART=3
ITS_PLUGGED_IN A SILK PART=2 LED503
A
SILK_PART=1 LED502 GREEN-3.6MCD
LED501 K
GREEN-3.6MCD
2.0X1.25MM-SM
K 2.0X1.25MM-SM
A SILK_PART=4
GREEN-3.6MCD
K
2.0X1.25MM-SM
CORE_VOLTAGES_ON
GPU_PRESENT_DRAIN
LED504
GREEN-3.6MCD
6 K 2.0X1.25MM-SM
3 This LED is a GPIO driven from
D the southbridge that indicates
that chipset has enumerated graphics
D Q502
Q502 2
2N7002DW-X-G VIDEO ON L
2N7002DW-X-G 21 IN GPU_GOOD G S SOT-363 IN 81
61 44 ALL SYS PWRGD 5 G S SOT 363

IN
1
4
C C
B B

PAGE TITLE
DEBUG LEDS
DRAWING NUMBER SIZE

REVISION
R
4.2.0
5 OF 113
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MLB to AC-DC Supplemental Signal Connector S0 Rails Ground/Common

SILK_PART=PwrSig Enabled when system is in run
CRITICAL GND
J601 97 PP12V_S0 PP12V_S0_FET 70
95 PP1V5_S0
MAKE_BASE=TRUE
PP1V5_S0_FET 70
MAKE_BASE=TRUE
53780-8606 MAKE_BASE=TRUE
=PP12V_S0_REG_CPUCORE_S0 63
=PP1V5_S0_CPU_MEM 11 13 16
M-RT-SM
7 =PP12V_S0_REG_VCCSA_S0 =PP1V5_S0_AUD_DIG 52
66
R606 74 68 66 65 62 6 =PP3V3_S0_VRD =PP12V S0 REG P1V05 S0 65
=PP1V5_S0_SENSE 41
1
0 2 1
45 OUT PWR_BTN PWR_BTN_R =PP12V_S0_SNS_GPUCORE_R 48
5% 2 =PP12V_S0_SNS_GPUUNCORE_R 48 PPDDRVTT_S0 PPDDRVTT_S0_LDO

NOSTUFF 1/16W 2 1 95 68
C600 1 MF-LF
402
D600 94 50 OUT SNS_ACDC_N 3 R601 =PP12V_S0_AUDIO_SPKRAMP 54 55
MAKE_BASE=TRUE
=PPDDRVTT_S0_CLAMP 28
10K
D 1UF
10%
6.3V 2
6.8V-100PF
402
94 50
67 45
OUT
IN
SNS_ACDC_P
BURSTMODE_EN_L
4
5
5%
1/16W
MF-LF
=PP12V_S0_BKLT
=PP12V_S0_FAN
86
51
=PPDDRVTT_S0_MEM_A
=PPDDRVTT S0 MEM B
29
30
D
CERM
402 1 45 6 OUT SMC_ACDC_ID 6 2 402 =PP12V_S0_LCD 81
SMC_ACDC_ID 97 PP12V_S0_GPUCORE PP12V_S0_SNS_GPUCORE 48 PPDDRVREF DQ_MEM_A_S3 PPDDRVREF_DQ_MEM_A

8 45 6
MAKE_BASE=TRUE 97 32
=PP12V_S0_REG_GPUCORE_S0 80
MAKE_BASE=TRUE
=PPDDRVREF_DQ_MEM_A 29
97 PP12V_S0_GPUUNCORE PP12V_S0_SNS_GPUUNCORE 48
MAKE_BASE=TRUE
=PP12V_S0_REG_GPU_P1V05_S0 74
=PP12V_S0_REG_GPU_VDDQ_S0 97 PPDDRVREF_CA_MEM_A_S3 PPDDRVREF_CA_MEM_A 32

74
MLB to AC-DC Connector MAKE_BASE=TRUE
=PPDDRVREF_CA_MEM_A 29
97 PPHDD_S0 PPHDD_S0_SNS 48
MAKE_BASE=TRUE
=PP5V S0 SATA 41
97 PPDDRVREF DQ_MEM_B_S3 PPDDRVREF_DQ_MEM_B 32
MAKE_BASE=TRUE
CRITICAL 97 PP5V_S0 PP5V_S0_FET 70 =PPDDRVREF_DQ_MEM_B 30
MAKE_BASE=TRUE
=PP5V S0 REG CPUCORE S0 62
J600 =PP5V S0 REG VCCSA S0 66
43650-0603
F-RT-TH =PP5V_S0_REG_P1V05_S0 65 97 PPDDRVREF CA_MEM_B_S3 PPDDRVREF_CA_MEM_B 32
MAKE_BASE=TRUE
1 =PP5V_S0_REG_GPU_P1V05_S0 74 =PPDDRVREF_CA_MEM_B 30
2 PP12V_G3H_ACDC 6
=PP5V_S0_REG_P1V8_S0 68
3 =PP5V_S0_REG_GPUCORE_S0 80
4 =PP5V_S0_REG_GPU_VDDQ_S0 74 95 PP1V05_S0 PP1V05_S0_REG 65

MAKE_BASE=TRUE
5 EMC EMC =PP5V_S0_VRD 68 =PP1V05_S0_DP
6 J600.6:3mm J600.7:3mm J600.8:3mm =PP5V S0 AUDIO 52 59 =PP1V05 S0 P1V05TBTFET 36
1 1 1 =PP5V S0 CAMERA =PP1V05 S0 PCH

C601 C602 C603 40 18 24
10UF 1000PF 1000PF =PP5V_S0_ISENSE 48 =PP1V05_S0_PCH_VCC_ADPLL 17

10% 5% 5%
25V 25V 25V =PP5V_S0_LPCPLUS 46 =PP1V05_S0_PCH_VCC_ASW 22 24
2 X5R 2 NP0 C0G 2 NP0 C0G
805 402 402 =PP5V_S0_PCH 24 =PP1V05_S0_PCH_VCC_CORE 22 24
C G3 Rails
=PP5V_S0_BKLT
=PPHDD_S0_SNS_R
86
48
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCC_DIFFCLK
22 24
22
C
Always on: Keeps the PCH RTC alive
=PP1V05_S0_PCH_VCC_SSC 22
PP3V3 G3 PP3V3 G3H RTC 22 26 PP3V3_S0 PP3V3_S0_FET =PP1V05 S0 PCH VCCIO DMI 22
97 70
MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3 G3 PCH 18 19
S4 Rails MAKE_BASE=TRUE
=PP3V3_S0_P3V3TBTFET 36
=PP1V05 S0 PCH VCCIO PCIE 18 19 22
NET_SPACING_TYPE=POWER Enabled when system has AC and is in run or sleep
=PP3V3_S0_PWRCTL 70 80
=PP1V05_S0_PCH_VCCIO_SATA 18 22 24
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM 97 PP5V_S4 PP5V_S4_REG =PP3V3_S0_VRD =PP1V05_S0_PCH_VCCIO_USB 22
67 6 62 65 66 68 74
MAX_NECK_LENGTH=3MM MAKE_BASE=TRUE
=PP5V_S4_REG_VDDQ_S3 68 =PP3V3_S0_AUDIO 40 52 54 55 58
=PP1V05_S0_PCH_V_PROC_IO 22 24
G3H Rails =PP5V_S4_FET_P5V_S0 70 =PP3V3_S0_AUDIO_DIG 56

=PPVCCIO_S0_CPU 10 11 13 16 62
=PP5V S4 MEMRESET 28 =PP3V3 S0 BT =PPVCCIO_S0_SMC 45

33
97 PP12V_ACDC PP12V_G3H_ACDC 6 =PP5V_S4_PWRCTL =PP3V3_S0_CAMERA =PPVCCIO_S0_XDP 25
70 40
MAKE_BASE=TRUE
=PP12V_G3H_SNS_R 48 =PP5V_S4_USB 42 43 =PP3V3_S0_DP 47 81 83
=PP3V3_S0_ENET 37
96 PPVCORE_S0_CPU PPCPUCORE_S0_REG 63
MAKE_BASE=TRUE
PP12V_G3H PP12V_G3H_SNS =PP3V3_S0_FAN =PPVCORE_S0_CPU 13 16 48 62
97 48 51
MAKE_BASE=TRUE
=PP12V_G3H_REG_3V42_G3H 69 =PP3V3_S0_INTDPMUX 82
=PP12V_G3H_FET_P12V_S5 69 97 PP3V3_S4 PP3V3_S4_FET 70 =PP3V3_S0_LED 5

MAKE_BASE=TRUE PPVAXG_S0 PPCPUAXG_S0_REG
=PP12V_G3H_FET_P12V_S0 70 =PP3V3_S4_FET_ENET 38 =PP3V3_S0_LED_SATA 15 41
96
MAKE_BASE=TRUE
64
=PP3V3_S4_PWRCTL 70 =PP3V3_S0_PCH =PPVAXG_S0_CPU 13 17 48 62

18 21 24
97 PP3V42_G3H PP3V42_G3H_REG 69 =PP3V3_S4_ALS 40 =PP3V3_S0_PCH_GPIO 15 19 20 36

MAKE_BASE=TRUE
=PP3V3_G3H_BT 33 =PP3V3_S4_AP 33 =PP3V3_S0_PCH_PM 26
=PP3V3_G3H_SMC =PP3V3_S4_LED =PP3V3_S0_PCH_STRAPS 95 PPVCCSA_S0 PPVCCSA_S0_REG 66

44 45 5 15
MAKE_BASE=TRUE
=PP3V3_RTC_D 26 =PP3V3_S4_MEMRESET =PP3V3_S0_PCH_VCC =PPVCCSA_S0_CPU 13 16
28 22 24
=PPVIN_G3H_SMCVREF 45 =PP3V3_S4_PCH 15 =PP3V3_S0_PCH_VCC_ADAC 17
=PP3V3_G3H_SMC_USBMUX =PP3V3_S4_PM =PP3V3_S0_PCH_VCC_GPIO

S5 Rails
42 28 22 24
Thunderbolt Rails (S0)
=PP3V3 S4 SDCARD 15 39 =PP3V3 S0 PCH VCC HVCMOS 22 24
Enabled when Thunderbolt cable is plugged in
Enabled when system has AC and is in S5 =PP3V3_S4_SMC 45 =PP3V3_S0_PCH_VCC_PCI 22 24
PP3V3 TBTLC =PP3V3 TBTLC FET
B 97 PP12V S5 PP12V_S5_FET 69
=PP3V3_S4_SMBUS_SMC_2
=PP3V3_S4_TBT
47
34 35 36 84 85
=PP3V3_S0_RSTBUF
=PP3V3_S0_SDCARD
26
39
97
MAKE_BASE=TRUE
=PP3V3 TBT PCH GPIO
36
15
B
MAKE_BASE=TRUE =PP3V3_S4_TBTAPWRSW =PP3V3_S0_SENSE =PP3V3_TBTLC_RTR 34 35 36
=PP12V_S5_REG_P3V3P5V_S5 67
45 84 41 48 49 50
=PP3V3_S4_TBTBPWRSW =PP3V3_S0_SMBUS =PPVDDIO_TBT_CLK 26

=PP12V S5 REG VDDQ S3 68
45 85 47
=PP12V S5 PWRCTL 60 61 70
=PP3V3_S4_USB_HUB 27 =PP3V3_S0_SMBUS_SMC_0 47
=PPHV_SW_TBTAPWRSW 84
=PP3V3 S4 VREFMRGN 32 =PP3V3 S0 SMBUS SMC 1 47
95 PP1V05_TBTLC =PP1V05_TBTLC_FET 36
=PPHV_SW_TBTBPWRSW =PP3V3 S0 SMBUS SMC 3 47 MAKE_BASE=TRUE
85 =PP1V05_TBTLC_RTR 35 36
=PP12V_S5_SNS 48
=PP3V3 S0 SMC 45
=PP3V3_S0_TBTPWRCTL 36
PP5V_S5 PP5V_S5_LDO =PP3V3_S0_BKLT_VDDIO 86 95 PP1V05_TBTCIO =PP1V05_TBTCIO_FET 36

97
MAKE_BASE=TRUE
67
S3 Rails =PP3V3_GPU_IFPX_PLLVDD
MAKE_BASE=TRUE
=PP1V05_TBTCIO_RTR
=PP5V_S5_PWRCTL 67 70
Enabled when system is in run or sleep
77 35
=PP5V S5 PCH 24
=PP3V3_GPU_MISC 77 80
97 PP3V3 ENET PP3V3_ENET_FET 38 =PP3V3_GPU_VDD33 71 77 78 79
97 PP3V3 S5 PP3V3 S5 REG 67

MAKE_BASE=TRUE
=PP3V3 ENET PHY 37 38 =PPSPD S0 MEM A 29
GPU Rails (S0)
MAKE_BASE=TRUE =PP3V3 ENET SYSCLK =PPSPD S0 MEM B Enabled when system is in run
=PP3V3_S5_LDO_P1V05_S5 26 30
=PP3V3_S5_FET_P3V3_S4 70
=PPVDDIO ENET CLK 26 PPVCORE_S0_GPU PPGPUCORE_S0_REG
97 80
MAKE_BASE=TRUE
=PP3V3_S5_FET_P3V3_S0 70 =PPVCORE_GPU 72 79
=PP3V3_S5_PWRCTL 60 61 70 78
=PP3V3_S5_VRD 95 PPVDDQ_S3 PPVDDQ_S3_REG 68

67 68
MAKE_BASE=TRUE 97 PP1V05 S0 GPU PP1V05 S0 GPU REG 74
=PP3V3 S5 LED 5
=PPVDDQ_S3_FET_VDDQ_S0 70 MAKE_BASE=TRUE
PP3V3_S0_SSD PP3V3_S0_SSD_FET =PP1V05_GPU_IFPCD_IOVDD 77
=PP3V3 S5 LPCPLUS =PPVDDQ_S3_LDO_DDRVTT 68
97
MAKE_BASE=TRUE
70
46
=PPSSD_S0_SNS_R =PP1V05_GPU_IFPEF_IOVDD 77
=PP3V3 S5 PCH =PPVDDQ_S3_SNS_DDR_R 49
49
19 24 26 =PP1V05_GPU_PEX_IOVDD 73 79
=PP3V3_S5_PCH_STRAPS 15
=PPVDDQ S3 VSNS PPSSD_S0 PPSSD_S0_SNS
97 49 =PP1V05_GPU_PEX_PLLVDD 77 79
MAKE_BASE=TRUE
=PP3V3_S5_PCH_VCC_DSW 22 24 =PP3V3_S0_SSD 41
=PP3V3_S5_PCH_VCC_SPI 22 24 =PP3V3_S0_SATAMUX 41
PPVDDQ_S3_DDR PPVDDQ_S3_SNS_DDR 97 PPVDDQ S0 GPU PP1V5R1V35 S0 GPU REG 74
=PP3V3_S5_PCH_VCCSUS_HDA 22 24
95 49
MAKE_BASE=TRUE
A =PP3V3_S5_PCH_VCCSUS_USB 22 24
MAKE_BASE=TRUE
=PPVDDQ_S3_DDR_VREF
=PPVDDQ_S3_MEM_A
32
97 PP1V8_S0
MAKE_BASE=TRUE
PP1V8_S0_REG
=PP1V8_S0_CAMERA
68
40
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_S0_FB
72 75 76
73
=PP3V3_S5_ROM 46
29
PAGE TITLE
=PP1V8_S0_CPU_PLL
=PP3V3 S5 SENSE
=PP3V3 S5 SMC
48
45
=PPVDDQ_S3_MEM_B
=PPVDDQ_S3_MEMRESET
30
28
=PP1V8_S0_PCH
13 16
19
Power Connectors/Aliases
=PP1V8_S0_PCH_VCC_DFTERM 22 24
DRAWING NUMBER SIZE
=PP3V3_S5_USBMUX 42 43
051-9509 D
=PP1V8_S0_PCH_VCC_VRM 24
Apple Inc.
=PP3V3_S5_XDP 25
REVISION
=PPVDDIO S0 SBCLK 26
PPDDRVTT_S3 PPDDRVTT_S3_LDO R
95
MAKE_BASE=TRUE
68
=PP1V8 S0 GPUVID 80
4.2.0
=PPDDRVTT_S3_VREFCA 32
=PP1V8_S0_ENET 38
6 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Heatsink WIRELESS CARD MTG HOLES
4mm Plated Holes (998-0850) 998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)
OMIT OMIT OMIT OMIT

ZH0700 ZH0701 ZH0702 ZH0703
8P5R5-NSP 8P5R5-NSP 8P5R5-NSP 8P5R5-NSP CRITICAL CRITICAL
1 1 1 1
ZH0721 ZH0722 D
D 5P5R2P3-4P3B-NSP
1
5P5R2P3-4P3B-NSP
1
GPU HEATSINK MOUNTING FEATURES

(860-0988)
CRITICAL POGO PINS

CRITICAL
SH0777 SH0779
STDOFF-4.5OD.98H-1.1-3.48-TH APN: 870-1939
STDOFF-4.5OD.98H-1.1-3.48-TH CRITICAL 1
1 SH0778
STDOFF-4.5OD.98H-1.1-3.48-TH
1
C C
Rear Cover
998-4559 (Plated holes, 4mm inner diameter, 8mm pad)
CRITICAL CRITICAL
ZH0713 ZH0714 CRITICAL
CRITICAL
7P0R4P0-8P0B-NSP 7P0R4P0-8P0B-NSP ZH0715 ZH0716
1 1 7P0R4P0-8P0B-NSP
1 7P0R4P0-8P0B-NSP
1
USB Can holes

B 998-3975 (Plated slot holes, 1.10mm x 0.45mm)
B
ZH0730 ZH0731
TH-NSP
TH-NSP
1 1
SL-1.1X0.45-1.4X0.75 SL-1.1X0.45-1.4X0.75
SSD STANDOFF
APN: 860-1461
CRITICAL
NUT0713
STDOFF-4.5OD2.2ID-5.6H-SM
1

PAGE TITLE
Holes/PD parts
DRAWING NUMBER SIZE

REVISION
R
4.2.0
7 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Reserved PCH Clocks PCH Unused Display PCH SATA PCH Test Points
10 TP_CPU_RSVD<16..1> NC_CPU RSVD<16..1> 19 TP_CRT_IG_RED NC_CRT_IG_RED 18 TP_SATA_C_R2D_CN NC_SATA_C R2D_CN 21 TP_PCH_TP1 NC_PCH TP1
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
10 TP_CPU_RSVD<46..19> NC_CPU_RSVD<46..19> 19 TP_CRT_IG_GREEN NC_CRT_IG_GREEN 18 TP_SATA_C_R2D_CP NC_SATA_C R2D_CP 21 TP_PCH_TP2 NC_PCH TP2
91 10 CPU_CFG<15..12> TP_CPU_CFG<15..12> 18 TP_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4N 19 TP_CRT_IG_BLUE NC_CRT_IG_BLUE 18 TP_SATA_C_D2RN NC_SATA_C D2RN 21 TP_PCH_TP3 NC_PCH TP3
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 TP PCIE CLK100M PE4P NC PCIE CLK100M PE4P 19 TP CRT IG HSYNC NC CRT IG HSYNC 18 TP SATA C D2RP NC SATA C D2RP 21 TP PCH TP4 NC PCH TP4
19 TP_CRT_IG_VSYNC NC_CRT_IG_VSYNC 21 TP_PCH_TP5 NC_PCH TP5
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
21 TP_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6N
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK 18 TP_SATA_D_R2D_CN NC_SATA_D R2D_CN 21 TP_PCH_TP6 NC_PCH TP6
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
D 21 TP_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6P
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP CRT IG DDC DATA NC CRT IG DDC DATA
MAKE_BASE=TRUE NO_TEST=TRUE
18 TP SATA D R2D CP NC SATA D R2D CP
21 TP PCH TP7 NC PCH TP7
D
18 TP_SATA_D_D2RN NC_SATA_D D2RN 21 TP_PCH_TP8 NC_PCH TP8
CPU Memory 21 TP PCIE CLK100M PE7N NC PCIE CLK100M PE7N
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_B_MLN<3..0> NC_DP_IG_B_MLN<3..0> 18 TP_SATA_D_D2RP NC_SATA_D D2RP 21 TP_PCH_TP9 NC_PCH TP9
12 TP_MEM_A_DQ_CB<7..0> NC_MEM_A_DQ_CB<7..0> 21 TP_PCIE_CLK100M_PE7P NC_PCIE_CLK100M_PE7P
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP IG B MLP<3..0> NC DP IG B MLP<3..0> 21 TP PCH TP10 NC PCH TP10
12 TP_MEM_A_DQS_N<8> NC_MEM A_DQSN<8> 19 DP_IG_B_AUX_N NC_DP_IG_B_AUXN TP_SATA_E_R2D_CN NC_SATA_E R2D_CN TP_PCH_TP11 NC_PCH TP11
18 21
12 TP_MEM_A_DQS_P<8> NC_MEM_A_DQSP<8> 10 TP PE TX N<3..0> NC PE TXN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_B_AUX_P NC_DP_IG_B_AUXP 18 TP_SATA_E_R2D_CP NC_SATA_E R2D_CP 21 TP_PCH_TP12 NC_PCH TP12
10 TP_PE_TX_P<3..0> NC_PE_TXP<3..0>
12 TP_MEM_B_DQ_CB<7..0> NC_MEM B_DQ_CB<7..0> MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_B_HPD NC_DP_IG_B_HPD 18 TP_SATA_E_D2RN NC_SATA_E D2RN 21 TP_PCH_TP13 NC_PCH TP13
10 TP_PE_RX_N<3..0> NC_PE_RXN<3..0>
TP MEM B DQS N<8> NC MEM B DQSN<8> MAKE_BASE=TRUE NO_TEST=TRUE 19 DP IG B DDC CLK NC DP IG B CTRL CLK 18 TP SATA E D2RP NC SATA E D2RP 21 TP PCH TP14 NC PCH TP14
12
10 TP PE RX P<3..0> NC PE RXP<3..0>
TP_MEM_B_DQS_P<8> NC_MEM B_DQSP<8> MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_B_DDC_DATA NC_DP_IG_B_CTRL_DATA 21 TP_PCH_TP15 NC_PCH TP15
12
18 TP_SATA_F_R2D_CN NC_SATA_F_R2D_CN 21 TP_PCH_TP16 NC_PCH TP16
MEM A CLK N<2..3> NC MEM A CLKN<2..3> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
88 12
MAKE_BASE=TRUE NO_TEST=TRUE 18 DMI_MIDBUS_CLK100M_N NC_DMI MIDBUS_CLK100N
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP IG C MLN<3..0> NC DP IG C MLN<3..0> 18 TP SATA F R2D CP NC SATA F R2D CP 21 TP PCH TP17 NC PCH TP17
MEM_A_CLK_P<2..3> NC_MEM A_CLKP<2..3> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
88 12
MAKE_BASE=TRUE NO_TEST=TRUE 18 DMI MIDBUS CLK100M P NC DMI MIDBUS CLK100P
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_C_MLP<3..0> NC_DP_IG_C_MLP<3..0> 18 TP_SATA_F_D2RN NC_SATA_F_D2RN 21 TP_PCH_TP18 NC_PCH TP18
88 12 MEM_A_CS_L<2..3> NC_MEM A_CS_L<2..3> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_C_AUX_N NC_DP_IG_C_AUXN 18 TP_SATA_F_D2RP NC_SATA_F_D2RP 21 TP_PCH_TP19 NC_PCH TP19
MEM A CKE<2..3> NC MEM A CKE<2..3> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
88 12
MAKE_BASE=TRUE 18 TP_CLKOUT_PEG_A_N NC_CLKOUT PEG_AN
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 19 DP IG C AUX P NC DP IG C AUXP 21 TP PCH TP20 NC PCH TP20
MEM_B_CLK_N<2..3> NC_MEM_B_CLKN<2..3> 18 TP CLKOUT PEG A P NC CLKOUT PEG AP
88 12
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_C_HPD NC_DP_IG_C_HPD
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE PCH Reserved
88 12 MEM B CLK P<2..3> NC MEM B CLKP<2..3> DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_CLK
19
MEM_B_CS_L<2..3> NC_MEM B_CS_L<2..3> 19 TP_PCH_RESERVE_0 NC_PCH_RESERVE_0
88 12
18 TP PCH CLKOUT DPN NC PCH CLKOUT DPN 19 DP IG C CTRL DATA NC DP IG C CTRL DATA MAKE_BASE=TRUE NO_TEST=TRUE
MEM_B_CKE<2..3> NC_MEM_B_CKE<2..3> 19 TP PCH RESERVE 1 NC PCH RESERVE 1
88 12
18 TP_PCH_CLKOUT_DPP NC_PCH_CLKOUT_DPP MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE PCH PCI
C 18 PCH_CLK25M_XTALOUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_CLK25M_XTALOUT
NO_TEST=TRUE
19 DP_IG_D_MLN<3..0> NC_DP_IG_D_MLN<3..0>
19 TP_PCH_RESERVE_2 NC_PCH_RESERVE_2
C
88 12 MEM_A_ODT<2..3> NC_MEM A_ODT<2..3> TP_PCH_RESERVE_3 NC_PCH RESERVE_3 TP_PCI_AD<31..0> NC_PCI_AD<31..0>
19 20
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP IG D MLP<3..0> NC DP IG D MLP<3..0> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
88 12 MEM B ODT<2..3> NC MEM B ODT<2..3> MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO64_CLKOUTFLEX0 19 TP_PCH_RESERVE_4 NC_PCH_RESERVE_4 20 TP_PCI_C_BE_L<3..0> NC_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_D_AUXN NC_DP_IG_D_AUXN MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO65_CLKOUTFLEX1 19 TP_PCH_RESERVE_5 NC_PCH RESERVE_5 20 TP_PCI_PAR NC_PCI_PAR
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_D_AUXP NC_DP_IG_D_AUXP MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCH_GPIO66_CLKOUTFLEX2 NC_PCH GPIO66_CLKOUTFLEX2 19 TP_PCH_RESERVE_6 NC_PCH_RESERVE_6 20 TP_PCI_RESET_L NC_PCI RESET_L
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_D_HPD NC_DP_IG_D_HPD MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 TP_PCH_GPIO67_CLKOUTFLEX3 NC_PCH GPIO67_CLKOUTFLEX3 19 TP_PCH_RESERVE_7 NC_PCH_RESERVE_7
MAKE_BASE=TRUE NO_TEST=TRUE 19 DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_CLK MAKE_BASE=TRUE NO_TEST=TRUE
19 TP PCH RESERVE 8 NC PCH RESERVE 8 19 TP PCH INIT3V3 L NC PCH INIT3V3 L
19 DP_IG_D_CTRL_DATA NC_DP_IG_D_CTRL_DATA MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
PCH USB 19 TP_PCH_RESERVE_9 NC_PCH_RESERVE_9
18 TP_LPC_DREQ0_L NC_LPC_DREQ0_L
20 USB_PCH_4_N NC_USB PCH_4_N 19 TP_SDVO_TVCLKINN NC_SDVO_TVCLKINN MAKE_BASE=TRUE NO_TEST=TRUE
19 TP_PCH_RESERVE_11 NC_PCH RESERVE_11
20 USB_PCH_4_P NC_USB PCH_4_P 19 TP_SDVO_TVCLKINP NC_SDVO_TVCLKINP MAKE_BASE=TRUE NO_TEST=TRUE
20 USB_PCH_5_N NC_USB_PCH_5_N PCH and CPU FDI 19 TP_SDVO_STALLN NC_SDVO_STALLN
MAKE_BASE=TRUE NO_TEST=TRUE PCH Miscellaneous
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_PCH_RESERVE_13 NC_PCH_RESERVE_13
19 TP_SDVO_STALLP NC_SDVO_STALLP MAKE_BASE=TRUE NO_TEST=TRUE
20 USB_PCH_5_P NC_USB PCH_5_P MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_HDA_SDIN1 NC_HDA_SDIN1
MAKE_BASE=TRUE NO_TEST=TRUE 91 10 CPU_FDI_TX_N<7..0> NC_CPU FDI_TXN<7..0> 19 TP_PCH_RESERVE_14 NC_PCH_RESERVE_14 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_SDVO_INTN NC_SDVO_INTN MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_HDA_SDIN2 NC_HDA_SDIN2
91 10 CPU_FDI_TX_P<7..0> NC_CPU_FDI_TXP<7..0> 19 TP_PCH_RESERVE_15 NC_PCH RESERVE_15 MAKE_BASE=TRUE NO_TEST=TRUE
20 USB_PCH_6_N NC_USB_PCH_6_N MAKE_BASE=TRUE NO_TEST=TRUE 19 TP_SDVO_INTP NC_SDVO_INTP MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP HDA SDIN3 NC HDA SDIN3
19 PCH_FDI_RX_N<7..0> NC_PCH_FDI_RXN<7..0> 19 TP_PCH_RESERVE_16 NC_PCH RESERVE_16 MAKE_BASE=TRUE NO_TEST=TRUE
20 USB_PCH_6_P NC_USB_PCH_6_P MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
19 PCH_FDI_RX_P<7..0> NC_PCH_FDI_RXP<7..0> 19 TP_PCH_RESERVE_17 NC_PCH RESERVE_17 21 TP_PCH_PWM0 NC_PCH PWM0
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_L_BKLTCTL NC_PCH_L_BKLTCTL MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
20 USB PCH 11 N NC USB PCH 11 N 19 TP PCH RESERVE 18 NC PCH RESERVE 18 21 TP PCH PWM1 NC PCH PWM1
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_L_BKLTEN NC_PCH L_BKLTEN MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
20 USB_PCH_11_P NC_USB PCH_11_P 91 10 CPU_FDI_FSYNC<1..0> NC_CPU FDI_FSYNC<1..0> 19 TP_PCH_RESERVE_19 NC_PCH_RESERVE_19 21 TP_PCH_PWM2 NC_PCH_PWM2
B MAKE_BASE=TRUE NO_TEST=TRUE
91 10 CPU_FDI_LSYNC<1..0>
NC_CPU_FDI_LSYNC<1..0>
18 TP_PCH_L_VDD_EN NC_PCH_L_VDD_EN
19 TP_PCH_RESERVE_20
MAKE_BASE=TRUE
NC_PCH RESERVE_20
NO_TEST=TRUE
21 TP_PCH_PWM3
MAKE_BASE=TRUE
NC_PCH PWM3
NO_TEST=TRUE
B
20 USB_PCH_12_N NC_USB_PCH_12_N
MAKE_BASE=TRUE NO_TEST=TRUE 91 10 CPU FDI INT NC CPU FDI INT 19 TP PCH RESERVE 21 NC PCH RESERVE 21 21 TP PCH SST NC PCH SST
20 USB_PCH_12_P NC_USB PCH_12_P
MAKE_BASE=TRUE NO_TEST=TRUE UNUSED GRAPHICS ALIASES 19 TP_PCH_RESERVE_22 NC_PCH_RESERVE_22
MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_CL_CLK1 NC_PCH CL CLK1
19 PCH_FDI_FSYNC<1..0> NC_PCH_FDI_FSYNC<1..0> 19 TP_PCH_RESERVE_23 NC_PCH RESERVE_23
20 USB PCH 13 N NC USB PCH 13 N MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP PCH CL DATA1 NC PCH CL DATA1
19 PCH FDI LSYNC<1..0> NC PCH FDI LSYNC<1..0> TP DVPCNTL M<0..1> NC DVPCNTL M<0..1> 19 TP PCH RESERVE 24 NC PCH RESERVE 24
20 USB_PCH_13_P NC_USB PCH_13_P MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 TP_PCH_CL_RST1 NC_PCH CL RST1
19 PCH_FDI_INT NC_PCH FDI_INT TP_DVPCNTL<0..2> NC_DVPCNTL<0..2> 19 TP_PCH_RESERVE_25 NC_PCH_RESERVE_25
TP_DVPCLK NC_DVPCLK 19 TP_PCH_RESERVE_26 NC_PCH_RESERVE_26 20 TP_PCI_CLK33M_OUT2 NC_PCI CLK33M_OUT2
TP_DVPDATA<4..23> NC_DVPDATA<4..23> 19 TP_PCH_RESERVE_27 NC_PCH_RESERVE_27 20 TP_PCI_CLK33M_OUT3 NC_PCI CLK33M_OUT3
19 TP PCH RESERVE 28 NC PCH RESERVE 28 21 TP PCH GPIO8 NC PCH GPIO8
HDMI_EG_CLK_C_P NC_HDMI_EG_CLK_C_P MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
HDMI EG CLK C N NC HDMI EG CLK C N
MAKE_BASE=TRUE NO_TEST=TRUE 22 PP1V05_S0_PCH_FDIPLL NC_PP1V05 S0_PCH_FDIPLL
HDMI_EG_DDC_CLK NC_HDMI_EG_DDC_CLK
MAKE_BASE=TRUE NO_TEST=TRUE 22 PP1V05_S0_PCH_VCC_A_CLK NC_PP1V05_S0_PCH_VCC_A_CLK
HDMI_EG_DDC_DATA NC_HDMI_EG_DDC_DATA
MAKE_BASE=TRUE NO_TEST=TRUE 22 TP PPVOUT PCH DCPSUSBYP NC PPVOUT PCH DCPSUSBYP
HDMI_EG_DATA_C_P<0..2> NC_HDMI_EG_DATA_C P<0..2>
PCH PLL HDMI_EG_DATA_C_N<0..2> NC_HDMI EG_DATA_C N<0..2>
22 PP1V05_S0_PCH_VCCAPLLDMI2 NC_PP1V05_S0_PCH_VCCAPLLDMI2
MAKE_BASE=TRUE NO_TEST=TRUE 77 GPU TDIODE P NC GPU TDIODE P
22 PP1V05_S0_PCH_VCCAPLL_EXP NC_PP1V05 S0_PCH_VCCAPLL_EXP 77 GPU_TDIODE_N NC_GPU_TDIODE_N
A 22 PP1V05 S0 PCH VCCAPLL SATA NC PP1V05 S0 PCH VCCAPLL SATA

78 EG LCD PWR EN NC EG LCD PWR EN
SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A
PAGE TITLE
Unused Signal Aliases

DRAWING NUMBER SIZE

REVISION
R
4.2.0
8 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Whistler aliases
89 71 PEG_D2R_N<0..15> =PEG_D2R_N<15..0> 10
MAKE_BASE=TRUE
89 71 PEG_D2R_P<0..15> =PEG_D2R_P<15..0> 10
MAKE_BASE=TRUE
89 71 PEG R2D C N<0..15> =PEG R2D C N<15..0> 10
MAKE_BASE=TRUE
89 71 PEG_R2D_C_P<0..15> =PEG_R2D_C_P<15..0> 10
MAKE_BASE=TRUE
C C
B B

PAGE TITLE
Signal Aliases
DRAWING NUMBER SIZE

REVISION
R
4.2.0
9 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SHORT B4 & C4 TOGETHER ROUTE AS A SINGLE 4 MIL TRACE TO R1010 1
ROUTE B5 TO R1010 1 AS A SEPERATE 10 MIL TRACE
OMIT_TABLE
=PPVCCIO S0 CPU
90 19 IN DMI_S2N_N<0> W4 DMI_RX_0* OMIT_TABLE PEG_COMPI B4
PLACE NEAR=U1000 B4 12 7mm 6 10 11 13 16 62
U1000
90 19 IN DMI_S2N_N<1> V4 DMI_RX_1* U1000 PEG_ICOMPO B5 R1010 IVY-BRIDGE
24.9 2 BGA-SKT-K70
90 19 IN DMI_S2N_N<2> Y4 DMI_RX_2* IVY-BRIDGE PEG_RCOMPO C4 89 CPU_PEG_COMP 1
90 19 DMI S2N N<3> AA5 DMI_RX_3* BGA-SKT-K70 1% SYM 5 OF 10
IN 1/16W
SYM 1 OF 10 C38 P35
MF-LF 8 TP_CPU_RSVD<1> RSVD_C38 RSVD_P35 TP_CPU_RSVD<20> 8
90 19 IN DMI_S2N_P<0> W5 DMI_RX_0 PEG_RX_0* B12 =PEG_D2R_N<0> IN 9 402
8 TP_CPU_RSVD<2> C39 RSVD_C39 RSVD_P37 P37 TP_CPU_RSVD<21> 8
90 19 DMI_S2N_P<1> V3 DMI_RX_1 PEG_RX_1* D11 =PEG_D2R_N<1> 9
IN IN TP_CPU_RSVD<3> D38 P39 TP_CPU_RSVD<22>
Y3 C9 8 RSVD_D38 RSVD_P39 8
90 19 DMI S2N P<2> DMI_RX_2 PEG_RX_2* =PEG D2R N<2> 9
D 90 19
IN
IN DMI S2N P<3> AA4 DMI_RX_3 PEG_RX_3* E9
B7
=PEG D2R N<3>
IN
IN 9
8
8
TP_CPU_RSVD<4>
TP_CPU_RSVD<5>
H7
H8
RSVD_H7
RSVD_H8
RSVD_R34
RSVD_R36
R34
R36
TP_CPU_RSVD<23>
TP_CPU_RSVD<24>
8
8
D
PEG_RX_4* =PEG_D2R_N<4> IN 9
DMI_N2S_N<0> V6 DMI_TX_0* TP_CPU_RSVD<6> J9 RSVD_J9 RSVD_R38 R38 TP_CPU_RSVD<25>
DMI
90 19 OUT 8 8
PEG_RX_5* C5 =PEG_D2R_N<5> IN 9
90 19 DMI N2S N<1> W8 DMI_TX_1* 8 TP CPU RSVD<7> J31 RSVD_J31 RSVD_R40 R40 TP CPU RSVD<26> 8
OUT A6 =PEG_D2R_N<6>
Y7 PEG_RX_6* IN 9
J33 AB6
90 19 OUT DMI N2S N<2> DMI_TX_2* 8 TP CPU RSVD<8> RSVD_J33 RSVD_AB6 TP CPU RSVD<27> 8
PEG_RX_7* E1 =PEG_D2R_N<7> 9
DMI N2S N<3> AA8 IN TP CPU RSVD<9> J34 AB7 TP CPU RSVD<28>
90 19 OUT DMI_TX_3* F3 8 RSVD_J34 RSVD_AB7 8
PEG_RX_8* =PEG_D2R_N<8> IN 9
8 TP_CPU_RSVD<10> K9 RSVD_K9 RSVD_AD34 AD34 TP_CPU_RSVD<29> 8
90 19 DMI_N2S_P<0> V7 DMI_TX_0 PEG_RX_9* G1 =PEG_D2R_N<9> 9
OUT IN TP_CPU_RSVD<11> K31 AD35 TP_CPU_RSVD<30>
W7 H4 8 RSVD_K31 RSVD_AD35 8
90 19 OUT DMI N2S P<1> DMI_TX_1 PEG_RX_10* =PEG D2R N<10> IN 9
8 TP_CPU_RSVD<12> K34 RSVD_K34 RSVD_AD37 AD37 TP_CPU_RSVD<31> 8
RESERVED
90 19 DMI N2S P<2> Y6 DMI_TX_2 PEG_RX_11* J2 =PEG D2R N<11> 9
OUT IN TP_CPU_RSVD<13> L9 AE6 TP_CPU_RSVD<32>
AA7 K4 8 RSVD_L9 RSVD_AE6 8
90 19 OUT DMI_N2S_P<3> DMI_TX_3 PEG_RX_12* =PEG_D2R_N<12> IN 9
8 TP_CPU_RSVD<14> L31 RSVD_L31 RSVD_AF4 AF4 TP_CPU_RSVD<33> 8
PEG_RX_13* L2 =PEG_D2R_N<13> IN 9
8 TP CPU RSVD<15> L33 RSVD_L33 RSVD_AG4 AG4 TP CPU RSVD<34> 8
91 8 CPU_FDI_TX_N<0> AC7 FDI_TX_0* PEG_RX_14* M4 =PEG_D2R_N<14> IN 9
8 TP CPU RSVD<16> L34 RSVD_L34 RSVD_AJ11 AJ11 TP CPU RSVD<35> 8
91 8 CPU_FDI_TX_N<1> AC3 FDI_TX_1* PEG_RX_15* N2 =PEG_D2R_N<15> IN 9
NC SNS CPU THERMDN M34 RSVD_M34 ThermDC RSVD_AJ29 AJ29 TP CPU RSVD<36> 8
91 8 CPU_FDI_TX_N<2> AD1 FDI_TX_2* NO_TEST=TRUE
PEG_RX_0 B11 =PEG_D2R_P<0> IN 9 NC_SNS_CPU_THERMDP N33 RSVD_N33 ThermDA RSVD_AJ30 AJ30 TP_CPU_RSVD<37> 8
CPU_FDI_TX_N<3> AD3 FDI_TX_3* NO_TEST=TRUE
FLEXIBLE DISPLAY INTERFACE

91 8
PEG_RX_1 D12 =PEG_D2R_P<1> IN 9 8 TP_CPU_RSVD<19> N34 RSVD_N34 RSVD_AJ31 AJ31 TP_CPU_RSVD<38> 8
91 8 CPU FDI TX N<4> AD6 FDI_TX_4*
PEG_RX_2 C10 =PEG_D2R_P<2> IN 9 RSVD_AN20 AN20 TP_CPU_RSVD<39> 8
91 8 CPU FDI TX N<5> AE8 FDI_TX_5*
PEG_RX_3 E10 =PEG_D2R_P<3> IN 9 91 25 IN CPU_CFG<0> H36 CFG_0 RSVD_AP20 AP20 TP_CPU_RSVD<40> 8
91 8 CPU_FDI_TX_N<6> AF2 FDI_TX_6*
PEG_RX_4 B8 =PEG_D2R_P<4> IN 9 91 25 IN CPU_CFG<1> J36 CFG_1 RSVD_AT11 AT11 TP_CPU_RSVD<41> 8
91 8 CPU_FDI_TX_N<7> AG1 FDI_TX_7*
PEG_RX_5 C6 =PEG_D2R_P<5> IN 9 91 25 15 IN CPU_CFG<2> J37 CFG_2 RSVD_AT14 AT14 TP_CPU_RSVD<42> 8
91 8 CPU FDI TX P<0> AC8 FDI_TX_0 PEG_RX_6 A5 =PEG D2R P<6> IN 9 91 25 15 IN CPU CFG<3> K36 CFG_3 RSVD_AU10 AU10 TP CPU RSVD<43> 8
(Unused)
91 8 CPU FDI TX P<1> AC2 FDI_TX_1 PEG_RX_7 E2 =PEG D2R P<7> IN 9 91 25 IN CPU CFG<4> L36 CFG_4 RSVD_AV34 AV34 TP CPU RSVD<44> 8
91 8 CPU_FDI_TX_P<2> AD2 FDI_TX_2 PEG_RX_8 F4 =PEG_D2R_P<8> IN 9 91 25 15 IN CPU_CFG<5> N35 CFG_5 RSVD_AW34 AW34 TP_CPU_RSVD<45> 8
PCI EXPRESS -- GRAPHICS

91 8 CPU_FDI_TX_P<3> AD4 FDI_TX_3 PEG_RX_9 G2 =PEG_D2R_P<9> IN 9 91 25 15 IN CPU_CFG<6> L37 CFG_6 RSVD_AY10 AY10 TP_CPU_RSVD<46> 8
91 8 CPU_FDI_TX_P<4> AD7 FDI_TX_4 PEG_RX_10 H3 =PEG_D2R_P<10> IN 9 91 25 IN CPU_CFG<7> M36 CFG_7

AE7 J1 J38 RSVD_NCTF_AV1 AV1 TP CPU RSVD NCTF<1>
91 8 CPU_FDI_TX_P<5> FDI_TX_5 PEG_RX_11 =PEG_D2R_P<11> IN 9 91 25 IN CPU_CFG<8> CFG_8
AF3 K3 L35 RSVD_NCTF_AW2 AW2 TP CPU RSVD NCTF<2>
91 8 CPU_FDI_TX_P<6> FDI_TX_6 PEG_RX_12 =PEG_D2R_P<12> IN 9 91 25 IN CPU_CFG<9> CFG_9
RSVD_NCTF_AY3 AY3
C 11 10 6
62 16 13
=PPVCCIO_S0_CPU
91 8 CPU_FDI_TX_P<7> AG2 FDI_TX_7 PEG_RX_13
PEG_RX_14
L1
M3
=PEG_D2R_P<13>
=PEG D2R P<14>
IN 9
9
91 25
91 25
IN CPU_CFG<10>
CPU CFG<11>
M38
N36
CFG_10
CFG_11
RSVD_NCTF_B39 B39
TP_CPU_RSVD_NCTF<3>
TP_CPU_RSVD_NCTF<4> C
CPU_FDI_FSYNC<0> AC5 FDI_FSYNC_0 IN IN
91 8
PEG_RX_15 N1 =PEG D2R P<15> IN 9 91 8 IN CPU CFG<12> N38 CFG_12 NCTF_A38 A38 TP CPU NCTF<1>
91 8 CPU_FDI_FSYNC<1> AE5 FDI_FSYNC_1
91 8 IN CPU_CFG<13> N39 CFG_13 NCTF_C2 C2 TP_CPU_NCTF<2>
C14
R10111 91 8 CPU_FDI_INT AG3 FDI_INT PEG_TX_0* =PEG_R2D_C_N<0> OUT 9
91 8 IN CPU_CFG<14> N37 CFG_14 NCTF_D1 D1 TP_CPU_NCTF<3>
24.9 PEG_TX_1* E13 =PEG_R2D_C_N<1> OUT 9
1% 91 8 IN CPU_CFG<15> N40 CFG_15 NCTF_AU40 AU40 TP_CPU_NCTF<4>
1/16W 91 8 CPU FDI LSYNC<0> AC4 FDI_LSYNC_0 PEG_TX_2* G13 =PEG R2D C N<2> OUT 9
MF-LF 91 25 IN CPU_CFG<16> G37 CFG_16 NCTF_AW38 AW38 TP_CPU_NCTF<5>
402 2 91 8 CPU_FDI_LSYNC<1> AE4 FDI_LSYNC_1 PEG_TX_3* F11 =PEG_R2D_C_N<3> OUT 9
91 25 IN CPU_CFG<17> G36 CFG_17
PEG_TX_4* J13 =PEG_R2D_C_N<4> OUT 9 INTEL SUGGESTS TO KEEP THESE TPS
91 CPU_FDI_COMPIO AE2 FDI_COMPIO
PEG_TX_5* D7 =PEG_R2D_C_N<5> OUT 9
AE1 FDI_ICOMPO
PEG_TX_6* C3 =PEG_R2D_C_N<6> OUT 9
PEG_TX_7* E5 =PEG_R2D_C_N<7> 9
TP_PE_RX_N<0> P4 OUT
8 PE_RX_0* F7
PEG_TX_8* =PEG_R2D_C_N<8> OUT 9
8 TP_PE_RX_N<1> R1 PE_RX_1*
PEG_TX_9* G9 =PEG_R2D_C_N<9> OUT 9
(Available for Workstation only)
8 TP_PE_RX_N<2> T3 PE_RX_2*
PEG_TX_10* G6 =PEG_R2D_C_N<10> OUT 9
8 TP_PE_RX_N<3> U1 PE_RX_3*
PEG_TX_11* K8 =PEG_R2D_C_N<11> OUT 9
8 TP_PE_RX_P<0> P3 PE_RX_0 PEG_TX_12* J6 =PEG_R2D_C_N<12> OUT 9

PCI EXPRESS
8 TP_PE_RX_P<1> R2 PE_RX_1 PEG_TX_13* M7 =PEG_R2D_C_N<13> OUT 9
TP_PE_RX_P<2> T4 L5 =PEG_R2D_C_N<14>
CFG[1:0] Reserved config lane
8 PE_RX_2 PEG_TX_14* OUT 9
TP_PE_RX_P<3> U2 N6 =PEG_R2D_C_N<15>
CFG[2] PCIe Static x16 lane reversal; Refer to page 15 for more info
8 PE_RX_3 PEG_TX_15* OUT 9
CFG[3] PCIe Static x4 lane reversal; Refer to page 15 for more info
8 TP_PE_TX_N<0> P7 PE_TX_0* PEG_TX_0 C13 =PEG_R2D_C_P<0> OUT 9 CFG[4] Reserved config lane
8 TP_PE_TX_N<1> T8 PE_TX_1* PEG_TX_1 E14 =PEG_R2D_C_P<1> OUT 9 CFG[6:5] PCIe bifurcation; Refer to page 15 for more info
8 TP_PE_TX_N<2> R5 PE_TX_2* PEG_TX_2 G14 =PEG_R2D_C_P<2> OUT 9 CFG[17:7] Reserved config lanes
8 TP_PE_TX_N<3> U6 PE_TX_3* PEG_TX_3 F12 =PEG_R2D_C_P<3> OUT 9
PEG_TX_4 J14 =PEG R2D C P<4> OUT 9

8 TP_PE_TX_P<0> P8 PE_TX_0
PEG_TX_5 D8 =PEG_R2D_C_P<5> OUT 9
8 TP_PE_TX_P<1> T7 PE_TX_1
B 8 TP_PE_TX_P<2> R6
U5
PE_TX_2
PEG_TX_6
PEG_TX_7
D3
E6
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
OUT
OUT
9
9
B
8 TP PE TX P<3> PE_TX_3
PEG_TX_8 F8 =PEG_R2D_C_P<8> OUT 9
PEG_TX_9 G10 =PEG_R2D_C_P<9> OUT 9
PEG_TX_10 G5 =PEG_R2D_C_P<10> OUT 9
PEG_TX_11 K7 =PEG R2D C P<11> OUT 9
PEG_TX_12 J5 =PEG R2D C P<12> OUT 9
PEG_TX_13 M8 =PEG R2D C P<13> OUT 9
PEG_TX_14 L6 =PEG_R2D_C_P<14> OUT 9
PEG_TX_15 N5 =PEG_R2D_C_P<15> OUT 9

PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE

REVISION
R
4.2.0
10 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
62 16 13 11 10 6 =PPVCCIO_S0_CPU
R11011 OMIT_TABLE
51
5%
1/16W U1000
MF-LF IVY-BRIDGE
402 2
BGA-SKT-K70
SYM 2 OF 10
CLOCKS
BASED ON INTEL MOBILE SOLUTION BCLK_ITP C40 ITPCPU_CLK100M_P IN 15 91
60 OUT CPU SKTOCC L AJ33 SKTOCC*
BCLK_ITP* D40 ITPCPU_CLK100M_N IN 15 91
=PPVCCIO S0 CPU 19 OUT CPU_PROC_SEL K32 PROC_SEL

62 16 13 11 10 6
BCLK_0 W2 DMI_CLK100M_CPU_P IN 18 90
BCLK_0* W1 DMI_CLK100M_CPU_N IN 18 90
45 OUT CPU_CATERR_L E37 CATERR*

PLACE NEAR=U1000 F36 50mm
PRDY* K38 XDP_CPU_PRDY_L
THERMAL
OUT 25
R11241 45 44 21 BI CPU_PECI J35 PECI PREQ* K40 XDP_CPU_PREQ_L IN 25
75
5%
1/16W 0 R1102
1 1/16W
MF-LF 62 45 44 BI CPU PROCHOT L 2 CPU PROCHOT R L H34 PROCHOT* TCK M40 XDP CPU TCK IN 25 91
402 2 MF-LF 5% 402 TMS L38 XDP CPU TMS IN 25 91
45 OUT CPU_THRMTRIP_L G35 THERMTRIP* TRST* J39 XDP_CPU_TRST_L IN 25
R1125 TDI L40 XDP_CPU_TDI
JTAG & BPM

PWR MGMT
IN 25 91
CPU_RESET_L 43 PLT_RESET_LS1V05_L F36 RESET* XDP_CPU_TDO

26 IN
2 1 TDO L39 OUT 25 91
5%
C 1/16W
MF-LF
402
19 IN PM_SYNC E38 PM_SYNC DBR* E39 XDP_DBRESET_L OUT 25 C
25 21 IN CPU_PWRGD J40 UNCOREPWRGOOD
BPM[0]* H40 XDP BPM L<0> BI 25 91
BPM[1]* H38 XDP_BPM_L<1> BI 25 91
PM_MEM_PWRGD_R AJ19 SM_DRAMPWROK BPM[2]* G38 XDP_BPM_L<2>
DDR3 MISC
BI 25 91
BPM[3]* G40 XDP_BPM_L<3> BI 25 91

=PP1V5_S0_CPU_MEM 28 OUT CPU MEM RESET L AW18 SM_DRAMRST*
16 13 11 6
BPM[4]* G39 XDP_BPM_L<4> BI 25 91
97 11 CPU_DDR_VREF AJ22 SM_VREF BPM[5]* F38 XDP_BPM_L<5> BI 25 91
R11201 BPM[6]* E40 XDP_BPM_L<6> BI 25 91

200 97 32 OUT CPU DIMM VREF DAC B AH1 SB_DIMM_VREFDQ BPM[7]* F40 XDP BPM L<7> BI 25 91
1%
FROM PCH 1/16W 97 32 CPU_DIMM_VREF_DAC_A AH4 SA_DIMM_VREFDQ
MF-LF OUT
402 2 R1121
130
28 19 IN PM_MEM_PWRGD 2 1
1%
1/16W
MF-LF
402
1
R1111
1K
5%
1/16W
MF-LF
2 402
16 13 11 6 =PP1V5_S0_CPU_MEM
B B
1
R1140
1K
1%
1/16W
MF-LF
2 402
CPU_DDR_VREF 11 97
1
R1141 1 C1140
1K 0.1UF
1% 10%
1/16W
MF-LF 2 16V
X7R-CERM
2 402 402

PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

REVISION
R
4.2.0
11 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE OMIT_TABLE
U1000 U1000
IVY-BRIDGE IVY-BRIDGE
BGA-SKT-K70 BGA-SKT-K70
88 31 MEM A DQ<0> AJ3 SA_DQ_0 SYM 3 OF 10 SA_CK_0 AY25 MEM A CLK P<0> 29 88 88 31 MEM B DQ<0> AG7 SB_DQ_0 SYM 4 OF 10 SB_CK_0 AL21 MEM B CLK P<0> 30 88
BI OUT BI OUT
88 31 BI MEM_A_DQ<1> AJ4 SA_DQ_1 SA_CK_0* AW25 MEM_A_CLK_N<0> OUT 29 88 88 31 BI MEM_B_DQ<1> AG8 SB_DQ_1 SB_CK_0* AL22 MEM_B_CLK_N<0> OUT 30 88
88 31 MEM_A_DQ<2> AL3 SA_DQ_2 88 31 MEM_B_DQ<2> AJ9 SB_DQ_2

BI BI
AL4 SA_CKE_0 AV19 MEM_A_CKE<0> OUT 29 88
AJ8 SB_CKE_0 AU16 MEM_B_CKE<0> OUT 30 88
88 31 BI MEM_A_DQ<3> SA_DQ_3 88 31 BI MEM_B_DQ<3> SB_DQ_3
D 88 31
88 31
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AJ2
AJ1
SA_DQ_4
SA_DQ_5
SA_CK_1 AU24
SA_CK_1* AU25
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
OUT
29 88
29 88
88 31
88 31
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AG5
AG6
SB_DQ_4
SB_DQ_5
SB_CK_1 AL20
SB_CK_1* AK20
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
OUT
30 88
30 88
D
88 31 BI MEM_A_DQ<6> AL2 SA_DQ_6 88 31 BI MEM_B_DQ<6> AJ6 SB_DQ_6
AL1 SA_CKE_1 AT19 MEM_A_CKE<1> OUT 29 88
AJ7 SB_CKE_1 AY15 MEM_B_CKE<1> OUT 30 88
88 31 BI MEM A DQ<7> SA_DQ_7 88 31 BI MEM B DQ<7> SB_DQ_7
DDR SYSTEM MEMORY A

88 31 MEM A DQ<8> AN1 SA_DQ_8 SA_CK_2 AW27 MEM A CLK P<2> 8 88 88 31 MEM B DQ<8> AL7 SB_DQ_8 SB_CK_2 AL23 MEM B CLK P<2> 8 88
BI OUT BI OUT
DDR SYSTEM MEMORY B

88 31 MEM A DQ<9> AN4 SA_DQ_9 SA_CK_2* AY27 MEM A CLK N<2> 8 88 88 31 MEM B DQ<9> AM7 SB_DQ_9 SB_CK_2* AM22 MEM B CLK N<2> 8 88
BI OUT BI OUT
88 31 BI MEM_A_DQ<10> AR3 SA_DQ_10 88 31 BI MEM_B_DQ<10> AM10 SB_DQ_10
AR4 SA_CKE_2 AU18 MEM_A_CKE<2> OUT 8 88
AL10 SB_CKE_2 AW15 MEM_B_CKE<2> OUT 8 88
88 31 BI MEM_A_DQ<12> AN2 SA_DQ_12 SA_CK_3 AV26 MEM_A_CLK_P<3> OUT 8 88 88 31 BI MEM_B_DQ<12> AL6 SB_DQ_12 SB_CK_3 AP21 MEM_B_CLK_P<3> OUT 8 88
88 31 BI MEM_A_DQ<13> AN3 SA_DQ_13 SA_CK_3* AW26 MEM_A_CLK_N<3> OUT 8 88 88 31 BI MEM_B_DQ<13> AM6 SB_DQ_13 SB_CK_3* AN21 MEM_B_CLK_N<3> OUT 8 88
88 31 MEM_A_DQ<14> AR2 SA_DQ_14 88 31 MEM_B_DQ<14> AL9 SB_DQ_14

BI BI
AR1 SA_CKE_3 AV18 MEM_A_CKE<3> OUT 8 88
AM9 SB_CKE_3 AV15 MEM_B_CKE<3> OUT 8 88
88 31 MEM A DQ<16> AV2 SA_DQ_16 SA_CS_0* AU29 MEM A CS L<0> 29 88 88 31 MEM B DQ<16> AP7 SB_DQ_16 SB_CS_0* AN25 MEM B CS L<0> 30 88
BI OUT BI OUT
88 31 MEM A DQ<17> AW3 SA_DQ_17 SA_CS_1* AV32 MEM A CS L<1> 29 88 88 31 MEM B DQ<17> AR7 SB_DQ_17 SB_CS_1* AN26 MEM B CS L<1> 30 88
BI OUT BI OUT
88 31 MEM_A_DQ<18> AV5 SA_DQ_18 SA_CS_2* AW30 MEM_A_CS_L<2> 8 88 88 31 MEM_B_DQ<18> AP10 SB_DQ_18 SB_CS_2* AL25 MEM_B_CS_L<2> 8 88
BI OUT BI OUT
88 31 MEM_A_DQ<19> AW5 SA_DQ_19 SA_CS_3* AU33 MEM_A_CS_L<3> 8 88 88 31 MEM_B_DQ<19> AR10 SB_DQ_19 SB_CS_3* AT26 MEM_B_CS_L<3> 8 88
BI OUT BI OUT
88 31 MEM_A_DQ<20> AU2 SA_DQ_20 88 31 MEM_B_DQ<20> AP6 SB_DQ_20
BI BI
88 31 MEM_A_DQ<21> AU3 SA_DQ_21 SA_ODT_0 AV31 MEM_A_ODT<0> 29 88 88 31 MEM_B_DQ<21> AR6 SB_DQ_21 SB_ODT_0 AL26 MEM_B_ODT<0> 30 88
BI OUT BI OUT
88 31 MEM_A_DQ<22> AU5 SA_DQ_22 SA_ODT_1 AU32 MEM_A_ODT<1> 29 88 88 31 MEM_B_DQ<22> AP9 SB_DQ_22 SB_ODT_1 AP26 MEM_B_ODT<1> 30 88
BI OUT BI OUT
88 31 MEM_A_DQ<23> AY5 SA_DQ_23 SA_ODT_2 AU30 MEM_A_ODT<2> 8 88 88 31 MEM_B_DQ<23> AR9 SB_DQ_23 SB_ODT_2 AM26 MEM_B_ODT<2> 8 88
BI OUT BI OUT
88 31 MEM A DQ<24> AY7 SA_DQ_24 SA_ODT_3 AW33 MEM A ODT<3> 8 88 88 31 MEM B DQ<24> AM12 SB_DQ_24 SB_ODT_3 AK26 MEM B ODT<3> 8 88
BI OUT BI OUT
88 31 MEM A DQ<25> AU7 SA_DQ_25 88 31 MEM B DQ<25> AM13 SB_DQ_25
BI BI
88 31 BI MEM_A_DQ<26> AV9 SA_DQ_26 SA_DQS_0* AK2 MEM_A_DQS_N<0> BI 31 88 88 31 BI MEM_B_DQ<26> AR13 SB_DQ_26 SB_DQS_0* AH6 MEM_B_DQS_N<0> BI 31 88
88 31 MEM_A_DQ<27> AU9 SA_DQ_27 SA_DQS_1* AP2 MEM_A_DQS_N<1> 31 88 88 31 MEM_B_DQ<27> AP13 SB_DQ_27 SB_DQS_1* AL8 MEM_B_DQS_N<1> 31 88
BI BI BI BI
88 31 MEM_A_DQ<28> AV7 SA_DQ_28 SA_DQS_2* AV4 MEM_A_DQS_N<2> 31 88 88 31 MEM_B_DQ<28> AL12 SB_DQ_28 SB_DQS_2* AP8 MEM_B_DQS_N<2> 31 88
BI BI BI BI
88 31 MEM_A_DQ<29> AW7 SA_DQ_29 SA_DQS_3* AW8 MEM_A_DQS_N<3> 31 88 88 31 MEM_B_DQ<29> AL13 SB_DQ_29 SB_DQS_3* AN12 MEM_B_DQS_N<3> 31 88
BI BI BI BI
88 31 MEM_A_DQ<30> AW9 SA_DQ_30 SA_DQS_4* AV36 MEM_A_DQS_N<4> 31 88 88 31 MEM_B_DQ<30> AR12 SB_DQ_30 SB_DQS_4* AN28 MEM_B_DQS_N<4> 31 88
BI BI BI BI
C 88 31
88 31
BI MEM_A_DQ<31>
MEM A DQ<32>
AY9
AU35
SA_DQ_31
SA_DQ_32
SA_DQS_5*
SA_DQS_6*
AP39
AK39
MEM_A_DQS_N<5>
MEM A DQS N<6>
BI 31 88
31 88
88 31
88 31
BI MEM_B_DQ<31>
MEM B DQ<32>
AP12
AR28
SB_DQ_31
SB_DQ_32
SB_DQS_5*
SB_DQS_6*
AR33
AM33
MEM_B_DQS_N<5>
MEM B DQS N<6>
BI 31 88
31 88
C
BI BI BI BI
88 31 MEM A DQ<33> AW37 SA_DQ_33 SA_DQS_7* AF39 MEM A DQS N<7> 31 88 88 31 MEM B DQ<33> AR29 SB_DQ_33 SB_DQS_7* AG34 MEM B DQS N<7> 31 88
BI BI BI BI
88 31 BI MEM_A_DQ<34> AU39 SA_DQ_34 SA_DQS_8* AV12 TP_MEM_A_DQS_N<8> 8 88 31 BI MEM_B_DQ<34> AL28 SB_DQ_34 SB_DQS_8* AN15 TP_MEM_B_DQS_N<8> 8
88 31 MEM_A_DQ<35> AU36 SA_DQ_35 88 31 MEM_B_DQ<35> AL29 SB_DQ_35

BI AK3 MEM_A_DQS_P<0> BI AH7 MEM_B_DQS_P<0>
AW35 SA_DQS_0 BI 31 88
AP28 SB_DQS_0 BI 31 88
SA_DQS_1 AP3 MEM A DQS P<1> 31 88 SB_DQS_1 AM8 MEM B DQS P<1> 31 88
MEM_A_DQ<37> AY36 BI MEM_B_DQ<37> AP29 BI
88 31 BI SA_DQ_37 AW4 88 31 BI SB_DQ_37 AR8
SA_DQS_2 MEM_A_DQS_P<2> BI 31 88 SB_DQS_2 MEM_B_DQS_P<2> BI 31 88
88 31 MEM_A_DQ<38> AU38 SA_DQ_38 88 31 MEM_B_DQ<38> AM28 SB_DQ_38
BI AV8 MEM_A_DQS_P<3> BI AN13 MEM_B_DQS_P<3>
AU37 SA_DQS_3 BI 31 88
AM29 SB_DQS_3 BI 31 88
SA_DQS_4 AV37 MEM_A_DQS_P<4> 31 88 SB_DQS_4 AN29 MEM_B_DQS_P<4> 31 88
MEM A DQ<40> AR40 BI MEM B DQ<40> AP32 BI
88 31 BI SA_DQ_40 AP38 88 31 BI SB_DQ_40 AP33
88 31 BI MEM_A_DQ<41> AR37 SA_DQ_41 88 31 BI MEM_B_DQ<41> AP31 SB_DQ_41
SA_DQS_6 AK38 MEM_A_DQS_P<6> 31 88 SB_DQS_6 AL33 MEM_B_DQS_P<6> 31 88
MEM_A_DQ<42> AN38 BI MEM_B_DQ<42> AP35 BI
88 31 BI SA_DQ_42 AF38 88 31 BI SB_DQ_42 AG35
88 31 MEM_A_DQ<43> AN37 SA_DQ_43 88 31 MEM_B_DQ<43> AP34 SB_DQ_43
BI AV13 TP_MEM_A_DQS_P<8> BI AN16 TP_MEM_B_DQS_P<8>
AR39 SA_DQS_8 8
AR32 SB_DQS_8 8
88 31 BI MEM_A_DQ<45> AR38 SA_DQ_45 SA_MA_0 AV27 MEM_A_A<0> OUT 29 88 88 31 BI MEM_B_DQ<45> AR31 SB_DQ_45 SB_MA_0 AK24 MEM_B_A<0> OUT 30 88
88 31 BI MEM_A_DQ<46> AN39 SA_DQ_46 SA_MA_1 AY24 MEM_A_A<1> OUT 29 88 88 31 BI MEM_B_DQ<46> AR35 SB_DQ_46 SB_MA_1 AM20 MEM_B_A<1> OUT 30 88
88 31 MEM_A_DQ<47> AN40 SA_DQ_47 SA_MA_2 AW24 MEM_A_A<2> 29 88 88 31 MEM_B_DQ<47> AR34 SB_DQ_47 SB_MA_2 AM19 MEM_B_A<2> 30 88
BI OUT BI OUT
88 31 MEM_A_DQ<48> AL40 SA_DQ_48 SA_MA_3 AW23 MEM_A_A<3> 29 88 88 31 MEM_B_DQ<48> AM32 SB_DQ_48 SB_MA_3 AK18 MEM_B_A<3> 30 88
BI OUT BI OUT
88 31 MEM_A_DQ<49> AL37 SA_DQ_49 SA_MA_4 AV23 MEM_A_A<4> 29 88 88 31 MEM_B_DQ<49> AM31 SB_DQ_49 SB_MA_4 AP19 MEM_B_A<4> 30 88
BI OUT BI OUT
88 31 BI MEM_A_DQ<50> AJ38 SA_DQ_50 SA_MA_5 AT24 MEM_A_A<5> OUT 29 88 88 31 BI MEM_B_DQ<50> AL35 SB_DQ_50 SB_MA_5 AP18 MEM_B_A<5> OUT 30 88
88 31 MEM_A_DQ<51> AJ37 SA_DQ_51 SA_MA_6 AT23 MEM_A_A<6> 29 88 88 31 MEM_B_DQ<51> AL32 SB_DQ_51 SB_MA_6 AM18 MEM_B_A<6> 30 88
BI OUT BI OUT
88 31 MEM_A_DQ<52> AL39 SA_DQ_52 SA_MA_7 AU22 MEM_A_A<7> 29 88 88 31 MEM_B_DQ<52> AM34 SB_DQ_52 SB_MA_7 AL18 MEM_B_A<7> 30 88
BI OUT BI OUT
88 31 BI MEM_A_DQ<53> AL38 SA_DQ_53 SA_MA_8 AV22 MEM_A_A<8> OUT 29 88 88 31 BI MEM_B_DQ<53> AL31 SB_DQ_53 SB_MA_8 AN18 MEM_B_A<8> OUT 30 88
88 31 MEM_A_DQ<54> AJ39 SA_DQ_54 SA_MA_9 AT22 MEM_A_A<9> 29 88 88 31 MEM_B_DQ<54> AM35 SB_DQ_54 SB_MA_9 AY17 MEM_B_A<9> 30 88
BI OUT BI OUT
88 31 BI MEM A DQ<55> AJ40 SA_DQ_55 SA_MA_10 AV28 MEM A A<10> OUT 29 88 88 31 BI MEM B DQ<55> AL34 SB_DQ_55 SB_MA_10 AN23 MEM B A<10> OUT 30 88
88 31 MEM_A_DQ<56> AG40 SA_DQ_56 SA_MA_11 AU21 MEM_A_A<11> 29 88 88 31 MEM_B_DQ<56> AH35 SB_DQ_56 SB_MA_11 AU17 MEM_B_A<11> 30 88
BI OUT BI OUT
B 88 31
88 31
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AG37
AE38
SA_DQ_57
SA_DQ_58
SA_MA_12
SA_MA_13
AT21
AW32
MEM_A_A<12>
MEM_A_A<13>
OUT
OUT
29 88
29 88
88 31
88 31
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AH34
AE34
SB_DQ_57
SB_DQ_58
SB_MA_12
SB_MA_13
AT18
AR26
MEM_B_A<12>
MEM_B_A<13>
OUT
OUT
30 88
30 88
B
88 31 MEM_A_DQ<59> AE37 SA_DQ_59 SA_MA_14 AU20 MEM_A_A<14> 29 88 88 31 MEM_B_DQ<59> AE35 SB_DQ_59 SB_MA_14 AY16 MEM_B_A<14> 30 88
BI OUT BI OUT
88 31 BI MEM_A_DQ<60> AG39 SA_DQ_60 SA_MA_15 AT20 MEM_A_A<15> OUT 29 88 88 31 BI MEM_B_DQ<60> AJ35 SB_DQ_60 SB_MA_15 AV16 MEM_B_A<15> OUT 30 88
88 31 MEM_A_DQ<61> AG38 SA_DQ_61 88 31 MEM_B_DQ<61> AJ34 SB_DQ_61

BI AU12 TP_MEM_A_DQ_CB<0> BI AL16 TP_MEM_B_DQ_CB<0>
AE39 SA_ECC_CB_0 8
AF33 SB_ECC_CB_0 8
SA_ECC_CB_1 AU14 TP_MEM_A_DQ_CB<1> 8 SB_ECC_CB_1 AM16 TP_MEM_B_DQ_CB<1> 8
88 31 MEM A DQ<63> AE40 SA_DQ_63 88 31 MEM B DQ<63> AF35 SB_DQ_63
BI AW13 TP_MEM_A_DQ_CB<2> BI AP16 TP_MEM_B_DQ_CB<2>
SA_ECC_CB_2 8 SB_ECC_CB_2 8
88 29 MEM_A_BA<0> AY29 SA_BS_0 SA_ECC_CB_3 AY13 TP_MEM_A_DQ_CB<3> 8 88 30 MEM_B_BA<0> AP23 SB_BS_0 SB_ECC_CB_3 AR16 TP_MEM_B_DQ_CB<3> 8
OUT OUT
88 29 OUT MEM_A_BA<1> AW28 SA_BS_1 SA_ECC_CB_4 AU13 TP_MEM_A_DQ_CB<4> 8 88 30 OUT MEM_B_BA<1> AM24 SB_BS_1 SB_ECC_CB_4 AL15 TP_MEM_B_DQ_CB<4> 8
88 29 OUT MEM A BA<2> AV20 SA_BS_2 SA_ECC_CB_5 AU11 TP MEM A DQ CB<5> 8 88 30 OUT MEM B BA<2> AW17 SB_BS_2 SB_ECC_CB_5 AM15 TP MEM B DQ CB<5> 8
SA_ECC_CB_6 AY12 TP MEM A DQ CB<6> 8 SB_ECC_CB_6 AR15 TP MEM B DQ CB<6> 8

88 29 OUT MEM_A_CAS_L AV30 SA_CAS* 88 30 OUT MEM_B_CAS_L AK25 SB_CAS*
SA_ECC_CB_7 AW12 TP_MEM_A_DQ_CB<7> 8 SB_ECC_CB_7 AP15 TP_MEM_B_DQ_CB<7> 8
88 29 OUT MEM_A_RAS_L AU28 SA_RAS* 88 30 OUT MEM_B_RAS_L AP24 SB_RAS*
88 29 OUT MEM A WE L AW29 SA_WE* 88 30 OUT MEM B WE L AR25 SB_WE*

PAGE TITLE
CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

REVISION
R
4.2.0
12 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE OMIT_TABLE
62 48 16 13 6 =PPVCORE_S0_CPU
U1000 U1000
62 48 16 13 6 =PPVCORE_S0_CPU IVY-BRIDGE =PPVCCIO_S0_CPU 6 10 11 13 16 62
IVY-BRIDGE
BGA-SKT-K70 =PPVAXG S0 CPU BGA-SKT-K70
62 48 17 6
D
A12
A13
VCC_001
VCC_002
SYM 6 OF 10 VCCIO_01
VCCIO_02
A11
A7
AB33
AB34
VCCAXG_01
VCCAXG_02
SYM 7 OF 10
D
OMIT_TABLE A14 AA3
VCC_003 VCCIO_03 AB35
U1000 A15 VCC_004 VCCIO_04 AB8 AB36
VCCAXG_03
IVY-BRIDGE VCCAXG_04
A16 VCC_005 VCCIO_05 AF8 AB37
BGA-SKT-K70 VCCAXG_05
A18 VCC_006 VCCIO_06 AG33 AB38
F16 VCC_071 SYM 10 OF 10 VCC_131 K22 VCCAXG_06
A24 VCC_007 VCCIO_07 AJ16 AB39
F18 VCC_072 VCC_132 K24 VCCAXG_07
A25 VCC_008 VCCIO_08 AJ17 AB40
A27 VCC_009 VCCIO_09 AJ26 AC33
A28 VCC_010 VCCIO_10 AJ28 AC34
B15 VCC_011 VCCIO_11 AJ32 AC35
B16 VCC_012 VCCIO_12 AK15 AC36 =PP1V5_S0_CPU_MEM
F25 VCC_077 VCC_137 L13 VCCAXG_12 6 11 16
B18 VCC_013 VCCIO_13 AK17 AC37
F27 VCC_078 VCC_138 L14 VCCAXG_13
B24 VCC_014 VCCIO_14 AK19 AC38
F28 VCC_079 VCC_139 L15 VCCAXG_14
B25 VCC_015 VCCIO_15 AK21 AC39 AJ13
F30 VCC_080 VCC_140 L16 VCCAXG_15 VDDQ0
B27 VCC_016 VCCIO_16 AK23 AC40 AJ14
POWER
F31 L18 VCCAXG_16 VDDQ1
POWER
VCC_081 VCC_141 B28 AK27
F32 L19 VCC_017 VCCIO_17 T33 VCCAXG_17 VDDQ2 AJ20
VCC_082 VCC_142 B30 AK29
F33 CPU CORE SUPPLY L21 VCC_018 VCCIO_18 T34 VCCAXG_18 VDDQ3 AJ23
VCC_083 VCC_143 B31 AK30
F34 L22 VCC_019 VCCIO_19 T35 VCCAXG_19 VDDQ4 AJ24
IO POWER
VCC_084 VCC_144 B33 B9
G15 L24 VCC_020 VCCIO_20 T36 VCCAXG_20 VDDQ5 AR20
VCC_085 VCC_145 B34 D6
VCC_086 VCC_146 C15 D10
DDR3-1.5V RAILS
VCC_087 VCC_147 C16 E3
VCC_023 VCCIO_23 T39 AR23
GRAPHICS
G19 VCC_088 VCC_148 L28 VCCAXG_23 VDDQ8
C18 VCC_024 VCCIO_24 E4 T40 AR24
G21 VCC_089 VCC_149 L30 VCCAXG_24 VDDQ9
C19 VCC_025 VCCIO_25 G3 U33 AU19
G22 VCC_090 VCC_150 M14 VCCAXG_25 VDDQ10
C21 VCC_026 VCCIO_26 G4 U34 AU23
C22 VCC_027 VCCIO_27 J3 U35 AU27
G25 M16 VCCAXG_27 VDDQ12
C VCC_092 VCC_152 C24 VCC_028 VCCIO_28 J4 U36 AU31 C
POWER
C25 VCC_029 VCCIO_29 J7 U37 AV21
C27 VCC_030 VCCIO_30 J8 U38 AV24
CPU CORE SUPPLY

C28 VCC_031 VCCIO_31 L3 U39 AV25
C30 VCC_032 VCCIO_32 L4 U40 AV29
C31 L7
CPU CORE SUPPLY
G33 M25 VCC_033 VCCIO_33 W33 VCCAXG_33 VDDQ18 AV33

VCC_098 VCC_158 C33 M13
H13 M27 VCC_034 VCCIO_34 W34 VCCAXG_34 VDDQ19 AW31
VCC_099 VCC_159 C34 N3
H14 M28 VCC_035 VCCIO_35 W35 VCCAXG_35 VDDQ20 AY23
VCC_100 VCC_160 C36 N4
H15 M30 VCC_036 VCCIO_36 W36 VCCAXG_36 VDDQ21 AY26
VCC_101 VCC_161 D13 N7
H16 VCC_037 VCCIO_37 W37 VCCAXG_37 VDDQ22 AY28
VCC_102 D14 R3
H18 =PPVCCSA_S0_CPU 6 16 VCC_038 VCCIO_38 W38 VCCAXG_38
VCC_103 D15 R4
H19 VCC_039 VCCIO_39 Y33 VCCAXG_39
VCC_104 D16 R7
H21 H10 VCC_040 VCCIO_40 Y34 VCCAXG_40 =PP1V8 S0 CPU PLL 6 16
VCC_105 VCCSA0 D18 U3
H22 H11 VCC_041 VCCIO_41 Y35 VCCAXG_41
VCC_106 VCCSA1 D19 U4
VCC_042 VCCIO_42 Y36 VCCPLL0 AK11
1.8V
H24 VCC_107 VCCSA2 H12 VCCAXG_42
D21 VCC_043 VCCIO_43 U7 =PPVCCIO_S0_CPU Y37
H25 VCC_108 VCCSA3 J10 6 10 11 13 16 62
VCCAXG_43 VCCPLL1 AK12
D22 VCC_044 VCCIO_44 V8 Y38
H27 K10 VCCAXG_44
VCCSA
VCC_109 VCCSA4 D24 W3

H28 K11 VCC_045 VCCIO_45
VCC_110 VCCSA5 D25 PLACE NEAR=U1000 A37 10mm
H30 L11 VCC_046 PLACE NEAR=U1000 B37 10mm
1
H31
VCC_111 VCCSA6
L12
D27 VCC_047 R13021 R1300
VCC_112 VCCSA7 D28 75
H32 M10 VCC_048 110 1%
VCC_113 VCCSA8 D30 1% 1/16W
J12 M11 VCC_049 1/16W MF-LF
VCC_114 VCCSA9 D31 VCCIO_SEL P33 NC_CPU_VCCIO_VID MF-LF 2 402
J15 M12 VCC_050 NO_TEST=TRUE 402 2
VCC_115 VCCSA10 D33
J16 VCC_051 VCCSA_VID P34 NC_CPU_VCCSA_VID
CPU VIDS
J18
VCC_116 D34 VCC_052
NO_TEST=TRUE R1310
VCC_117 D35 96 CPU_VIDALERT_R_L 44.2 2 CPU VIDALERT L
J19 VCC_053 VIDALERT* A37 1% 1 1/16W IN 62 96
VCC_118 MF-LF 402
B J21
J22
VCC_119
D36
E15
VCC_054
VCC_055 VIDSCLK C37 96 CPU VIDSCLK R R1311 B
VCC_120 E16 0
J24 A4 VCC_056 5% 1 2 1/16W CPU_VIDSCLK 62 96
VCC_121 VSS_NCTF0 MF-LF 402 OUT
E18 VCC_057 VIDSOUT B37 96 CPU VIDSOUT R
NCTF
J25 VCC_122 VSS_NCTF1 B3

E19
J27 VCC_123 VSS_NCTF2 AV39
E21
VCC_058 R1312
J28 AY37 VCC_059 0 CPU VIDSOUT
VCC_124 VSS_NCTF3 5% 1 2 1/16W BI 62 96
E22 VCC_060 MF-LF 402
J30 VCC_125 E24 VCC_061
K15 VCC_126
SENSE LINES
E25 VCC_062 VCCSA_SENSE T2 SNS_CPU_VCCSA 66 95

K16 OUT
VCC_127 E27
K18 VCC_063
VCC_128 E28
K19 VCC_064 VCC_SENSE A36 SNS_CPU_VCORE_P OUT 62 96
VCC_129 E30
K21 VCC_065 VSS_SENSE B36 SNS_CPU_VCORE_N OUT 62 96
VCC_130 E31 VCC_066
E33 VCC_067 VCCIO_SENSE AB4 SNS_CPU_VCCIO_P 65 95
OUT
E34 VCC_068 VSSIO_SENSE AB3 SNS_CPU_VCCIO_N 65 95
OUT
E35 VCC_069
F15 VCC_070 VCCAXG_SENSE L32 SNS_CPU_VAXG_P 62 96
OUT
VSSAXG_SENSE M32 SNS_CPU_VAXG_N OUT 62 96

PAGE TITLE
CPU POWER
DRAWING NUMBER SIZE

REVISION
R
4.2.0
13 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
OMIT_TABLE
U1000 U1000
IVY-BRIDGE IVY-BRIDGE
BGA-SKT-K70
BGA-SKT-K70
AV11 VSS_181 SYM 9 OF 10 VSS_271 G8
A17 VSS_001 SYM 8 OF 10 VSS_091 AM27
AV14 VSS_182 VSS_272 H1
A23 VSS_002 VSS_092 AM3
AV17 VSS_183 VSS_273 H17
A26 VSS_003 VSS_093 AM30
AV3 VSS_184 VSS_274 H2
A29 VSS_004 VSS_094 AM36
AV35 VSS_185 VSS_275 H20
A35 VSS_005 VSS_095 AM37
AV38 VSS_186 VSS_276 H23
AA33 VSS_006 VSS_096 AM38
AV6 VSS_187 VSS_277 H26
AA34 VSS_007 VSS_097 AM39
AW10 VSS_188 VSS_278 H29
D
AA35
AA36
VSS_008
VSS_009
VSS_098
VSS_099
AM4
AM40
AW11
AW14
VSS_189 VSS_279 H33
H35
D
AA37 AM5 VSS_190 VSS_280
VSS_010 VSS_100 AW16 H37
AA38 AN10 VSS_191 VSS_281
VSS_011 VSS_101 AW36 H39
AA6 AN11 VSS_192 VSS_282
VSS_012 VSS_102 AW6 H5
AB5 AN14 VSS_193 VSS_283
VSS_013 VSS_103 AY11 H6
AC1 AN17 VSS_194 VSS_284
VSS_014 VSS_104 AY14 H9
AC6 AN19 VSS_195 VSS_285
VSS_015 VSS_105 AY18 J11
AD33 AN22 VSS_196 VSS_286
VSS_016 VSS_106 AY35 J17
VSS_017 VSS_107 AY4 J20
VSS_018 VSS_108
VSS
AY6 VSS_199 VSS_289 J23
AD39 VSS_019 VSS_109 AN30
AY8 VSS_200 VSS_290 J26
VSS
B10 VSS_201 VSS_291 J29
B13 VSS_202 VSS_292 J32
B14 VSS_203 VSS_293 K1
AE3 VSS_023 VSS_113 AN34
B17 VSS_204 VSS_294 K12
B23 VSS_205 VSS_295 K13
B26 VSS_206 VSS_296 K14
AF1 VSS_026 VSS_116 AN5
B29 VSS_207 VSS_297 K17
B32 VSS_208 VSS_298 K2
B35 VSS_209 VSS_299 K20
B38 VSS_210 VSS_300 K23
B6 VSS_211 VSS_301 K26
AF5 VSS_031 VSS_121 AP1
C11 VSS_212 VSS_302 K29
C12 VSS_213 VSS_303 K33
C17 VSS_214 VSS_304 K35
AG36 VSS_034 VSS_124 AP17
C20 K37
C AH2
AH3
VSS_035
VSS_036
VSS_125
VSS_126
AP22
AP25
C23
VSS_215
VSS_216
VSS_305
VSS_306 K39 C
C26 VSS_217 VSS_307 K5
AH33 VSS_037 VSS_127 AP27
C29 VSS_218 VSS_308 K6
C32 VSS_219 VSS_309 L10
C35 VSS_220 VSS_310 L17
C7 VSS_221 VSS_311 L20
C8 VSS_222 VSS_312 L23
D17 VSS_223 VSS_313 L26
D2 VSS_224 VSS_314 L29
AH8 VSS_044 VSS_134 AR11
D20 VSS_225 VSS_315 L8
AJ12 VSS_045 VSS_135 AR14
D23 VSS_226 VSS_316 M1
D26 VSS_227 VSS_317 M17
D29 VSS_228 VSS_318 M2
D32 VSS_229 VSS_319 M20
D37 VSS_230 VSS_320 M23
D39 VSS_231 VSS_321 M26
D4 VSS_232 VSS_322 M29
D5 VSS_233 VSS_323 M33
AK1 VSS_053 VSS_143 AT1
D9 VSS_234 VSS_324 M35
E11 VSS_235 VSS_325 M37
E12 VSS_236 VSS_326 M39
E17 VSS_237 VSS_327 M5
E20 VSS_238 VSS_328 M6
E23 VSS_239 VSS_329 M9
E26 VSS_240 VSS_330 N8
E29 VSS_241 VSS_331 P1
B AK32
AK33
VSS_061
VSS_062
VSS_151
VSS_152
AT25
AT27
E32
E36
VSS_242 VSS_332 P2
P36
B
AK34 AT28 VSS_243 VSS_333
VSS_063 VSS_153 E7 P38
VSS_064 VSS_154 E8 P40
VSS_065 VSS_155 F1 P5
VSS_066 VSS_156 F10 P6
VSS_067 VSS_157 F13 R33
VSS_068 VSS_158 F14 R35
VSS_069 VSS_159 F17 R37
VSS_070 VSS_160 F2 R39
VSS_071 VSS_161 F20 R8
VSS_072 VSS_162 F23 T1
VSS_073 VSS_163 F26 T5
AL11 AT38 VSS_254 VSS_344
VSS_074 VSS_164 F29 T6
VSS_075 VSS_165 F35 U8
VSS_076 VSS_166 F37 V1
VSS_077 VSS_167 F39 V2
VSS_078 VSS_168 F5 V33
VSS_079 VSS_169 F6 V34
VSS_080 VSS_170 F9 V35
VSS_081 VSS_171 G11 V36
VSS_082 VSS_172 G12 V37
AM1 AU1 VSS_263 VSS_353
VSS_083 VSS_173 G17 V38
VSS_084 VSS_174 G20 V39
VSS_085 VSS_175 G23 V40
VSS_086 VSS_176 G26 V5
A AM2
AM21
VSS_087
VSS_088
VSS_177
VSS_178
AU4
AU6
G29
VSS_267
VSS_268
VSS_357
VSS_358 W6 SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A
G34 VSS_269 VSS_359 Y5 PAGE TITLE
AM23 AU8
AM25
VSS_089
VSS_090
VSS_179
VSS_180 AV10
G7 VSS_270 VSS_360 Y8 CPU GROUNDS
DRAWING NUMBER SIZE

REVISION
R
4.2.0
14 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
15 6 =PP3V3_S5_PCH_STRAPS
R1501 15 6 =PP3V3_S0_PCH_STRAPS
IVB PCIe Straps configuration:
10K1 2 SMC_WAKE_SCI_L 21 44
5% 1/16W MF-LF 402 CFG[5:6] = Sel PCIe Cfg CFG[3]=Direct/Rev for X4 CFG[2]= Direct/Rev for x16
R1502 11 = 1x16 (default) 1 = DIR 1 = DIR
10K1 2 TBT GO2SX BIDIR
5% 1/16W MF-LF 402
21 34
10 = 2x8 0 = REV 0 = REV
10K 1 R1504 10K1 2
R1509 DP AUXCH ISOL
00 = 1x8,2x4
2 PCH_SUSWARN_L 19
15 18
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
10K 1 R1563 10K1 2

R1510 PCH_GPIO1
2 PCH_GPIO72 19
21
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
D 1K 1
5%
2
R1564
1/16W MF-LF 402
PM PWRBTN L 19 25 44
10K1
5%
2
R1511
1/16W MF-LF 402
PCH GPIO48 21
NOSTUFF
D
10K 1 R1590 CPU CFG<5>
1K 1 2
R1512
2 PCH_SMBALERT_L 18
91 25 10
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402

NOSTUFF
DP_AUXIO_EN Inversion 91 25 10 CPU_CFG<6>
1K 1 2
R1513
5% 1/16W MF-LF 402
Inverts PCH GPIO DP_AUXCH_ISOL to drive DP_AUXIO_EN for external DP
1K NOSTUFF R1523
15 6 =PP3V3 S0 PCH STRAPS 91 25 10 CPU CFG<3> 1 2
5% 1/16W MF-LF 402
1 U1000.18:3mm
15 6 =PP3V3_S5_PCH_STRAPS R1507 CPU CFG<2>
1K 1 2
R1522
R1519 10K 91 25 10
10K1 2 USB EXTA OC L 20 42
5% 5% 1/16W MF-LF 402
1/16W
5% 1/16W MF-LF 402 MF-LF
R1518 2 402
10K 1 2 USB_EXTB_OC_L 20 42
5% 1/16W MF-LF 402 DP_AUXIO_EN OUT 84 85
CRITICAL
10K 1 2
R1517 USB_EXTC_OC_L 20 43
Q1509
5% 1/16W MF-LF 402
SSM3K15AMFVAPE D 3
VESM
10K 1 2
R1516 USB_EXTD_OC_L
20 43
5% 1/16W MF-LF 402
1K
R1536 USB_EXTB_OC_EHCI_L 1 G S 2 R1570
1 2 20 100K1
60 44 33 19 PM_SLP_S5_L 2
5% 1/16W MF-LF 402 DP_AUXCH_ISOL 5% 1/16W MF-LF 402
18 15
1K 1 2
R1537 USB_EXTD_OC_EHCI_L 20
R1571
60 44 19 PM_SLP_S4_L 100K1 2
5% 1/16W MF-LF 402
39 6 =PP3V3 S4 SDCARD 5% 1/16W MF-LF 402
15 6 =PP3V3 S0 PCH STRAPS 100K1
R1572
NOSTUFF 60 45 44 38 28 19 PM_SLP_S3_L 2
C 4.7K1 2
R1529
PCH_SPKR 18
21 PCH GPIO22 10K 1
5% 1/16W MF-LF 402
2
R1533 C
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
10K1 R1520 10K1 2

R1528 SATARDRVR_EN 20K 1 R1532
2 SDCONN_STATE_CHANGE 20 39
18
21 PCH_GPIO6 2
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
10K1 2
R1527 PCH_CAM_EXT_BOOT 10K 1 R1531
21
93 37 18 ENET MEDIA SENSE 2
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
10K 1 R1526
2 PCH_CAM_RESET 21
WOL_EN 10K 1 2
R1530
NOSTUFF 5% 1/16W MF-LF 402 38 21
R1553 5% 1/16W MF-LF 402
0 10K1 R1525
91 25 18 ITPXDP_CLK100M_N 1 2 ITPCPU_CLK100M_N 11 91 2 MLB_RAM_CFG1 21
19 PCH_GPIO29 10K 1 2
R1555
5%
5% 1/16W MF-LF 402
1/16W
5% 1/16W MF-LF 402
MF LF
402 10K 1 2
R1524 MLB_RAM_CFG0 TBT_CIO_PLUG_EVENT 10K1 2
R1521
21 34 21
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
NOSTUFF 10K1 R1503
10K 1 R1542 26 21 ENET_LOW_PWR_PCH 2
R1554 2 SMC_RUNTIME_SCI_L 21 44 5% 1/16W MF-LF 402
0 5% 1/16W MF-LF 402
91 25 18 ITPXDP_CLK100M_P 1 2 ITPCPU_CLK100M_P 11 91
5%
1/16W
MF LF
402
41 6 =PP3V3_S0_LED_SATA 6 =PP3V3_S4_PCH 15 6 =PP3V3_S0_PCH_STRAPS
1 10K 1 R1540 UNUSED clock terminations for FCIM MODE

R1556 1
R1505 5%
2
1/16W MF-LF 402
TBT_CLKREQ_L 21 36
10K 1 R1551
10K 10K 18 PCH_CLKIN_GND1 2
5% 5% R1539 5% 1/16W MF-LF 402
1/16W 10K 1 2 ENET CLKREQ L
B 2
MF-LF
402
1/16W
MF-LF
2 402
5% 1/16W MF-LF 402
18 37
18 PCH CLKIN GND0 10K 1 2

R1550 B
10K 1 2
R1538 AP_CLKREQ_L
5% 1/16W MF-LF 402
21 33
PCH_SATALED_L AP_PWR_EN 5% 1/16W MF-LF 402 PCH_CLK14P3M_REFCLK 10K 1 2

R1549
18 41 20 33 18
10K 1 2
R1541 SSD CLKREQ L 18
5% 1/16W MF-LF 402
41
5% 1/16W MF-LF 402 PCH_CLK100M_DMIN 10K 1 2
R1548
18
R1508 PLACE_NEAR=U1800.P33:5mm 5% 1/16W MF-LF 402
10K 1 2 PEG_CLKREQ_L 18 71
15 6 =PP3V3 S5 PCH STRAPS 5% 1/16W MF-LF 402 10K 1 R1547
18 PCH_CLK100M_DMIP 2
PLACE_NEAR=U1800.R33:5mm 5% 1/16W MF-LF 402
2
PCH_CLK100M_SATAN
10K
1 2
R1546
18
PLACE_NEAR=U1800.AF55:5mm 5% 1/16W MF-LF 402
SPI DESCRIPTOR OVERRIDE L S SOT23-3-HF =PP3V3 TBT PCH GPIO
44 6
IN 1
G
NTR1P02L 10K 1 R1545
Q1500 18 PCH CLK100M SATAP 2
R1562 PLACE_NEAR=U1800.AG56:5mm 5% 1/16W MF-LF 402
10K
1 2 JTAG_TBT_TDO 21 34
D 5% 1/16W MF-LF 402 PCH_CLK96M_DOTN 10K 1 2
R1544
18
3 PLACE_NEAR=U1800.BD38:5mm 5%
10K
1 2
R1561 JTAG TBT TDI
1/16W MF-LF 402
21 34
PLACE_NEAR=R1805.4:3mm R1543
5% 1/16W MF-LF 402
18 PCH CLK96M DOTP 10K 1 2
R1552 R1560 PLACE_NEAR=U1800.BF38:5mm 5% 1/16W MF-LF 402
SPI_DESCRIPTOR_OVERRIDE_R 330 1 2 HDA_SDOUT_R OUT 18 92
10K
1 2 JTAG_TBT_TMS 18 34
5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
NOSTUFF R1559
10K
1 2 TBT SW RESET R L 21
5% 1/16W MF-LF 402
10K
1 2
R1567 JTAG_TBT_TCK
36 20 19 6 =PP3V3_S0_PCH_GPIO 21 34
5% 1/16W MF-LF 402
10K 1
R1558
2 BT_PWR_RST_L 20 33
A 10K 1
5% 1/16W MF-LF 402
2
R1557 SYNC MASTER=D7 TONY SYNC DATE=01/11/2012 A
TBT_PWR_REQ_L 20 34 PAGE TITLE
5% 1/16W MF-LF 402
HDA_SYNC
1K 1 2
R1514 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
92 52 18
5% 1/16W MF-LF 402 DRAWING NUMBER SIZE

REVISION
R
4.2.0
15 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE DECOUPLING

14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor) 10x 10UF and 10x 1UF CAPACITORS
PLACEMENT_NOTE (C1600-C1613):
62 48 16 13 6
=PPVCORE_S0_CPU Place inside socket cavity
16 13 6 =PPVCORE_S0_CPU Place inside socket cavity
62 48
1 C1620 1 C1621 1 C1622 1 C1623 1 C1624 1 C1625 1 C1626 1 C1627 1 C1628 1 C1629 D
D 1 C1600
22UF
1 C1601
22UF
1 C1602
22UF
1 C1603
22UF
1 C1604
22UF
1 C1605
22UF
1 C1606
22UF
1 C1607
22UF
1 C1608
22UF
1 C1609
22UF
10UF
20% 20%
10UF 10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
603 603 603 603 603 603 603 603 603 603
805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3 805-3
1 C1630 1 C1631 1 C1632 1 C1633 1 C1634 1 C1635 1 C1636 1 C1637 1 C1638 1 C1639
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
1 C1610 1 C1611 1 C1612 1 C1613 16V
2 X5R 16V
2 X5R 16V
2 X5R 16V
2 X5R 16V
2 X5R 16V
2 X5R 16V
2 X5R 16V
2 X5R 16V
2 X5R 16V
2 X5R
22UF 22UF 22UF 22UF 402 402 402 402 402 402 402 402 402 402
20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
805-3 805-3 805-3 805-3
BULK CAPS ON CPU VREG PAGE 72
CPU VCCIO DECOUPLING

C 8X 22UF 0805, 6X 10UF 0805 INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders C
13 11 10 6 =PPVCCIO_S0_CPU
62 Place under socket cavity on secondary side.
1 C1650 1 C1651 1 C1652 1 C1653 1 C1654 1 C1655 1 C1656 1 C1657

22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
805 805 805 805 805 805 805 805
Place at edge of socket.
1 C1660 1 C1661 1 C1662 1 C1663 1 C1664 1 C1665

10uF 10uF 10uF 10uF 10uF 10uF
20% 20% 20% 20% 20% 20%
2 6.3V
X5R
6.3V
2 X5R 2 6.3V
X5R
6.3V
2 X5R 2 6.3V
X5R 2 6.3V
X5R
603 603 603 603 603 603
CPU VCCSA DECOUPLING

2x 10uF 0603. INTEL RECOMMENDATION 2X 10uF 0805
BULK CAPS ON CPU VREG PAGE 74
13 6 =PPVCCSA_S0_CPU
B 1
C1670
330UF-0.0045OHM B
20%
2 2V
1 C1666 1 C1667
POLY 10uF 10uF
CASE-D2-SM 20% 20%
6.3V
2 X5R 2 6.3V
X5R
603 603
Bulk decoupling is on VCCSA reg page 75
Memory (CPU VCCDDR) DECOUPLING

13 11 6 =PP1V5 S0 CPU MEM
1 C1676 1 C1677 1 C1678 1 C1679 1 C1680 1 C1681 1 C1682 1 C1683 1 C1684 1 C1685 1 C1686
22uF 22uF 22uF 22uF 22uF 22uF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 X5R 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 2 6.3V
X5R
NOSTUFF 805 805 805 805 805 805 0201 0201 0201 0201 0201
1
C1687
330UF-0.0045OHM
20%
2 2V
POLY
CASE-D2-SM
PLL (CPU VCCSFR) DECOUPLING

A 2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 1x 10uF 0805
13 6 =PP1V8 S0 CPU PLL PAGE TITLE
CPU NON-GFX DECOUPLING

DRAWING NUMBER SIZE
1 C1693 1 C1694 1 C1692 1 C1691 1 C1695 1 C1690 1 C1696 1 C1697 Apple Inc. 051-9509 D
1UF 1UF 2.2UF 4.7UF 10UF 22uF 47UF 47UF REVISION
10% 10% 10% 10% 20% 20% 20% 20% R
10V
2 X5R 10V
2 X5R 6.3V
2 X5R 6.3V
2 X5R-CERM 6.3V
2 X5R 6.3V
2 CERM-X5R 6.3V
2 X5R 2 6.3V
X5R 4.2.0
402 402 402 603 603 805 0805 0805 NOTICE OF PROPRIETARY PROPERTY: BRANCH
BULK CAPS ON VTT REG PAGE 77 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
16 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
VAXG DECOUPLING
INTEL RECOMMENDATION 4X22UF 0805,3X 4.7UF
Place inside socket cavity
62 48 13 6 =PPVAXG_S0_CPU
1 C1704 1 C1705 1 C1706 1 C1707 1 C1708 1 C1709

22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
805-3 805-3 805-3 805-3 805-3 805-3
1 C1710 1 C1711 1 C1712

4.7UF 4.7UF 4.7UF
10% 10% 10%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
603 603 603
C BULK CAPS ON CPU VREG PAGE 73 C
R1720
0
6 =PP3V3_S0_PCH_VCC_ADAC 1 2 PP3V3_S0_PCH_VCCA_DAC_F 22
MAKE_BASE=TRUE
5% MIN_LINE_WIDTH=0.4 MM
1/16W MIN_NECK_WIDTH=0.2 MM
MF-LF CRITICAL VOLTAGE=3.3V
402 IG:Y IG:Y IG:Y
1 C1720 1 C1721 1 C1722
10UF 0.1UF 0.01UF
20% 10% 10%
6.3V
2 X5R 2 16V 2 16V
X5R CERM
603 402 402
OMIT_TABLE
CRITICAL
L1730
R1730 10UH-0.12A-0.36OHM
0
6 =PP1V05 S0 PCH VCC ADPLL 1 2 PP1V05 S0 PCH VCCADPLLA R 1 2 PP1V05 S0 PCH VCCADPLLA F 22 24
MIN_LINE_WIDTH=0.4MM 0603
MAKE_BASE=TRUE
5% MIN_NECK_WIDTH=0.2MM CRITICAL NOSTUFF MIN_LINE_WIDTH=0.4MM
1/16W VOLTAGE=1.05V IG:Y MIN_NECK_WIDTH=0.2MM
B MF-LF
402 1
C1730 1 C1731
1UF
VOLTAGE=1.05V
B
220UF 10%
20%
6.3V
2 2.5V 2 CERM
TANT
B16 402 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
152S1070 2 IND,WW,10UH,20%.120MA,0.36OHMS L1730,L1740 CRITICAL IG:Y
113S0022 2 RES,MF,1/10W,0OHM,5,0603,SMD,LF L1730,L1740 IG:N
OMIT_TABLE
CRITICAL
L1740
R1740 10UH-0.12A-0.36OHM
1
0 2 PP1V05 S0 PCH VCCADPLLB R 1 2 PP1V05 S0 PCH VCCADPLLB F 22 24
MIN_LINE_WIDTH=0.4MM 0603 MAKE_BASE=TRUE
5% MIN_NECK_WIDTH=0.2MM CRITICAL MIN_LINE_WIDTH=0.4MM
1/16W VOLTAGE=1.05V IG:Y NOSTUFF MIN NECK_WIDTH=0.2MM
MF-LF VOLTAGE=1.05V
402 1
C1740 1 C1741
220UF 1UF
20% 10%
2 2.5V 2 6.3V
CERM
TANT
B16 402

PAGE TITLE
GFX DECOUPLING & PCH PWR ALIAS

DRAWING NUMBER SIZE

REVISION
R
4.2.0
17 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
90 41 IN PCIE_SSD_D2R_N<0> J20 PERN1 OMIT_TABLE SMBALERT*/GPIO11 BN49 PCH_SMBALERT_L 15
90 41 IN PCIE_SSD_D2R_P<0> L20 PERP1 U1800 92 26 IN PCH_CLK32K_RTCX1 BR39 RTCX1 OMIT_TABLE FWH0/LAD0 BK15 92 LPC_R_AD<0> R1860 1
1/16W
2402 5%
MF LF
LPC_AD<0> BI 44 46 92
90 41 OUT PCIE SSD R2D C N<0> F25 PETN1 PANTHER-POINT SMBCLK BT47 SMBUS PCH CLK OUT 47 94 92 26 OUT PCH CLK32K RTCX2 BN39 RTCX2 U1800 FWH1/LAD1 BJ17 92 LPC R AD<1>
33
R1861
1/16W
1
33
2402 5%
MF LF
LPC AD<1> BI 44 46 92
90 41 PCIE_SSD_R2D_C_P<0> F23 PETP1 FCBGA SMBDATA BR49 SMBUS_PCH_DATA 47 94 PANTHER-POINT FWH2/LAD2 BJ20 92 LPC_R_AD<2> R1862 1 2402 5% LPC_AD<2> 44 46 92
OUT BI BI
(2 0F 10) FCBGA BG20
1/16W 33 MF LF
R1863 1
FWH3/LAD3 92 LPC_R_AD<3> 2402 5% LPC_AD<3> BI 44 46 92
P20 (1 OF 10) 1/16W 33 MF LF
90 41 IN PCIE_SSD_D2R_N<1> PERN2 SML0ALERT*/GPIO60 BU49 USB_EXTB_SEL_XHCI OUT 42 45 18 RTC_RESET_L BT41 RTCRST*
90 41 PCIE_SSD_D2R_P<1> R20 PERP2 FWH4/LFRAME* BG17 LFRAME_L R1864 1 2402 5% LPC_FRAME_L OUT 44 46 =PP3V3_S0_PCH 6 21 24
IN 92
90 41 PCIE_SSD_R2D_C_N<1> C22 PETN2 SML0CLK BT51 SML_PCH_0_CLK 47 94 18 PCH_SRTCRST_L BN37 SRTCRST*
1/16W 33 MF LF
1 R1820
OUT OUT
A22 SML0DATA BM50 LDRQ0* BK17
RTC
LPC
90 41 OUT PCIE_SSD_R2D_C_P<1> PETP2 SML_PCH_0_DATA BI 47 94 TP_LPC_DREQ0_L 8 10K
5%
18 PCH INTRUDER L BM38 INTRUDER* LDRQ1*/GPIO23 BA20 TBT PWR EN PCH 26 1/16W
D 90 37 IN PCIE ENET D2R N H17

J17
PERN3 SML1ALERT*/PCHHOT*/GPIO74 BR46 USB EXTD SEL XHCI OUT 43
BN41 INTVRMEN
2
MF LF
402 D
90 37 IN PCIE_ENET_D2R_P PERP3 18 PCH_INTVRMEN SERIRQ AV52 LPC_SERIRQ BI 44 46
90 37 PCIE_ENET_R2D_C_N E21 PETN3 SML1CLK/GPIO58 BJ46 SML_PCH_1_CLK 47

OUT OUT
90 37 PCIE_ENET_R2D_C_P B21 PETP3 SML1DATA/GPIO75 BK46 SML_PCH_1_DATA 47
OUT BI
SMBUS
92 18 HDA_BIT_CLK_R BU22 HDA_BCLK SATA0RXN AC56 SATA_HDD_D2R_N 41 91
IN
90 33 IN PCIE_AP_D2R_N P17 PERN4 SATA0RXP AB55 SATA_HDD_D2R_P IN 41 91
90 33 PCIE_AP_D2R_P M17 PERP4 92 18 HDA_SYNC_R BP23 HDA_SYNC SATA0TXN AE46 SATA_HDD_R2D_C_N 41 91

IN OUT
90 33 PCIE AP R2D C N F18 PETN4 SATA0TXP AE44 SATA HDD R2D C P 41 91
OUT OUT
90 33 PCIE AP R2D C P E17 PETP4 15 PCH SPKR BE56 SPKR
OUT
SATA1RXN AA53 SATA_SSD_D2R_N
IHDA
IN 41 91
90 34 PCIE_TBT_D2R_N<0> N15 PERN5 92 18 HDA_RST_R_L BC22 HDA_RST* SATA1RXP AA56 SATA_SSD_D2R_P 41 91

IN IN
90 34 PCIE_TBT_D2R_P<0> M15 PERP5 CLKOUT_PEG_A_N AG8 TP_CLKOUT_PEG_A_N 8 SATA1TXN AG49 SATA_SSD_R2D_C_N 41 91
IN OUT OUT
PEG
90 34 PCIE_TBT_R2D_C_N<0> B17 PETN5 CLKOUT_PEG_A_P AG9 TP_CLKOUT_PEG_A_P 8 92 52 HDA_SDIN0 BD22 HDA_SDIN0 SATA1TXP AG47 SATA_SSD_R2D_C_P 41 91
OUT OUT IN OUT
90 34 PCIE_TBT_R2D_C_P<0> C16 PETP5 8 TP_HDA_SDIN1 BF22 HDA_SDIN1
OUT
8 TP_HDA_SDIN2 BK22 HDA_SDIN2 SATA2RXN AL50 TP_SATA_C_D2RN 8
90 34 PCIE TBT D2R N<1> J15 PERN6 CLKOUT_DMI_N P31 DMI CLK100M CPU N 11 90 8 TP HDA SDIN3 BJ22 HDA_SDIN3 SATA2RXP AL49 TP SATA C D2RP 8
IN OUT
90 34 PCIE TBT D2R P<1> L15 PERP6 CLKOUT_DMI_P R31 DMI CLK100M CPU P 11 90 SATA2TXN AL56 TP SATA C R2D CN 8
IN OUT
90 34 PCIE_TBT_R2D_C_N<1> A16 PETN6 92 18 15 HDA_SDOUT_R BT23 HDA_SDO SATA2TXP AL53 TP_SATA_C_R2D_CP 8
OUT
90 34 PCIE_TBT_R2D_C_P<1> B15 PETP6
OUT
CLKOUT_DP_N N56 TP_PCH_CLKOUT_DPN JTAG_TBT_TMS BC25 GPIO33 AN46 TP_SATA_D_D2RN
PCI-E*
OUT 8 34 15 SATA3RXN 8
FROM CLK BUFFER

90 34 PCIE_TBT_D2R_N<2> J12 PERN7 CLKOUT_DP_P M55 TP_PCH_CLKOUT_DPP 8 93 37 15 ENET_MEDIA_SENSE BA25 GPIO13 SATA3RXP AN44 TP_SATA_D_D2RP 8
IN OUT
SATA
90 34 PCIE_TBT_D2R_P<2> H12 PERP7 SATA3TXN AN56 TP_SATA_D_R2D_CN 8
IN
90 34 PCIE_TBT_R2D_C_N<2> F15 PETN7 SATA3TXP AM55 TP_SATA_D_R2D_CP 8
OUT
90 34 PCIE TBT R2D C P<2> F13 PETP7 CLKIN_DMI_N P33 PCH CLK100M DMIN 15 91 25 XDP PCH TCK BA43 JTAG_TCK
OUT IN
CLKIN_DMI_P R33 PCH CLK100M DMIP IN 15 SATA4RXN AN49 TP SATA E D2RN 8
90 34 PCIE TBT D2R N<3> H10 PERN8 91 25 XDP PCH TMS BC50 JTAG_TMS SATA4RXP AN50 TP SATA E D2RP 8
IN
JTAG
J10 AT50
C 90 34
90 34
IN
OUT
PCIE_TBT_D2R_P<3>
PCIE_TBT_R2D_C_N<3> B13
PERP8
PETN8 CLKIN_DOT_96N BD38 PCH_CLK96M_DOTN IN 15 91 25 XDP_PCH_TDI BC52 JTAG_TDI
SATA4TXN
SATA4TXP AT49
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
8
8
C
90 34 PCIE_TBT_R2D_C_P<3> D13 PETP8 CLKIN_DOT_96P BF38 PCH_CLK96M_DOTP 15 =PP1V05_S0_PCH_VCCIO_SATA 6 22 24
OUT IN
91 25 XDP_PCH_TDO BF47 JTAG_TDO SATA5RXN AT46 TP_SATA_F_D2RN 8
AE6 CLKOUT_PCIE0N AT44 PLACE_NEAR=U1800.AJ53:2mm
90 41 OUT PCIE_CLK100M_SSD_N SATA5RXP TP_SATA_F_D2RP 8
1
R1830
90 41 OUT PCIE_CLK100M_SSD_P AC6 CLKOUT_PCIE0P CLKIN_SATA_N AF55 PCH_CLK100M_SATAN IN 15 SATA5TXN AV50 TP_SATA_F_R2D_CN 8 37.4
1%
CLKIN_SATA_P AG56 PCH CLK100M SATAP IN 15 SATA5TXP AV49 TP SATA F R2D CP 8 1/16W
MF LF
90 33 OUT PCIE_CLK100M_AP_N AA5 CLKOUT_PCIE1N 92 46 OUT SPI_CLK_R AR54 SPI_CLK 402
2
90 33 OUT PCIE_CLK100M_AP_P W5 CLKOUT_PCIE1P SATAICOMPO AJ53 91 PCH_SATAICOMP
REFCLK14IN AN8 PCH_CLK14P3M_REFCLK IN 15 92 46 OUT SPI_CS0_R_L AT57 SPI_CS0* SATAICOMPI AJ55 TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
SPI
90 34 PCIE_CLK100M_TBT_N AB12 CLKOUT_PCIE2N
OUT
90 34 PCIE_CLK100M_TBT_P AB14 CLKOUT_PCIE2P =PP1V05_S0_PCH_VCCIO_PCIE 6 19 22 NC_SPI_CS1_L AR56 SPI_CS1* SATALED* BF57 PCH_SATALED_L 15 41
OUT
NO_TEST=TRUE SIGNAL_MODEL=EMPTY
CLKIN_PCILOOPBACK BD15 PCH_CLK33M_PCIIN IN 26 92 SIGNAL_MODEL=EMPTY
71 15 IN PEG_CLKREQ_L AV43 PCIECLKRQ2*/GPIO20/SMI* DOES THIS NEED LENGTH MATCH???
PLACE_NEAR=U1800.AL2:2mm
92 46 OUT SPI_MOSI_R AU53 SPI_MOSI SATA0GP/GPIO21 BC54 25 DP_AUXCH_ISOL_R R1841 0 1 2 DP_AUXCH_ISOL OUT 15
1
SATA1GP/GPIO19 AY52 25 SATARDRVR_EN_R R1842 0 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
SATARDRVR_EN OUT 15
90 37 PCIE_CLK100M_ENET_N AB9 CLKOUT_PCIE3N XTAL25_IN AJ3 PCH_CLK25M_XTALIN 26 92

R1890 92 46 SPI_MISO AT55 SPI_MISO
OUT IN IN
90.9 =PP1V05_S0_PCH 6 24
90 37 PCIE_CLK100M_ENET_P AB8 CLKOUT_PCIE3P XTAL25_OUT AJ5 PCH_CLK25M_XTALOUT 8 1% MF LF
OUT
1/16W
L_BKLTCTL AG12 TP_PCH_L_BKLTCTL 1 PLACE_NEAR=U1800.AE52:2mm
402
8 R1831
8 TP_PCIE_CLK100M_PE4N Y9 CLKOUT_PCIE4N 2
L_BKLTEN AG18 TP_PCH_L_BKLTEN 8 49.9
OUT
1%
8 OUT TP_PCIE_CLK100M_PE4P Y8 CLKOUT_PCIE4P XCLK_RCOMP AL2 92 PCH_XCLK_RCOMP L_VDD_EN AG17 TP_PCH_L_VDD_EN 8 1/16W
MF LF
2 402
89 71 OUT PEG CLK100M N AF3 CLKOUT_PCIE5N SATA3COMPI AE54
89 71 PEG_CLK100M_P AG2 CLKOUT_PCIE5P CLKOUTFLEX0/GPIO64 AT9 TP_PCH_GPIO64_CLKOUTFLEX0 8 SATA3RCOMP0 AE52 91 PCH_SATA3COMP
OUT
SATA3RBIAS AC52 91 PCH_SATA3RBIAS
CLOCK
FLEX
18 PCIE_CLKREQ5_GPIO44_L BL54 PCIECLKRQ5*/GPIO44 CLKOUTFLEX1/GPIO65 BA5 TP_PCH_GPIO65_CLKOUTFLEX1 8

IN
PLACE_NEAR=U1800.AC52:2mm
8 DMI_MIDBUS_CLK100M_N AE12 CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66 AW5 TP_PCH_GPIO66_CLKOUTFLEX2 8

R18321
B 8
OUT
OUT DMI_MIDBUS_CLK100M_P AE11 CLKOUT_PEG_B_P 750
1%
1/16W
B
CLKOUTFLEX3/GPIO67 BA2 TP PCH GPIO67 CLKOUTFLEX3 8 MF LF
402
2
CLKOUT_ITPXDP_N R52 ITPXDP_CLK100M_N

CLKOUT_ITPXDP_P N52 ITPXDP_CLK100M_P
15 25 91
R1805
15 25 91
33
5%
CLKIN_GND0_N W53 PCH_CLKIN_GND0 15 92 18 15 HDA_SDOUT_R 1 8 HDA_SDOUT OUT 52 92
CLKIN_GND0_P V52 92 18 HDA_BIT_CLK_R 2 7 HDA_BIT_CLK OUT 52 92
92 18 HDA_SYNC_R 3 6 HDA_SYNC 15 52 92
OUT
CLKIN_GND1_N R27 PCH CLKIN GND1 15 92 18 HDA RST R L 4 5 HDA RST L OUT 52 92
CLKIN_GND1_P P27 1/16W

SM-LF
PLACE THIS RESISTOR PACK CLOSE TO PCH (MIN 500MIL)
CL_CLK1 BA50 TP_PCH_CL_CLK1 8
CL_DATA1 BF50 TP_PCH_CL_DATA1 8
CL_RST1* BF49 TP_PCH_CL_RST1 8
19 6 =PP3V3 G3 PCH
1 1
R1802 R1803
20K 20K
5% 5%
R1851 R1800 1 1
R1801
1/16W
MF LF
1/16W
MF LF
SSD_CLKREQ_L 1
0 2
402
2 2
402
41 15 390K 1M
5% 5%
5% 1/16W 1/16W
1/16W RTC RESET L
A MF-LF
402
MF LF
402
2 2
MF LF
402
PCH SRTCRST L
18 45
18 SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A

PCIE CLKREQ5 GPIO44 L 18 PCH INTRUDER L PAGE TITLE
NOSTUFF
PCH_INTVRMEN PCH SATA/PCIE/CLK/LPC/SPI
DRAWING NUMBER SIZE
R1852 C1802 1 1
C1803 051-9509 D
37 15 ENET_CLKREQ_L 1
0 2 1UF 1UF Apple Inc. REVISION
10% 10%
R
5%
1/16W
10V
X5R 2 2
10V
X5R 4.2.0
402 402
MF-LF
402
18 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
90 10 IN DMI_N2S_N<0> D33 DMI0RXN OMIT_TABLE FDI_RXN0 C42 PCH_FDI_RX_N<0> 8
90 10 IN DMI_N2S_N<1> A36 DMI1RXN U1800 FDI_RXN1 F45 PCH_FDI_RX_N<1> 8 8 TP_PCH_RESERVE_0 J57 OMIT_TABLE SDVO_TVCLKINN U9 TP_SDVO_TVCLKINN 8
90 10 IN DMI N2S N<2> B37 DMI2RXN PANTHER-POINTFDI_RXN2 H41 PCH FDI RX N<2> 8 8 TP PCH RESERVE 1 U43 U1800 SDVO_TVCLKINP U8 TP SDVO TVCLKINP 8
90 10 DMI_N2S_N<3> E37 DMI3RXN FCBGA FDI_RXN3 C46 PCH_FDI_RX_N<3> 8 8 TP_PCH_RESERVE_2 M49 PANTHER-POINT
IN
(3 OF 10) FCBGA
FDI_RXN4 B45 PCH_FDI_RX_N<4> 8 8 TP_PCH_RESERVE_3 M50 SDVO_STALLN U5 TP_SDVO_STALLN 8
B33 (4 OF 10)
90 10 IN DMI_N2S_P<0> DMI0RXP FDI_RXN5 B47 PCH_FDI_RX_N<5> 8 8 TP_PCH_RESERVE_4 R50 SDVO_STALLP W3 TP_SDVO_STALLP 8
D 90 10
90 10
IN
IN
DMI_N2S_P<1>
DMI_N2S_P<2>
B35
C36
DMI1RXP
DMI2RXP
FDI_RXN6 J43
FDI_RXN7 M43
PCH_FDI_RX_N<6>
PCH_FDI_RX_N<7>
8
8
8
8
TP_PCH_RESERVE_5
TP_PCH_RESERVE_6
Y41
H50 SDVO_INTN T3 TP_SDVO_INTN 8
D
90 10 DMI_N2S_P<3> F38 DMI3RXP 8 TP_PCH_RESERVE_7 U44 SDVO_INTP U2 TP_SDVO_INTP 8
IN
FDI_RXP0 B43 PCH FDI RX P<0> 8 8 TP PCH RESERVE 8 U46
90 10 OUT DMI S2N N<0> J36 DMI0TXN FDI_RXP1 F43 PCH FDI RX P<1> 8 8 TP PCH RESERVE 9 U50 SDVO_CTRLCLK AL15 DP IG B DDC CLK 8
DMI
FDI
90 10 OUT DMI S2N N<1> P38 DMI1TXN FDI_RXP2 J41 PCH FDI RX P<2> 8 8 TP PCH RESERVE 10 R44 SDVO_CTRLDATA AL17 DP IG B DDC DATA 8
22 18 6 =PP1V05_S0_PCH_VCCIO_PCIE 90 10 OUT DMI_S2N_N<2> H38 DMI2TXN FDI_RXP3 D47 PCH_FDI_RX_P<3> 8 8 TP_PCH_RESERVE_11 U49
90 10 OUT DMI_S2N_N<3> M41 DMI3TXN FDI_RXP4 A46 PCH_FDI_RX_P<4> 8 8 TP_PCH_RESERVE_12 AB44 DDPB_AUXN R9 DP_IG_B_AUX_N 8
PLACE_NEAR=U1800.E31:2mm FDI_RXP5 C49 PCH_FDI_RX_P<5> 8 8 TP_PCH_RESERVE_13 AB49 DDPB_AUXP R8 DP_IG_B_AUX_P 8

1
90 10 OUT DMI_S2N_P<0> H36 DMI0TXP FDI_RXP6 H43 PCH_FDI_RX_P<6> 8 8 TP_PCH_RESERVE_14 E52 DDPB_HPD T1 DP_IG_B_HPD 8
R1900 RESERVED
49.9 90 10 OUT DMI_S2N_P<1> R38 DMI1TXP FDI_RXP7 P43 PCH_FDI_RX_P<7> 8 8 TP_PCH_RESERVE_15 H52
1%
1/16W 90 10 OUT DMI S2N P<2> J38 DMI2TXP =PP3V3 S0 PCH GPIO 6 15 20 36 8 TP PCH RESERVE 16 F53 DDPB_0N R12 DP IG B MLN<0> 8
MF LF
402 90 10 DMI S2N P<3> P41 DMI3TXP FDI_INT H46 PCH FDI INT 8 8 TP PCH RESERVE 17 J55 DDPB_0P R14 DP IG B MLP<0> 8
2 OUT OUT
8 TP PCH RESERVE 18 L56 DDPB_1N M12 DP IG B MLN<1> 8
PCH_DMI2RBIAS A32 DMI2RBIAS FDI_FSYNC0 B51 PCH_FDI_FSYNC<0> OUT 8 8 TP_PCH_RESERVE_19 K46 DDPB_1P M11 DP_IG_B_MLP<1> 8
FDI_FSYNC1 C52 PCH_FDI_FSYNC<1> OUT 8

1
R1998 8 TP_PCH_RESERVE_20 Y50 DDPB_2N K8 DP_IG_B_MLN<2> 8
90 PCH_DMI_COMP E31 DMI_ZCOMP 10K 8 TP_PCH_RESERVE_21 AB50 DDPB_2P H8 DP_IG_B_MLP<2> 8
DIGITAL DISPLAY INTERFACE

SHORT THESE TWO PINS VERY NEAR THE PINS 5%
PLACE THE RESISTOR VERY CLOSE TO COMMON POINT B31 DMI_IRCOMP FDI_LSYNC0 E49 PCH_FDI_LSYNC<0> OUT 8 1/16W 8 TP_PCH_RESERVE_22 L53 DDPB_3N M3 DP_IG_B_MLN<3> 8
MF LF
FDI_LSYNC1 D51 PCH_FDI_LSYNC<1> OUT 8
2
402 8 TP_PCH_RESERVE_23 Y44 DDPB_3P L5 DP_IG_B_MLP<3> 8
PLACE_NEAR=U1800.A32:2mm 1 G56
R1920 8 TP_PCH_RESERVE_24
750 44 26 25 IN PM SYSRST L BE52 SYS_RESET* WAKE* BC44 PCIE WAKE L IN 19 33 38 8 TP PCH RESERVE 25 AB46 DDPC_CTRLCLK AL12 DP IG C CTRL CLK 8
1%
K49 DDPC_CTRLDATA AL14
SYSTEM POWER
1/16W 8 TP PCH RESERVE 26 DP IG C CTRL DATA 8
MANAGEMENT
MF LF
402 61 45 IN PM_PCH_SYS_PWROK BJ53 SYS_PWROK GPIO32 BC56 PCH_GPIO32 8 TP_PCH_RESERVE_27 K50
2
8 TP_PCH_RESERVE_28 M48 DDPC_AUXN U12 DP_IG_C_AUX_N 8
61 26 IN PM_PCH_PWROK BJ38 PWROK SUS_STAT*/GPIO61 BN54 LPC_PWRDWN_L OUT 26 44 46 DDPC_AUXP U14 DP_IG_C_AUX_P 8
DDPC_HPD N2 DP_IG_C_HPD 8
28 11 OUT PM_MEM_PWRGD BG46 DRAMPWROK SUSCLK/GPIO62 BA47 PM_CLK32K_SUSCLK_R OUT 45 92
C BT37 DPWROK SLP_S5*/GPIO63 BH50 PM SLP S5 L 15 33 44 60

DDPC_0N
DDPC_0P
J3
L2
DP_IG_C_MLN<0>
DP IG C MLP<0>
8
8
C
OUT
DDPC_1N G4 DP IG C MLN<1> 8
26 24 19 6 =PP3V3_S5_PCH
61 IN PM_PCH_APWROK BC46 APWROK SLP_S4* BN52 PM_SLP_S4_L OUT 15 44 60 DDPC_1P G2 DP_IG_C_MLP<1> 8
DDPC_2N F5 DP_IG_C_MLN<2> 8
1 PM_RSMRST_PCH_L BK38 RSMRST* SLP_S3* BM53 PM_SLP_S3_L DDPC_2P F3 DP_IG_C_MLP<2>
R1999 61 IN OUT 15 28 38 44 45 60 8
10K DDPC_3N E2 DP_IG_C_MLN<3> 8

5%
1/16W 15 PCH_SUSWARN_L BU46 SUSWARN*/GPIO30 SLP_A* BC41 TP_PM_SLP_A_L DDPC_3P E4 DP_IG_C_MLP<3> 8
MF LF KEEPING TP, IF NEED TO USE IT LATER
402 8 TP_CRT_IG_BLUE AM1 CRT_BLUE
2
1
44 25 15 PM PWRBTN L BT43 PWRBTN* 8 TP CRT IG GREEN AN2 CRT_GREEN DDPD_CTRLCLK AL9 DP IG D CTRL CLK 8
R1905 IN
10K 8 TP_CRT_IG_RED AN6 CRT_RED DDPD_CTRLDATA AL8 DP_IG_D_CTRL_DATA 8
5%
PCH_GPIO31_ACPRESENT BG43 GPIO31 PMSYNCH F55 PM_SYNC
CRT
1/16W OUT 11
MF LF
402 15 PCH_GPIO72 AV46 GPIO72 8 TP_CRT_IG_DDC_CLK AW3 CRT_DDC_CLK DDPD_AUXN R6 DP_IG_D_AUXN 8
2
SLP_LAN*/GPIO29 BH49 PCH_GPIO29 15 8 TP_CRT_IG_DDC_DATA AW1 CRT_DDC_DATA DDPD_AUXP N6 DP_IG_D_AUXP 8
PCH_RI_L BJ48 RI* DDPD_HPD M1 DP_IG_D_HPD 8
8 TP_CRT_IG_HSYNC AR4 CRT_HSYNC

DF_TVS R47 PCH_DF_TVS 19 8 TP_CRT_IG_VSYNC AR2 CRT_VSYNC DDPD_0N B5 DP_IG_D_MLN<0> 8
DDPD_0P D5 DP_IG_D_MLP<0> 8
8 TP_PCH_INIT3V3_L BN56 INIT3_3V* DSWVRMEN BR42 PCH_DSWVRMEN 19 PCH_DAC_IREF AT3 DAC_IREF DDPD_1N D7 DP_IG_D_MLN<1> 8
PLACE_NEAR=U1800.AT3:3mm AM6 CRT_IRTN DDPD_1P C6 DP_IG_D_MLP<1> 8
SLP_SUS* BD43 TP_PCH_SLP_SUS_L 1 DDPD_2N C9 DP_IG_D_MLN<2>

R1909
1 R1951 8
1K DDPD_2P B7 DP_IG_D_MLP<2> 8
10K 5%
5%
1/16W
SUSACK* BP45 TP_PCH_SUSACK_L 1/16W DDPD_3N B11 DP_IG_D_MLN<3> 8
MF LF
MF LF
DDPD_3P E11 DP_IG_D_MLP<3>
402
2
2 402 8
PLACE CLOSE TO U1800 PIN
B B
=PP1V8 S0 PCH 6
=PP3V3_S5_PCH 6 19 24 26
=PP3V3_G3_PCH 6 18
1
1 R1925 1
R1915 1K R1981
390K 1% 2.2K
5% 1/16W 5%
1/16W MF LF 1/16W
MF LF 402 2 MF LF
402 402
2 2
R1980
4.7K
19 PCH_DF_TVS 2 1 CPU_PROC_SEL 11
5%
PCIE WAKE L
38 33 19 =TBT WAKE L 34 1/16W
PCH_DSWVRMEN 19 MAKE_BASE=TRUE MF LF
402

PAGE TITLE
PCH DMI/FDI/GRAPHICS
DRAWING NUMBER SIZE

REVISION
R
4.2.0
19 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 TP_PCI_AD<0> BF15 AD0 OMIT_TABLE USBP0N BF36 USB_PCH_0_N BI 42 93

EXT A
8 TP_PCI_AD<1> BF17 AD1 U1800 USBP0P BD36 USB_PCH_0_P BI 42 93
8 TP_PCI_AD<2> BT7 AD2 PANTHER-POINT

8 TP_PCI_AD<3> BT13 AD3 FCBGA USBP1N BC33 USB_PCH_1_N 42 93
BI
(5 OF 10)
8 TP PCI AD<4> BG12 AD4 USBP1P BA33 USB PCH 1 P BI 42 93 EXT B
8 TP_PCI_AD<5> BN11 AD5
8 TP_PCI_AD<6> BJ12 AD6 USBP2N BM33 USB_PCH_2_N BI 43 93
8 TP_PCI_AD<7> BU9 AD7 USBP2P BM35 USB_PCH_2_P BI 43 93 EXT C
D 8
8
TP_PCI_AD<8>
TP_PCI_AD<9>
BR12
BJ3
AD8
AD9 USBP3N BT33 USB_PCH_3_N BI 43 93
D
8 TP_PCI_AD<10> BR9 AD10 USBP3P BU32 USB_PCH_3_P BI 43 93 EXT D
8 TP PCI AD<11> BJ10 AD11
8 TP PCI AD<12> BM8 AD12 USBP4N BR32 USB PCH 4 N BI 8
TP PCI AD<13> BF3 USB PCH 4 P UNUSED

8 AD13 USBP4P BT31 BI 8
8 TP_PCI_AD<14> BN2 AD14

8 TP_PCI_AD<15> BE4 AD15 USBP5N BN29 USB_PCH_5_N BI 8
TP_PCI_AD<16> BE6 USB_PCH_5_P UNUSED

8 AD16 USBP5P BM30 BI 8
8 TP_PCI_AD<17> BG15 AD17

8 TP_PCI_AD<18> BC6 AD18 USBP6N BK33 USB_PCH_6_N BI 8
8 TP PCI AD<19> BT11 AD19 USBP6P BJ33 USB PCH 6 P BI 8 UNUSED

8 TP PCI AD<20> BA14 AD20
8 TP PCI AD<21> BL2 AD21 USBP7N BF31 USB PCH 7 N BI 27 93
TP_PCI_AD<22> BC4 USB_PCH_7_P INTERNAL HUB (BT,SMC12)

8 AD22 USBP7P BD31 BI 27 93
8 TP_PCI_AD<23> BL4 AD23

8 TP_PCI_AD<24> BC2 AD24 USBP8N BN27 USB_PCH_8_N BI 40
TP_PCI_AD<25> BM13 USB_PCH_8_P CAMERA

8 AD25 USBP8P BR29 BI 40
8 TP_PCI_AD<26> BA9 AD26

8 TP_PCI_AD<27> BF9 AD27 USBP9N BR26 USB_PCH_9_N BI 42 93
TP PCI AD<28> BA8 USB PCH 9 P EHCI - EXT B

8 AD28 USBP9P BT27 BI 42 93
8 TP PCI AD<29> BF8 AD29

8 TP_PCI_AD<30> AV17 AD30 USBP10N BK25 USB_PCH_10_N BI 43 93
8 TP_PCI_AD<31> BK12 AD31 USBP10P BJ25 USB_PCH_10_P BI 43 93 EHCI - EXT D
USB
8 TP_PCI_C_BE_L<0> BN4 C/BE0* USBP11N BJ31 USB_PCH_11_N BI 8
8 TP_PCI_C_BE_L<1> BP7 C/BE1* USBP11P BK31 USB_PCH_11_P BI 8 UNUSED

C 8
8
TP_PCI_C_BE_L<2>
TP PCI C BE L<3>
BG2
BP13
C/BE2*
C/BE3* USBP12N BF27 USB PCH 12 N 8
C
=PP3V3_S0_PCH_GPIO BI
36 19 15 6
USBP12P BD27 USB PCH 12 P BI 8 UNUSED
R2010 10K 1 2 PCI_INTA_L BK10 PIRQA*
5% 1/16W MF-LF 402
R2011 10K 1 2 PCI_INTB_L BJ5 PIRQB* USBP13N BJ27 USB_PCH_13_N BI 8
PCI
R2012 10K 5% 1/16W MF-LF 402
1 2 PCI_INTC_L BM15 PIRQC* USBP13P BK27 USB_PCH_13_P BI 8 UNUSED
R2013 10K 5% 1/16W MF-LF 402
1 2 PCI_INTD_L BP5 PIRQD*
5% 1/16W MF-LF 402
USBRBIAS* BP25 93 PCH_USB_RBIAS
R2015 10K 1 2 PCI_REQ0_L BG5 REQ0* USBRBIAS BM25
TIE TRACES TOGETHER CLOSE TO PINS
5% 1/16W MF-LF 402
R2016 10K 1 2 JTAG GMUX TMS BT5 REQ1*/GPIO50
PLACE THE RESISTOR CLOSE TO COMMON POINT
R2017 10K 5% 1/16W MF-LF 402 PLACE_NEAR=U1800.BM25:2mm

1 2 BLC_I2C_MUX_SEL BK8 REQ2*/GPIO52 USB3RP1 J31 USB3_EXTA_RX_F_P IN 42 93
1
5% 1/16W MF-LF 402
33 15 OUT BT_PWR_RST_L AV11 REQ3*/GPIO54 R2070
22.6
USB3RN1 H31 USB3_EXTA_RX_F_N IN 42 93 1%
1/16W
TP_PCH_PCI_GNT0_L BA15 GNT0* MF-LF
TP_PCH_STRP_BBS1 AV8 GNT1*/GPIO51 USB3TP1 E29 USB3_EXTA_TX_P 42 93
2 402
OUT
TP_PCH_STRP_ESI_L BU12 GNT2*/GPIO53
PCH_STRP_TOPBLK_SWP_L BE2 GNT3*/GPIO55 USB3TN1 C29 USB3_EXTA_TX_N OUT 42 93
NOSTUFF1
R2030 10K 1 2 BLC_GPIO BN9 PIRQE*/GPIO2 USB3RP2 L27 USB3_EXTB_RX_F_P IN 42 93
5% 1/16W MF-LF 402
R2019 58 IN AUD_IP_PERIPHERAL_DET AV9 PIRQF*/GPIO3
10K 34 15 IN TBT_PWR_REQ_L BT15 PIRQG*/GPIO4 USB3RN2 J27 USB3_EXTB_RX_F_N IN 42 93
5%
1/16W 56 IN AUD_I2C_INT_L BR4 PIRQH*/GPIO5
MF-LF
402 2 USB3TP2 E27 USB3_EXTB_TX_P OUT 42 93
8 TP_PCI_RESET_L AV14 PCIRST*

USB3TN2 F28 USB3 EXTB TX N OUT 42 93
R2020 10K 1 2 PCI_SERR_L BR6 SERR*
R2021 10K 5% 1/16W MF-LF 402
B 1 2
5% 1/16W MF-LF 402
PCI_PERR_L BM3 PERR* USB3RP3 L25 USB3_EXTC_RX_F_P IN 43 93
B
R2022 10K 1 2 PCI_IRDY_L BF11 IRDY* USB3RN3 J25 USB3_EXTC_RX_F_N IN 43 93
5% 1/16W MF-LF 402
8 TP_PCI_PAR BH8 PAR
R2023 10K 1 2 PCI_DEVSEL_L BH9 DEVSEL* USB3TP3 B27 USB3_EXTC_TX_P OUT 43 93
5% 1/16W MF-LF 402
R2024 10K 1 2 PCI FRAME L BC11 FRAME*
5% 1/16W MF-LF 402
USB3TN3 C26 USB3 EXTC TX N OUT 43 93
R2027 10K 1 2 PCI PLOCK L BA17 PLOCK*
5% 1/16W MF-LF 402
USB3RP4 J22 USB3_EXTD_RX_F_P IN 43 93
R2025 10K 1 2 PCI_STOP_L BC12 STOP*

R2026 10K 5% 1/16W MF-LF 402
1 2 PCI_TRDY_L BC8 TRDY* USB3RN4 L22 USB3_EXTD_RX_F_N IN 43 93
5% 1/16W MF-LF 402
TP_PCI_PME_L AV15 PME* USB3TP4 D25 USB3_EXTD_TX_P OUT 43 93
26 OUT PLT RESET L BK48 PLTRST* USB3TN4 B25 USB3 EXTD TX N OUT 43 93
92 26 OUT LPC_CLK33M_SMC_R AT11 CLKOUT_PCI0 OC0*/GPIO59 BM43 25 USB_EXTA_OC_R_L R2001 0 1 2 USB_EXTA_OC_L IN 15 42
92 26 OUT LPC_CLK33M_LPCPLUS_R AN14 CLKOUT_PCI1 OC1*/GPIO40 BD41 25 USB_EXTB_OC_R_L R2002 0 1 2

5%
5%
1/20W
1/20W
MF
MF
201
201
USB_EXTB_OC_L IN 15 42
8 TP_PCI_CLK33M_OUT2 AT12 CLKOUT_PCI2 OC2*/GPIO41 BG41 25 USB_EXTC_OC_R_L R2003 0 1 2 USB_EXTC_OC_L IN 15 43
8 TP_PCI_CLK33M_OUT3 AT17 CLKOUT_PCI3 OC3*/GPIO42 BK43 25 USB_EXTD_OC_R_L R2004 0 1 2

5%
5%
1/20W
1/20W
MF
MF
201
201
USB_EXTD_OC_L IN 15 43
92 26 OUT PCH_CLK33M_PCIOUT AT14 CLKOUT_PCI4 OC4*/GPIO43 BP43 25 USB_EXTB_OC_EHCI_R_L R2005 0 1 2

5% 1/20W MF 201
USB_EXTB_OC_EHCI_L IN 15
OC5*/GPIO9 BJ41 25 USB_EXTD_OC_EHCI_R_L R2006 0 1 2 USB_EXTD_OC_EHCI_L IN 15
OC6*/GPIO10 BT45 25 AP PWR EN R R2007 0 1 2

5%
5%
1/20W
1/20W
MF
MF
201
201
AP PWR EN OUT 15 33
OC7*/GPIO14 BM45 25 SDCONN STATE CHANGE R R2008 0 1 2

5% 1/20W MF 201
SDCONN STATE CHANGE IN 15 39
SIGNAL_MODEL=EMPTY
A SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY PAGE TITLE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY PCH PCI/USB
DRAWING NUMBER SIZE

REVISION
R
4.2.0
20 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SIGNAL_MODEL=EMPTY
=PP3V3 S0 PCH
34 15 TBT_CIO_PLUG_EVENT R2101 0 1 2
5%
25 TBT_CIO_PLUG_EVENT_R
1/20W MF 201
AW55 BMBUSY*/GPIO0 OMIT_TABLE CLKOUT_PCIE6N AB3 TP_PCIE_CLK100M_PE6N 8
6 18 21 24
U1800 CLKOUT_PCIE6P AA2 TP_PCIE_CLK100M_PE6P 8
15 PCH_GPIO1 BR19 TACH1/GPIO1 PANTHER-POINT

FCBGA CLKOUT_PCIE7N AE2 TP PCIE CLK100M PE7N 8
R2150 1
D 15 PCH GPIO6 BA22 TACH2/GPIO6 (6 OF 10)
CLKOUT_PCIE7P AF1 TP PCIE CLK100M PE7P 8
10K
5%
1/16W
1
R2155
D
MF LF
402 10K
44 15 SMC_RUNTIME_SCI_L BR16 TACH3/GPIO7 A20GATE BB57 PCH_A20GATE 2
5%
IN
1/16W
MISC NOSTUFF MF LF
24 21 18 6 =PP3V3_S0_PCH 8 TP_PCH_GPIO8 BP51 GPIO8 R2170 2

402
0
PECI H48 PCH_PECI 1 2 CPU_PECI BI 11 44 45
1/16W MF LF
38 15 WOL_EN BK50 LAN_PHY_PWR_CTRL/GPIO12 5% Place this near the T point
R21901 RCIN* BG56 PCH RCIN L
402
CPU
100K R2140
5% 25 XDP PIN03 BM55 GPIO15
1/16W 0
PROCPWRGD D53 PCH_PROCPWRGD 1 2 CPU_PWRGD
MF LF
402
2 AUD_IPHS_SWITCH_EN_PCH 0 R2103
1 2 25 AUD_IPHS_SWITCH_EN_PCH_R AU56 SATA4GP/GPIO16
1/16W
5%
MF LF OUT 11 25
NCTF
26 OUT
5% 1/20W MF 201 402
46 IN
SIGNAL_MODEL=EMPTY
LPCPLUS_GPIO BT17 TACH0/GPIO17 X THRMTRIP* E56 PM_THRMTRIP_L IN 45
TP1 P22 TP_PCH_TP1 8
GPIO
15 PCH_GPIO22 BA53 SCLOCK/GPIO22
TP2 L31 TP PCH TP2 8
34 15 TBT GO2SX BIDIR BP53 GPIO24/PROC_MISSING

TP3 L33 TP_PCH_TP3 8
44 15 SMC_WAKE_SCI_L BJ43 GPIO27

SIGNAL_MODEL=EMPTY R2104 TP4 M38 TP_PCH_TP4 8
32 28 OUT ISOLATE_CPU_MEM_L 0 1 2 25 ISOLATE_CPU_MEM_R_L BJ55 GPIO28

5% 1/20W MF 201
TP5 L36 TP_PCH_TP5
SIGNAL_MODEL=EMPTY
TBT_SW_RESET_L 0 1 R2105
2 15 TBT_SW_RESET_R_L BL56 STP_PCI*/GPIO34
8
36 OUT
5% 1/20W MF 201
TP6 Y18 TP PCH TP6
5 GPU GOOD
SIGNAL_MODEL=EMPTY
0 R2106
1 2 25 GPU GOOD R BJ57 GPIO35/NMI*
8
OUT
5% 1/20W MF 201
TP7 Y17 TP PCH TP7
SIGNAL_MODEL=EMPTY
0 R2107 BB55 SATA2GP/GPIO36
8
C 82 58 OUT DP_GPU_TBT_SEL
SIGNAL_MODEL=EMPTY
1 2
R2108
5%
25 DP_GPU_TBT_SEL_R
1/20W MF 201
TP8 AB18 TP_PCH_TP8 8
C
34 15 OUT JTAG_TBT_TCK 0 1 2 25 JTAG_TBT_TCK_R BG53 SATA3GP/GPIO37
5% 1/20W MF 201
TP9 AB17 TP_PCH_TP9 8
34 15 JTAG_TBT_TDO BE54 SLOAD/GPIO38

IN
TP10 BM46 TP_PCH_TP10 8
34 15 JTAG TBT TDI BF55 SDATAOUT0/GPIO39

TP11 BA27 TP_PCH_TP11 8
33 15 IN AP_CLKREQ_L AV44 PCIECLKRQ6*/GPIO45

TP12 BC49 TP_PCH_TP12 8
36 15 IN TBT_CLKREQ_L BP55 PCIECLKRQ7*/GPIO46

TP13 AE49 TP_PCH_TP13 8
15 PCH_GPIO48 AW53 SDATAOUT1/GPIO48

TP14 AE41 TP_PCH_TP14
26 15 ENET_LOW_PWR_PCH 0 R2109
1 2 25 ENET_LOW_PWR_PCH_R BA56 SATA5GP_GPIO49
8
OUT
5% 1/20W MF 201
SIGNAL_MODEL=EMPTY TP15 AE43 TP_PCH_TP15 8
92 46 IN SPIROM_USE_MLB BT53 GPIO57

TP16 AE50 TP_PCH_TP16
PCH_CAM_EXT_BOOT_R 33 1 R2110
2 15 PCH_CAM_EXT_BOOT BU16 TACH4/GPIO68
8
40 OUT
5% 1/20W MF 201
TP17 BA36 TP_PCH_TP17
40 PCH_CAM_RESET_R 33 1 R2111
2 15 PCH_CAM_RESET BM18 TACH5/GPIO69
8
OUT
5% 1/20W MF 201
TP18 AY36 TP PCH TP18 8
15 MLB_RAM_CFG1 BN17 TACH6/GPIO70

TP19 Y14 TP_PCH_TP19 8
15 MLB_RAM_CFG0 BP15 TACH7/GPIO71

TP20 Y12 TP_PCH_TP20 8
RSVD
8 TP_PCH_PWM0 BN21 PWM0
B 8 TP_PCH_PWM1 BT21
BM20
PWM1 B
8 TP PCH PWM2 PWM2
8 TP PCH PWM3 BN19 PWM3
8 TP_PCH_SST BC43 SST
A4
A6
B2
NCTF
BM1
BM57
BP1
BP57
BT2
VSS_NCTF
BU4
BU52
BU54
BU6
D1
F1
A54 NC_1
A52 NC_2
F57 NC_3
D57 NC_4
A AU2 VSSADAC NC_5 AY20 NC SYNC MASTER=D7 TONY SYNC DATE=01/11/2012 A

PAGE TITLE
PCH MISC
DRAWING NUMBER SIZE

REVISION
R
4.2.0
21 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OMIT_TABLE
U1800
PANTHER-POINT OMIT_TABLE
FCBGA
(10 OF 10)
U1800
8 PP1V05_S0_PCH_VCC_A_CLK AL5 VCCACLK AY25 =PP1V05_S0_PCH_VCCIO_USB 6 PANTHER-POINT
AY27 FCBGA
AV41 DCPSUSBYP VCCIO AV24 (7 OF 10)
8 TP_PPVOUT_PCH_DCPSUSBYP 17 PP3V3_S0_PCH_VCCA_DAC_F
AV26 AT1 VCCADAC AC24
CRT
Max and Idle = 1 MA =PP1V05_S0_PCH_VCC_CORE 6 24
CLOCK AND MISCELLANEOUS

PCH output, for decoupling only BR54 DCPRTC AC26
PPVOUT_G3_PCH_DCPRTC 1.44 A Max, 474mA Idle
MIN NECK WIDTH=0 2 mm
MIN LINE WIDTH=0 2 mm U31 =PP3V3_S5_PCH_VCCSUS_USB 6 24 24 22 PP1V8_S0_PCH_VCCVRM_F AC28
1
C2210 VOLTAGE=3 3V
BT56 DCPRTC_NCTF AV30 97mA Max, 15mA Idle 159mA Max, 114mA Idle R56 VCCVRM1 AC30
0.1UF (VCCVRM 4 total)
(VCCSUS3_3 - 11 TOTAL)
USB
DMI
20% AV32 AC32
10V
2 CERM
24 22 PP1V8_S0_PCH_VCCVRM_F R54 VCCVRM2 AY31 24 6 =PP1V05_S0_PCH_VCC_DMI E41 AE24
402
AY33 57 mA Max, 30mA Idle B41 VCCDMI AE28
PLACE_NEAR=U1800.BR54:2mm
VCC CORE
24 17 PP1V05_S0_PCH_VCCADPLLA_F AB1 VCCADPLLA VCCSUS3_3 BJ36 AE30
40mA Max, 5mA Idle BK36 Y30 AE32
6 =PP1V05_S0_PCH_VCCIO_DMI
24 17 PP1V05_S0_PCH_VCCADPLLB_F AC2 VCCADPLLB BM36 Y32 AE34
40mA Max, 10mA Idle AT40 AA34 AE36
VCCIO_DMI/CLK
AU38 Y34 AG32
BT35 AA36 VCCCORE AG34
Y36 VCCIO AJ32
PCH output, for decoupling only V33 AJ34
C MIN LINE WIDTH=0 2 mm
PPVOUT_S0_PCH_DCPSST
MIN NECK WIDTH=0 2 mm VOLTAGE=3 3V
BA46 DCPSST V5REF_SUS BT25 =PP5V_S5_PCH_V5REFSUS
Max and Idle = 1mA
24
V36 AJ36 C
V31 AL32
PLACE_NEAR=U1800.BA46:2mm AA32 F30 AL34
TP_DCPSUS_0
1
C2222 AT41
0.1UF TP_DCPSUS_1 DCPSUS V5REF BF1 =PP5V_S0_PCH_V5REF 24 AN32
10% A39 Max and Idle = 1mA AN34
6 3V
TP_DCPSUS_2
2 X5R A12 AF57 VCC3_3_0 AR32
PCI/GPIO/LPC
201
=PP3V3 S0 PCH VCC PCI 6 24 24 6 =PP3V3 S0 PCH VCC
PCI/GPIO/LPC
AU20 409 mA Max, 42mA Idle 8 PP1V05_S0_PCH_VCCAPLL_EXP B53 VCCAPLLEXP AR34
VCC3_3 (VCC3_3[1-9] total)
AL38 AV20
24 6 =PP3V3_S0_PCH_VCC_GPIO
AN38 PP1V8_S0_PCH_VCCVRM_F AJ1 VCCVRM0 =PP3V3_S0_PCH_VCC_HVCMOS
FDI
24 22 6 24
VCC3_3
HVCMOS
Need to check layout decoupling AU22 BC17
AJ38 =PP1V05_S0_PCH_VCCIO_SATA 6 18 24 BD17
VCC3_3
AE40 24 6 =PP1V05_S0_PCH_VCC_ASW AU32 BD20
AG40 AV36
VCCASW
1.61A Max, 433mA Idle
AG38 AU34
SATA
CPU
24 6 =PP1V05_S0_PCH_V_PROC_IO D55 V_PROC_IO VCCIO AG41 AG24 VCCAFDIPLL C54 PP1V05_S0_PCH_FDIPLL 8

Max and Idle = 1mA B56 V_PROC_IO_NCTF BA38 AG26
AN40 AG28 VCCAPLLDMI2 A19 PP1V05_S0_PCH_VCCAPLLDMI2 8
This should stay as RTC, correct? AN41 AJ24

RTC
26 6 PP3V3_G3H_RTC BU42 VCCRTC AL40 AJ26 VCCCLKDMI AJ20=PP1V05_S0_PCH_VCCCLKDMI 24

AJ28 20mA Max, 10mA Idle
1
C2231 1
C2232 =PP1V8 S0 PCH VCC DFTERM T55 VCCDFTERM0 AL24 Y20 =PP1V05 S0 PCH VCCIO PCIE
VCCIO_PCIE
24 6 6 18 19
1UF 0.1UF 200 mA Max, 2mA Idle T57 VCCDFTERM1 AL28 Y22 3.456A Max 426mA Idle
10% 20%
(VCCIO[1-31] total)
2
6 3V
CERM 2
10V
CERM VCCAPLLSATA U56 PP1V05_S0_PCH_VCCAPLL_SATA 8 AN22 Y24
402 402
6 =PP1V05_S0_PCH_VCC_DIFFCLK AE15 AN24 VCCASW Y26
55mA Max, 5mA Idle AE17 AN26 Y28
VCCDIFFCLKN VCCIO
AG15 VCCVRM3 R2 PP1V8_S0_PCH_VCCVRM_F 22 24
AN28 V22
B PLACE_NEAR=U1800.BU42:2mm
PLACE_NEAR=U1800.BU42:2mm AV40 VCCDSW3_3
AR24
AR26
V25
V27
B
24 6 =PP3V3 S5 PCH VCC DSW
3mA Max, 1mA Idle
VCCSUSHDA AV28 =PP3V3 S5 PCH VCCSUS HDA 6 24 AR28 F20
AN52 VCCSPI 10 mA Max, 1mA Idle AR30
24 6 =PP3V3_S5_PCH_VCC_SPI
20mA Max, 1mA Idle AR36
AC20 AR38
HDA
6 =PP1V05_S0_PCH_VCC_SSC
105mA Max, 90mA Idle AE20 VCCSSC AU30
AU36

PAGE TITLE
PCH POWER
DRAWING NUMBER SIZE

REVISION
R
4.2.0
22 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
OMIT_TABLE
U1800 U1800
PANTHER-POINT PANTHER-POINT
AE56 FCBGA AN12
(8 OF 10) BG38 FCBGA J46
BR36 AN15 (9 OF 10)
BH52 J48
C12 AN17
BH6 J5
AY22 AN18
BJ1 J53
A26 AN20
D A29
A42
AN30
AN36
BJ15
BK20
K52
K6
D
BK41 K9
A49 AN4
BK52 L12
A9 AN43
BK6 L17
AA20 AN47
BM10 L38
AA22 AN54
BM12 L41
AA24 AN9
BM16 L43
AA26 AR20
BM22 M20
AA28 AR22
BM23 M22
AA30 AR52
BM26 M25
AA38 AR6
BM28 M27
AB11 AT15
BM32 M31
AB15 AT18
BM40 M33
AB40 AT43
BM42 M36
AB41 AT47
BM48 M46
AB43 AT52
BM5 M52
AB47 AT6
BN31 M57
AB52 AT8
BN47 M6
AB57 AU24
BN6 M8
AB6 AU26
BP3 M9
AC22 AU28
BP33 N4
AC34 AU5
BP35 N54
AC36 AV12
BR22 R11
AC38 AV18
BR52 R15
AC4 AV22
BU19 R17
AC54 AV34
BU26 R22
AE14 AV38
C AE18 AV47
BU29
BU36
R4
R41
C
AE22 AV6
BU39 R43
AE26 AW57
C19 R46
AE38 AY38
C32 R49
AE4 AY6 VSS
C39 T52
AE47 B23 VSS
VSS C4 T6
AE8 VSS BA11
D15 U11
AE9 BA12
D23 U15
AF52 BA31
D3 U17
AF6 BA41
D35 U20
AG11 BA44
D43 U22
AG14 BA49
D45 U25
AG20 BB1
E19 U27
AG22 BB3
E39 U33
AG30 BB52
E54 U36
AG36 BB6
E6 U38
AG43 BC14
E9 U41
AG44 BC15
F10 U47
AG46 BC20
F12 U53
AG5 BC27
F16 V20
AG50 BC31
F22 V38
AG53 BC36
F26 V6
AH52 BC38
F32 W1
AH6 BC47
F33 W55
AJ22 BC9
F35 W57
AJ30 BD25
B AJ57
AK52
BD33
BF12
F36
F40
Y11
Y15
B
F42 Y38
AK6 BF20
F46 Y40
AL11 BF25
F48 Y43
AL18 BF33
F50 Y46
AL20 BF41
F8 Y47
AL22 BF43
G54 Y49
AL26 BF46
H15 Y52
AL30 BF52
H20 Y6
AL36 BF6
H22 AL43
AL41 BG22
H25 AL44
AL46 BG25
H27 R36
AL47 BG27
H33 P36
AM3 BG31
H6 R25
AM52 BG33
J1 P25
AM57 BG36
J33
AN11

PAGE TITLE
PCH GROUNDS
DRAWING NUMBER SIZE

REVISION
R
4.2.0
23 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Sequencing 1V05 S0 Rails
21 18 6 =PP3V3_S0_PCH
6 =PP5V_S0_PCH PCH V5REF Filter & Follower =PP1V05_S0_PCH_VCCCLKDMI 22
22 6 =PP1V05_S0_PCH_VCC_CORE
1 mA (PCH Reference for 5V Tolerance on PCI)
PLACE_NEAR=U1800.Y20:2mm 18 6 =PP1V05 S0 PCH
D R2405
100
2 A
D2400
SOD-523
1 C2471
22UF
1
C2481
1UF
1
C2482
1UF
1
C2483
1UF
1
C2400
1UF
1 C2460
10UF
1 C2461
10UF
D
5%
1/16W BAT54XV2T1 20%
6 3V
10%
6 3V
10%
6 3V
10%
6 3V
10%
6 3V
20%
6 3V
20%
6 3V
MF LF K 2 CERM 2 2 2 2 2 X5R 2 X5R 1 C2411
CERM CERM CERM CERM
402 1 805 402 402 402 402 603 603 1UF
10%
PP5V_S0_PCH_V5REF 2 16V
X5R
MIN LINE WIDTH=0 3MM PLACE_NEAR=U1800.F20:2mm 402
PLACE_NEAR=U1800.BF1:2mm MIN NECK WIDTH=0 25MM <1 MA PLACE_NEAR=U1800.AC24:2mm
VOLTAGE=5V PLACE_NEAR=U1800.AC20:2mm PLACE_NEAR=U1800.AJ20:2mm
C2439 1
MAKE BASE=TRUE PLACE_NEAR=U1800.AE15:2mm
1UF PLACE_NEAR=U1800.AA34:2mm
10%
=PP5V_S0_PCH_V5REF 22
10V
X5R 2
402
22 6 =PP1V05_S0_PCH_VCC_ASW
PLACE_NEAR=U1800.AN24:2mm
1 C2470 1
C2426 1
C2456 1 C2496 1 C2428
22UF 1UF 1UF 1.0UF 10UF
20% 10% 10% 20% 20%
26 19 6 =PP3V3 S5 PCH 2 6 3V
CERM 2
6 3V
CERM 2
6 3V
CERM 2 6 3V
X5R
6 3V
2 X5R
=PP5V S5 PCH 805 402 402 0201 MUR 603
6 PCH V5REF_SUS Filter & Follower
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB) PLACE_NEAR=U1800.AJ24:2mm
A PLACE_NEAR=U1800.AN22:2mm
R2404 2 D2401 PLACE_NEAR=U1800.AN22:2mm
10 SOD-523
5%
1/16W BAT54XV2T1
MF LF K
402
1
PP5V_S5_PCH_V5REFSUS
MIN LINE WIDTH=0 3MM
PLACE_NEAR=U1800.BT25:2mm MIN NECK WIDTH=0 25MM <1 MA S0-S5 22 18 6 =PP1V05_S0_PCH_VCCIO_SATA
VOLTAGE=5V
C2438 1 MAKE BASE=TRUE PLACE_NEAR=U1800.AJ38:2mm
0.1UF =PP5V S5 PCH V5REFSUS 1 C2452 1 C2453
C
20%
10V
CERM
402
2
22
2
1UF
10%
6 3V
2
1UF
10%
6 3V
C
CERM CERM
402 402
PLACE_NEAR=U1800.AG38:2mm
22 6 =PP1V05_S0_PCH_V_PROC_IO
1V8 S0 Rails PLACE_NEAR=U1800.D55:2mm
1 C2416 1 C2417 1 C2430
4.7UF 0.1UF 0.1UF
6 =PP1V8_S0_PCH_VCC_VRM R2400 20% 10% 10%
0 6 3V 16V 16V
2 X5R 2 X5R 2 X5R
1 2 PP1V8_S0_PCH_VCCVRM_F 402 402 402
MIN LINE WIDTH=0 5MM
5% MIN NECK WIDTH=0 25MM
1/16W VOLTAGE=1 8V
MF LF
402
MAKE BASE=TRUE
1
C2447 1
C2436 1
C2443 1 C2445 PLACE_NEAR=U1800.D55:2mm
PLACE_NEAR=U1800.D55:2mm
0.1UF 1UF 1UF 10UF
10% 10% 10% 20%
16V 6 3V 6 3V 6.3V
2 X5R 2 CERM 2 CERM 2 X5R
402 402 402 603
PLACE_NEAR=U1800.R56:2mm PLACE_NEAR=U1800.AJ1:2mm 22 6 =PP1V05_S0_PCH_VCC_DMI

22 6 =PP1V8_S0_PCH_VCC_DFTERM PLACE_NEAR=U1800.R54:2mm PLACE_NEAR=U1800.E41:2mm
PLACE_NEAR=U1800.T55:2mm 1
C2487
1
C2440 1UF
0.1UF 10%
20% 6 3V
10V 2 CERM
2 CERM 402
402
B B
22 17 PP1V05_S0_PCH_VCCADPLLA_F 22 17 PP1V05_S0_PCH_VCCADPLLB_F
PLACE_NEAR=U1800.AB1:2mm PLACE_NEAR=U1800.AC2:2mm
1 C2490 1 C2491
1UF 1UF
3V3 S5 Rails 2
10%
6 3V
CERM
402
2
10%
6 3V
CERM
402
22 6 =PP3V3_S5_PCH_VCCSUS_USB
PLACE_NEAR=U1800.BT35:2mm
1 C2484 1 C2455 1 C2413
0.1UF 2.2UF 0.1UF
10% 10% 10%
16V 16V 16V
2 X5R 2 X5R 2 X5R
402 603 402
PLACE_NEAR=U1800.U31:2mm
PLACE_NEAR=U1800.AV30:2mm
22 6 =PP3V3 S5 PCH VCC DSW 22 6 =PP3V3 S5 PCH VCCSUS HDA

PLACE_NEAR=U1800.AV40:2mm
C2499 1 PLACE_NEAR=U1800.AV28:2mm 1
C2441
0.1UF
20%
10V
0.1UF
20%
3V3 S0 Rails
A CERM
402
2
2
10V
CERM
402 SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A
PAGE TITLE
22 6 =PP3V3_S0_PCH_VCC_HVCMOS 22 6 =PP3V3_S0_PCH_VCC 22 6 =PP3V3_S0_PCH_VCC_GPIO 22 6 =PP3V3_S0_PCH_VCC_PCI

PCH DECOUPLING
22 6 =PP3V3_S5_PCH_VCC_SPI DRAWING NUMBER SIZE
PLACE_NEAR=U1800.AN52:2mm
1 C2442 1 C2424 1 C2427
PLACE_NEAR=U1800.AF57:2mm
1 C2485
PLACE_NEAR=U1800.A12:2mm
1 C2421 1 C2422 Apple Inc. 051-9509 D
1UF 0.1UF 0.1UF
1 C2423 0.1UF 0.1UF 1UF REVISION
R
2
10%
6 3V
2
10%
16V
2
10%
16V
0.1UF
10%
2
10%
6 3V
2
10%
16V
2
10%
6 3V 4.2.0
CERM X5R X5R 16V X5R X5R CERM
402 402 402 2 X5R 201 402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
402
PLACE_NEAR=U1800.BC17:2mm PLACE_NEAR=U1800.AL38:2mm PLACE_NEAR=U1800.AU20:2mm PROPRIETARY PROPERTY OF APPLE INC.
PLACE_NEAR=U1800.BC17:2mm I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
24 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Micro2-XDP 25 6 =PPVCCIO_S0_XDP
25 6 =PPVCCIO_S0_XDP CRITICAL
XDP_CONN XDP XDP XDP
J2500.52:10MM U1000.L40:10MM U1000.L38:10MM
J2500 1
R2510 1
R2511 1
R2512
DF40RC-60DP-0.4V
M-ST-SM 51 51 51
5% 5% 5%
62 61 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
2 402 2 402 2 402
91 25 11 XDP CPU TDO
D 2
4
1
3
91 25 11 XDP CPU TDI D
11 BI XDP_CPU_PREQ_L obsen_a0 obsen_c0 CPU_CFG<16> IN 10 91 91 25 11 XDP_CPU_TMS
11 XDP_CPU_PRDY_L obsen_a1 6 5 obsen_c1 CPU_CFG<17> 10 91 91 25 11 XDP_CPU_TCK
IN IN
91 11 XDP_BPM_L<4> 8 7 25 11 XDP_CPU_TRST_L
IN
91 11 XDP_BPM_L<5> 91 11 XDP_BPM_L<0> obsdata_a0 10 9 obsdata_c0 CPU_CFG<0> 10 25 91 XDP XDP
IN IN IN
91 11 XDP_BPM_L<6> 91 11 XDP_BPM_L<1> obsdata_a1 12 11 obsdata_c1 CPU_CFG<1> 10 91 U1000.J39:10MM U1000.M40:10MM
IN IN IN
XDP_BPM_L<7> 14 13 1 1
91 11 IN R2513 R2514
91 11 XDP BPM L<2> obsdata_a2 16 15 obsdata_c2 CPU CFG<2> 10 15 91 51 51
IN IN
18 17 5% 5%
91 11 IN XDP BPM L<3> obsdata_a3 obsdata_c3 CPU CFG<3> IN 10 15 91 1/16W 1/16W
20 19 MF-LF MF-LF
XDP 2 402 2 402
U1000.J40:10MM 91 10 CPU_CFG<10> obsen_b0 22 21 obsen_d0 CPU_CFG<8> 10 91
IN IN
1K CPU_CFG<11> obsen_b1 24 23 obsen_d1 CPU_CFG<9>
21 11 IN CPU PWRGD R2500 1 2
91 10 IN IN 10 91
26 25 XDP
5% MF-LF
1/16W 402 obsdata_b0 28 27 obsdata_d0 CPU_CFG<4> 10 91 R1554.1:5MM
IN
obsdata_b1 30 29 obsdata_d1 CPU_CFG<5> 0
XDP IN 10 15 91
R2504 1 2 ITPXDP_CLK100M_P IN 15 18 91
32 31
U4900.D10:10MM 5% MF-LF
obsdata_b2 34 33 obsdata_d2 CPU CFG<6> 10 15 91 1/16W 402
IN
R2501 0 36 35
44 25 19 15 PM_PWRBTN_L 1 2 obsdata_b3 obsdata_d3 CPU_CFG<7> 10 91
OUT IN
38 37 XDP
5% MF-LF
1/16W 402 R1553.1:5MM
XDP_CPU_PWRGD pwrgd/hook0 40 39 itpclk/hook4 91 XDP_CPU_CLK100M_P
XDP 42 41 R2505 0
XDP_CPU_PWRBTN_L hook1 itpclk#/hook5 91 XDP_CPU_CLK100M_N 1 2 ITPXDP_CLK100M_N 15 18 91
IN
U1000.H36:10MM 44 43
vcc_obs_ab vcc_obs_cd 1K series resistor on csa 26 (PCH Support) 5% MF-LF
R2502 1K 46 45
1/16W 402
91 25 10 CPU_CFG<0> 1 2 XDP_CPU_CFG<0> hook2 reset#/hook6 XDP_CPU_PLTRST_L
OUT IN 26
5% MF-LF XDP VR READY hook3 48 47 dbr#/hook7 XDP DBRESET L
1/16W 402 XDP
50 49
XDP 52 51 SW2800.2:10MM Pull-up to 3.3V on csa 26 (PCH Support)
47 25 BI =SMBUS XDP SDA sda tdo XDP CPU TDO IN 11 25 91
J2500.47:10MM 54 53 R2506 0
C 62 61 OUT PM_PGOOD_REG_CPUCORE_S0 R2503 1
0
2
47 25 IN =SMBUS_XDP_SCL scl
tck1 NC
56 55
trstn
tdi
XDP_CPU_TRST_L
XDP_CPU_TDI
OUT
OUT
11 25
11 25 91
1
5%
1/16W
2
MF-LF
402
PM_SYSRST_L OUT 19 26 44
C
5% MF-LF 91 25 11 XDP_CPU_TCK tck0 58 57 tms XDP_CPU_TMS 11 25 91
1/16W 402 OUT OUT
60 59 xdp_present# OUT 11 25
Connects to PCH XDP Conn
XDP XDP
C2500 1 64 63 1 C2501
PCH Signals XDP Signals 0.1UF 0.1UF
10% 10%
20 OUT USB_EXTA_OC_R_L R2520 33 1 2 MF-LF 5% XDP_DA0_USB_EXTA_OC_L 25
16V
X5R 2
16V
2 X5R
402 1/16W 998-2516
20 OUT USB_EXTB_OC_R_L R2521 33 1 2 MF-LF 5% XDP_DA1_USB_EXTB_OC_L 25
402 402
402 1/16W
20 OUT USB EXTC OC R L R2522 33 1 2 MF-LF 5% XDP DA2 USB EXTC OC L 25
402 1/16W XDP_CONN
20 OUT USB_EXTD_OC_R_L R2523 33 1 2 MF-LF 5% XDP_DA3_USB_EXTD_OC_L 25
R2567
402 1/16W
20 OUT USB_EXTB_OC_EHCI_R_L R2524 33 1 2 MF-LF 5% XDP_DB0_USB_EXTB_OC_EHCI_L 25 0
R2525 402 1/16W 25 6 =PP3V3_S5_XDP 1 2 PP3V3_S5_XDP_R
20 OUT USB_EXTD_OC_EHCI_R_L 33 1 2 MF-LF 5% XDP_DB1_USB_EXTD_OC_EHCI_L 25
VOLTAGE=3.3V
402 1/16W 5%
20 IN AP_PWR_EN_R R2526 33 1 2 MF-LF 5% XDP_DB2_AP_PWR_EN 25 1/16W MIN_LINE_WIDTH=0.2MM
402 1/16W MF-LF MIN_NECK_WIDTH=0.15MM
20 OUT SDCONN_STATE_CHANGE_R R2527 33 1 2 MF-LF 5% XDP_DB3_SDCONN_STATE_CHANGE 25 402 MAX_NECK_LENGTH=3MM
402 1/16W
R2528 33 1
21
21
OUT
IN
TBT_CIO_PLUG_EVENT_R
ISOLATE_CPU_MEM_R_L R2529 33 1
2
2
MF-LF 5%
402 1/16W
MF-LF 5%
XDP_FC1_TBT_CIO_PLUG_EVENT
XDP_DC0_ISOLATE_CPU_MEM_L
25
25
PCH Micro2-XDP XDP
J2500.52:10MM
1 1
XDP
U1800.BC52:10MM
XDP
U1800.BC50:10MM
1
402 1/16W
21 IN GPU_GOOD_R R2530 33 1 2 MF-LF 5% XDP_DC1_GPU_GOOD 25
R2560 R2561 R2562
R2531 402 1/16W 200 200 200
18 IN DP_AUXCH_ISOL_R 33 1 2 MF-LF 5%
402 1/16W
XDP_DC2_DP_AUXCH_ISOL 25 25 6 =PP3V3_S5_XDP CRITICAL 5% 5% 5%
R2532 XDP_CONN 1/16W 1/16W 1/16W
18 IN SATARDRVR_EN_R 33 1 2 MF-LF 5% XDP_DC3_SATARDRVR_EN 25 MF-LF MF-LF MF-LF
402 1/16W
DP_GPU_TBT_SEL_R R2533 33 1 2 402 2 402 2 402
21 IN
R2534
2 MF-LF 5%
402 1/16W
XDP_DD0_DP_GPU_TBT_SEL 25
J2550 91 25 18 XDP PCH TDO
21 IN JTAG_TBT_TCK_R 33 1 2 MF-LF 5% XDP_DD1_JTAG_TBT_TCK 25 DF40RC-60DP-0.4V XDP_PCH_TDI
402 1/16W M-ST-SM
21 IN AUD_IPHS_SWITCH_EN_PCH_R R2535 33 1 2 MF-LF 5% XDP_DD2_AUD_IPHS_SWITCH_EN_PCH 25
91 25 18
402 1/16W 91 25 18 XDP_PCH_TMS

21 ENET_LOW_PWR_PCH_R R2536 33 1 2 MF-LF 5% XDP_DD3_ENET_LOW_PWR_PCH 25
62 61
IN 402 1/16W XDP_PCH_TCK
91 25 18
21 IN XDP PIN03 R2537 33 1 2 MF-LF 5%
402 1/16W
XDP FC0 PCH GPIO15 25
XDP XDP XDP XDP
2 1 J2500.52:10MM U1800.BA43:10MM U1800.BA43:10MM U1800.BA43:10MM
B obsen_a0 NC
4
6
3
5
obsen_c0 XDP_FC0_PCH_GPIO15 IN 25 gpio15
1
R2563
100
1
R2564
100
1
R2565
100
1
R2566
51
B
obsen_a1 NC obsen_c1 XDP FC1 TBT CIO PLUG EVENT IN 25 gpio0 5% 5% 5% 5%
8 7 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
oc0#/gpio59 25 XDP_DA0_USB_EXTA_OC_L obsdata_a0 10 9 obsdata_c0 XDP_DC0_ISOLATE_CPU_MEM_L 25 mgpio7/gpio28 2 402 2 402 2 402 2 402
IN IN
oc1#/gpio40 25 XDP_DA1_USB_EXTB_OC_L obsdata_a1 12 11 obsdata_c1 XDP_DC1_GPU_GOOD 25 gpio35
IN IN
14 13
oc2#/gpio41 25 XDP_DA2_USB_EXTC_OC_L obsdata_a2 16 15 obsdata_c2 XDP_DC2_DP_AUXCH_ISOL 25 sata0gp/gpio21

IN IN
oc3#/gpio42 25 XDP_DA3_USB_EXTD_OC_L obsdata_a3 18 17 obsdata_c3 XDP_DC3_SATARDRVR_EN 25 sata1gp/gpio19
IN IN
20 19
obsen_b0 22 21 obsen_d0
XDP NC NC
obsen_b1 24 23 obsen_d1
J2550.30:10MM NC NC
26 25
R2550 1K
25 6 IN =PP3V3 S5 XDP 1 2
oc4#/gpio43 25 XDP_DB0_USB_EXTB_OC_EHCI_L obsdata_b0 28 27 obsdata_d0 XDP_DD0_DP_GPU_TBT_SEL 25 sata2gp/gpio36
IN IN
5% MF-LF XDP_DB1_USB_EXTD_OC_EHCI_L 30 29 XDP_DD1_JTAG_TBT_TCK
1/16W 402 oc5#/gpio9 25 IN obsdata_b1 obsdata_d1 IN 25 sata3gp/gpio37
32 31
XDP
oc6#/gpio10 25 XDP_DB2_AP_PWR_EN obsdata_b2 34 33 obsdata_d2 XDP_DD2_AUD_IPHS_SWITCH_EN_PCH 25 sata4gp/gpio16
U4900.D10:10MM IN IN
oc7#/gpio14 XDP_DB3_SDCONN_STATE_CHANGE obsdata_b3 36 35 obsdata_d3 XDP_DD3_ENET_LOW_PWR_PCH sata5gp/gpio49
R2551 0 25 IN IN 25
44 25 19 15 OUT PM_PWRBTN_L 1 2 38 37
5% MF-LF XDP PCH PWRGD 40 39
1/16W 402 pwrgd/hook0 NC itpclk/hook4
XDP_PCH_PWRBTN_L hook1 42 41 itpclk#/hook5
NC
vcc_obs_ab 44 43 vcc_obs_cd 1K series resistor on csa 26 (PCH Support)
hook2 46 45 reset#/hook6 XDP_PCH_PLTRST_L
PCH/XDP Signal Isolation Notes: NC IN 26
hook3 48 47 dbr#/hook7 XDP_DBRESET_L
NC OUT 11 25
- USB OC#’s not isolated, avoid USB port overcurrent 50 49
events while using PCH XDP. 47 25 =SMBUS_XDP_SDA sda 52 51 tdo XDP_PCH_TDO 18 25 91

BI IN
- Unused GPIOs 0 & 15 not isolated. =SMBUS XDP SCL 54 53
A - MXM_GOOD not isolated as only LED is affected.
47 25 IN scl
tck1 NC
56 55
NC trstn
tdi XDP PCH TDI OUT 18 25 91 A
- For isolated GPIOs: 91 25 18 XDP PCH TCK tck0 58 57 tms XDP PCH TMS 18 25 91
PAGE TITLE
OUT OUT
- ’Output’ non-XDP signals require pulls. 60 59 xdp_present# CPU and PCH XDP
- ’Output’ PCH/XDP signals require pulls. DRAWING NUMBER SIZE
XDP XDP
If PCH XDP not implemented, all of R2524-R2537 can C2550 1 64 63 1 C2551 Apple Inc. 051-9509 D
0.1UF 0.1UF REVISION
be replaced with aliases. Otherwise these R’s must R
be stuffed even in production so that PCH pins

10%
16V
10%
16V 4.2.0
X5R 2 998-2516
2 X5R
402 402
connect to appropriate non-XDP signals on PCB.
R2524-R2537 should be placed where signal path THE POSESSOR AGREES TO THE FOLLOWING: PAGE
needs to split between route from PCH to J2550 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
25 OF 113
and path to non-XDP signal destination. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform Reset Connections

System 25MHz Clock Generator PLT_RESET_L 1
R2681
33
2 DEBUG_RESET_L
20 IN OUT 46
MAKE BASE=TRUE
5%
1/16W
VDD must be powered if any VDDIO is.

Unbuffered MF LF
402
ENET > S0 > TBT, so ENET is used here. R2655

GreenClk 25MHz Power 6 =PP3V3_ENET_SYSCLK 33
1 2 SMC_LRESET_L OUT 44
MAKE_BASE=TRUE
5%
1/16W
D Ethernet XTAL Power

SB XTAL Power
6
6
=PPVDDIO_ENET_CLK
=PPVDDIO_S0_SBCLK
MF LF
402 D
XDP
TBT XTAL Power =PPVDDIO_TBT_CLK
6
R2699
1K
1 2 XDP_PCH_PLTRST_L OUT 25
5%
C2624 1
C2622 1
C2620 1 1
C2602
VDD 2
VDDIO_A 6
VDDIO_B 3
VDDIO_C 7
1/16W
MF LF
0.1UF 0.1UF 0.1UF 1UF 402
20% 20% 20% 10%
10V 10V 10V 6 3V
CERM 2 CERM 2 CERM 2 2 CERM XDP
402 402 402 402 R2698
1K
1 2 XDP_CPU_PLTRST_L OUT 25
U2600 Buffered 5%
1/16W
MF LF MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
C2605 SLG3NB146V 402
12PF R2605 TDFN

0 CRITICAL R2694
2 1 92 SYSCLK_CLK25M_X2 1 2 92 SYSCLK_CLK25M_X2_R 10 XOUT 33
1 2 PCA9557D_RESET_L OUT 32
5%
5% NO STUFF 1 XIN 25MHZ_A 5 SYSCLK_CLK25M_SB 26 92 26 6 =PP3V3_S0_RSTBUF
1/16W 5%
50V CRITICAL 1
25MHZ_B 4 SYSCLK CLK25M ENET R 1/16W
1
MF LF
CERM 402 R2606 26 92
MF LF
402 NC Y2605 1M 25MHZ_C 8 SYSCLK CLK25M TBT 402
2 4
OUT 34 92
NC 25.000MHZ-12PF-20PPM 5% MC74VHC1G08
SM 3 2X2 5MM 1/16W
5 SOT23-5-HF
C2606 R2690
3
MF LF
1
9 GND
402
12PF 2 THRM 33
PAD 4 PLT_RST_BUF_L 1 2 GPU_RESET_L
1 2 92 SYSCLK CLK25M X1 U2680 OUT 71 78
11
2 5%
5%
NOTE: 30 PPM crystal required 1
1/16W
MF LF
50V 3 R2680 402
CERM
402
C2680 1 100K
0.1UF 5%
1/16W
R2691
20% 33
10V MF LF
CERM 2 2 402
1 2 TBT PLT RST L
402 MAKE_BASE=TRUE
5% =TBT RESET L OUT 36
1/16W
C PCH 25MHZ CLOCK

MF LF
402 C
R2688
33
1 2 AP_RESET_L OUT 33
R2671 5%
604 1/16W
RTC Power Sources 92 26 SYSCLK_CLK25M_SB

From GreenClk @ 1.8V
1
1%
1/16W
2 PCH_CLK25M_XTALIN
To PCH @ 1.1V OUT 18 92 MF LF
402
MF LF 1
R2672 R2692
D2600 402 33
ENET_SD_RESET_L
BAT54DW-X-G 1K 1 2
OUT 39
1%
SOT 363 1/16W 5%
PP3V3 G3H RTC 6 22 MF LF 1/16W
402 MF LF
6 =PP3V3_RTC_D 1 6 2 402
Coin-Cell Holder R2602 =PP3V3_S0_RSTBUF
1K
26 6
R2693
PPVBATT_G3_RTC 2 1 PPVBATT_G3_RTC_R 4 3 33
MIN LINE WIDTH=0 3 mm MIN LINE WIDTH=0 3 mm 1 2 SSD_RESET_L OUT 41
MIN NECK WIDTH=0 2 mm 5% MIN NECK WIDTH=0 2 mm
VOLTAGE=3 3V 1/16W VOLTAGE=3 3V 5%
MF LF
NC
5 NC NC 2 NC 1/16W
402 MF LF
1
J2600 OPEN-DRAIN BUFFER 402
BB10201-C1403-7H
2 SM 5 U2690 VTT VOLTAGE DIVIDER AND PU ON CPU PAGE
74LVC1G07
511-0054 SC70
NOTE: R2800 and D2800 form the double- 2 4 CPU_RESET_L OUT 11
fault protection for RTC battery. GPIO Isolation to prevent glitches on critical core well GPIOs
NC
1 3
C2690 1
24 19 6 =PP3V3_S5_PCH 0.1UF NC
20%
10V
1
C2650 CERM 2
0.1UF 402
B PCH RTC Crystal 2

20%
10V
CERM
402
B
PLACE_NEAR=Y2810.3:2mm
14 CRITICAL
C2610
R2610 12pF VCC
0
92 18 IN PCH CLK32K RTCX2 1 2 92 PCH CLK32K RTCX2 R 1 2 U2650
5%
74LVC08
1/16W 5% TBT_PWR_EN_PCH 1 TSSOP-HF 3 TBT_PWR_EN =PP3V3_S0_PCH_PM
R26111 MF LF CRITICAL 50V
18
2
1A 08 1Y OUT 34 6
4
402 CERM LPC_PWRDWN_L

46 44 19
10M Y2610 402 1B
5%
1/16W
MF LF PLACE_NEAR=U1800.BR39:10mm
32.768K-12.5PF
SM-HF
C2611
26 21
61 26 19
AUD IPHS SWITCH EN PCH 4
PM PCH PWROK 5
2A
2B
2Y
6 AUD IPHS SWITCH EN OUT 56
1
R2697
4.7K
Reset Button
1
402 2 10 8 5%
12pF 21 15 ENET_LOW_PWR_PCH 3Y ENET_LOW_PWR 37 39 1/16W
3A OUT
MF LF
92 18 PCH_CLK32K_RTCX1 1 2 61 26 19 PM_PCH_PWROK 9 402
OUT 3B 2
13 11
5% 4A 4Y NC PM SYSRST L OUT 19 25 44
50V 12
CERM 4B
402
PLACE_NEAR=Y2810.1:2mm GND 1 NOSTUFF

R2696
7 0
SILK_PART=SYS RESET 5%
1/16W
MF LF
2 402
Clock series termination 26 21 AUD_IPHS_SWITCH_EN_PCH
1
R2650
R2625 100K
PLACE NEAR=U1800 AT11 10mm 33 5%
LPC CLK33M SMC R LPC CLK33M SMC
A 92 20 IN
5%
1/20W
1 2
OUT 44 92 1/16W
MF LF
2 402 SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A
MF PAGE TITLE
R2626
92 20 IN LPC_CLK33M_LPCPLUS_R
201
PLACE NEAR=U1800 AN14 10mm
1
33
2 LPC_CLK33M_LPCPLUS OUT 46 92
CHIPSET SUPPORT
DRAWING NUMBER SIZE
5%
1/16W
MF LF Apple Inc. 051-9509 D
R2627 402 REVISION
PLACE NEAR=U1800 AT14 10mm 33 R
92 20 IN PCH_CLK33M_PCIOUT 1 2 PCH_CLK33M_PCIIN OUT 18 92 4.2.0
5%
1/16W
R2628 MF LF THE INFORMATION CONTAINED HEREIN IS THE
33 402 PROPRIETARY PROPERTY OF APPLE INC.
92 26 SYSCLK_CLK25M_ENET_R 1 2 SYSCLK_CLK25M_ENET OUT 37 92 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACE NEAR=U2800 4 10mm 5%
1/16W
26 OF 113
MF LF SHEET
402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
27 6 =PP3V3 S4 USB HUB
D D
1 C2708 1 C2709 1 C2710 1 C2711
0.1UF 0.1UF 0.1UF 0.1UF =PP3V3_S4_USB_HUB 6 27
10% 10% 10% 10%
25V 25V 25V 25V
2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
MIN_NECK_WIDTH=0.2MM
MAX NECK_LENGTH=3MM
VOLTAGE=1.2V NON_REM 0 and 1 are used to indicate whether the
downstream ports have removable devices or not
NON_REM[1:0] = 00 ---> all ports removable
MIN_LINE_WIDTH=0.4MM 1 NON_REM[1:0] = 01 ---> port 1 is non-removable
MIN_NECK_WIDTH=0.2MM R2712 NON_REM[1:0] = 1x ---> ports 1 and 2 are non-removable
MAX NECK_LENGTH=3MM
VOLTAGE=1.2V
10K
5%
1/16W
MF-LF
PPUSB HUB VDD1V2 2 402
C2705 1 C2706 1 1 C2707 =PP3V3_S4_USB_HUB 6 27
4.7UF 0.1UF 0.1UF PPUSB_HUB_VDD1V2PLL
10% 10% 10%
6.3V 25V 2 2 25V
X5R-CERM 2 X5R X5R
603 402 402
C2703 1 1 C2704
0.1UF 0.1UF
10% 10%
10
14
20
27
PLLFILT 25
16V 2 2 16V
CRFILT 9
X5R X5R 1
1
R2703 402 402 R2705
VDD33
VDD33
VDD33
VDD33
VDD33
100K
10K 5%
5% 1/16W
1/16W MF-LF
MF-LF 2 402
2 402 U2700 Y2700
USB2412-DZK 24.000M-60PPM-16PF
1 2 USB HUB XTAL_R
QFN
USB HUB VBUS DET 18 VBUS_DET SUSP_IND/NON_REM0 19 USB HUB NON REM0
22 USBDP_UP
C2701 1 5X3.2X1.4-SM 1 C2702
NON_REM1 13 18PF
C 93 20
93 20
BI
BI
USB_PCH_7_P
USB_PCH_7_N 21 USBDM_UP
HS_IND 16
USB_HUB_NON_REM1
USB HUB HS IND

5%
50V
CERM 2
R2706
1M
5%
18PF
2 50V
C
402 1 2 CERM
USB BT P 1 USBDP_DN1 402
93 33 BI
28 USBDM_DN1 RESET* 17 USB_HUB_RESET_L 5%
93 33 BI USB_BT_N 1/16W
MF-LF
3 USBDP_DN2 TEST 6 402
93 USB_HUB_2_P
93 USB HUB 2 N 2 USBDM_DN2 XTALIN/CLKIN
93 24 USB HUB XTAL1 R2709
23 1
0 2
XTALOUT
93 USB_HUB_XTAL2
7 PRTPWR1
NC 5%
11 PRTPWR2 NC 5 1/16W
NC NC MF-LF
402
NC
8OCS1* TEST1 15
NC
12 OCS2*
C2712 1 R27081 1
R2704
100K 100K
USB_HUB_RBIAS 26 RBIAS 0.1UF 5% 5%
NOSTUFF NOSTUFF 93 10% 1/16W 1/16W
EPAD
16V MF-LF MF-LF
1 1 X5R 2
R2710 R2711 1 402
402 2 2 402
0 0 R2707
5% 5%
12K
29
1/16W 1/16W
MF-LF MF-LF 1%
402 2 2 402 1/16W
MF
2 402
93 44 BI USB_SMC_P
93 44 BI USB_SMC_N
B B
A SYNC MASTER=D7 NICK SYNC DATE=12/13/2011 A

PAGE TITLE
USB HUB
DRAWING NUMBER SIZE

REVISION
R
4.2.0
27 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
D WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
MEMVTT_EN = PM_PGOOD_FET_VDDQ_S0 * PM_SLP_S3_L

1V5 S0 "PGOOD" for CPU
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
6 =PP5V_S4_MEMRESET
6 =PP3V3 S4 PM
1
R2815
100K
5%
1/16W
MF-LF
402 2
5 U2820
74LVC1G07
SC70
MEMRESET_ISOL_LS5V_L 70 60 28 IN PM_PGOOD_FET_VDDQ_S0 2 4 PM_MEM_PWRGD OUT 11 19
NC
CRITICAL =PPVDDQ_S3_MEMRESET
Q2815 D 3 C2821 1 1 3
0.01UF NC
SSM6N15AFE 20%
16V
SOT563
CERM 2
R28161 402
20K
5%
1 C2816
5 G S 4 1/16W 0.1UF
MF-LF 10%
28 6 IN =PP3V3_S4_MEMRESET CRITICAL 402 2 2 16V
X5R
C 32 21 ISOLATE CPU MEM L Q2815
402
C
IN
2
G
SOT563
S
D
11 IN CPU_MEM_RESET_L MEM_RESET_L OUT 29 30 88
MAKE_BASE=TRUE
6
1
SSM6N15AFE
60 45 44 38 28 19 15 IN PM_SLP_S3_L
MEMVTT Clamp
1
R2810 Ensures CKE signals are held low in S3
10K
5%
1/16W
MF-LF
2 402 6 =PPDDRVTT_S0_CLAMP
60 45 44 38 28 19 15 PM_SLP_S3_L MEMVTT_EN OUT 28 60
CRITICAL
R28501
10 75mA max load @ 0.75V
D 3 5%
Q2810 1/10W 60mW max power
R28021 SSM6N15AFE MF-LF
603 2
10K SOT563
5%
1/16W VTTCLAMP_L
MF-LF MIN_NECK_WIDTH=0.25mm
402 2
=PP3V3_S4_MEMRESET CRITICAL MIN_LINE_WIDTH=0.25mm
5 G S 4 28 6
Q2850 D 6
B MEMVTT_EN_L
R28511 SSM6N15AFE B
SOT563
CRITICAL 100K
5%
1/16W
Q2810 D 6 MF-LF
402 2 2 G S 1
SSM6N15AFE
SOT563
VTTCLAMP_EN
CRITICAL
2 G S 1 NO STUFF
Q2850 D 3
C2851 1
SSM6N15AFE
70 60 28 IN PM PGOOD FET VDDQ S0 SOT563 0.001UF
20%
50V
CERM 2
402
5 G S 4
60 28 IN MEMVTT_EN
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN

S0 0 1 1 1 1 CPU_MEM_RESET_L 1
1 0 1 1 1 1 1
to 2 0 0 1 1 1 0
3 0 0 0 X 1 0
A S3 4 0 0 1 X 1 0
PAGE TITLE
to 5
6
0
0
1
1
1
1
0 (*)
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 CPU_MEM_RESET_L 1
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
4.2.0
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 28 OF 113
must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PPDDRVREF_DQ_MEM_A 1 2
6 VREFDQ VSS_0
3 4 =MEM_A_DQ<4>
VSS_1 DQ4 BI 31
31 BI =MEM_A_DQ<0> 5
DQ0 J2900 DQ5
6 =MEM_A_DQ<5> BI 31
=MEM_A_DQ<1> 7 F-RT-SM 8
31 BI DQ1 VSS_2
2013311
9 10 =MEM_A_DQS_N<0> BI
VSS_3 DQS0* 31
1 C2930 1 C2931 11
DM0 DQS0
12 =MEM_A_DQS_P<0> BI 31
2.2UF 0.1UF 13
VSS_4 VSS_5
14
20% 20%
2 6.3V
CERM 2 10V
CERM 31 BI =MEM_A_DQ<2> 15
DQ2 DQ6
16 =MEM_A_DQ<6> BI 31
402-LF 402 =MEM A DQ<3> 17 18 =MEM A DQ<7>
31 BI DQ3 DQ7 BI 31
19 20
VSS_6 VSS_7
=MEM_A_DQ<8> 21 22 =MEM_A_DQ<12>
31 BI DQ8 DQ12 BI 31
=MEM_A_DQ<9> 23 24 =MEM_A_DQ<13>
D 31 BI =MEM_A_DQS_N<1>
25
27
VSS_8
DQS1*
VSS_9
DM1
26
28 D
=MEM_A_DQS_P<1> 29 30 MEM_RESET_L
31 BI DQS1 RESET* IN 28 30 88
31 32
VSS_10 VSS_11
=MEM A DQ<10> 33 34 =MEM A DQ<14>
31 BI DQ10 DQ14 BI 31
=MEM A DQ<11> 35 36 =MEM A DQ<15>

31 BI DQ11 DQ15 BI 31
37 38
VSS_12 VSS_13
=MEM_A_DQ<16> 39 40 =MEM_A_DQ<20>
31 BI DQ16 DQ20 BI 31
=MEM_A_DQ<17> 41 42 =MEM_A_DQ<21>
31 BI DQ17 DQ21 BI 31
43 44
VSS_14 VSS_15
=MEM_A_DQS_N<2> 45 46
31 BI DQS2* DM2
=MEM A DQS P<2> 47 48
31 BI DQS2 VSS_16
49 50 =MEM A DQ<22>
VSS_17 DQ22 BI 31
=MEM A DQ<18> 51 52 =MEM A DQ<23>

31 BI DQ18 DQ23 BI 31
=MEM_A_DQ<19> 53 54
31 BI DQ19 VSS_18
55 56 =MEM_A_DQ<28>
VSS_19 DQ28 BI 31
=MEM_A_DQ<24> 57 58 =MEM_A_DQ<29>
31 BI DQ24 DQ29 BI 31
=MEM_A_DQ<25> 59 60
31 BI DQ25 VSS_20
61 62 =MEM_A_DQS_N<3> BI
VSS_21 DQS3* 31
63 64 =MEM_A_DQS_P<3> BI
DM3 DQS3 31
65 66
VSS_22 VSS_23
=MEM A DQ<26> 67 68 =MEM A DQ<30>
31 BI DQ26 DQ30 BI 31
=MEM_A_DQ<27> 69 70 =MEM_A_DQ<31>
31 BI DQ27 DQ31 BI 31
71 72
VSS_24 VSS_25
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR) KEY
MEM A CKE<0> 73 74 MEM A CKE<1>
88 12 IN CKE0 CKE1 IN 12 88
=PPVDDQ S3 MEM A 75 76 =PPVDDQ S3 MEM A

29 6 VDD_0 VDD_1 6 29
77 78 MEM_A_A<15>
C 1 C2910 1 C2911 1 C2912 1 C2913 1 C2914 1 C2915 1 C2916 1 C2917 1 C2902 88 12 IN MEM_A_BA<2>
NC
79
NC_0
BA2
A15
A14
80 MEM_A_A<14>
IN
IN
12 88
12 88
C
81 82
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VDD_2 VDD_3 1 1 1 1 1 1 1
20% 20% 20% 20% 20% 20% 20% 20% 20% MEM_A_A<12> 83 84 MEM_A_A<11> C2900 C2901 C2918 C2919 C2920 C2921 C2922 1 C2923 1 C2924
10V
2 CERM 10V
2 CERM 2 10V 2 10V 10V
2 CERM 10V
2 CERM 10V
2 CERM 2 10V 2 10V
88 12 IN A12/BC* A11 IN 12 88
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
402 402
CERM
402
CERM
402 402 402 402
CERM
402
CERM
402 88 12 MEM_A_A<9> 85
A9 A7
86 MEM_A_A<7> 12 88
20%
6.3V
20%
6.3V
20%
10V
20% 20% 20% 20% 0.1UF 0.1UF
IN
87 88
IN
2 X5R 2 X5R 2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 20%
10V
20%
10V
VDD_4 VDD_5 603 603 402 402 402 402 402 2 CERM 2 CERM
MEM A A<8> 89 90 MEM A A<6> 402 402
88 12 IN A8 A6 IN 12 88
MEM_A_A<5> 91 92 MEM_A_A<4>
88 12 IN A5 A4 IN 12 88
93 94
VDD_6 VDD_7
MEM_A_A<3> 95 96 MEM_A_A<2>
88 12 IN A3 A2 IN 12 88
MEM_A_A<1> 97 98 MEM_A_A<0>
88 12 IN A1 A0 IN 12 88
99 100
VDD_8 VDD_9
MEM_A_CLK_P<0> 101 102 MEM_A_CLK_P<1>
88 12 IN CK0 CK1 IN 12 88
MEM_A_CLK_N<0> 103 104 MEM_A_CLK_N<1>

88 12 IN CK0* CK1* IN 12 88
105 106
VDD_10 VDD_11
MEM_A_A<10> 107 108 MEM_A_BA<1>
88 12 IN A10_AP BA1 IN 12 88
MEM_A_BA<0> 109 110 MEM_A_RAS_L

88 12 IN BA0 RAS* IN 12 88
111 112
VDD_12 VDD_13
MEM_A_WE_L 113 114 MEM_A_CS_L<0>
88 12 IN WE* S0* IN 12 88
MEM_A_CAS_L 115 116 MEM_A_ODT<0>

88 12 IN CAS* ODT0 IN 12 88
117 118
VDD_14 VDD_15
MEM A A<13> 119 120 MEM A ODT<1>
88 12 IN A13 ODT1 IN 12 88
MEM_A_CS_L<1> 121 122

88 12 IN S1* NC_1 NC
123 124
VDD_16 VDD_17
125 126 =PPDDRVREF_CA_MEM_A
NC TEST VREFCA 6
127 128
VSS_26 VSS_27
=MEM_A_DQ<32> 129 130 =MEM_A_DQ<36>
31 DQ32 DQ36 31
B 31
BI
BI =MEM_A_DQ<33> 131
133
DQ33 DQ37
132
134
=MEM_A_DQ<37>
BI
BI 31
1 C2935
2.2UF
1 C2936
0.1UF
B
VSS_28 VSS_29 20% 20%
=MEM A DQS N<4> 135 136 2 6.3V 10V
2 CERM
31 BI DQS4* DM4 CERM
=MEM_A_DQS_P<4> 137 138 402-LF 402
31 BI DQS4 VSS_30
139 140 =MEM_A_DQ<38>
VSS_31 DQ38 BI 31
MEM_A_SA<1> =MEM_A_DQ<34> 141 142 =MEM_A_DQ<39>

29 31 BI DQ34 DQ39 BI 31
=MEM_A_DQ<35> 143 144

MEM A SA<0> 31 BI DQ35 VSS_32
29 145 146
VSS_33 DQ44 =MEM_A_DQ<44> BI 31
=PPSPD_S0_MEM_A =MEM_A_DQ<40> 147 148 =MEM_A_DQ<45>

29 6 31 BI DQ40 DQ45 BI 31
=MEM A DQ<41> 149 150

1 1 31 BI DQ41 VSS_34
1 C2940 R2940 R2941 151
VSS_35 DQS5*
152 =MEM A DQS N<5>BI 31
2.2UF 10K 10K 153 154
20% 5% 5% DM5 DQS5 =MEM_A_DQS_P<5>BI 31
1/16W 1/16W
2 6.3V
CERM MF-LF MF-LF 155
VSS_36 VSS_37
156
402-LF 2 402 2 402 31 =MEM_A_DQ<42> 157
DQ42 DQ46
158 =MEM_A_DQ<46> 31
BI BI
=MEM_A_DQ<43> 159 160 =MEM_A_DQ<47>
31 BI DQ43 DQ47 BI 31
=PPDDRVTT S0 MEM A
161 162 6 29
29 6 =PPDDRVTT_S0_MEM_A VSS_38 VSS_39

=MEM_A_DQ<48> 163 164 =MEM_A_DQ<52>
31 BI DQ48 DQ52 BI 31
=MEM A DQ<49> 165 166 =MEM A DQ<53>

31 BI DQ49 DQ53 BI 31
167 168
VSS_40 VSS_41
31 BI =MEM_A_DQS_N<6> 169
DQS6* DM6
170 1 C2950 1 C2951 1 C2952 1 C2953
31 BI =MEM_A_DQS_P<6> 171
DQS6 VSS_42
172 1UF 1UF 1UF 1UF
10% 10% 10% 10%
173 174 =MEM_A_DQ<54> 2 10V 2 10V 2 10V 10V
2 X5R
VSS_43 DQ54 BI 31 X5R X5R X5R
=MEM_A_DQ<50> 175 176 =MEM_A_DQ<55> 402 402 402 402
31 BI DQ50 DQ55 BI 31
=MEM_A_DQ<51> 177 178

31 BI DQ51 VSS_44
179 180 =MEM_A_DQ<60>
VSS_45 DQ60 BI 31
=MEM A DQ<56> 181 182 =MEM A DQ<61>

A 31
31
BI
BI =MEM A DQ<57> 183
DQ56
DQ57
DQ61
VSS_46
184
BI 31

185 186 =MEM A DQS N<7>BI PAGE TITLE
VSS_47 DQS7* 31
187
189
DM7 DQS7
188
190
=MEM_A_DQS_P<7>BI 31 DDR3 SO-DIMM Connector A
VSS_48 VSS_49 DRAWING NUMBER SIZE
31 BI =MEM_A_DQ<58> 191
DQ58 DQ62
192 =MEM_A_DQ<62> BI 31
=MEM_A_DQ<59> 193 194 =MEM_A_DQ<63> REVISION
31 BI DQ59 DQ63 BI 31
R
195
VSS_50 VSS_51
196 4.2.0
MEM_A_SA<0> 197 198 MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
29 SA0 EVENT* OUT 30 44 45
=PPSPD S0 MEM A 199 200 =I2C SODIMMA SDA THE INFORMATION CONTAINED HEREIN IS THE
29 6 VDDSPD SDA BI 47
MEM_A_SA<1> 201 202 =I2C_SODIMMA_SCL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
29 SA1 SCL IN 47
203
VTT_0 VTT_1
204 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
29 OF 113
205 206 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG_PIN MTG_PIN
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PPDDRVREF_DQ_MEM_B 1 2
6 VREFDQ VSS_0
3 4 =MEM_B_DQ<4>
VSS_1 DQ4 BI 31
31 BI =MEM_B_DQ<0> 5
DQ0 J3100 DQ5
6 =MEM_B_DQ<5> BI 31
=MEM_B_DQ<1> 7 F-RT-SM 8
DQ1 VSS_2
1 C3130 1 C3131 31 BI
2013290
9 10 =MEM_B_DQS_N<0> BI
2.2UF 0.1UF 11
VSS_3 DQS0*
12
31
20% 20%
DM0 DQS0 =MEM_B_DQS_P<0> BI 31
2 6.3V
CERM 2 10V
CERM 13 14
402-LF 402 VSS_4 VSS_5
=MEM_B_DQ<2> 15 16 =MEM_B_DQ<6>
31 BI DQ2 DQ6 BI 31
=MEM_B_DQ<3> 17 18 =MEM_B_DQ<7>
31 BI DQ3 DQ7 BI 31
19 20
VSS_6 VSS_7
=MEM_B_DQ<8> 21 22 =MEM_B_DQ<12>
=MEM_B_DQ<9> 23 24 =MEM_B_DQ<13>
D 31 BI =MEM_B_DQS_N<1>
25
27
VSS_8
DQS1*
VSS_9
DM1
26
28 D
=MEM B DQS P<1> 29 30 MEM RESET L
31 BI DQS1 RESET* IN 28 29 88
31 32
VSS_10 VSS_11
=MEM_B_DQ<10> 33 34 =MEM_B_DQ<14>
31 BI DQ10 DQ14 BI 31
=MEM_B_DQ<11> 35 36 =MEM_B_DQ<15>
31 BI DQ11 DQ15 BI 31
37 38
VSS_12 VSS_13
=MEM B DQ<16> 39 40 =MEM B DQ<20>
31 BI DQ16 DQ20 BI 31
=MEM_B_DQ<17> 41 42 =MEM_B_DQ<21>
31 BI DQ17 DQ21 BI 31
43 44
VSS_14 VSS_15
=MEM B DQS N<2> 45 46
31 BI DQS2* DM2
=MEM_B_DQS_P<2> 47 48
31 BI DQS2 VSS_16
49 50 =MEM_B_DQ<22>
VSS_17 DQ22 BI 31
=MEM_B_DQ<18> 51 52 =MEM_B_DQ<23>
31 BI DQ18 DQ23 BI 31
=MEM_B_DQ<19> 53 54
31 BI DQ19 VSS_18
55 56 =MEM B DQ<28>
VSS_19 DQ28 BI 31
=MEM_B_DQ<24> 57 58 =MEM_B_DQ<29>
31 BI DQ24 DQ29 BI 31
=MEM_B_DQ<25> 59 60
31 BI DQ25 VSS_20
61 62 =MEM_B_DQS_N<3> BI
VSS_21 DQS3* 31
63 64 =MEM_B_DQS_P<3> BI
DM3 DQS3 31
65 66
VSS_22 VSS_23
=MEM_B_DQ<26> 67 68 =MEM_B_DQ<30>
31 BI DQ26 DQ30 BI 31
=MEM_B_DQ<27> 69 70 =MEM_B_DQ<31>
31 BI DQ27 DQ31 BI 31
71 72
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR) VSS_24 VSS_25
73 KEY 74
88 12 IN MEM_B_CKE<0> CKE0 CKE1 MEM_B_CKE<1> IN 12 88
=PPVDDQ_S3_MEM_B 75 76 =PPVDDQ_S3_MEM_B 6
30 6 VDD_0 VDD_1 30
77 78 MEM_B_A<15>
C 1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115 1 C3116 1 C3117 1 C3102 88 12 IN MEM B BA<2>
NC
79
NC_0
BA2
A15
A14
80 MEM B A<14>
IN
IN
12 88
12 88
C
81 82 1 C3100 1 C3101 1 C3118 1 C3119 1 C3120 1 C3121 1 C3122
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF VDD_2 VDD_3 1 C3123 1 C3124
20% 20% 20% 20% 20% 20% 20% 20% 20% MEM_B_A<12> 83 84 MEM_B_A<11> 10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
88 12 IN
85
A12/BC* A11
86
IN 12 88
20% 20% 20% 20% 20% 20% 20% 0.1UF 0.1UF
402 402 402 402 402 402 402 402 402 88 12 MEM_B_A<9> A9 A7 MEM_B_A<7> 12 88 2 6.3V
X5R 2 6.3V
X5R 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM
20%
10V
20%
IN
87 88
IN
603 603 402 402 402 402 402 2 CERM 2 10V
CERM
VDD_4 VDD_5 402 402
MEM_B_A<8> 89 90 MEM_B_A<6>
88 12 IN A8 A6 IN 12 88
MEM_B_A<5> 91 92 MEM_B_A<4>
88 12 IN A5 A4 IN 12 88
93 94
VDD_6 VDD_7
MEM B A<3> 95 96 MEM B A<2>
88 12 IN A3 A2 IN 12 88
MEM_B_A<1> 97 98 MEM_B_A<0>
88 12 IN A1 A0 IN 12 88
99 100
VDD_8 VDD_9
MEM_B_CLK_P<0> 101 102 MEM_B_CLK_P<1>
88 12 IN CK0 CK1 IN 12 88
MEM_B_CLK_N<0> 103 104 MEM_B_CLK_N<1>

88 12 IN CK0* CK1* IN 12 88
105 106
VDD_10 VDD_11
MEM_B_A<10> 107 108 MEM_B_BA<1>
88 12 IN A10_AP BA1 IN 12 88
MEM B BA<0> 109 110 MEM B RAS L

88 12 IN BA0 RAS* IN 12 88
111 112
VDD_12 VDD_13
MEM_B_WE_L 113 114 MEM_B_CS_L<0>
88 12 IN WE* S0* IN 12 88
MEM_B_CAS_L 115 116 MEM_B_ODT<0>

88 12 IN CAS* ODT0 IN 12 88
117 118
VDD_14 VDD_15
MEM_B_A<13> 119 120 MEM_B_ODT<1>
=PPSPD S0 MEM B 88 12 IN A13 ODT1 IN 12 88
30 6 121 122
88 12 IN MEM_B_CS_L<1> S1* NC_1 NC
123 124
VDD_16 VDD_17
125 126 =PPDDRVREF CA MEM B
NC TEST VREFCA 6
127 128
VSS_26 VSS_27
1 =MEM_B_DQ<32> 129 130 =MEM_B_DQ<36>
R3141 DQ32 DQ36
C3135 C3136
31 31
B 10K
5%
31
BI
BI =MEM_B_DQ<33> 131
133
DQ33 DQ37
132
134
=MEM_B_DQ<37>
BI
BI 31
1
2.2UF
1
0.1UF
20%
B
1/16W VSS_28 VSS_29 20% 10V
MF-LF 135 136 6.3V 2 CERM
2 402 31 BI =MEM B DQS N<4> DQS4* DM4 2 CERM 402
=MEM_B_DQS_P<4> 137 138 402-LF
31 BI DQS4 VSS_30
139 140 =MEM_B_DQ<38>
VSS_31 DQ38 BI 31
MEM_B_SA<1> =MEM_B_DQ<34> 141 142 =MEM_B_DQ<39>

30 31 BI DQ34 DQ39 BI 31
=MEM_B_DQ<35> 143 144

MEM_B_SA<0> 31 BI DQ35 VSS_32
30 145 146
VSS_33 DQ44 =MEM B DQ<44> BI 31
=MEM_B_DQ<40> 147 148 =MEM_B_DQ<45>

31 BI DQ40 DQ45 BI 31
=MEM_B_DQ<41> 149 150

1 31 BI DQ41 VSS_34
R3140 151
VSS_35 DQS5*
152 =MEM B DQS N<5>BI 31
10K 153 154 =MEM_B_DQS_P<5>BI
5% DM5 DQS5 31
1/16W 155 156
MF-LF VSS_36 VSS_37
2 402 =MEM_B_DQ<42> 157 158 =MEM_B_DQ<46>
31 BI DQ42 DQ46 BI 31
=PPDDRVTT_S0_MEM_B =MEM_B_DQ<43> 159 160 =MEM_B_DQ<47> =PPDDRVTT_S0_MEM_B

30 6 31 BI DQ43 DQ47 BI 31 6 30
161 162
VSS_38 VSS_39
=MEM_B_DQ<48> 163 164 =MEM_B_DQ<52>
31 BI DQ48 DQ52 BI 31
31 BI =MEM_B_DQ<49> 165
DQ49 DQ53
166 =MEM_B_DQ<53> BI 31
1 C3150 1 C3151 1 C3152 1 C3153
167
VSS_40 VSS_41
168 1UF 1UF 1UF 1UF
10% 10% 10% 10%
=MEM_B_DQS_N<6> 169 170 2 10V 2 10V 2 10V 2 10V
31 BI DQS6* DM6 X5R X5R X5R X5R
=MEM_B_DQS_P<6> 171 172 402 402 402 402
31 BI DQS6 VSS_42
173 174 =MEM_B_DQ<54>
VSS_43 DQ54 BI 31
=MEM B DQ<50> 175 176 =MEM B DQ<55>

=PPSPD S0 MEM_B 31 BI DQ50 DQ55 BI 31
30 6 177 178
31 BI =MEM_B_DQ<51> DQ51 VSS_44
179 180 =MEM_B_DQ<60>
VSS_45 DQ60
1 C3140 =MEM B DQ<56> 181 182 =MEM B DQ<61>
BI 31
A 2.2UF
20%
2 6.3V
31
31
BI
BI =MEM_B_DQ<57> 183
DQ56
DQ57
DQ61
VSS_46
184
BI 31

CERM 185 186 =MEM_B_DQS_N<7>BI PAGE TITLE
402-LF VSS_47 DQS7* 31
187
189
DM7 DQS7
188
190
=MEM_B_DQS_P<7>BI 31 DDR3 SO-DIMM CONNECTOR B
VSS_48 VSS_49 DRAWING NUMBER SIZE
31 BI =MEM B DQ<58> 191
DQ58 DQ62
192 =MEM B DQ<62> BI 31
=MEM_B_DQ<59> 193 194 =MEM_B_DQ<63> REVISION
31 BI DQ59 DQ63 BI 31
195
VSS_50 VSS_51
196 R
4.2.0
MEM_B_SA<0> 197 198 MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
30 SA0 EVENT* OUT 29 44 45
=PPSPD_S0_MEM_B 199 200 =I2C_SODIMMB_SDA THE INFORMATION CONTAINED HEREIN IS THE

30 6 VDDSPD SDA BI 47
201 202 PROPRIETARY PROPERTY OF APPLE INC.
30 MEM B SA<1> SA1 SCL =I2C SODIMMB SCL IN 47 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
203
VTT_0 VTT_1
31 OF 113
205 206 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG_PIN MTG_PIN
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
88 12 MEM_A_DQS_N<0> =MEM_A_DQS_N<0> 29 88 12 MEM_B_DQS_N<0> =MEM_B_DQS_N<0> 30

MAKE_BASE=TRUE MAKE_BASE=TRUE
88 12 MEM_A_DQS_P<0> =MEM_A_DQS_P<0> 29 88 12 MEM_B_DQS_P<0> =MEM_B_DQS_P<0> 30
88 12 MEM_A_DQ<7> =MEM_A_DQ<7> 29 88 12 MEM_B_DQ<7> =MEM_B_DQ<7> 30

88 12 MEM A DQ<6> =MEM A DQ<6> 29 88 12 MEM B DQ<6> =MEM B DQ<6> 30
D 88 12
88 12
MEM_A_DQ<2>
MEM_A_DQ<1>
MAKE_BASE=TRUE
=MEM_A_DQ<2>
=MEM_A_DQ<1>
29
29
88 12
88 12
MEM_B_DQ<2>
MEM_B_DQ<1>
MAKE_BASE=TRUE
=MEM_B_DQ<2>
=MEM_B_DQ<1>
30
30
D




C 88 12 MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<16> 29 88 12 MEM_B_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<16> 30 C



B B
88 12 MEM A DQS N<5> =MEM A DQS N<5> 29 88 12 MEM B DQS N<5> =MEM B DQS N<5> 30
88 12 MEM A DQS P<5> =MEM A DQS P<5> 29 88 12 MEM B DQS P<5> =MEM B DQS P<5> 30

88 12 MEM A DQS N<6> =MEM A DQS N<6> 29 88 12 MEM B DQS N<6> =MEM B DQS N<6> 30

A 88 12 MEM A DQS N<7>

MAKE_BASE=TRUE
=MEM A DQS N<7> 29 88 12 MEM B DQS N<7>
MAKE_BASE=TRUE
=MEM B DQS N<7> 30 SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A
PAGE TITLE
DDR3 ALIASES AND BITSWAPS
88 12 MEM_A_DQ<63> =MEM_A_DQ<63> 29 88 12 MEM_B_DQ<63> =MEM_B_DQ<63> 30 DRAWING NUMBER SIZE
88 12 MEM_A_DQ<62>
MAKE_BASE=TRUE
=MEM_A_DQ<62> 29 88 12 MEM_B_DQ<62>
MAKE_BASE=TRUE
=MEM_B_DQ<62> 30
88 12 MEM_A_DQ<61> =MEM_A_DQ<61> 29 88 12 MEM_B_DQ<61> =MEM_B_DQ<61> 30 REVISION
MAKE_BASE=TRUE MAKE_BASE=TRUE R
88 12 MEM_A_DQ<60>
MAKE_BASE=TRUE
=MEM_A_DQ<60> 29 88 12 MEM_B_DQ<60>
MAKE_BASE=TRUE
=MEM_B_DQ<60> 30 4.2.0
88 12 MEM_A_DQ<59> =MEM_A_DQ<59> 29 88 12 MEM_B_DQ<59> =MEM_B_DQ<59> 30 NOTICE OF PROPRIETARY PROPERTY: BRANCH
88 12 MEM A DQ<58> =MEM A DQ<58> 29 88 12 MEM B DQ<58> =MEM B DQ<58> 30 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE INC.
88 12 MEM_A_DQ<57> =MEM_A_DQ<57> 29 88 12 MEM_B_DQ<57> =MEM_B_DQ<57> 30 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
88 12 MEM_A_DQ<56>
MAKE_BASE=TRUE
=MEM_A_DQ<56> 29 88 12 MEM_B_DQ<56>
MAKE_BASE=TRUE
=MEM_B_DQ<56> 30
33 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
6 =PP3V3_S4_VREFMRGN
=PPDDRVTT S3 VREFCA
OMIT 6
VREFMRGN:EXT
R3418 R3403
1
SHORT2 97 PP3V3_S4_VREFMRGN_DAC 200
1 2
MIN_LINE_WIDTH=0.3 mm
NONE MIN NECK_WIDTH=0.2 mm VREFMRGN:EXT 1%
NONE VOLTAGE=3.3V
NONE
402
C3400 1 1C3401 1/16W
MF-LF
2.2UF 0.1UF CRITICAL VREFMRGN:EXT 402
20% 20%
C3403 1
VRef DQ 6.3V 2
CERM
402-LF
VREFMRGN:EXT
2 10V
CERM
402
8
VREFMRGN:EXT
U3400 0.1UF
20%
10V
PPDDRVREF CA MEM A 6
VDD CERM 2 B1CRITICAL VREFMRGN:EXT

Driven by CPU =I2C VREFDACS SCL 6 SCL 1
402 A2 MAX4253
47 IN MSOP VOUTA NC V+ UCSP R3404
133
D
DAC5574
NOTE: CPU DAC output step sizes: =I2C_VREFDACS_SDA 7 SDA VOUTB 2 A1
D DDR3 (1.5V) 7.70mV per step
47 BI
9 A0 VOUTC 4
NC
VREFMRGN_SODIMMS_CA
VREFMRGN:EXT
A3
U3402
A4
VREFMRGN CA SODIMMA BUF 1
1%
1/16W
2
V- MF-LF
Addr=0x98(WR)/0x99(RD) 10 A1 VREFMRGN MEMVREG FBVREF
B4 402
VOUTD 5
GND
3
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable VREFMRGN:EXT
OMIT both at the same time! R3405
200
R3419 VREFMRGN:EXT
1 2
SHORT2 1
1 97 PP3V3 S4 VREFMRGN CTRL
R3401 1%
1/16W
NONE MIN_NECK_WIDTH=0.2 mm 100K MF-LF
402
NONE VOLTAGE=3.3V CRITICAL 5%
NONE 1/16W
=PPVDDQ_S3_DDR_VREF MF-LF
16
32 6 402 VREFMRGN:EXT PPDDRVREF CA MEM B
CRITICAL PLACE_NEAR=Q3420.3:1mm C3402 1 2 402 6
1 0.1UF VCC B1CRITICAL VREFMRGN:EXT

Q3420 C3440 1 R3441 20%
10V U3401 C2 MAX4253 R3406
0.1UF 1K CERM 2 V+ UCSP
SSM6N15AFE 1% 402 PCA9557 133
ISOLATE_CPU_MEM_L 10% C1
5
1/16W VREFMRGN CA SODIMMB BUF 1 2

32 28 21
16V 2 MF-LF VREFMRGN:EXT QFN
(OD) P0 6
U3402
G
SOT563 X5R
402 2 402 NC C3 C4 1%
3 A0 1/16W
PLACE_NEAR=Q3420.3:2mm P1 7 NC V- MF-LF
PPDDRVREF_DQ_MEM_B Addr=0x30(WR)/0x31(RD) 4 A1 P2 9
B4 402
S
D
97 11 CPU_DIMM_VREF_DAC_B 6 NC
5 A2 10 VREFMRGN_CA_SODIMMA_EN
3
4
P3
1 P4 11 VREFMRGN_CA_SODIMMB_EN
C3441 1 R3442 P5 12 VREFMRGN_MEMVREG_EN
0.1UF 1K
10% 1%
1/16W 47 IN =I2C PCA9557D SCL 1 SCL P6 13 VREFMRGN FRAMEBUF EN VREFMRGN:EXT
16V 2 1
X5R
402
MF-LF
2 402
47 BI =I2C_PCA9557D_SDA 2 SDA P7 14
NC R3402
100K
PLACE_NEAR=R3441.2:1mm RESET* 15 5%
C THRM
PAD GND
1/16W
MF-LF
2 402
C
17
8
26 IN PCA9557D_RESET_L
RST* on ’platform reset’ so that system

watchdog will disable margining. VREFMRGN:EXT
C3404 1
32 6 =PPVDDQ_S3_DDR_VREF 0.1UF
20% VREFMRGN:EXT
CRITICAL PLACE_NEAR=Q3420.6:1mm 10V
1 CERM 2 PLACE_NEAR=R7320.2:1mm
Q3420 R3421 NOTE: Margining will be disabled across all 402 B1CRITICAL
C3420 1
1K A2 MAX4253 R3414
SSM6N15AFE 0.1UF 1% soft-resets and sleep/wake cycles. V+ UCSP
33.2K2 TP_DDRREG_FB
ISOLATE_CPU_MEM_L 10%
2
32 28 21 16V 2 1/16W VREFMRGN:EXT A1 VREFMRGN_MEMVREG_BUF 1

MF-LF U3403
G
SOT563 X5R
402 2 402 A3 A4 1%
PLACE_NEAR=Q3420.6:2mm V- 1/16W
PPDDRVREF_DQ_MEM_A MF-LF
B4 402
S
97 11 CPU_DIMM_VREF_DAC_A 6
Currently unused
6
1
Function TBD
1
C3421 1 R3422
0.1UF 1K
10% 1%
16V 2 1/16W
X5R MF-LF
402 2 402
PLACE_NEAR=R3421.2:1mm
VREFMRGN:EXT
1
R3407 VREFMRGN_FRAMEBUF_BUF
100K
B PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION VREFMRGN:EXT
1
R3416
5%
1/16W
MF-LF 1
VREFMRGN:EXT
R3417
B
116S0004 2 RES,MTL FLM,0,5%,402,SM,LF R3403,R3405 VREFMRGN:N
0 2 402 0
5% 5%
1/16W 1/16W
MF-LF B1 MF-LF
2 402 C2 MAX4253 2 402
V+ UCSP
C1
VREFMRGN_FRAMEBUF_BUF_R
U3403 To be incorporated in design
VREFMRGN MEMVREG FBVREF R C3 C4
V- Implementation TBD
B4
VREFMRGN:EXT
1
R3408
100K
5%
1/16W
MF-LF
2 402
A MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef) SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A
PAGE TITLE
DAC Channel: C C D D DDR3/FRAMEBUF VREF MARGINING

DRAWING NUMBER SIZE
PCA9557D Pin: 3 4 5 6 051-9509 D
Apple Inc.
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) REVISION
R
4.2.0
Margined target: 0.300V - 1.200V (+/- 450mV) 1.000V - 2.000V (+/- 500mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.000V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) THE INFORMATION CONTAINED HEREIN IS THE
VRef current: +3.4mA - -3.4mA (- = sourced) +61uA - -61uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 34 OF 113
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP & BT Load Switch
TPS22924B
SWITCH
CHANNEL
N TYPE
18 4 MOHM @3 3V
AIRPORT
RDS(ON)
LOADING
2 A (EDP)
BLUETOOTH
U3510 L3502 CRITICAL

D TPS22924B
CSP
220-OHM-1.4A
PP3V3_S4_AP_FLT
D
33 6 =PP3V3_S4_AP A2 A1 45 PP3V3_S4_AP_FET 1 2 33
B2 VIN VOUT B1 MIN_LINE_WIDTH=0.6 mm 0603 MIN_LINE_WIDTH=0.6 mm 514S0335

MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm CRITICAL
VOLTAGE=3.3V VOLTAGE=3.3V
AP_PWR_EN C2 ON
1 C3502 1 C3503 1 C3504 J3500
33 20 15 IN
GND
0.1UF 0.1UF 10UF SSD-K99
10% 10% 20%
2 16V
X5R
16V
2 X5R 6.3V
2 X5R F-RT-SM1
C1
402 402 603
1
PLACE NEAR=J3500 4 3mm 45 44 BI AP_EVENT_L 2
0.1UF 3
90 18 IN PCIE_AP_R2D_C_N C3505 1 2
201 10% X5R 6.3V 90 PCIE AP R2D N 4
C3506 1 0.1UF 90 PCIE AP R2D P 5

90 18 IN PCIE_AP_R2D_C_P 2
6
201 10% X5R 6.3V
PLACE NEAR=J3500 5 3mm 90 18 IN PCIE_CLK100M_AP_N 7
90 18 IN PCIE_CLK100M_AP_P 8
9
90 18 OUT PCIE_AP_D2R_P 10
90 18 OUT PCIE AP D2R N 11

12
33 OUT AP_WAKE_L 13
33 AP RESET CONN L 14
OUT AP CLKREQ Q L
33
15
U3540 L3501 CRITICAL

220-OHM-1.4A
93 33 USB_BT_MUX_N
16
TPS22924B 93 33 USB_BT_MUX_P
17
CSP PP3V3_G3H_BT_FLT
6 =PP3V3_G3H_BT A2 A1 33 PP3V3_G3H_BT_FET 1 2 18
C B2 VIN VOUT B1 VOLTAGE=3.3V

0603 VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM 19
C
C2 ON 20
45 44 SMC_S4_WAKESRC_EN GND C3507 1 C3508 1
21
0.1UF 10UF
C1
10% 20%
CRITICAL 16V 2 6.3V 2
X5R X5R
402 603
Q3540 1
R3542
SSM6L36FE
SOT563 D 3 10K
P-CH
BT PWR RST 33 5%
1/16W
MF-LF
2 402
20 15 BT_PWR_RST_L 5 G
IN
6 =PP3V3_S0_BT 4 S
D 6 BT_PWR_EN
33 BT_PWR_RST 2 G
Supervisor & CLKFREG # Isolation

1 1 S
R3543 Delay = 60 ms +/- 20%
N-CH
10K
5%
1/16W
MF-LF
2 402
PP3V3_S4_AP_FLT 33 =PP3V3_S4_AP 6 33
CRITICAL
1
B 1
R3530
100K
1
R3531
232K VDD 1 C3530 B
1%
1/16W
1%
1/16W U3530 0.1uF
20%
MF-LF MF-LF SLG4AP016V
2 402 2 402 2 10V
CERM
TDFN 402
P3V3AP_VMON 2 SENSE
+
0.7V -
Wake from BT in G3H circuit
DLY
PP3V3 G3H BT FET 33 AP_RESET_CONN_L 4 RESET*
33 MR* 3 AP_RESET_L IN 26
45 44 OUT SMC_PME_S4_WAKE_L
EN 6 AP_PWR_EN IN 15 20 33
OUT 8 AP_CLKREQ_L OUT 15 21

1 33 AP_CLKREQ_Q_L 7 IN (OD)
C3500 THRM
Q3501 R3500 1 0.1UF
20% 1
PAD GND
3 D R3532
5
SSM3K15FV
15K 10V
SOD-VESM-HF
CERM 2 100K
1% 402
1/20W VDD 1%
MF 1/16W
201 2 U3501 MF-LF
2 402
USB3740
2 S G 1 93 27 BI USB_BT_N 6 DP_2 DFN
93 27 USB_BT_P 7 DM_2 CRITICAL

BI 10 USB_BT_MUX_N 33
DP 93
PP3V3_S4_AP_FLT 33
USB BT WAKEN 2 DP_1
DM 9 USB_BT_MUX_P 33 93
USB_BT_WAKEP 1 DM_1
1
R3570
3 10K
R3502 OE* Q3570
A 5%
A
G 1
0 SSM3K15FV 1/16W
60 44 19 15 IN PM SLP S5 L 1 2 USB BT EN 4 S MF-LF SYNC MASTER=D7 NICK SYNC DATE=12/13/2011
5% GND SOD-VESM-HF 2 402 PAGE TITLE
1/16W
NOSTUFF AIRPORT/BT
8
1 MF-LF
R3501
D
S
402 1 C3501 SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO 38 19 PCIE_WAKE_L AP_WAKE_L 33
15K DRAWING NUMBER SIZE
3
2
0.1uF
1%
1/20W 20%
10V Apple Inc. 051-9509 D
MF 2 CERM REVISION
201 2 402 R
4.2.0
35 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
90 18 IN PCIE_TBT_R2D_C_P<0> C3600 1 2
AB9 OMIT_TABLE AD5
C3640 1 2 PCIE_TBT_D2R_P<0> OUT 18 90
10% 16V X5R CER0201 90 PCIE_TBT_R2D_P<0> PERP_0 PETP_0 90 PCIE_TBT_D2R_C_P<0> 10% 16V X5R CER0201
0.1UF 0.1UF
90 PCIE_TBT_R2D_N<0> AA10
PERN_0 U3600 PETN_0 AD7 90 PCIE_TBT_D2R_C_N<0>
90 18 IN PCIE TBT R2D C N<0> C3601 1 2
CACTUSRIDGE4C C3641 1 2
PCIE TBT D2R N<0> OUT 18 90
10% 16V X5R CER0201 10% 16V X5R CER0201
0.1UF FCBGA 0.1UF
(SYM 1 OF 2)
90 18 IN PCIE_TBT_R2D_C_P<1> C3602 1 2 C3642 1 2 PCIE_TBT_D2R_P<1> OUT 18 90
PCIE GEN2
PCIE_TBT_R2D_P<1> AA12 AD9 PCIE_TBT_D2R_C_P<1>
10% 16V X5R CER0201 90 PERP_1 PETP_1 90 10% 16V X5R CER0201
0.1UF AB13 AD11
0.1UF
90 PCIE_TBT_R2D_N<1> PERN_1 PETN_1 90 PCIE_TBT_D2R_C_N<1>
RECEIVE
TRANSMIT
90 18 IN PCIE_TBT_R2D_C_N<1> C3603 1 2
C3643 1 2
PCIE_TBT_D2R_N<1> OUT 18 90
10% 16V X5R CER0201 10% 16V X5R CER0201
0.1UF 0.1UF
90 18 PCIE TBT R2D C P<2> C3604 1 2 C3644 1 2 PCIE TBT D2R P<2> 18 90
D
IN
0.1UF
10% 16V X5R CER0201 90
90
PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_N<2>
AB15
AA16
PERP_2
PERN_2
PETP_2
PETN_2
AD13
AD15
90
90
PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>
0.1UF
10% 16V X5R CER0201
OUT
D
90 18 IN PCIE_TBT_R2D_C_N<2> C3605 1 2 C3645 1 2 PCIE_TBT_D2R_N<2> OUT 18 90
10% 16V X5R CER0201 10% 16V X5R CER0201
0.1UF 0.1UF
85 84 36 35 34 6 =PP3V3 S4 TBT
90 18 IN PCIE TBT R2D C P<3> C3606 1 2
AA18 AD17
C3646 1 2 PCIE TBT D2R P<3> OUT 18 90
10% 16V X5R CER0201 90 PCIE_TBT_R2D_P<3> PERP_3 PETP_3 90 PCIE_TBT_D2R_C_P<3> 10% 16V X5R CER0201
R3610 1 0.1UF
90 PCIE_TBT_R2D_N<3> AB19
PERN_3 PETN_3 AD19 90 PCIE_TBT_D2R_C_N<3>
0.1UF
47K 90 18 IN PCIE_TBT_R2D_C_N<3> C3607 1 2 C3647 1 2 PCIE_TBT_D2R_N<3> OUT 18 90
5% 10% 16V X5R CER0201 10% 16V X5R CER0201
1/16W 0.1UF 0.1UF
MF LF R6 U20
402
2
36 IN TBT_PCIE_RESET_L PERST_N RSENSE TBT_RSENSE
TBT_PWR_ON_POC_RST_L J2
36 IN PWR_ON_POC_RSTN W20
RBIAS TBT_RBIAS 1
R3655
NO STUFF NOTE: The following pins require testpoints:
AD23
1K
=PP3V3_TBTLC_RTR 6 34 35 36 C3610 1 TP_TBT_MONDC0 MONDC0 U4 1% 0 - GPIO_13 8 - GPIO_15
0.1UF AC24 NC NC 1/20W
10% OMIT TP_TBT_MONDC1 MONDC1 MF 1 - GPIO_1 9 - GPIO_11
16V 201
R3615 1
2
X5R 2 DEBUG For monitoring current/voltage 2 - GPIO_2 10 - GPIO_14
1 402 W18
R3692 1
1
C3690 R3693 NOSTUFF TBT_MONOBSP MONOBS_P 3 - GPIO_3 11 - GPIO_0
R3690 1
1
R3691 1UF 3.3K 3.3K
NONE
NONE TBT MONOBSN W16
MONOBS_N 4 - GPIO_5 12 - GPIO_12
3.3K 3.3K 10%
5% 5% NONE Not used in host mode.
PCIE RESET
6 3V
5% 5% 2 1/16W 1/16W 402 2 DEBUG For monitoring clock 5 - PCIE_RST_1_N 13 - GPIO_10
MISC
CERM N6 TP_TBT_PCIE_RESET0_L
1/16W 1/16W 402 CRITICAL MF LF MF LF Y7 PCIE_RST_0_N
MF LF MF LF 402 402 TP_TBT_THERM_DP THERMDA T1 6 - PCIE_RST_2_N 14 - PB_LSTX
OMIT_TABLE 2 2 TP_TBT_PCIE_RESET1_L
402
2 2
402 8 Use AA8 GND ball for THERM DN PCIE_RST_1_N
Y5 7 - PCIE_RST_3_N 15 - PB_LSRX
VCC R4 PCIE_RST_2_N TP_TBT_PCIE_RESET2_L
98 TBT_SPI_MOSI EE_DI U2 TP TBT PCIE RESET3 L
EEPROM
P5 PCIE_RST_3_N
(TBT_SPI_MOSI) 5 D U3690 Q 2 (TBT_SPI_MISO) 98 TBT_SPI_MISO EE_DO
M95256 RMC6XG TBT_SPI_CS_L AD3
98 EE_CS_N W6
(TBT_SPI_CLK) 6 C MLP
W4 PCIE_CLKREQ_OD_N =TBT_CLKREQ_L OUT 36
98 TBT_SPI_CLK EE_CLK =PP3V3_TBTLC_RTR 6 34 35 36
(TBT_SPI_CS_L) 1 S* K5 TBT_EN_LC_PWR
JTAG/TEST PORT
V1 EN_LC_PWR OUT 36
21 15 IN JTAG TBT TDI TDI 1
R3698
TBTROM_WP_L 3 W* AB3
18 15 IN JTAG TBT TMS TMS 10K
AA6 REFCLK_100_IN_P AB21 PCIE_CLK100M_TBT_P IN 18 90 5%
C TBTROM_HOLD_L 7 HOLD*
VSS THM
PAD
21 15
21 15
IN
OUT
JTAG_TBT_TCK
JTAG_TBT_TDO R2
TCK
TDO
REFCLK_100_IN_N AD21 PCIE_CLK100M_TBT_N IN 18 90
2
1/16W
MF LF
402
R3695
C
TBT_TEST_EN N4
CLOCKS
TEST_EN AA24
806
4 9
AB5 XTAL_25_IN 92 SYSCLK CLK25M TBT R 1 2 SYSCLK CLK25M TBT IN 26 92
TBT_TEST_PWR_GOOD TEST_PWR_GOOD AB23
XTAL_25_OUT TP_TBT_XTAL25OUT 1%
1/16W Divides 3.3V to 1.8V
MF LF
1 1
R3625 R3629 98 34 DP_TBTSNK0_ML_P<3> E14
DPSNK0_3_P TMU_CLK_OUT AA4 TBT_TMU_CLK_OUT
402
0 0 D13 Y3
5% 5% 98 34 DP_TBTSNK0_ML_N<3> DPSNK0_3_N TMU_CLK_IN TBT_TMU_CLK_IN 36 35 34 6 =PP3V3_TBTLC_RTR
1/16W 1/16W
MF LF MF LF E16 NO STUFF
402 2 2 402 98 34 DP_TBTSNK0_ML_P<2> DPSNK0_2_P 1 1 1 1
98 34 DP_TBTSNK0_ML_N<2> D15
DPSNK0_2_N DPSRC_3_P A14 TP_DP_TBTSRC_ML_CP<3> 82
R3697 R3699 R3696 R3680
DISPLAYPORT
SINK PORT 0
B15
100K 10K 1K 10K
E18 DPSRC_3_N TP_DP_TBTSRC_ML_CN<3> 82 5% 5% 5% 5%
98 34 DP_TBTSNK0_ML_P<1> DPSNK0_1_P 1/16W 1/16W 1/16W 1/16W
D17 A12 MF LF MF LF MF LF MF LF
98 34 DP_TBTSNK0_ML_N<1> DPSNK0_1_N DPSRC_2_P TP_DP_TBTSRC_ML_CP<2> 82
2 402 402 2 2 402 2
402
B13 TP_DP_TBTSRC_ML_CN<2>
E20 DPSRC_2_N 82
DP_TBTSNK0_ML_P<0> TBT_DDC_XBAR_EN_L
SOURCE PORT 0
98 34 DPSNK0_0_P 83 34
DP_TBTSNK0_ML_N<0> D19 A10 TP_DP_TBTSRC_ML_CP<1> TBT_GO2SX_BIDIR

98 34 DPSNK0_0_N DPSRC_1_P 82 34 21 15
B11 TP_DP_TBTSRC_ML_CN<1>
A6 DPSRC_1_N 82 R3681 for CYA,
98 34 DP_TBTSNK0_AUXCH_P DPSNK0_AUX_P 1
B5 A8 allows separation R3681
98 34 DP_TBTSNK0_AUXCH_N DPSNK0_AUX_N DPSRC_0_P TP_DP_TBTSRC_ML_CP<0> 82
SNK0 AC Coupling B9 TP_DP_TBTSRC_ML_CN<0>
of GPIO_2/GPIO_9 0
U6 DPSRC_0_N 82 5%
78 OUT DP_TBTSNK0_HPD DPSNK0_HPD if necessary. 1/16W
98 77 IN DP_TBTSNK0_ML_C_P<0> C3620 1 2 DP_TBTSNK0_ML_P<0> 34 98
C2 MF LF
10% 16V DPSRC_AUX_P TP_DP_TBTSRC_AUXCH_CP 82 Stuff one of R3861/2. 2
402
0.1UF X5R CER0201 E6 D3
R3630 1 98 34 DP_TBTSNK1_ML_P<3> DPSNK1_3_P DPSRC_AUX_N TP_DP_TBTSRC_AUXCH_CN 82
98 77 IN DP_TBTSNK0_ML_C_N<0> C3621 1 2 DP_TBTSNK0_ML_N<0> 34 98
D5 34 TBT_GPIO_9
10% 16V 100K 98 34 DP TBTSNK1 ML N<3> DPSNK1_3_N V3
0.1UF X5R CER0201 5% DPSRC_HPD_OD DP_TBTSRC_HPD 82 34 TBT_GPIO_14
1/16W E8
MF LF 98 34 DP_TBTSNK1_ML_P<2> DPSNK1_2_P NO STUFF
98 77 IN DP_TBTSNK0_ML_C_P<1> C3622 1 2 DP_TBTSNK0_ML_P<1> 34 98 402 D7
10% 16V
2
98 34 DP_TBTSNK1_ML_N<2> DPSNK1_2_N 1
R3632 R3683 1
1
R3682
SINK PORT 1
0.1UF Y1 TBT_GO2SX_BIDIR
X5R CER0201 GPIO_2/GO2SX BI 15 21 34
100K 10K 10K
98 77 IN DP_TBTSNK0_ML_C_N<1> C3623 1 2 DP_TBTSNK0_ML_N<1> 34 98 98 34 DP_TBTSNK1_ML_P<1> E10
DPSNK1_1_P (FORCE PWR) GPIO_3 W2 TBT_PWR_EN IN 26 5% 5% 5%
10% 16V D9 J4 1/16W 1/16W 1/16W
0.1UF X5R CER0201 98 34 DP_TBTSNK1_ML_N<1> DPSNK1_1_N GPIO_4/WAKE_N_OD =TBT_WAKE_L 19 MF LF MF LF MF LF
B 98 77 IN DP_TBTSNK0_ML_C_P<2> C3624 1 2 DP_TBTSNK0_ML_P<2> 34 98 98 34 DP_TBTSNK1_ML_P<0> E12

DPSNK1_0_P
GPIO_5/CIO_PLUG_EVENT AA2
AB1
TBT_CIO_PLUG_EVENT
OUT
OUT 15 21
2
402 402
2 2
402
B
10% 16V D11 GPIO_6/CIO_SDA_OD =I2C TBTRTR SDA BI 47 98
0.1UF X5R CER0201 98 34 DP_TBTSNK1_ML_N<0> DPSNK1_0_N AC2
GPIO_7/CIO_SCL_OD =I2C TBTRTR SCL IN 47 98
A4 P3
10% 16V 98 34 DP_TBTSNK1_AUXCH_P DPSNK1_AUX_P GPIO_8/EN_CIO_PWR_OD* (TBT_EN_CIO_PWR_L) TBT_PWR_REQ_L OUT 15 20
0.1UF X5R CER0201 B3 M5
98 34 DP_TBTSNK1_AUXCH_N DPSNK1_AUX_N GPIO_9/OK2GO2SX_OD* TBT_GPIO_9 34 TBT_EN_CIO_PWR_L OUT 36
MAKE BASE=TRUE 85 84 36 35 34 6 =PP3V3 S4 TBT
98 77 IN DP_TBTSNK0_ML_C_P<3> C3626 1 2
DP_TBTSNK0_ML_P<3> 34 98 T5 GPIO_14 T3 TBT_GPIO_14 34
10% 16V 78 OUT DP TBTSNK1 HPD DPSNK1_HPD V5
0.1UF X5R CER0201 GPIO_15 TBT_DDC_XBAR_EN_L OUT 34 83

R3631 1 R3685 1
1
0.1UF
10% 16V
X5R CER0201 98 84 TBT_A_R2D_C_P<0> G24
PA_CIO0_TX_P/DP_SRC_0_P PB_CIO2_TX_P/DP_SRC_0_P R24 TBT_B_R2D_C_P<0> 85 98
R3686
100K OUT OUT 10K 10K
TBT A R2D C N<0> E24 N24 TBT B R2D C N<0>
5% 98 84 OUT PA_CIO0_TX_N/DP_SRC_0_N PB_CIO2_TX_N/DP_SRC_0_N OUT 85 98 5% 5%
1/16W 1/16W 1/16W
DP TBTSNK0 AUXCH C P C3628 1 2 DP TBTSNK0 AUXCH P
PORT0
PORT2
98 71 BI 34 98 MF LF G22 R22 MF LF MF LF
10% 16V 402
2
98 84 IN TBT_A_D2R_P<0> PA_CIO0_RX_P PB_CIO2_RX_P TBT_B_D2R_P<0> IN 85 98 402
2 2
402
0.1UF X5R CER0201 E22 N22
98 84 IN TBT_A_D2R_N<0> PA_CIO0_RX_N PB_CIO2_RX_N TBT_B_D2R_N<0> IN 85 98
98 71 BI DP_TBTSNK0_AUXCH_C_N C3629 1 2 DP_TBTSNK0_AUXCH_N 34 98 84 34 TBT_A_DP_PWRDN
10% 16V K1 P1
0.1UF X5R CER0201 84 OUT TBT_A_CONFIG1_BUF PA_CONFIG1/CIO_0_LSEO PB_CONFIG1/CIO_2_LSEO TBT_B_CONFIG1_BUF OUT 85 85 34 TBT_B_DP_PWRDN
TBT_A_CONFIG2_RC G4 H5 TBT_B_CONFIG2_RC TBT_A_HV_EN
84 IN PA_CONFIG2/CIO_0_LSOE PB_CONFIG2/CIO_2_LSOE IN 85 84 34
SNK1 AC Coupling 85 34 TBT_B_HV_EN

TBT_A_R2D_C_P<1> L24 W24 TBT_B_R2D_C_P<1>
98 84 OUT PA_CIO1_TX_P/DP_SRC_2_P PB_CIO3_TX_P/DP_SRC_2_P OUT 85 98
98 77 IN DP_TBTSNK1_ML_C_P<0> C3630 1 2 DP_TBTSNK1_ML_P<0> 34 98 J24 U24
10% 16V 98 84 OUT TBT A R2D C N<1> PA_CIO1_TX_N/DP_SRC_2_N PB_CIO3_TX_N/DP_SRC_2_N TBT B R2D C N<1> OUT 85 98
R3688 1 1
R3687
0.1UF X5R CER0201
10K 10K
PORT1
PORT3
98 77 IN DP_TBTSNK1_ML_C_N<0> C3631 1 2 DP_TBTSNK1_ML_N<0> 34 98 98 84 IN TBT_A_D2R_P<1> L22
PA_CIO1_RX_P PB_CIO3_RX_P W22 TBT_B_D2R_P<1> IN 85 98 5% 5%
10% 16V J22 U22 1/16W 1/16W
0.1UF X5R CER0201 98 84 IN TBT_A_D2R_N<1> PA_CIO1_RX_N PB_CIO3_RX_N TBT_B_D2R_N<1> IN 85 98 MF LF MF LF
402 402
2 2
98 77 IN DP_TBTSNK1_ML_C_P<1> C3632 1 2 DP_TBTSNK1_ML_P<1> 34 98 84 OUT TBT_A_LSTX N2
PA_LSTX/CIO_1_LSEO PB_LSTX/CIO_3_LSEO L6 TBT_B_LSTX OUT 85
10% 16V J6 G6
0.1UF X5R CER0201 84 IN TBT_A_LSRX PA_LSRX/CIO_1_LSOE PB_LSRX/CIO_3_LSOE TBT_B_LSRX IN 85

10% 16V
PORTS
0.1UF DP_TBTPA_ML_C_P<1> A16 A20 DP_TBTPB_ML_C_P<1>
X5R CER0201 98 84 OUT PA_DPSRC_1_P PB_DPSRC_1_P OUT 85 98
DP TBTPA ML C N<1> B17 B21 DP TBTPB ML C N<1>

A 98 77 IN DP_TBTSNK1_ML_C_P<2> C3634
0.1UF
1 2
10% 16V
X5R CER0201
DP_TBTSNK1_ML_P<2> 34 98
98 84
98 84
OUT
DP_TBTPA_ML_C_P<3> A18
PA_DPSRC_1_N
PA_DPSRC_3_P
PB_DPSRC_1_N
PB_DPSRC_3_P A22 DP_TBTPB_ML_C_P<3>

OUT 85 98
85 98
SYNC MASTER=D7 DOUG SYNC DATE=01/11/2012 A
OUT OUT PAGE TITLE
C3635 B19 B23
98 77 IN DP_TBTSNK1_ML_C_N<2>
0.1UF
1 2
10% 16V
X5R CER0201
DP_TBTSNK1_ML_N<2> 34 98 98 84 OUT DP_TBTPA_ML_C_N<3> PA_DPSRC_3_N PB_DPSRC_3_N DP_TBTPB_ML_C_N<3> OUT 85 98
Thunderbolt Host (1 of 2)
F3 D1 DRAWING NUMBER SIZE
DP TBTPA AUXCH C P PA_AUX_P PB_AUX_P DP TBTPB AUXCH C P
98 77 IN DP_TBTSNK1_ML_C_P<3> C3636 1 2
10% 16V
DP_TBTSNK1_ML_P<3> 34 98
98 84
98 84
BI
DP TBTPA AUXCH C N F1
PA_AUX_N PB_AUX_N E2 DP TBTPB AUXCH C N
BI 85 98
85 98 Apple Inc. 051-9509 D

0.1UF BI BI
X5R CER0201 REVISION
R
98 77 IN DP_TBTSNK1_ML_C_N<3> C3637 1 2 DP_TBTSNK1_ML_N<3> 34 98 84 IN DP_TBTPA_HPD H1
PA_DPSRC_HPD PB_DPSRC_HPD K3 DP_TBTPB_HPD IN 85 4.2.0
10% 16V
0.1UF X5R CER0201
TBT_A_HV_EN G2 M1 TBT_B_HV_EN
84 34 OUT GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 OUT 34 85
M3 L2 THE INFORMATION CONTAINED HEREIN IS THE
84 OUT TBT_A_CIO_SEL GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 TBT_B_CIO_SEL OUT 85 PROPRIETARY PROPERTY OF APPLE INC.
98 71 BI DP_TBTSNK1_AUXCH_C_P C3638 1 2 DP_TBTSNK1_AUXCH_P 34 98 H3 L4 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10% 16V 84 34 OUT TBT_A_DP_PWRDN GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2 TBT_B_DP_PWRDN OUT 34 85
0.1UF X5R CER0201 36 OF 113
98 71 BI DP_TBTSNK1_AUXCH_C_N C3639 1 2 DP_TBTSNK1_AUXCH_N 34 98
10% 16V For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
0.1UF X5R CER0201 IV ALL RIGHTS RESERVED 34 OF 100
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V05_TBTCIO_RTR 6
CRITICAL
D 36 6 =PP1V05 TBTLC RTR
J10 OMIT_TABLE K11
???? mW (Single-Port)
2700 mW (Dual-Port)
D
??? mW (Single Port) VCC1P0_ON VCC1P0
J12 U3600 K15 EDP: 3000 mA
250 mW (Dual Port) VCC1P0_ON VCC1P0
EDP: 1000 mA C3700 1 1
C3710 1
C3711 1
C3712 1
C3713 J14
VCC1P0_ON CACTUSRIDGE4C VCC1P0 L10
C3740 1
C3741 1
C3742 1
C3743 1
C3744 1
C3745 1 1
C3705
10UF 1UF 1UF 1UF 1UF J16 FCBGA L14 1UF 1UF 1UF 1UF 1UF 1UF 10UF
20% 20% 20% 20% 20% VCC1P0_ON (SYM 2 OF 2) VCC1P0 20% 20% 20% 20% 20% 20% 20%
6 3V 6 3V 6 3V 6 3V 6 3V J8 M11 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V
CERM X5R 2 2 X5R 2 X5R 2 X5R 2 X5R VCC1P0_ON VCC1P0 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 2 CERM X5R
0402 1 0201 0201 0201 0201 K17 M15 0201 0201 0201 0201 0201 0201 0402 1
VCC1P0_ON VCC1P0
T15 N10
VCC1P0_ON VCC1P0
U14 N14
VCC1P0_ON VCC1P0
V7 P11
VCC1P0_ON VCC1P0
W8 P15
C3701 1 1 C3714 1 C3715 1 C3716 1 C3717 VCC1P0_ON VCC1P0
10UF 1UF 1UF 1UF 1UF VCC1P0 R10
20% 20% 20% 20% 20% G10
VCC1P0_PE
VCC
6 3V 6 3V 6 3V 6 3V 6 3V R14
CERM X5R 2 2 X5R 2 X5R 2 X5R 2 X5R G12 VCC1P0
0402 1 0201 0201 0201 0201 VCC1P0_PE T11
G14 VCC1P0
VCC1P0_PE U10
G16 VCC1P0
VCC1P0_PE V11
G18 VCC1P0
VCC1P0_PE W10
=PP3V3_TBTLC_RTR 6 34 36
H19 VCC1P0
VCC1P0_PE ??? mW (Single-Port)
K19
VCC1P0_PE M7 250 mW (Dual-Port)
M19 VCC3P3
VCC1P0_PE P7 EDP: 240 mA
P19 VCC3P3
VCC1P0_PE T7
T19 VCC3P3 C3770 1
C3771 1
C3772 1
C3773 1
C3774 1 1
C3760
VCC1P0_PE 1UF 1UF 1UF 1UF 1UF 10UF
V15 L18 20% 20% 20% 20% 20% 20%
VCC1P0_PE VCC3P3_CIO 6 3V 6 3V 6 3V 6 3V 6 3V 6 3V
V19 N18 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 2 CERM X5R
VCC1P0_PE VCC3P3_CIO 0201 0201 0201 0201 0201 0402 1
W12 R18
VCC1P0_PE VCC3P3_CIO
W14
VCC1P0_PE H11
VCC3P3_DP
H13
C G8
H9
VCC1P0_DPAUX
VCC1P0_DPAUX
VCC3P3_DP
VCC3P3_DP H15 C
H17
VCC3P3_DP
AD1 H7
VSS VCC3P3_DPAUX
K13
VSS
K9
VSS
L12 =PP3V3_S4_TBT
VSS 6 34 36 84 85
L16 K7
VSS VCC3P3_POC EDP: 10 mA
L8
VSS
M13 C22
VSS VSSPE C3790 1
M17
VSS VSSPE C24 1UF
20%
M9 C4 6 3V
VSS VSSPE X5R 2
N12 C6 0201
VSS VSSPE
N16 C8
VSS VSSPE
N8 D21
VSS VSSPE
P13 D23
VSS VSSPE
P17 E4
VSS VSSPE
P9 F11
VSS VSSPE
R12 F13
VSS VSSPE
R16 F15
VSS VSSPE
R8 F17
VSS VSSPE
T13 F19
VSS VSSPE
T17 F21
VSS VSSPE
T9 F23
VSS VSSPE
U12 F5
VSS VSSPE
GND
U16 F7
VSS VSSPE
B U8
V9
VSS
VSS
VSSPE
VSSPE
F9
G20
B
H21
VSSPE
A2 H23
VSSPE VSSPE
A24 J18
VSSPE VSSPE
AA14 J20
VSSPE VSSPE
AA20 K21
VSSPE VSSPE
AA22 K23
VSSPE VSSPE
AA8 L20
VSSPE VSSPE
AB11 M21
VSSPE VSSPE
AB17 M23
VSSPE VSSPE
AB7 N20
VSSPE VSSPE
AC10 P21
VSSPE VSSPE
AC12 P23
VSSPE VSSPE
AC14 R20
VSSPE VSSPE
AC16 T21
VSSPE VSSPE
AC18 T23
VSSPE VSSPE
AC20 U18
VSSPE VSSPE
AC22 V13
VSSPE VSSPE
AC4 V17
VSSPE VSSPE
AC6 V21
VSSPE VSSPE
AC8 V23
VSSPE VSSPE
B1 Y11
VSSPE VSSPE
B7 Y13
VSSPE VSSPE
C10 Y15
VSSPE VSSPE
C12 Y17
VSSPE VSSPE
A C14
C16
VSSPE
VSSPE
VSSPE
VSSPE
Y19
Y21 SYNC MASTER=D7 DOUG SYNC DATE=01/11/2012 A

PAGE TITLE
C18 Y23
C20
VSSPE
VSSPE
VSSPE
VSSPE Y9 Thunderbolt Host (2 of 2)
DRAWING NUMBER SIZE

REVISION
R
4.2.0
37 OF 113
EDP current / power consumption figures from CR DG v0.57, IBL doc #472455.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PPVIN_SW_TBTBST (8-13V Boost Input)
- =PP15V_TBT_REG (15V Boost Output)
- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)
- =PP3V3_TBT_FET (3.3V FET Output)
- =PP3V3_S0_TBTPWRCTL
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)
- =PP1V05_TBT_FET (1.05V FET Output)
Signal aliases required by this page:
D - =TBT_CLKREQ_L
- =TBT_RESET_L
D
BOM options provided by this page:
TBTBST:Y - Stuffs 15V boost circuitry.
Supervisor & CLKREQ# Isolation

=PP3V3_TBTLC_RTR 6 34 35 36
C C
6 =PP3V3_S0_TBTPWRCTL
C3800 1
CRITICAL 1
R3807
1
0.1UF
Q3840 1
R3840 10%
25V
VDD 100K
5%
SSM3K15AMFVAPE 10K 2
U3800 1/16W
G 1
X5R
5% 402 MF LF
VESM 1/16W
SLG4AP016V 2
402
MF LF
2
402 TDFN =PP1V05_TBTLC_RTR 6 35
+ SENSE
2
D
34 IN TBT_EN_LC_PWR - 0.7V
3
Platform (PCIe) Reset DLY

RESET* 4 TBT_PCIE_RESET_L OUT 34
26 IN =TBT_RESET_L 3 MR*
DLY = 60 ms +/- 20%
Platform(PCIe) Reset
6 EN
=TBT_CLKREQ_L IN 34
21 15 OUT TBT_CLKREQ_L 8 OUT
(OD) IN 7 TBT_CLKREQ_ISOL_L
Pull-up provided by SB page. MAKE BASE=TRUE
THRM
GND PAD
5
TBT "POC" Power-up Reset

Intel investigating whether RC is sufficient.
B 3.3V TBT "LC" Switch 85 84 35 34 6 =PP3V3_S4_TBT

B
U3810 SMC_DELAYED_PWRGD IN 44 45 61
=PP3V3_S0_P3V3TBTFET TPS22924 =PP3V3_TBTLC_FET CRITICAL
1
6 6
CSP
A2 A1 Max Current = 2A (85C) Pull-up: R3610
VDD =PP3V3_S0_PCH_GPIO 6 15 19 20
B2 VIN VOUT B1
2 SENSE U3830 RESET* 6 TBT_PWR_ON_POC_RST_L
CRITICAL U3810 TPS3808
OUT 34
C2 ON (IPU
TBTPOCRST_CT 3 QFN 4 TBTPOCRST_MR_L 1
GND Part TPS22924C CT MR* R3830
THRM
GND PAD Q3825 100K
C1
C3810
5
1
Type Load Switch SSM6N37FEAPE 5%
1 C3831 C3830 1
G
1/16W
1UF
7
SOT563 MF LF
10%
R(on) 18.5 mOhm Typ 0.0047UF 0.1UF TPS3808G25 402
6 3V 10% 10% 2
CERM 2 25V 25V
@ 2.5V 25.8 mOhm Max 2 2 Vt = 2.33V +/- 2%
S
402 CERM X5R TBT_SW_RESET_L
402 402 IN 21
Delay = 27.3ms
4
TBT_EN_LC_ISOL
C3825 1
330PF
10%
R3816 1 50V
2
36.5K CERM
402
1%
1/16W
MF LF
402
2
TBT_EN_LC_RC
1.05V TBT "LC" Switch 36 6 =PP1V05_S0_P1V05TBTFET 1.05V TBT "CIO" Switch
36 35 34 6 =PP3V3_TBTLC_RTR
U3815 U3820
36 6 =PP1V05 S0 P1V05TBTFET TPS22924 =PP1V05 TBTLC FET 6
TPS22920 =PP1V05 TBTCIO FET 6
A2
CSP
A1 Max Current = 2A (85C) R3820 1 A2
CSP
A1 Max Current = 4A (85C)
VIN VOUT 100K
B2 B1 5% B2 B1
VIN VOUT
CRITICAL U3815 1/16W
MF LF C2 C1 U3820
A C3815
1UF
1 C2 ON
GND Part TPS22924C
402
2
TBT_EN_CIO_PWR D2 ON
CRITICAL
Part TPS22920 SYNC MASTER=D7 DOUG SYNC DATE=01/11/2012 A
10% PAGE TITLE
GND
C1
6 3V
CERM 2 Type Load Switch Type Load Switch
Thunderbolt Power Support
D1
402
D 6 C3820 1
R(on) 20.3 mOhm Typ Q3825 1UF R(on) 8 mOhm Typ DRAWING NUMBER SIZE
@ 1.0V 28.6 mOhm Max SSM6N37FEAPE
SOT563
10%
6 3V
2
@ 1.05V 11.5 mOhm Max
C3816 1 CERM
402 REVISION
R
1UF 4.2.0
10%
6 3V
CERM 2 2 G S 1
402
34 IN TBT_EN_CIO_PWR_L PROPRIETARY PROPERTY OF APPLE INC.
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 38 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_ENET_PHY 38
396mA (1000base-T, Caesar II)

38 37 6 =PP3V3_ENET_PHY
281mA (1000base-T max power, Caesar IV) VDD for Card Reader I/O
38 PP3V3R1V8_CR_VDDIO
MIN_LINE_WIDTH=0.3 mm ENET_SR_LX
CRITICAL MIN_NECK_WIDTH=0.15 mm 38
VOLTAGE=3.3V Internal 1.2V Switching Regulator pins.
L3900 ENET_SR_VFB CRITICAL
FERR-600-OHM-300MA-0.85OHM 38
L3920
1 2 ENET_XTALVDDH FERR-600-OHM-300MA-0.85OHM
D 0402 MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V C3900 1
VOLTAGE=3.3V
PP1V2_ENET_PHY AVDDL 1 2
D
MIN_LINE_WIDTH=0.4 mm 0402
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
16V
X5R-CERM 2
0201
C3921 1 1 C3920
CRITICAL 0.1UF 4.7UF
10% 20%
L3905 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL
FERR-600-OHM-300MA-0.85OHM 0201 402 L3925
1 2 PP3V3_ENET_PHY BIASVDDH FERR-600-OHM-0.5A
0402
MIN_NECK_WIDTH=0.2 mm PP1V2 ENET PHY PCIEPLL 1 2
VOLTAGE=3.3V C3905 1 MIN_LINE_WIDTH=0.4 mm SM
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
16V
X5R-CERM 2
0201
C3926 1 1 C3925
CRITICAL 0.1UF 4.7UF
10% 20%
L3910 16V
X5R-CERM 2 2 6.3V
X5R-CERM1 CRITICAL
FERR-600-OHM-300MA-0.85OHM 0201 402 L3930
1 2 PP3V3 ENET PHY AVDDH FERR-600-OHM-300MA-0.85OHM
0402
VOLTAGE=3.3V R39101
1 C3910 1 C3911 PP1V2_ENET_PHY GPHYPLL
1 2
0.1UF 0.1UF MIN_NECK_WIDTH=0.15 mm 0402
4.7K 10% 10% VOLTAGE=1.2V
5% 16V
2 X5R-CERM 16V
1/16W
MF-LF 0201
2 X5R-CERM
0201
C3931 1 1 C3930
402 2 0.1UF 4.7UF
10% 20%
16V 2 6.3V
X5R-CERM 2 X5R-CERM1
0201 402
R39401 1
R3941 C3915 1 1 C3916
4.7K 4.7K 4.7UF 0.1UF
20% 10%
42
48
BIASVDDH 37
XTALVDDH 17
20
56
62
SR_VDD 14
SR_VDDP 15
SR_LX 16
SR_VFB 13
39
45
51
29
32
GPHY_PLLVDDL 36
35
61
6.3V 16V C3936 1 1 C3935
7
5% 5%
1/16W 1/16W X5R-CERM1 2 2 X5R-CERM
0.1UF 10UF
C =PP3V3_S0_ENET MF-LF
402 2
MF-LF
2 402
402 0201 10% 20%
C
PCIE_PLLVDDL
6 AVDDH VDDO AVDDL VDDC 16V
X5R-CERM 2 2 6.3V
X5R LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
0201 603 the card reader on-chip I/O.
1
C3950 R3942 Connect only to U3900 pin 20.
1K
0.1UF 5% Current
1 2 1/16WLimiting OMIT_TABLE
90 18 OUT PCIE_ENET_D2R_N MF-LF
2 402 Resistor U3900
10%
16V
X5R-CERM
C3951 ENET_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD ENET) BCM57766C0KMLG TRD0_P 40 ENETCONN_MDI_P<0> BI 38 93
0201 0.1UF QFN-8X8 41 ENETCONN_MDI_N<0>
1 2 TRD0_N BI 38 93
90 18 OUT PCIE_ENET_D2R_P
90 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 ENETCONN_MDI_P<1> BI 38 93
10% 90 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENETCONN_MDI_N<1> 38 93
16V BI
X5R-CERM 46 ENETCONN_MDI_P<2>
C3955 0201 90 PCIE_ENET_R2D_P 33 PCIE_RXD_P TRD2_P BI 38 93
PP3V3R1V8_ENET_LR_OUT
0.1UF TRD2_N 47 ENETCONN_MDI_N<2> BI 38 93
38
1 2
90 PCIE_ENET_R2D_N 34 PCIE_RXD_N
90 18 IN PCIE_ENET_R2D_C_P TRD3_P 50 ENETCONN_MDI_P<3> BI 38 93
VOLTAGE=3.3V
10% 90 18 IN PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 ENETCONN_MDI_N<3> BI 38 93
16V
X5R-CERM
C3956 90 18 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
0201 0.1UF ENET_CR_1V8_EN
1 2 GPIO_0/CR_ACT_LED* 5 38
PCIE_ENET_R2D_C_N ENET_RESET_L 11 PERST*
(IPD
90 18 IN 39 IN (IPD)
GPIO_1/LR_OUT 8
10% 18 15 ENET_CLKREQ_L 12 CLKREQ* (OD) GPIO_2/MEDIA_SENSE 9 ENET_MEDIA_SENSE 15 18 93
16V OUT OUT
X5R-CERM NOTE "IPx" == Programmable pull up/down
38 =ENET_WAKE_L 0201 3 WAKE* (OD)
OUT ENET_SD_DETECT_L
(See note)
(IPx ENET) SD_DETECT
SD DETECT can only be used active low due to errata
o1 IN 39 93
39 26 IN ENET_LOW_PWR 4 LOW_PWR (IPD) (IPU ENET) CR_CMD 26 93 ENET_SD_CMD R3961 33 1 2 SDCONN_CMD IN 39 93

WAKE# 5% 1/20W MF 201
CR_CLK 21 93 ENET_SD_CLK R3979 33 1 2 SDCONN_CLK OUT 39 93
Must isolate from PCIe WAKE# if PHY SMB_ENET_SCL 6 SMB_CLK 5% 1/20W MF 201
is powered-down in S3/S5. Standard SMB ENET SDA 10 SMB_DATA (IPD ENETM) CR_DATA0 25 93 ENET CR DATA<0> R3971 33 1 2 SDCONN DATA<0> BI 39 93
N-channel FET isolation suggested. CR_DATA1 24 93 ENET_CR_DATA<1> R3972 33 1 2 5% 1/20W MF 201

SDCONN_DATA<1> BI 39 93
93 37 ENET_SCLK 66 SCLK_SPD1000LED* R3973 33 5% 1/20W MF 201
B If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
93 37
BI
IN ENET_MISO 64 SI/EEDATA
CR_DATA2
CR_DATA3
23
22
93 ENET_CR_DATA<2>
ENET_CR_DATA<3> R3974 33
1
1
2
2 5% 1/20W MF 201
SDCONN_DATA<2>
SDCONN_DATA<3>
BI 39 93
B
(IPU
93 39 93
ENET MOSI 65 BI
93 37 BI SO_LINKLED* 52 ENET_CR_DATA<4> R3975 33 5% 1/20W MF 201
SDCONN_DATA<4>
(IPU-ENET
CR_DATA4 93 1 2 BI 39 93
93 37 BI ENET CS L 63 CS*/EECLK R3976 33 5% 1/20W MF 201
CR_DATA5 53 93 ENET_CR_DATA<5> 1 2 SDCONN_DATA<5> BI 39 93
38 ENET_CR_3V3_EN_L 2 SPD100LED*/SERIAL_DO (OD) CR_DATA6 54 93 ENET_CR_DATA<6> R3977 33 1 2 5% 1/20W MF 201

SDCONN_DATA<6> BI 39 93
38 OUT ENET TRAFFICLED L 67 TRAFFICLED*/SERIAL_DI (OD) CR_DATA7 55 93 ENET CR DATA<7> R3978 33 1 2

5% 1/20W MF 201
SDCONN DATA<7> BI 39 93
No MS (Memory Stick) Insert feature needed. 5% 1/20W MF 201
(IPU ENET)
MS_INS* 59 Control signal to light LED or control SD bus power.
92 26 IN SYSCLK CLK25M ENET 18 XTALI NC
19 XTALO
(IPU
CR_LED*/CR_BUS_PWR 60
ENET) ENET_CR_PWREN OUT 39
NC (IPU ENET)
CR_WP* 57 SDCONN_WP IN 39 93
93 ENET RDAC 38 RDAC (NO IPU OR IPD ENET) SR_DISABLE 68 ENET SR DISABLE R3981 1K 1 2 402
THRM_PAD 5% 1/16W MF-LF
(See note)
PHY Non-Volatile Memory
69
1
R3965 ENET 1.2V SR IS ENABLED IF FLOATING. ENET supports both active-levels for WP.
1.24K
ROM contains MAC address, PCIe config 1% ENET_CR Signals
1/16W
info as well as code for Bonjour proxy. MF-LF
Avoids need for EFI to program at startup. 2 402 BCM requests SD CR[0:7], CMD, CLK termination. PLACEMENT NOTE=PLACE R3961 NEAR U3900
(Required ROM size 1 Mbit)

ENET_SR_DISABLE PLACEMENT NOTE=PLACE R3979 NEAR U3900
38 37 6 =PP3V3_ENET_PHY If ENET switching regulator is PLACEMENT NOTE=PLACE R3971 NEAR U3900
used, this pin can float (alias to PLACEMENT NOTE=PLACE R3972 NEAR U3900
TP_). If not used, must be pulled

6
PLACEMENT NOTE=PLACE R3973 NEAR U3900

1 C3990 to 3.3V ENET via 1K resistor (not PLACEMENT NOTE=PLACE R3974 NEAR U3900
VCC 0.1UF
10% provided on this page). PLACEMENT NOTE=PLACE R3975 NEAR U3900
U3990 2 16V
X5R-CERM
0201 PLACEMENT NOTE=PLACE R3976 NEAR U3900
AT45DB011D
SOIC-8S1 PLACEMENT NOTE=PLACE R3977 NEAR U3900
93 37 IN ENET_SCLK 2 SCK OMIT_TABLE SI 1 ENET_MOSI IN 37 93 PLACEMENT NOTE=PLACE R3978 NEAR U3900
A 93 37 ENET_CS_L 4 CS*
IN PAGE TITLE
SO 8 ENET_MISO
5 WP*
NOSTUFF
OUT 37 93
ETHERNET PHY (CAESAR IV)
1 DRAWING NUMBER SIZE
3 RESET*
GND
R3990 1R3997 051-9509 D
4.7K
5%
4.7K
5%
Apple Inc. REVISION
7
NOTE: Pull-down on SO plus internal pull-ups on 1/16W 1/16W R

MF-LF MF-LF 4.2.0
other 3 SPI pins configures ENET for the 2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Atmel AT45DB011D (1Mbit) ROM. If a different THE INFORMATION CONTAINED HEREIN IS THE
ROM is used then the straps must change. PROPRIETARY PROPERTY OF APPLE INC.
NOTE: ENETM requires SI pull-down instead of SO. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
39 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V ENET FET

CAESAR IV 1.2V INT.VR CMPTS ENET Enable Generation CRITICAL
Q4020
CAESAR IV ACTIVITY LED
"ENET" = "S0" || ("S3/S5" && "WOL_EN")
NTR4101P
SOT-23-HF
L4010 38 37 6 =PP3V3_ENET_PHY
38 37 6 =PP3V3_ENET_PHY 4.7UH-0.8A 6 =PP3V3_S4_FET_ENET 2 S D 3 PP3V3_ENET_FET 6
37 ENET_SR_LX 1 2 PP1V2 ENET INTREG 38
D Power decoupling
1 C4010 1 C4011
VOLTAGE=1.2V
PCAA031B-SM
MIN NECK_WIDTH=0.2MM R40201
1 C4020
0.033UF
G
DEVELOPMENT
1
R4050
D
4.7UF 0.1UF SWITCH_NODE=TRUE C4012 1
C4013 1 VOLTAGE=1.2V 10K
5%
10%
16V
2 X5R
1 330
20% 10% DIDT=TRUE 10UF 0.1UF 5%
6.3V
2 X5R-CERM1 2 16V
X5R
20%
6.3V
10%
16V
1/16W
MF-LF R4021
402 C4021 1/16W
MF-LF
402 402 Feedback loop X5R 2 X5R 2 402 2 0.01UF
603 402
100K 2 1 2 402
PM_EN_ENET_L 1 2 P3V3ENET_SS ENET_ACT
5%
3 1/16W 10% A
50V DEVELOPMENT
Q4021 D
MF-LF
402 X7R
2N7002DW-X-G 402 LED3850
SOT-363 GREEN 3 6MCD
2 0X1 25MM SM
21 15 WOL_EN 5 G S 6 K
IN SILKSCREEN:ENET ACT
Q4021 D
4 2N7002DW-X-G
SOT-363
60 45 44 28 19 15 PM SLP S3 L 2 G S
IN
38 PP1V2_ENET_INTREG =PP1V2 ENET PHY 37
1 37
ENET_TRAFFICLED_L
MAKE_BASE=TRUE
ENET_SR_VFB 37
38 =PP3V3_S4_ENET_FET 6 =PP1V8_S0_ENET
38 =PP3V3_S4_ENET_FET
CAESAR IV WAKE# ISOLATION

R40321 R40331
4 1 10K 10K
C =PP3V3 ENET PHY 6 37 38
5%
1/20W
MF
5%
1/20W
MF
C
OMIT_TABLE 201 2 201 2
38 37 ENET CR 3V3 EN L 5 38 37 ENET CR 1V8 EN 2
1 G S UFET-1.60X1.60 G S UFET-1.60X1.60
Q4070 R4070 FDME1024NZT FDME1024NZT 38 37 ENET_CR_3V3_EN_L
SSM3K15AMFVAPE 10K ENET_CR_1V8_EN
5% Q4030 Q4030 38 37
G 1
VESM 1/16W D D
MF-LF
2 402 3 8 6 7
R4030
D
33 19 PCIE_WAKE_L ENET_WAKE_L =ENET_WAKE_L 37 0

MAKE_BASE=TRUE PP3V3R1V8_CR_FET 1 2
3
MIN_NECK_WIDTH=0.15MM 5%
VOLTAGE=3.3V 1/16W
MF-LF
402 PP3V3R1V8_CR_VDDIO 37
NOSTUFF
R4031
0
37 PP3V3R1V8_ENET_LR_OUT 1 2 1 C4030 1 C4031 1 C4032
5% 4.7UF 0.1UF 0.1UF
514-0822 1/16W 20% 10% 10%
157S0058 CRITICAL MF-LF 6.3V
2 X5R-CERM12
16V 16V
CRITICAL 402 X5R-CERM 2 X5R-CERM
402 0201 0201
T4000 J4000
93 37 ENETCONN_MDI_P<1> 1 SM 12 ENETCONN_MDI_T_P<1> BI 38 93
K70-K72
BI F-ANG-TH
ENET_MDI
ENETCONN_MDI_N<1> 2 11 ENETCONN_MDI_T_N<1> BI
93 37 BI 38 93
93 38 BI ENETCONN MDI T N<3> 8 ENET_MDI_TRAN3-
93 38 ENETCONN_MDI_T_P<3> 7 ENET_MDI_TRAN3+ PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
BI
3 93 10 ENETCONN MCT1
ENETCONN_MDI_T_N<1> 6 ENET_MDI_TRAN1-
TX
93 38 BI 376S1092 1 MOSFET COMP N /P CH 20V 3 8/2 6A Q4030 CRITICAL
93 38 BI ENETCONN_MDI_T_N<2> 5 ENET_MDI_TRAN2-
LFE8904CF 93 38 BI ENETCONN_MDI_T_P<2> 4 ENET_MDI_TRAN2+
4 93 9 ENETCONN_MCT3
93 38 ENETCONN_MDI_T_P<1> 3 ENET_MDI_TRAN1+
B ENETCONN_MDI_P<3> 5 8 ENETCONN_MDI_T_P<3> BI
93 38
BI
BI ENETCONN_MDI_T_N<0> 2 ENET_MDI_TRAN0- B
93 37 BI 38 93
93 38 BI ENETCONN MDI T P<0> 1 ENET_MDI_TRAN0+
ENETCONN MDI N<3> 6 7 ENETCONN MDI T N<3> BI

93 37 BI 38 93 9
RX 10
11
CRITICAL 12 SHIELD
PINS
T4010
SM
13
93 37 ENETCONN_MDI_N<2> 1 12 ENETCONN_MDI_T_N<2> BI 38 93 14
BI
93 37 ENETCONN MDI P<2> 2 11 ENETCONN MDI T P<2> BI 38 93

BI
TX
LFE8904CF
93 37 ENETCONN MDI N<0> 5 8 ENETCONN MDI T N<0> BI 38 93

BI
93 37 ENETCONN_MDI_P<0> 6 7 ENETCONN_MDI_T_P<0> BI 38 93
BI
RX
ENETCONN_TCT
1 1 1 1
R4000 R4001 R4002 R4003
A 1 C4001
0.1UF
1 C4002
0.1UF
1 C4003
0.1UF
1 C4004
0.1UF
75
5% 5%
75
5%
75
5%
75 SYNC MASTER=D7 NICK SYNC DATE=01/12/2012 A
20% 20% 20% 20% 1/16W 1/16W 1/16W 1/16W PAGE TITLE
10V 10V 10V 10V MF-LF MF-LF MF-LF MF-LF
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402 2 402 2 402 2 402 2 402 Ethernet Support & Connector
DRAWING NUMBER SIZE
93 ENETCONN_MCT_BS Apple Inc. 051-9509 D
MIN_LINE_WIDTH=0.4 MM REVISION
MIN_NECK_WIDTH=0.2 mm R
NOSTUFF 4.2.0
1 C4000 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1000PF THE INFORMATION CONTAINED HEREIN IS THE
10% PROPRIETARY PROPERTY OF APPLE INC.
2KV THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 CERM
40 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SD CARD 3.3V OVERCURRENT PROTECTION CHIP
=PP3V3_S0_SDCARD 6 39
1
R4101 D
D 353S2548
5%
10K
1/16W
U4100 MF-LF =PP3V3 S0 SW SD PWR 39
TPS2553 2 402
=PP3V3 S0 SDCARD 6 IN SON
39 6 OUT 1 PP3V3 S0 SW SD PWR
CRITICAL MAKE_BASE=TRUE
ILIM 2 SDCONN_ILIM MIN LINE WIDTH=0 4 mm
VOLTAGE=3 3V
37 IN ENET_CR_PWREN 4 EN FAULT* 3 SDCONN_OC_L
CRITICAL THRML
GND PAD 1 1
C4104 1 C4100 1 C4101 1 R4113 1 C4102 1 C4103 R4100
7
100UF 10UF 0.1UF 26.1 10UF 0.1UF 47K
20% 20% 10% 1% 20% 10% 5%
6 3V 2 6.3V 2 16V 1/16W 2 6.3V
X5R
16V
2 X7R-CERM 1/16W
POLY TANT X5R X7R-CERM 2 MF-LF
603 402
MF-LF
CASE B2 SM 603 402 2 402 2 402
NOSTUFF
516-0249
SD CARD CONNECTOR
J4100
SD-CARD-K70-K72
F-ANG-TH
R4107 0
C 93 37
93 37
BI SDCONN_DATA<3>
SDCONN CMD
MF-LF 1/16W 1 2 402 5%
R4103 1 2 0
93
93
SDCONN_DATA_R_<3>
SDCONN CMD R
1
2
CD/DAT3
CMD
C
OUT
MF-LF 1/16W 5% 402 3 VSS
39 =PP3V3_S0_SW_SD_PWR 4 VDD
93 37 IN SDCONN_CLK R4102 1 2 0 93 SDCONN_CLK_R 5 CLK
MF-LF 1/16W 5% 402 6 VSS
93 37 BI SDCONN_DATA<0> R4104 1 2 0 93 SDCONN_DATA_R_<0> 7 DAT0
93 37 SDCONN_DATA<1> MF-LF 1/16W 5% 402 R4105 1 2 0 93 SDCONN_DATA_R_<1> 8 DAT1
BI
93 37 BI SDCONN_DATA<2> R4106 1 2 0 MF-LF 1/16W 5% 402 93 SDCONN_DATA_R_<2> 9 DAT2
93 37 BI SDCONN DATA<4> MF-LF 1/16W 5% 402 R4108 1 2 0 93 SDCONN DATA R <4> 10 DAT4
93 37 SDCONN_DATA<5> R4109 1 2 0 MF-LF 1/16W 5% 402 93 SDCONN_DATA_R_<5> 11 DAT5
BI
93 37 BI SDCONN_DATA<6> MF-LF 1/16W 5% 402 R4116 1 2 0 93 SDCONN_DATA_R_<6> 12 DAT6
93 37 BI SDCONN_DATA<7> R4117 1 2 0 MF-LF 1/16W 5% 402 93 SDCONN_DATA_R_<7> 13 DAT7
MF-LF 1/16W 5% 402 14
39 SDCONN_DETECT_L CRD_DETECT_SWITCH
93 37 OUT SDCONN_WP 15 WRITE_PROTECT_SWITC
SD switch is normally connected (i.e. gnd)
16 SHLD_PIN
17 SHLD_PIN
18 SHLD_PIN
NOSTUFF NOSTUFF 19 SHLD_PIN
1 C4171 1 C4170 20 SHLD_PIN
22PF 15PF 21
5% 5% SHLD_PIN
SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION. 2 50V
CERM
50V
2 CERM 22 SHLD_PIN
402 402
15 6 =PP3V3_S4_SDCARD 23 SHLD_PIN
24 SHLD_PIN
25 SHLD_PIN
B C4110
1UF
1
26
27
SHLD_PIN
SHLD_PIN
B
10%
10V
X5R 2
402 1
10
CRITICAL
VDD
U4111
SLG4AP026V
TDFN
2
R4114
R4111 37 26 IN ENET LOW PWR LOW_PWR
RST RST_OUT* 4 0
SLG_ENET_RESET_R_L 1 2 ENET_RESET_L OUT 37
0 3 RST_IN* LOGIC
26 IN ENET_SD_RESET_L 1 2 SLG_ENET_RESET_L 5%
1/16W
5% MF-LF
1/16W DET_CH_EN* 6 402
MF-LF NOSTUFF
402 39 SDCONN_DETECT_L 7 DET_IN
DLY (OD) 9
XOR
(IPU) SDCONN STATE CHANGE OUT -> TO PCH GPIO

R4110 1
FROM SD CONN -> 15 20
10K DET_CHNGD*
5% (OD) 8
XOR
ENET_SD_DETECT_L OUT 37 93 -> TO ENET CHIP

1/16W SD_DETECT_LVL 1
MF-LF DET_OUT
402 2
DET_LVL
THRM
R41151 GND PAD
10K
5
11
5%
1/16W
MF-LF
402 2
When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms
regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#
DLY block is 20ms nominal
NOSTUFF
R4112
A 1
0 2 SYNC MASTER=D7 NICK SYNC DATE=01/12/2012 A
5% PAGE TITLE
1/16W
MF-LF
402
SD READER CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
4.2.0
41 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB CAMERA CONTROLLER Camera/ALS/DMIC connector J4200
20455-020E-32
F-RT-SM
21
=PP3V3_S0_CAMERA =PP1V8_S0_CAMERA L4212 22
40 6 6 40 120-OHM-90MA
DLP0NS
1 C4222 1 C4224
93 40 SMIA DATA N 1 2 93 SMIA DATA F N 1
1 C4213 1.0UF 0.1UF
20% 10% 93 40 SMIA_DATA_P 93 SMIA_DATA_F_P 2
0.1UF 6.3V
2 X5R
6.3V
2 X5R
10% 3
2 6.3V
X5R
0201-MUR 201 4 3
4
201 SYM_VER 1
93 SMIA_CLK_F_N
SMIA_CLK_N 1 2
D
93 40
93 40 SMIA_CLK_P
93 SMIA_CLK_F_P 5
6
D
4 3 I2C_CAMSENSOR_SDA 7
L4220 PP1V2_S0_CAMERA 40
93 40
FERR-600-OHM-300MA-0.85OHM MIN_NECK_WIDTH=0.15 MM SYM_VER 1 93 40 I2C CAMSENSOR SCL 8

MIN_LINE_WIDTH=0.6 MM 9
1 2 PP3V3_S0_CAMFILT VOLTAGE=3.3V 1 C4228 L4214
120-OHM-90MA 10
0402 0.1UF DLP0NS 40 PP5V S0 CAMERA F
1 C4216 1 C4218 1 C4220 10% 11
6.3V 40 SMB_ALS_F_SDA
1.0UF 0.1UF 0.1UF 2 X5R
20% 10% 10% 201 40 SMB_ALS_F_SCL 12
6.3V
2 X5R 6.3V
2 X5R 2 6.3V 13
X5R
0201-MUR 201 201
PP1V8_S0_CAMERA_F 14
40 CAM AGND 40
40 PP3V3_S4_ALS_F 15
MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM 52 GND AUDIO DMIC
16
VOLTAGE=1.2V R4220 VOLTAGE=1.2V L4210 52 AUD DMIC SDA1 1 2 AUD DMIC SDA1 CONN 17
40 PP1V2_S0_CAMERA
PP1V2_S0_CAMFILT 1
10 2 PP1V2_S0_F_R 1 2 L4200 R4260 0 18
FERR-1000-OHM AUD_DMIC_CLK 1 2 AUD_DMIC_CLK_CONN 19
5% MF 0402 52
1 1 1
1/20W 201 FERR-1000-OHM 1
R4218 R4219 1
58 55 54 52 6 =PP3V3_S0_AUDIO 1 2 PP3V3_DMIC_CONN R4264 0 20
C4214 C4215 C4217
0.1UF 0.1UF 0.1UF 1K 1K 0402 MIN_NECK_WIDTH=0.15MM
10% 10% 10% 1 1 1% 1% MIN_LINE_WIDTH=0.4MM
6.3V 6.3V 6.3V C4221 C4223 1/20W 1/20W VOLTAGE=3.3V 1 23
2 X5R 2 X5R 2 X5R 1.0UF 0.1UF MF MF C4265
201 201 201 20% 10% 2 201 2 201 1UF 24
2 6.3V
X5R
6.3V
2 X5R 10%
16V
0201-MUR 201 2 X5R
DVDD3 16
DVDD4 34
DVDD6 43
MAVDD33 32
USB_VDDA0 23
OVDD2 40
USB_VDDL0 19
VDDA_PLL 26
402
OVDD1 7
CAM_PLLGND 40
L4202
FERR-1000-OHM
1 2
U4200 6 =PP5V_S0_CAMERA PP5V_S0_CAMERA_F 40
R4267
C VC0359
FQFN
0402
MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.6 MM
1 C4262
1UF 47 =SMB_ALS_SDA 1
0 2 SMB_ALS_F_SDA 40
C
48 37 VOLTAGE=5V 10% 5%
NC GPIO0 CS_PWDB TP_CS_PWD_L 16V
2 X5R 1/20W 1 C4267
47 38 MF
TP CAM GPIO1 GPIO1 CS_CLK TP ISM CLK 402 201 150PF
46 36 L4204 5%
21 PCH CAM EXT BOOT R GPIO3 CS_RSTB TP ISM RST L 50V
2 CERM
12 41 FERR-1000-OHM
GPIO3, EXT/IN FIRMWARE BOOT SEL NC GPIO9 CS_SCK I2C CAMSENSOR_SCL 40 93 402
42 =PP1V8 S0 CAMERA 1 2 PP1V8 S0 CAMERA_F 40 NOSTUFF
’1’= EXT FW 28 MRXDATAINP CS_SDA I2C_CAMSENSOR_SDA 40 93
40 6
93 40 SMIA_DATA_P 0402 1
’0’= INT FW 27 MRXDATAINN C4264
93 40 SMIA DATA N 337S4151 CLKIN 9 CAM XTAL IN 40 MIN_NECK_WIDTH=0.15 MM 1UF
MIN LINE_WIDTH=0.6 MM R4268
GPIO3 CAN BE CONFIGED AS GENERAL 30 MRXCLKINP CLKOUT 10 CAM_XTAL_OUT 40 VOLTAGE=1.8V 10%
0
93 40 SMIA_CLK_P 2 16V
X5R 47 =SMB ALS SCL 1 2 SMB ALS F SCL 40
GPIO AFTER POWER ON 29 MRXCLKINN
93 40 SMIA_CLK_N TEST 11 CAM_TEST 402
5%
L4206 1/20W 1 C4268
20 USB_PCH_8_P 93 USB_CAMERA P 20 USB_PADP USB_VRES 24 CAM_USB_VRES FERR-1000-OHM MF
150PF
201
MAKE_BASE=TRUE 21 1 2 5%
20 USB_PCH_8_N 93 USB_CAMERA_N USB_PADM PLACE_NEAR=U4200.24:5mm 6 =PP3V3_S4_ALS PP3V3_S4_ALS_F 40 50V
MAKE_BASE=TRUE AUD_CLK0 45 NC 1 1 0402
2 CERM
MIPI_RESISTOR 33 MIPI_RESISTOR R4213 1 C4226 R4216 1 C4266 402
NOSTUFF
LED_FIXED 17 TP_LED_PWM 8.2K 0.1UF 47 MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.6 MM 1UF
1 6 SF_CLK 1% 10% 1% VOLTAGE=3.3V 10%
R4204 93 40 CAM_SF_CLK
3 SF_CS* RST* 1 CAM_PROC_RESET_L 40
1/20W
MF
6.3V
2 X5R
1/20W
MF 2 16V
X5R Use 100 ohms and 150pF for 10MHz filter
24K 93 40 CAM_SF_CS_L
2 201 201 2 201
402
1% 5 SF_DIN
1/20W 93 40 CAM_SF_DIN UART1_RX 14 CAM_RX
USB_VSSA0
USB_VSDL0
MF 4 SF_DOUT UART1_TX 13 PLACE_NEAR=U4200.24:5mm

VSSA_PLL
CAM_SF_DOUT CAM_TX
2 201 93 40
1
PLACE_NEAR=U4200.33:5mm 93 40 CAM_SF_WP_L 2 SF_WP* R4210
DVSS4
DVSS6
MAVSS
OVSS1
OVSS2
DVSS3
10K
THRM
1%
PAD
CAM AGND 40 1/20W

=PP3V3 S0 CAMERA 6 40
MF
2 201
CRYSTAL
35
44
31
22
8
39
18
25
15
49
40 6 =PP3V3_S0_CAMERA
2 1 C4256
R4211 0.1UF R4215
C4227
10K 10% 18PF
B MF
201
1 1/20W
6.3V
2 X5R
201
40 CAM_XTAL_OUT 1
47
2 CAM_XTAL_OUT_R 1 2 B
XW4202
SHORT-0201
1% 1%
1/20W 5%
MF 25V
1 2 40 CAM_AGND CAM_PLLGND 40
5 74AHC1G08GV 2 201 NP0-C0G
=CAM_RESET_L 1 SOT753 201
61
B R4214
3
4 CAM_PROC_RESET_L
4
2
UART1_TX is strap for selection PCH_CAM_RESET_R 2
U4210 Y 40 1M
1%
2
1/20W
XW4203 of pos/neg edge sampling of
21 A MF
Y4200
1
SHORT-0201 3 201 1
SM-3.2X2.5MM
SPI clock during power-on. 12.000MHZ-30PPM-10PF
STITCH THERMAL PAD TO INNER GROUND 1 C4225
’1’ = POSITIVE EDGE 18PF
’0’ = NEGATIVE EDGE 40 CAM XTAL IN 1 2
5%
25V
NP0-C0G
201
PP1V2_S0_CAMERA Vreg 40 6 =PP3V3_S0_CAMERA
40 6 =PP1V8_S0_CAMERA 1 C4219
1 0.1UF
1 R4207 2 2 R4206 R4208 10%
8
C4255 6.3V
1UF 10K 10K 4.7K VCC 2 X5R
10% 1% 1% 5% 201
16V 1/20W 1/20W 1/20W
2 X5R MF
201
MF
201 MF U4202
402 2 201
PLACE_NEAR=U4200.6:5mm 1 1 1MBIT-104MHZ PLACE_NEAR=U4200.5:5mm
R4203 33 USON 33 R4205
93 40 CAM_SF_CLK 1 2 93 CAM_SF_CLK_R 6 SCLK SI/SIO0 5 93 CAM_SF_DOUT_R 2 1 CAM_SF_DOUT 40 93
1
1% MF MF 1%
1/20W 201 MX25L1006EZUI-10G 201 1/20W
VIN CRITICAL
93 40 CAM_SF_CS_L 1 CS* R4209
A 60 IN =PM EN REG P1V2 S0 3 EN U4250 VO 6 PP1V2 S0 CAMERA 40 93 40 CAM_SF_WP_L 3 WP*
7 HOLD*
OMIT_TABLE
SO/SIO1 2 93 CAM_SF_DIN_R 1
33
2 CAM_SF_DIN 40 93 A
ISL9021AIRUWZ-T MIN_NECK_WIDTH=0.15 MM CAM_SF_HOLD_L 1% PAGE TITLE
NC 2 MIN_LINE_WIDTH=0.6 MM 1/20W
DFN
NC 5
NC
NC
VOLTAGE=1.2V GND
THRM
PAD
MF
201
PLACE_NEAR=U4202.2:5mm
Camera Controller
4
1 335S0852 DRAWING NUMBER SIZE

C4258
GND 4.7UF Apple Inc. 051-9509 D
20% REVISION
6.3V
4
2 X5R-CERM1 R
402 4.2.0
SERIAL FLASH PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
42 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HDD Out-of-Band Temperature Sensing

Temperature read from SATA power connecter pin 11
HDD CONNECTORS 50 49 48 41 6 =PP3V3_S0_SENSE
6 =PP1V5_S0_SENSE
D 518S0251
SILK_PART=HDD
50 49 48 41 6 =PP3V3_S0_SENSE 1 1 C4507
D
R4500
CRITICAL 49.9K 0.1UF
10%
GND VOID TRUE
1% 16V
518S0812 1/16W 2
J4520 C4521 1 2 0.01UF
1
R4514 MF-LF
X5R
402
EP00-081-91 SATA_HDD_R2D_C_P IN 18 91 CRITICAL 10K 2 402
M-ST-SM
1
10% 25V X7R 402 J4530 5%
1/16W 1
Trip is 1.0V HDD_OOB_1V00_REF
50293-00471-H01 =PP5V_S0_SATA 6 MF LF R4502 =PP3V3_S0_SENSE 6 41 48 49 50
2 SATA_HDD_R2D_P
C4522 1 2 0.01UF SATA_HDD_R2D_C_N IN 18 91 M-ST-SM 2 402 100K 1 1 C4506
GND VOID TRUE 91
R4501 1
GND VOID TRUE
3 91 SATA_HDD_R2D_N
10% 25V X7R 402
1 R4508 5%
1/16W 100K 0.1UF R4505
4
GND VOID TRUE
2
523 MF LF 1%
10%
16V
1K
SMC OOB1 TX R L 1 2 SMC OOB1 TX L IN 44
2 402 1/16W 2 X5R 5%
5 GND VOID TRUE MF LF 402 1/16W
3
GND VOID TRUE 91 SATA HDD D2R C N
C4523 1 0.01UF
HDD OOB1 RX L 1%
1/16W 2 402 5 U4500 MF LF
2 402
GND VOID TRUE
6 91 SATA HDD D2R C P 2 SATA HDD D2R N OUT 18 91 4 MF-LF FERR-220-OHM 3
LMV331
402
7 10% 25V X7R 402 L4530 VCC+ SC70-5
4 SMC_OOB1_RX_L OUT
R4503 44
C4524 1 2 0.01UF SATA HDD D2R P Node is at 1.5V 1 3.3K 2 GND
10% 25V X7R 402
OUT 18 91
1 C4530 1 2 HDD_OOB1_RX_F_L HDD_OOB1_RX_R_L 1
GND VOID TRUE

10UF 0402 5% 2
20% From drive: 1/16W
6.3V
2 X5R Low: 0.0V to 0.3V MF LF
402
603 High: 1.2V to 2.0V
Notes:
Drive active: Valid signal protocol
Drive asleep: HDD drives HDD_OOB_TEMP low
Drive disconnected: Pulled high
GUMSTICK2 CONNECTOR
C SSD
PLACE_NEAR=J4500.1:3mm C
CRITICAL
L4500
PP3V3_S0_SSD_FLT
FERR-70-OHM-4A
1 2
=PP3V3_S0_SSD 6 SATA Activity LED
MIN_LINE_WIDTH=0.6mm 0603
MIN NECK_WIDTH=0.4mm SSD SSD 15 6 =PP3V3 S0 LED SATA
VOLTAGE=3.3V 1 C4500 1 C4501 DEVELOPMENT
0.1UF 0.1UF
20% 20% R45991
SSD 2 10V
CERM
10V
2 CERM 330
SILK_PART=SSD 402 402 5%
1/10W
CRITICAL MF-LF
603 2
SATALED_R_L
J4500 A DEVELOPMENT
SSD-K70
F-RT-SM1 GND VOID TRUE
DS4599
GND VOID TRUE GREEN-3.6MCD
1 GND VOID TRUE 2.0X1.25MM-SM
GND VOID TRUE
K
2 SSD 6 =PP3V3_S0_SATAMUX PCH SATALED L SATALED L SILK_PART=SATA ACTIVE
18 15
3 R4506 SSD SSD SSD MAKE_BASE=TRUE
4
90 PCIE_SSD_D2R_C_P<1> 2 1 PCIE_SSD_D2R_P<1> OUT 18 90 1 C4510 1 C4511 1 C4512
GND VOID TRUE 201 1/20W
0
5% MF R4507 SSD 0.1UF 0.1UF 0.1UF
5 90 PCIE_SSD_D2R_C_N<1> 2 1 PCIE_SSD_D2R_N<1> OUT 18 90 20% 20% 20%
GND VOID TRUE 10V 10V 10V
6 201 1/20W 5% MF SSD 2 CERM 2 CERM 2 CERM
0
7 PCIE SATA SSD D2R P 41 91 R45101 402 402 402
GND VOID TRUE
8 470K
GND VOID TRUE PCIE_SATA_SSD_D2R_N 41 91 5% GND VOID TRUE
9 SSD 1/16W GND VOID TRUE
90 PCIE_SSD_R2D_P<1> C45041 2 0.1UF PCIE_SSD_R2D_C_P<1> 18 90
MF-LF
402 2 GND VOID TRUE
10 IN GND VOID TRUE
10% 16V X5R-CERM 0201 SSD
10
GND VOID TRUE
C45051
6
GND VOID TRUE
11 90 PCIE_SSD_R2D_N<1> 2 PCIE_SSD_R2D_C_N<1> IN 18 90 SSD
0.1UF 10% 16V X5R-CERM 0201
12 C4513 1 0.1UF
VDD
VDD
VDD
PCIE SSD R2D N<0> 2 PCIE SSD R2D C N<0>
B 13
14
PCIE_SATA_SSD_R2D_P 41 91
90
10% 16V
SSD
X5R-CERM 0201
OUT 18 90
B
15
PCIE SATA SSD R2D N 41 91 U4510 90 PCIE_SSD_R2D_P<0> C4514 1 2 0.1UF PCIE_SSD_R2D_C_P<0> 18 90
CBTL02043ABQ 10% 16V X5R-CERM 0201
OUT
16 PCIE_CLK100M_SSD_P 3 VQFN
IN 18 90
91 41 PCIE_SATA_SSD_R2D_N A0_P B0_P 19 SSD
17 PCIE_CLK100M_SSD_N IN 18 90
91 41 PCIE_SATA_SSD_R2D_P 4 A0_N 353S3361 B0_N 18 90 PCIE_SSD_D2R_C_N<0> C4515 1 2 0.1UF PCIE_SSD_D2R_N<0> IN 18 90
18 10% 16V X5R-CERM 0201
91 41 PCIE_SATA_SSD_D2R_N 7 A1_P CRITICAL B1_P 17 SSD
91 41 PCIE_SATA_SSD_D2R_P
8 A1_N SSD B1_N 16 90 PCIE_SSD_D2R_C_P<0> C4516 1 2 0.1UF PCIE_SSD_D2R_P<0> IN 18 90
19 SSD_CLKREQ_L IN 15 18 10% 16V X5R-CERM 0201
20 SSD_RESET_L IN 26 C0_P 15 SSD
21 SATA_PCIE_SEL 9 SEL C0_N 14 C4517 1 0.1UF
SATA_PCIE_SEL 41 41 91 SATA_SSD_R2D_N 2 SATA_SSD_R2D_C_N OUT 18 91
22 SMC_OOB2_RX_L OUT 41 45 2 10% 16V X5R-CERM 0201
SSD SATAMUX EN L XSD C1_P 13 SSD
23 SMC_OOB2_TX_L IN 41 45 R4504
24
C1_N 12 91 SATA_SSD_R2D_P C4518 1 2 0.1UF SATA_SSD_R2D_C_P OUT 18 91
SSD P3V3S0 EN 2 1 PM EN FET P3V3 S0
THRM
IN 60 70
PAD
10% 16V X5R-CERM 0201
VSS
VSS
VSS
25 5% SSD
26
1/20W
MF
1
SSD 91 SATA SSD D2R C N C4519 1 2 0.1UF SATA SSD D2R N IN 18 91
201
R4511
5
11
20
21
10% 16V X5R-CERM 0201
0 10K SSD
27 5%
1/16W
GND
GND
VOID
VOID
TRUE
TRUE 91 SATA SSD D2R C P C4520 1 2 0.1UF SATA SSD D2R P IN 18 91
28 50 49 48 41 6 =PP3V3_S0_SENSE MF-LF GND VOID TRUE
10% 16V X5R-CERM 0201
2 402 GND VOID TRUE
29 GND VOID TRUE
GND VOID TRUE
GND VOID TRUE
GND VOID TRUE
30 GND VOID TRUE
GND VOID TRUE
GND VOID TRUE
31 1 1 GND VOID TRUE
R4512 R4513 GND VOID TRUE
10K 10K GND VOID TRUE
32 GND VOID TRUE
5% 5%
GND VOID TRUE
33 1/16W 1/16W
MF LF MF LF
34 2 402 2 402
35
A 36 45 41 SMC OOB2 RX L SYNC MASTER=D7 NICK SYNC DATE=12/16/2011 A
37 PAGE TITLE
SMC_OOB2_TX_L
38
39
45 41
SATA Connectors
DRAWING NUMBER SIZE
40
REVISION
R
4.2.0
45 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L4601
FERR-120-OHM-3A
PP5V S4 EXTA ILIM 1 2 PP5V S4 EXTA F
VOLTAGE=5V 0603 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
L4602
120-OHM-90MA 1 1
C4605 1 1 C4607
DLP0NS
SYM_VER 1 2 5 3 4 EXT PORT A
0.01UF
NC
IO
NC
IO
20% 0.1UF 4 3 TSSLP-2-1 TSSLP-2-1
16V 20% 6 VBUS ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
CERM 2 10V D4602 D4603
2 CERM
402
J4600
D
402
1 2
1 GND 2 2
USB-NO1-K70
F-ANG-TH
D
CRITICAL
D4601 1
VBUS
RCLAMP0582N 93 USB2 EXTA N 2
SLP1210N6 D-
93 USB2 EXTA P 3
CRITICAL D+
NOSTUFF 4
GND
93 USB3_EXTA_RX_N 5
STDA_SSRX-
6
6 =PP3V3 G3H SMC USBMUX L4603 93 USB3_EXTA_RX_P STDA_SSRX+
80OHM-25%-100MA 7
0504 GND_DRAIN
93 USB3_EXTA_TX_F_N 8
STDA_SSTX-
L2 93 USB3 EXTA TX F P 9
STDA_SSTX+
R46051 C4606
0.1UF
1
10K 20% 93 20 OUT USB3_EXTA_RX_F_N 4 3
5% 10V 10
2
5
1/16W CERM 2 2
MF-LF
402 2 VDD
402
1 D4604 D4605 11
93 20 OUT USB3_EXTA_RX_F_P 2 ESD0P2RF-02LS ESD0P2RF-02LS
12
U4610 L1 TSSLP-2-1 TSSLP-2-1
USB3740 GND_VOID=TRUE 1
13
93 20 BI USB_PCH_0_P 6 DP_2 DFN 1 14
15
93 20 BI USB_PCH_0_N 7 DM_2 CRITICAL
DP 10 93 USB2_EXTA_MUXED_P 16 SHIELD
45 44 OUT MOJO_RX_L 2 DP_1 17
DM 9 93 USB2 EXTA MUXED N
18
MOJO_TX_L 1 DM_1
43 6 =PP5V_S4_USB
45 44 IN L4604 19
3 OE* 80OHM-25%-100MA 20
0504
21
C4601 1 1
C4602 44 IN USB_DEBUGPRT_EN_L 4 S
L2 22
0.1UF 330UF-25MOHM
20% 20% GND C4608 0.1UF
C 10V 2 6.3V USB3_EXTA_TX_N 1 2 93 USB3_EXTA_TX_C_N 4 3
C
8
CERM 2 TANT
93 20 IN
402 10% X5R 6.3V 201
CASE-D2E
C4609 0.1UF
1
514-0817
93 20 USB3_EXTA_TX_P 1 2 93 USB3_EXTA_TX_C_P 2
IN
10% X5R 6.3V 201 L1
U4600 SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO
TPS2561DR GND_VOID=TRUE
SON
2 IN_0 OUT1 9
3 IN_1 OUT2 8
10 FAULT1* ILIM 7
20 15 OUT USB_EXTB_OC_L USB_ILIM1
6 FAULT2*
20 15 OUT USB_EXTA_OC_L
60 43 PM_EN_USB_PWR 4 EN1 R46021

5 EN2 23.2K
THRM 1%
1/16W
GND PAD MF-LF L4611
402 2 FERR-120-OHM-3A
1
11
PP5V_S4_EXTB_ILIM 1 2 PP5V_S4_EXTB_F
VOLTAGE=5V VOLTAGE=5V 1 1 EXT PORT B
MIN_LINE_WIDTH=0.6MM 0603 MIN_LINE_WIDTH=0.6MM
TSSLP-2-1 TSSLP-2-1
ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
L4612 D4612 D4613
C4615 1 1 C4617 120-OHM-90MA
DLP0NS 2 5 3 4 2 2 J4610
0.01UF 0.1UF SYM_VER 1
USB-NO2-K70
NC
IO
NC
IO
20% 20%
16V 10V 4 3 6 VBUS
CERM 2 2 CERM F-ANG-TH
402 402
1 GND 1
1 2 VBUS
93 USB2_EXTB_N 2
D-
CRITICAL 93 USB2_EXTB_P 3
D4611 4
D+
RCLAMP0582N GND
B SLP1210N6
CRITICAL
93
93
USB3_EXTB_RX_N
USB3_EXTB_RX_P
5
6
STDA_SSRX- B
STDA_SSRX+
NOSTUFF 7
GND_DRAIN
93 USB3 EXTB TX F N 8
STDA_SSTX-
93 USB3 EXTB TX F P 9
STDA_SSTX+
43 6 =PP3V3_S5_USBMUX
2 2 10
L4613 D4614 D4615 11
80OHM-25%-100MA ESD0P2RF-02LS ESD0P2RF-02LS
TSSLP-2-1 12
0504 TSSLP-2-1
13
L2 1 1 14
C4616 1
USB3_EXTB_RX_F_N 4 3 15
0.1UF 93 20 OUT
R46151 20%
10V
16 SHIELD
10K
5
CERM 2 17
5% 402 1
1/16W VDD 93 20 USB3_EXTB_RX_F_P 2 18
OUT
MF-LF L1
402 2 U4630 GND_VOID=TRUE
19
USB3740 20
93 20 BI USB PCH 1 P 6 DP_2 DFN 21
XHCI
93 20 BI USB_PCH_1_N 7 DM_2 CRITICAL 22
DP 10 93 USB2_EXTB_MUXED_P
93 20 BI USB_PCH_9_P 2 DP_1
DM 9 USB2_EXTB_MUXED_N
L4614
EHCI 93
80OHM-25%-100MA 514-0825
93 20 BI USB PCH 9 N 1 DM_1 0504
3 OE* L2
C4618 0.1UF
4 S USB3 EXTB TX N 1 2 93 USB3 EXTB TX C N 4 3
18 IN USB_EXTB_SEL_XHCI 93 20 IN
10% X5R 6.3V 201
A PCH GPIO60 GND
C46191 0.1UF SYNC MASTER=D7 NICK SYNC DATE=01/04/2012 A
8
2 1 2
93 20 IN USB3_EXTB_TX_P 93 USB3_EXTB_TX_C_P PAGE TITLE
10% X5R 6.3V 201 L1
GND_VOID=TRUE
EXTERNAL USB PORTS A & B
DRAWING NUMBER SIZE

REVISION
R
4.2.0
46 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L4701
FERR-120-OHM-3A
PP5V_S4_EXTC_ILIM 1 2 PP5V_S4_EXTC_F
VOLTAGE=5V 0603 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
1 1 EXT PORT C
C4705 1 1 C4707 L4702 TSSLP-2-1 TSSLP-2-1
0.01UF 120-OHM-90MA 2 5 3 4
ESD0P2RF-02LS ESD0P2RF-02LS CRITICAL
20% 0.1UF DLP0NS
NC
IO
NC
IO
16V
CERM 2
20%
10V
2 CERM
SYM_VER 1
6 VBUS
D4702 D4703 J4700
402 USB PCH 2 P 4 3 2 2
93 20
D
402 BI
1 GND USB-NO3-K70
F-ANG-TH D
93 20 USB_PCH_2_N 1 2
BI 1
VBUS
CRITICAL D4701 93 USB2_EXTC_N 2
D-
RCLAMP0582N 93 USB2_EXTC_P 3
SLP1210N6 D+
CRITICAL 4
GND
93 USB3_EXTC_RX_N 5
STDA_SSRX-
6
L4703 93 USB3 EXTC RX P
STDA_SSRX+
80OHM-25%-100MA 7
0504 GND_DRAIN
93 USB3_EXTC_TX_F_N 8
STDA_SSTX-
L2 93 USB3_EXTC_TX_F_P 9
STDA_SSTX+
93 20 USB3 EXTC RX F N 4 3
OUT
2 2 10
42 6 =PP5V_S4_USB 1 D4704 D4705 11
93 20 OUT USB3_EXTC_RX_F_P 2 ESD0P2RF-02LS ESD0P2RF-02LS
TSSLP-2-1 12
L1 TSSLP-2-1
13
GND_VOID=TRUE 1
1 14
C4701 1 1
C4702 15
0.1UF 330UF-25MOHM
20% 20% 16 SHIELD
10V
CERM 2 2 6.3V
TANT
L4704 17
402 CASE-D2E 80OHM-25%-100MA
0504 18
U4700 L2
19
TPS2561DR C47081 0.1UF 20
SON USB3_EXTC_TX_N 2 USB3_EXTC_TX_C_N 4 3
93 20 IN 93 21
2 IN_0 OUT1 9 10% X5R 6.3V 201
22
3 IN_1 OUT2 8 C47091 0.1UF
USB3 EXTC TX P 2 93 USB3 EXTC TX C P 1 2
C 20 15 OUT USB_EXTD_OC_L
10 FAULT1* ILIM 7
6 FAULT2*
USB_ILIM2
93 20 IN
10% X5R 6.3V 201 L1
514-0826
C
20 15 OUT USB EXTC OC L GND_VOID=TRUE
60 42 PM_EN_USB_PWR 4 EN1 R47021

5 EN2 23.2K
THRM 1%
PAD 1/16W
GND MF-LF
402 2
1
11
L4711
FERR-120-OHM-3A 1 1
PP5V_S4_EXTD_ILIM
1 2 PP5V_S4_EXTD_F
EXT PORT D
VOLTAGE=5V VOLTAGE=5V TSSLP-2-1 TSSLP-2-1
MIN_LINE_WIDTH=0.6MM 0603 MIN_LINE_WIDTH=0.6MM CRITICAL
ESD0P2RF-02LS ESD0P2RF-02LS
D4712 D4713 J4710
L4712 2 2
C4715 1 120-OHM-90MA
DLP0NS 2 5 3 4 USB-NO4-K70
1 C4717 SYM_VER 1 F-ANG-TH
NC
IO
NC
IO
0.01UF
20% 0.1UF 4 3 6 VBUS
16V 20% 1
CERM 2 10V VBUS
402 2 CERM 2
1 GND 93 USB2_EXTD_N
402 D-
1 2 93 USB2_EXTD_P 3
D+
4
CRITICAL GND
D4711 93 USB3_EXTD_RX_N 5
STDA_SSRX-
RCLAMP0582N 93 USB3_EXTD_RX_P 6
B SLP1210N6
CRITICAL
NOSTUFF
7
8
STDA_SSRX+
GND_DRAIN
B
93 USB3 EXTD TX F N
STDA_SSTX-
93 USB3 EXTD TX F P 9
STDA_SSTX+
2 2 10
L4713 D4714 D4715 11
80OHM-25%-100MA ESD0P2RF-02LS ESD0P2RF-02LS
42 6 =PP3V3 S5 USBMUX 0504 TSSLP-2-1 12
TSSLP-2-1
13
L2 1 1
14
93 20 OUT USB3_EXTD_RX_F_N 4 3 15
16 SHIELD
1 17
C4716 93 20 OUT USB3_EXTD_RX_F_P 1 2
0.1UF 18
R47151 20%
10V
L1
19
10K GND_VOID=TRUE
5
5% CERM 2
402 20
1/16W VDD
MF-LF 21
402 2 U4730 22
USB3740 L4714
93 20 BI USB_PCH_3_P 6 DP_2 DFN 80OHM-25%-100MA
XHCI 0504 514-0827
93 20 BI USB_PCH_3_N 7 DM_2 CRITICAL
DP 10 93 USB2 EXTD MUXED P L2
93 20 BI USB PCH 10 P 2 DP_1 C47181 0.1UF
EHCI DM 9 93 USB2_EXTD_MUXED_N USB3 EXTD TX N 2 93 USB3 EXTD TX C N 4 3
93 20 IN
93 20 USB_PCH_10_N 1 DM_1 10% X5R 6.3V 201
BI
3 C4719 0.1UF
OE* 93 20 USB3_EXTD_TX_P 1 2 93 USB3_EXTD_TX_C_P 1 2
IN
10% X5R 6.3V 201 L1
A 18 IN USB_EXTD_SEL_XHCI
PCH GPIO74
4 S
GND
GND_VOID=TRUE
PAGE TITLE
8
EXTERNAL USB PORTS C & D

DRAWING NUMBER SIZE

REVISION
R
4.2.0
47 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
L4901
45 6 =PP3V3_G3H_SMC 30-OHM-1.7A
those designated as inputs require pull-ups. 1 2 PP3V3_G3H_SMC_VDDA
MIN LINE WIDTH=0 25 MM
0402 MIN NECK WIDTH=0 1 MM
VOLTAGE=3 3V
1 C4901
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906 0.1UF
1UF 0.1UF 0.1UF 0.1UF 0.1UF 1 10%
10% 10% 10% 10% R4902 6.3V
20%
10V
CERM 2
6.3V
2 X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 1M U4900 2 X5R
201
603 201 201 201 201 5%
1/20W
LM4FSXAH5BB
MF BGA
201
2 (2 OF 2)
46 45 SMC_RESET_L G10 RST* SWCLK/TCK C10 SMC_TCK 45 46
IN
SWDIO/TMS A10 SMC TMS 45 46
D
1 C4907
0.1UF
10%
1 C4908
0.1UF
10%
1 C4909
0.1UF
10%
45 33 BI AP EVENT L (OD) B11
N13
PK4/RTCCLK SWO/TDO A11
B10
SMC TDO 45 46 D
6.3V 6.3V 6.3V
SMC_WAKE_L WAKE* OMIT_TABLE TDI SMC_TDI 45 46
2 X5R 2 X5R 2 X5R M12
201 201 201
NC_SMC HIB_L HIB*
NO_TEST=TRUE A2
NC NC
92 45 SMC_CLK32K M10 XOSC0
IN
NC_SMC XOSC1 N10 XOSC1
NO_TEST=TRUE
U4900 VDDA D3
PP3V3_G3H_AVREF_SMC 45
LM4FSXAH5BB 94 45 SMC EXTAL G12 OSC0
BGA 94 45 SMC XTAL G13 OSC1 VREFA+ D2
92 46 18 BI LPC_AD<0> arch B13 LPC0AD0 (1 OF 2) AIN00 E2 proj analog SMC_ADC0 IN 45
VREFA- D1 PLACE NEAR=U4900.D1:4mm PLACE_NEAR=U4900.D2:4mm
92 46 18 BI LPC_AD<1> arch A13 LPC0AD1 AIN01 E1 proj analog SMC_ADC1 IN 45 XW4900
K12 VBAT SM C4920 1 1 C4921
92 46 18 BI LPC AD<2> arch C12 LPC0AD2 OMIT_TABLE AIN02 F2 proj analog SMC ADC2 IN 45
94 49 48 45 C3 GND_SMC_AVSS 2 1 1UF 0.01UF
92 46 18 BI LPC AD<3> arch D11 LPC0AD3 AIN03 F1 proj analog SMC ADC3 IN 45
20% 10%
D7 GNDA E3 PLACE_NEAR=U4900.A1:4MM 6.3V 2 2 10V
LPC CLK33M SMC H12 B3 SMC ADC4 X5R X5R
92 26 IN arch LPC0CLK AIN04 proj analog IN 45 E6 0201 201
92 46 18 LPC_FRAME_L arch D12 LPC0FRAME* AIN05 A3 proj analog SMC_ADC5 45
IN IN 1 C4910 1 C4911 1 C4912 E8 A1
26 IN SMC_LRESET_L arch C13 LPC0RESET* AIN06 B4 proj analog SMC_ADC6 IN 45
1.0UF 1.0UF 1.0UF E9 C7
46 18 LPC_SERIRQ arch od H13 LPC0SERIRQ AIN07 A4 proj analog SMC_ADC7 45
20% 20% 20%
BI IN
2
25V
2
25V
2
25V F10 VDD D9
46 45 OUT PM_CLKRUN_L arch od G11 LPC0CLKRUN* AIN08 B5 proj analog SMC_ADC8 IN 45
X5R X5R X5R
402 402 402 J7 E5
46 26 19 IN LPC_PWRDWN_L arch F13 LPC0PD* AIN09 A5 proj analog SMC_ADC9 IN 45
J9 F9
21 15 SMC_RUNTIME_SCI_L arch F12 LPC0SCI* AIN10 B6 proj analog SMC_ADC10 45
OUT IN J10 H5
21 15 OUT SMC WAKE SCI L arch B12 PK5 AIN11 A6 proj analog SMC ADC11 IN 45
H9
AIN12 C1 proj analog SMC ADC12 45
GND
IN PP1V2_G3H_SMC_VDDC J1 J5
94 47 SMBUS_SMC_0_S0_SCL arch od E10 I2C0SCL AIN13 C2 proj analog SMC_ADC13 45 MIN LINE WIDTH=0 25 MM
BI IN
MIN NECK WIDTH=0 1 MM
J6 J8
94 47 BI SMBUS_SMC_0_S0_SDA arch od D13 I2C0SDA AIN14 B1 proj analog SMC_ADC14 IN 45 VOLTAGE=1 2V
1 C4913 1 C4914 1 C4915 1 C4916 1 C4917 K13 VDDC J11
94 47 BI SMBUS_SMC_1_S0_SCL arch od M4 I2C1SCL AIN15 B2 proj analog SMC_ADC15 IN 45
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF D6 K11
94 47 SMBUS_SMC_1_S0_SDA arch od N2 I2C1SDA AIN16 G2 proj analog SMC_ADC16 45
10% 10% 10% 10% 10%
BI IN 6.3V 6.3V 6.3V 6.3V 6.3V
N8 G1 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
94 47 BI SMBUS_SMC_2_S4_SCL arch od I2C2SCL AIN17 proj analog SMC_ADC17 IN 45
201 201 201 201 201
C 94 47
94 47
BI SMBUS_SMC_2_S4_SDA
SMBUS SMC 3 SCL
arch
arch
od
od
M8
L8
I2C2SDA
I2C3SCL
AIN18
AIN19
H1
H2
proj
proj
analog
analog
SMC_ADC18
SMC ADC19
IN 45
45
C
BI IN
94 47 BI SMBUS SMC 3 SDA arch od K8 I2C3SDA AIN20 B7 proj analog SMC ADC20 IN 45
45 BI SMBUS_SMC_4_ASF_SCL arch od N7 I2C4SCL AIN21 A7 proj analog SMC_ADC21 IN 45
45 BI SMBUS_SMC_4_ASF_SDA arch od M7 I2C4SDA AIN22 B8 proj analog SMC_ADC22 IN 45
94 45 BI SMBUS_SMC_5_G3H_SCL arch od N4 I2C5SCL AIN23 A8 proj analog SMC_ADC23 IN 45
94 45 BI SMBUS_SMC_5_G3H_SDA arch od N3 I2C5SDA

C0- K2 arch analog CPU_PROCHOT_L 11 45 62
IN
51 OUT SMC_FAN_0_CTL arch H11 PM6/FAN0PWM0 C0+ K1 arch analog SMC_VCCIO_CPU_DIV2 IN 45
51 IN SMC FAN 0 TACH arch L13 PM7/FAN0TACH0 C1- L2 arch analog SMC S5 PWRGD VIN IN 61
51 OUT SMC_FAN_1_CTL arch C11 PK6/FAN0PWM1 PC5/C1+ L1 arch SPI_DESCRIPTOR_OVERRIDE_L OUT 15
51 SMC_FAN_1_TACH arch A12 PK7/FAN0TACH1 T3CCP1/PJ5/C2- C5 arch SMC_CPU_CATERR_L 45

IN IN
45 SMC_PN2 proj G3 PN2/FAN0PWM2 T3CCP0/PJ4/C2+ D5 arch analog CPU_THRMTRIP_3V3 45
OUT IN
45 IN SMC_PN3 proj D10 PN3/FAN0TACH2
SSI0CLK/PA2 M2 arch SMC_PM_G2_EN 45 69
OUT
45 OUT SMC_PN4 proj L11 PN4/FAN0PWM3 SSI0FSS/PA3 M3 arch PM_DSW_PWRGD OUT 45 61
45 SMC_PN5 proj N12 PN5/FAN0TACH3 SSI0RX/PA4 L4 arch SMC_DELAYED_PWRGD 36 45 61

OUT OUT
45 SMC_PN6 proj N11 PN6/FAN0PWM4 SSI0TX/PA5 N1 arch SMC_PROCHOT 45
OUT OUT
45 SMC_PN7 proj M11 PN7/FAN0TACH4
IN
45 IN SMC_PH2 proj J4 PH2/FAN0PWM5 U1RX/B0 F11 arch MOJO_RX_L IN 42 45
45 OUT SMC_PH3 proj od J2 PH3/FAN0TACH5 U1TX/PB1 E11 arch MOJO_TX_L OUT 42 45
T0CCP0/PB6 F4 arch pwm SMC_SYS_LED 45

OUT
45 21 11 IN CPU_PECI arch analog C4 PECI0RX T0CCP1/PB7 F3 arch SMC_GFX_THROTTLE_L OUT 78
45 OUT SMC_PECI_L arch C6 PECI0TX

SSI1RX/PF0 M9 arch SPI SMC MISO 45 92
IN
45 IN SMC_PP0 proj int M13 PP0/IRQ116 SSI1TX/PF1 N9 arch SPI_SMC_MOSI OUT 45 92
L12
B 45
45 33
IN
IN
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
proj
proj
int
int M5
PP1/IRQ117
PP2/IRQ118
SSI1CLK/PF2
SSI1FSS/PF3
L10
K10
arch
arch
SPI_SMC_CLK
SPI_SMC_CS_L
OUT
OUT
45 92
45 92
B
45 SMC_PME_S4_DARK_L proj int J12 PP3/IRQ119 PF4 L9 arch S5_PWRGD 61
IN IN
45 33 OUT SMC_S4_WAKESRC_EN proj int J13 PP4/IRQ120 PF5 K9 arch SMC_PM_PCH_SYS_PWROK IN 45
45 IN SMC_PP5 proj int L5 PP5/IRQ121

45 IN SMC PP6 proj int D8 PP6/IRQ122 WT0CCP0/PG4 K7 arch USB DEBUGPRT EN L OUT 42
45 IN SMC PP7 proj int K6 PP7/IRQ123 WT0CCP1/PG5 L7 arch SMC GFX OVERTEMP IN 45 78
45 OUT ENET_ASF_GPIO arch od D4 PQ0/IRQ124 WT2CCP0/PH0 K3 arch ALL_SYS_PWRGD IN 5 61
45 IN SMS_INT_L arch int E4 PQ1/IRQ125 WT2CCP1/PH1 K4 arch SMC_THRMTRIP OUT 45
45 IN SMC_BC_ACOK arch int F5 PQ2/IRQ126

45 IN G3_POWERON_L arch int N5 PQ3/IRQ127 WT3CCP0/PH4 J3 arch od PM_PWRBTN_L OUT 15 19 25
60 45 38 28 19 15 PM_SLP_S3_L arch int N6 PQ4/IRQ128 WT3CCP1/PH5 H4 arch PM_SYSRST_L 19 25 26

IN OUT
60 19 15 PM SLP S4 L arch int K5 PQ5/IRQ129 WT4CCP0/PH6 H3 arch od MEM EVENT L 29 30 45
IN OUT
60 33 19 15 PM SLP S5 L arch int M6 PQ6/IRQ130 WT4CCP1/PH7 G4 proj SMC PH7 45
IN OUT
45 SMC ONOFF L arch int L6 PQ7/IRQ131
IN
T1CCP0/PJ0 C9 arch SMC_OOB1_RX_L 41
IN
46 45 SMC_RX_L arch L3 U0RX T1CCP1/PJ1 B9 arch SMC_OOB1_TX_L 41
IN OUT
46 45 SMC_TX_L arch M1 U0TX T2CCP0/PJ2 A9 proj SMC_PJ2 45
OUT IN
T2CCP1/PJ3 C8 proj SMC_PJ3 45
OUT
93 27 USB_SMC_N arch E13 USB0DM
BI
93 27 USB_SMC_P arch E12 USB0DP WT5CCP1/PM3 H10 arch SMC_BATLOW_L 45
BI OUT
A SYNC MASTER=D7 DOUG SYNC DATE=01/11/2012 A

PAGE TITLE
SMC
DRAWING NUMBER SIZE

REVISION
R
4.2.0
49 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ADC Channel Aliases
SMC Supervisor and AVREF Supply 44 SMC_ADC0 VSNS_P12VG3H 48 94 44 SMC_ADC14 VSNS_HDDS0 48 94
SMC SPI Support
MAKE_BASE=TRUE MAKE_BASE=TRUE Series R are NOSTUFF until topology of 2 SPI masters is verified
45 44 6 =PP3V3_G3H_SMC 44 SMC_ADC1 ISNS_P12VG3H 48 94 44 SMC_ADC15 ISNS_HDDS0 48 94
MAKE_BASE=TRUE MAKE_BASE=TRUE NOSTUFF
6 =PPVIN_G3H_SMCVREF 44 SMC_ADC2 VSNS_P12VS0 GPUCORE 48 94 44 SMC_ADC16 VSNS_SSDS0 49 94
R5050
MAKE_BASE=TRUE MAKE_BASE=TRUE 0
92 44 SPI_SMC_MISO 2 1 SPI_MLB_MISO 46 92
SMC_ADC3 ISNS_P12VS0_GPUCORE SMC_ADC17 ISNS_SSDS0 IN OUT
1 1 44 48 94 44 49 94 PLACE_NEAR=U5110.2:1MM
C5000 5%
3
R5005 MAKE_BASE=TRUE MAKE_BASE=TRUE
1/16W NOSTUFF
0.47UF 1K MF-LF
10%
6.3V
V+ VIN
5% Unused ADC Channels 402 R5051
CERM-X5R 2
402
U5000 1/16W
MF-LF 92 44 IN SPI_SMC_MOSI 2
0
1 SPI_MLB_MOSI OUT 46 92
VREF-3.3V-VDET-3.0V 2 402 PLACE_NEAR=U5110.5:1MM
5%
DFN 44 SMC_ADC6 VSNS_VDDQS3 DDR 49 94 44 SMC_ADC4 NC_SMC_ADC4 NOSTUFF 1/16W
6 MR1* (ipu) RESET* 5 SMC RESET L MF-LF
NC SN0903048 44 46 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE R5052
D NC
7 MR2* (ipu)
OUT
44 SMC ADC7 ISNS VDDQS3 DDR
MAKE_BASE=TRUE
49 94 44 SMC ADC5 NC SMC ADC5
MAKE_BASE=TRUE NO_TEST=TRUE 92 44 IN SPI_SMC_CLK 2
0
1
402
SPI_MLB_CLK OUT 46 92
D
SILK_PART=SMCReset 4 DELAY PLACE_NEAR=U5110.6:1MM
SMC_MANUAL_RST_L CRITICAL REFOUT 8 PP3V3_G3H_AVREF_SMC 44 44 SMC_ADC8 VSNS_P12VS0 GPUUNCORE 48 94 44 SMC_ADC18 NC_SMC ADC18 5%
MIN_LINE_WIDTH=0.4MM MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 1/16W NOSTUFF
THRM MF-LF
OMIT GND PAD MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V 44 SMC_ADC9 ISNS_P12VS0 GPUUNCORE 48 94 44 SMC_ADC19 NC_SMC_ADC19 402 R5053
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 0
R50011 SPI_SMC_CS_L 2 1 SPI_MLB_CS_L
9
92 44 IN OUT 46 92
C5001 1 C5005 1 1 C5006 44 SMC ADC10 VSNS CPUCORE 48 94 44 SMC ADC20 NC SMC ADC20 PLACE_NEAR=U5110.1:1MM
0 0.01UF 10UF 0.01UF MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 5%
5% 1/16W
1/10W 10% 20% 10% 44 SMC_ADC11 ISNS_CPUCORE 48 94 44 SMC_ADC21 NC_SMC_ADC21 MF-LF
16V 6.3V 16V 402
MF-LF CERM 2 X5R 2 2 CERM MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
603 2 402 603 402 44 SMC_ADC12 VSNS_CPUAXG 48 94 44 SMC_ADC22 NC_SMC ADC22
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
GND_SMC_AVSS 44 48 49 94
MIN_LINE_WIDTH=0.4MM 44 SMC_ADC13 ISNS_CPUAXG 48 94 44 SMC_ADC23 NC_SMC ADC23
VOLTAGE=0V
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE SMC 32KHz Clock
Note: IPU are pulled to VIN rail
SMC Controlled RTC Reset Project-specific Aliases Unused Project-specific R5060
To absorb current from discharging RTC Reset CAP 44 SMC_PN2 NC_SMC PN2 22
MAKE_BASE=TRUE NO_TEST=TRUE 92 19 PM CLK32K SUSCLK R 2 1 SMC CLK32K 44 92
R5094 IN
PLACE_NEAR=U1800.BA47:5MM OUT
330 44 SMC_PN3 NC_SMC_PN3 5%
Power Button CRITICAL RTC_RESET_L_R 1 2 RTC_RESET_L OUT 18 MAKE_BASE=TRUE NO_TEST=TRUE 1/16W
MF-LF
Q5099 5% 44 SMC PN4 NC SMC PN4 402
SSM3K15AMFVAPE D 3 1/16W MAKE_BASE=TRUE NO_TEST=TRUE
45 44 6 =PP3V3 G3H SMC MF-LF 44 SMC PH3 BDV BKL PWM 82
SILK_PART=PwrBtn
VESM 402 MAKE_BASE=TRUE 44 SMC_PN6 NC_SMC PN6
SMC Crystal
44 SMC_PN5 ACDC_BURST_EN_L 45 NOTE: SMC team wants 12MHz for this Xtal
1 SMC_PN7 NC_SMC PN7
R5020 MAKE_BASE=TRUE 44
MAKE_BASE=TRUE NO_TEST=TRUE SMC_EXTAL 44 94
DEVELOPMENT 10K
5% 44 SMC PP5 NC SMC PP5
J5020 1/20W
MF
1 G S 2 MAKE_BASE=TRUE NO_TEST=TRUE
NTC020AA1JB260T 2 201 45 SMC_ASSERT_RTCRST 44 SMC_PP6 NC_SMC PP6 NOSTUFF 1
44 SMC_PJ3 SMC OOB2_TX L 41 MAKE_BASE=TRUE NO_TEST=TRUE R5066
1 SM 2 NOSTUFF MAKE_BASE=TRUE
SMC_ONOFF_L
MAKE_BASE=TRUE
OUT 44 R50991 1 C5099 44 SMC PJ2 SMC OOB2 RX L 41
44 SMC_PP7 NC_SMC_PP7
MAKE_BASE=TRUE NO_TEST=TRUE 5%
1M
10K 1.0UF MAKE_BASE=TRUE 1/16W
5% 44 SMC DP HPD L NC SMC DP HPD L MF-LF
PWR_BTN 6 1/16W 20% 44 SMC_PP0 SMC ACDC_ID 6 MAKE_BASE=TRUE NO_TEST=TRUE 402 2
OUT 6.3V
MF-LF 2 X5R-CERM MAKE_BASE=TRUE
402 2 0402 44 SMC_PME_S4_DARK_L NC_SMC_PME_S4_DARK_L CRITICAL
C 3 4 44 SMC_PH2 SMC_ASSERT_RTCRST
MAKE_BASE=TRUE
45 44 SMC_PH7
TP for access if ZPB re-intstated
I939
MAKE_BASE=TRUE
TP_SMC PH7
MAKE_BASE=TRUE
NO_TEST=TRUE
Y5065
12.000MHZ-50PPM-8PF
R5065
0
C
1 2 SMC_XTAL_R 2 1 SMC_XTAL 44 94
44 SMBUS SMC 4 ASF SCL NC SMBUS SMC 4 ASF SCL
MAKE_BASE=TRUE NO_TEST=TRUE 5%
5X3.2X1.2-SM 1/16W
44 SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF SDA C5065 1 1 C5066 MF-LF
MAKE_BASE=TRUE NO_TEST=TRUE 402
12PF 12PF
94 44 SMBUS_SMC_5_G3H_SCL NC_SMBUS_SMC_5_G3H_SCL 5% 5%
=PPVCCIO S0 SMC 50V 50V
Enable TBT S4 Wake Sources 45 6 MAKE_BASE=TRUE NO_TEST=TRUE CERM 2 2 CERM
SMBUS_SMC_5_G3H_SDA NC_SMBUS_SMC_5_G3H SDA 402 402
94 44
1
R5023 MAKE_BASE=TRUE NO_TEST=TRUE
84 6 IN =PP3V3_S4_TBTAPWRSW =TBTAPWRSW_EN OUT 84 51
5%
1/20W
Platform Thermal Control FIXME!!! - Get final cap values for NX5032GB 8PF Xtal
85 6 IN =PP3V3_S4_TBTBPWRSW =TBTBPWRSW_EN OUT 85 MF
201 2
PM_THRMTRIP_L 21
Arch Pull Up/Down
BI
45 6 =PP3V3_S0_SMC
D 6
CRITICAL 44 30 29 MEM_EVENT_L R5070 10K 1 2 5% 1/20W
MF 201
PECI Support Q5023 46 44 PM_CLKRUN_L R5071 10K 1 2 5% 1/20W
MF 201
Level-shifter that allows SMC to drive PECI SSM6N15AFE
SOT563
Place this circuit near the Tee point to minimize reflections D 3 45 44 6 =PP3V3_G3H_SMC
2 G S 1 CRITICAL
45 6 =PPVCCIO_S0_SMC
Comparator Reference 78 44 IN SMC_GFX_OVERTEMP Q5023 44 ENET_ASF_GPIO R5075 10K 1 2 5% 1/20W
MF 201
CRITICAL SSM6N15AFE 44 G3_POWERON_L R5076 10K 1 2 5% 1/20W
45 6 =PPVCCIO_S0_SMC 44 IN SMC_PECI_L Q5035 R50241 SOT563
44 SMC_BATLOW_L R5077 100K 1
MF
2 5%
201
1/20W
SSM3K15AMFVAPE D 3 10K 5 G S 4 R5078 MF 201
PLACE_NEAR=U4900.K1:5MM 1 5% 44 SMC_BC_ACOK 100K 1 2 5% 1/20W
R5030 R50351 VESM 1/20W
MF 45 6 =PP3V3_S0_SMC 44 SMC_SYS_LED R5079 100K 1
MF
2 5%
201
1/20W
10K 0 201 2 R5080 MF 201
1% 5% 44 SMS_INT_L 10K 1 2 5% 1/20W
1/16W 1/16W MF 201
MF-LF MF-LF R5025 R5028 1 44 33 SMC PME S4 WAKE L R5081 10K 1 2 5% 1/20W
402 2 402 2 MF 201
1 G S 2 R5038 1K 3.3K
43 46 SMC_ROMBOOT 2 1 5%
B PLACE_NEAR=U4900.K1:5MM
SMC_VCCIO_CPU_DIV2 OUT 44
OMIT
SMC_PECI_L_R CPU_PECI_R 2
5%
1 CPU_PECI BI 11 21 44
IN
Note: For SMC recovery mode

5%
1/20W
1/20W
MF
201 2 3 CRITICAL
33 PP3V3_S4_AP_FET B
PLACE_NEAR=U4900.K1:3MM 1/16W MF
R50311 R50361 1
R5037 MF-LF 201 Q5027 44 33 AP_EVENT_L R5085 10K 1 2 5% 1/20W
1 C5031 402 SMC THRMTRIP 5 MF 201
10K NOSTUFF 330
44 IN MMDT3904-X-G
1% 0.1UF NONE 5% SOT-363-LF
10%
1/16W
MF-LF
16V
2 X5R
NONE
NONE
1/16W
MF-LF
R50261 4 44 33 SMC_S4_WAKESRC_EN R5017 100K 1 2 5% 1/20W
402 2 402 402 2 2 402 10K R5086 MF 201
5% 61 44 36 SMC_DELAYED_PWRGD 100K 1 2 5% 1/16W
1/20W MF-LF 402
MF 61 44 PM_DSW_PWRGD R5084 100K 1 2 5% 1/16W
FIXME!!! - Is 1.0uF the right value? 201 2 MF-LF 402
69 44 SMC_PM_G2_EN R5087 100K 1 2 5% 1/20W
MF 201
CPU THRMTRIP 3V3 OUT 44
Note:
Pull-down needed for SMC SSI signals
AC/DC Burst Mode Enable Serial/JTAG Interface Pull-ups

R5027 6 CRITICAL
6 =PP3V3 S5 SMC
=PP3V3_S4_SMC CPU_THRMTRIP_L 2
3.3K
1 CPU_TT_OC_L 2
Q5027 45 44 6 =PP3V3 G3H SMC
6 Note: 11 IN MMDT3904-X-G
Open-drain stage on S4 to account 5% SOT-363-LF 46 44 SMC_TX_L R5090 10K 1 2 5% 1/20W
R50401 R50411 case when SMC is initializing in S5,
1/20W
MF 1 46 44 SMC_RX_L R5091 100K 1
MF
2 5%
201
1/20W
10K 10K 201
R5092 MF 201
5% 5% and chip is not yet configured. 44 42 MOJO_TX_L 10K 1 2 5% 1/20W
1/20W 1/20W MF 201
MF MF and ACDC_BURST_EN_L could be floating. 44 42 MOJO RX L R5093 100K 1 2 5% 1/20W
201 2 201 2 MF 201
BURSTMODE_EN_L OUT 6 67
R5095
46 44 SMC_TCK 10K 1 2 5% 1/20W
MF 201
D 6 46 44 SMC_TDI R5096 10K 1 2 5% 1/20W
MF 201
CRITICAL 46 44 SMC_TDO R5097 10K 1 2 5% 1/20W
MF 201
Q5040 46 44 SMC_TMS R5098 10K 1 2 5% 1/20W
SSM6N15AFE PROCHOT Support MF 201
SOT563 Level-shifter that allows SMC to drive PROCHOT
2 G S 1
A ACDC_BURST
CRITICAL
CPU_PROCHOT_L BI 11 44 62
R5048 SYNC MASTER=D7 DOUG SYNC DATE=01/11/2012 A
D 3
Q5025 PM_PCH_SYS_PWROK 2
0
1 SMC_PM_PCH_SYS_PWROK
PAGE TITLE
CRITICAL
SSM3K15AMFVAPE
VESM
D 3
61 19 IN
5%
1/20W
OUT 44
SMC Support
Q5040 MF DRAWING NUMBER SIZE
SOT563
SSM6N15AFE 201
REVISION
5 G S 4 R5049 R
1 G S 2 0 4.2.0
45 ACDC_BURST_EN_L 11 IN CPU_CATERR_L 2 1 SMC_CPU_CATERR_L
OUT 44
IN SMC_PROCHOT
44 IN 5%
1/20W THE INFORMATION CONTAINED HEREIN IS THE
MF PROPRIETARY PROPERTY OF APPLE INC.
60 44 38 28 19 15 PM_SLP_S3_L 201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
50 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPI BootROM LPC+SPI Connector D

D MATT CONNECTOR
LPCPLUS
6 =PP3V3_S5_ROM CRITICAL
J5100
DF40C-30DP-0.4V
M-ST-SM
CRITICAL
8
1 1
R5112 R5111 C5110 1
6 =PP3V3_S5_LPCPLUS 31 32
10K 3.3K 1UF VDD 6 =PP5V_S0_LPCPLUS
5% 5% 10%
1/16W 1/16W 6 3V
2 1 2 SPI_ALT_MISO IN 46 92
MF LF
402
2
MF LF
402
2
CERM
402 U5110 92 26 LPC_CLK33M_LPCPLUS 3 4 LPC_FRAME_L 18 44 92
64MBIT IN IN
SOIC 92 44 18 BI LPC AD<0> 5 6 SPIROM USE MLB OUT 21 46 92
92 46 45 IN SPI_MLB_CLK 6 SCK SI 5 SPI_MLB_MOSI IN 45 46 92
7 8
SST25VF064C 92 44 18 LPC AD<2> 9 10 PM CLKRUN L 44 45
BI OUT
92 46 45 IN SPI_MLB_CS_L 1 CE* 92 44 18 BI LPC_AD<1> 11 12 SPI_ALT_CLK IN 46 92
SO 2 SPI_MLB_MISO OUT 45 46 92
LPC_AD<3>
SPI_WP_L 3 WP* OMIT_TABLE 92 44 18 BI
13 14 SPI_ALT_CS_L IN 46 92
92 46 21 IN SPIROM_USE_MLB 7 HOLD* 92 46 IN SPI_ALT_MOSI 15 16 LPC_SERIRQ BI 18 44
VSS 21 OUT LPCPLUS_GPIO 17 18 LPC_PWRDWN_L IN 19 26 44
DEBUG_RESET_L 19 20 SMC_TDI
4
26 IN OUT 44 45
45 44 OUT SMC_TDO 21 22 SMC_TCK OUT 44 45
TP SMC TRST L 23 24 SMC RESET L OUT 44 45
TP SMC MD1 25 26 SMC ROMBOOT OUT 45
45 44 IN SMC_TX_L 27 28 SMC_RX_L OUT 44 45

29 30 SMC_TMS OUT 44 45
33 34
C C
998-4235
SPI Series Termination

SPI_ALT_MISO 46 92
SPI_ALT_MOSI 46 92
SPI_ALT_CLK 46 92
SPI_ALT_CS_L 46 92
1 1 1 1
R5123 R5124 R5125 R5126 PLACE NEAR=J5100 11 5mm
0 33 33 33 PLACE NEAR=J5100 9 5mm
5% 5% 5% 5% PLACE NEAR=J5100 12 5mm
1/16W 1/16W 1/16W 1/16W PLACE NEAR=J5100 14 5mm
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402
R5120 R5127
15 33
92 18 SPI_CS0_R_L 1 2 92 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 45 46 92
B IN
PLACE NEAR=U1800 AT57 5mm
R5121
5%
1/16W
R5128
5%
1/16W
PLACE NEAR=R5126 2 5mm
B
MF LF MF LF
15 402 33 402
92 18 SPI CLK R 1 2 92 SPI CLK 1 2 SPI MLB CLK OUT 45 46 92
IN
PLACE NEAR=U1800 AR54 5mm PLACE NEAR=R5125 2 5mm
5% 5%
1/16W 1/16W
R5122 MF LF R5129 MF LF
15 402 33 402
92 18 SPI_MOSI_R 1 2 92 SPI_MOSI 1 2 SPI_MLB_MOSI OUT 45 46 92
IN
PLACE NEAR=U1800 AU53 5mm PLACE NEAR=R5124 2 5mm
5% 5%
1/16W 1/16W
MF LF R5130 MF LF
402 15 402
92 18 SPI_MISO 1 2 SPI_MLB_MISO 45 46 92
OUT IN
PLACE NEAR=U5110 2 5mm
5%
1/16W
MF LF
402

PAGE TITLE
SPI and Debug Connector

DRAWING NUMBER SIZE

REVISION
R
4.2.0
51 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Line Legend
47 6 =PP3V3 S0 SMBUS 6 =PP3V3 S0 SMBUS SMC 0 Master
47 6 =PP3V3 S0 SMBUS
Slave
R52601 1
R5261 R52001 1
R5201 1 1 Mux
2.2K 2.2K 2.2K 2.2K R5264 R5265
5% 5% 5% 5% 8.2K 8.2K
1/16W 1/16W 1/16W 1/16W 5% 5%
U1800 MF LF MF LF J3100 A/B U4900 MF LF MF LF U8000 1/16W 1/16W
402 402 402 402 U1800 MF LF MF LF
PCH (SMBus) 2 2 Memory Channel A SMC (SMBus 0) 2 2 GPU Die Temp 402
2 2 402
DIMM 0:
0xA0 Write 0x9E Write
18 SMBUS PCH CLK =I2C SODIMMA SCL 29 0xA1 Read SMB 0 S0 CLK 94 44 SMBUS SMC 0 S0 SCL GPU SMB CLK R 78 0x9F Read
94 MAKE BASE=TRUE MAKE BASE=TRUE 99 18 SML_PCH_0_CLK
D 18
94
SMBUS PCH DATA
MAKE BASE=TRUE
=I2C SODIMMA SDA 29 DIMM 2:
0xA2 Write
SMB 0 S0 DATA
MAKE BASE=TRUE
94 44 SMBUS SMC 0 S0 SDA GPU SMB DAT R 78
99
94
18
MAKE BASE=TRUE
SML PCH 0 DATA
D
0xA3 Read 94 MAKE BASE=TRUE
Unused PCH SM Link

J3200 A/B U5500
Memory Channel B Temp Sensors (Prod)
DIMM 1: U5500
0xA4 Write EMC1414 (Prod):
=I2C SODIMMB SCL 30 0xA5 Read =SMB SNS1 SCL 50 0x98 Write
0x99 Read
=I2C SODIMMB SDA 30 DIMM 3: =SMB SNS1 SDA 50
0xA6 Write
0xA7 Read
U3400 U1800
VRef DAC PCH (SML 1)
0x98 Write 0x88 Write
0x99 Read 0x89 Read
=I2C VREFDACS SCL 32 SML PCH 1 CLK 18
=I2C_VREFDACS_SDA 32 SML_PCH_1_DATA 18
U3401 U5590
Vref Control LCD Temp IRemote (Dev4Now)
0x30 Write U5590
0x31 Read TMP006 (Prod):
=I2C PCA9557D SCL 32 =SMB SNS3 SCL 50 0x8A Write
0x8B Read
83 81 6 =PP3V3 S0 DP K60 Panel Requires these pullups - Can NOSTUFF when we get K70 panels
=I2C PCA9557D SDA 32 =SMB SNS3 SDA 50
C R5290 1 1
R5291
C
2.2K 2.2K
5% 5%
1/16W 1/16W
U9700 J9100 MF LF MF LF U9700
402 402
Backlight Control Display TCon 2 2 BLC Control from TCon
0x?? Write U9700
0x?? Read 6 =PP3V3 S0 SMBUS SMC 1
=I2C BKLT SCL 86 81 SMB DP TCON SCL =SMB DP BLC SCL 86 0x?? Write
94 MAKE BASE=TRUE 0x??+01 Read
=I2C BKLT SDA 86
R52101 1
R5211 81
94
SMB DP TCON SDA
MAKE BASE=TRUE
=SMB DP BLC SDA 86
4.7K 4.7K
5% 5%
1/16W 1/16W
U4900 MF LF MF LF U5550 TCon has 4.7K pullup
402 402
U6550
SMC (SMBus 1) 2 2 Temp Sensors (Dev)
U5550
CHS SMB 1 S0 CLK 94 44 SMBUS SMC 1 S0 SCL =SMB SNS2 SCL 50
TMP423B (Dev):
0x9A Write
0x76 Write MAKE BASE=TRUE 0x9B Read
0x77 Read
=I2C CHS SCL 56 SMB 1 S0 DATA 94 44 SMBUS SMC 1 S0 SDA =SMB SNS2 SDA 50
MAKE BASE=TRUE
=I2C_CHS_SDA 56
J9100
U6551
Display TCon
TMP421:
Mikey SMB DP TCON SLA SCL 81
0x9E Write
0x9F Read
0x72 Write
0x73 Read
=I2C MIKEY SCL 56 SMB DP TCON SLA SDA 81 Panel/Vendor ID:
0x1A Write
0x1B Read
=I2C MIKEY SDA 56
B B
J2550
XDP 6 =PP3V3 S4 SMBUS SMC 2
0x94 Write
0x95 Read
=SMBUS XDP SCL 25 R52201 1
R5221
4.7K 4.7K
=SMBUS XDP SDA 25 5% 5%
1/16W 1/16W
U4900 MF LF MF LF J3510
402 2 2 402
SMC (SMBus 2) ALS
0x52 Write
0x53 Read
U3600 SMB 2 S4 CLK 94 44 SMBUS SMC 2 S4 SCL =SMB ALS SCL 40
MAKE BASE=TRUE
TBT SMB 2 S4 DATA 94 44 SMBUS SMC 2 S4 SDA =SMB ALS SDA 40
0x?? Write MAKE BASE=TRUE
0x?? Read
=I2C TBTRTR SCL 34
98
=I2C_TBTRTR_SDA 34
98
NOSTUFF NOSTUFF
R52621 1
R5263
0 0
5% 5%
1/16W 1/16W U4900
MF LF MF LF
402
2 2 402 SMC (SMBus 3) 6 =PP3V3 S0 SMBUS SMC 3
=SMBUS_PCH_SCL 47 R52301 1
R5231
4.7K 4.7K
=SMBUS PCH SDA 47 5% 5%
1/16W 1/16W
U4900 MF LF MF LF U1800
A SMC (SMBus 3) 402 2 2 402 PCH SYNC MASTER=D7 DOUG SYNC DATE=01/03/2012 A
PAGE TITLE
SMB_3_CLK
MAKE BASE=TRUE
94 44 SMBUS_SMC_3_SCL =SMBUS_PCH_SCL 47
SMBus Connections
SMB 3 DATA 94 44 SMBUS SMC 3 SDA =SMBUS PCH SDA 47 DRAWING NUMBER SIZE
MAKE BASE=TRUE
REVISION
SMC multi-master experiment R
4.2.0
52 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
12V G3H AC/DC lowside sense (System total) CPU Core Voltage sense and IMON amp (VC0C, IC0C)
PEAK: ~17.1A
CRITICAL TDP: ~15.4A U4900.B6:10mm
R5300 R5361
0.002 4.53K
1%
PP12V_G3H_SNS OUT 6 NOTE:VSNS on S5 to avoid burning G3H Power 62 16 13 6 =PPVCORE_S0_CPU 1 2 VSNS_CPUCORE OUT 45 94
1W
U4900.E2:10mm
MF 1 R5301 1% U4900.B6:10mm
1/16W
0612 18.2K MF LF 1 C5361
6 =PP12V_G3H_SNS_R 1 2 6 =PP12V_S5_SNS 1 2 VSNS_P12VG3H OUT 45 94 402
0.22UF
3 4 1% U4900.E2:10mm 20%
6 3V
1/16W U4900.E2:10mm 2 X5R
MF LF
402 1 402
R5302
D 6 =PP3V3 S5 SENSE 6.04K
1%
1 C5302
0.22UF
20%
GND SMC AVSS 44 45 48 49
94
D
1/16W
1 C5300 MF LF 2
6 3V
X5R =PP5V_S0_ISENSE
0.22UF 2 402 402 48 6
20%
3
6 3V 1
2 X5R GND SMC AVSS 44 45 48 49
94
C5360
V+ 402 0.01UF
20%
U4900.E1:10mm
U5300 R5305 2 16V
CERM
INA214 4.53K VMax = 0.9V R5362 402
94 SNS P12VG3H N 5 IN- SC70 OUT 6 94 ISNS P12VG3H R 1 2 ISNS P12VG3H 45 94 10K U4900.A6:10mm
OUT REG_CPUCORE_IMON 1 2 ISNS_CPUCORE_P 1 5
CRITICAL 1%
96 62 IN 94
R5365
1/16W 1%
4 5.1K
94 SNS_P12VG3H_P 4 IN+ REF 1 MF LF U4900.E1:10mm 1/16W CRITICAL 1 2 ISNS_CPUCORE OUT 45 94
402 MF LF
1 C5305 402 5% U4900.A6:10mm
94 ISNS CPUCORE N 3 1/16W
353S2208 GND 0.22UF 2 U5360 MF LF 1 C5365
20% 402
OPA348 0.22UF
2
Gain: 100 V/V 6 3V 1

2 X5R R5363 SC70-5 10%
402 6 3V
10K 2 CERM X5R
1% OMIT_TABLE 402
GND_SMC_AVSS 44 45 48 49 1/16W
R5364
94 MF LF
2 402 9.31K GND SMC AVSS 44 45 48 49
1 2 ISNS_CPUCORE_FB 94
12V S0 GPU highside sense for GPU Core Regulator
12V S0 GPU highside sense for GPU Frame Buffer 1.5V and 1.05V Regulators(Uncore) 1%
94
PEAK: ~2.5A 1/16W

TDP: ~1.85A PEAK: ~3.1A MF LF
CRITICAL TDP: ~2.8A 402
CRITICAL
R5310
0.005 PP12V_S0_SNS_GPUCORE 6
R5350 PP12V_S0_SNS_GPUUNCORE 6 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
1% OUT 0.005 OUT
1W
U4900.F2:10mm 1%
MF R5311 1W
U4900.F2:10mm
R5351 114S0312 1 RES,MTL FILM,1/16W,9.31K,0402 R5364 SNS_CPUCORE:3PHASE
0612 18.2K MF
6 =PP12V_S0_SNS_GPUCORE_R 1 2 1 2 VSNS_P12VS0_GPUCORE OUT
0612 18.2K
6 =PP12V S0 SNS GPUUNCORE R 1 2 1 2 VSNS P12VS0 GPUUNCORE OUT 114S0345 1 RES,MTL FILM,1/16W,21K,0402 R5364 SNS_CPUCORE:4PHASE
3 4 1% U4900.F2:10mm
1/16W U4900.F2:10mm 3 4 1% U4900.F2:10mm
MF LF
1
1/16W U4900.F2:10mm
402
R5312 1 C5312
MF LF
402 1
R5352 1 C5352
C 50 49 48 41 6 =PP3V3_S0_SENSE
1 C5310
6.04K
1%
1/16W
MF LF
0.22UF
20%
6 3V
2 X5R
48 41 6
50 49
=PP3V3_S0_SENSE
1%
6.04K
1/16W
0.22UF
20%
CPU AXG Voltage sense and IMON amp (VC0G, IC0G)
C
402 1 C5350 MF LF
6 3V
2 X5R
0.22UF 2 402
20% 0.22UF 2 402 402
3
6 3V GND_SMC_AVSS 20%
2 U4900.C1:10mm
3
44 45 48 49
X5R 94 6 3V GND_SMC_AVSS
V+ 402 2 X5R 44 45 48 49
R5371
94
V+ 402
U4900.F1:10mm 4.53K
U5310 R5315 U5350 U4900.F1:10mm 62 17 13 6 =PPVAXG_S0_CPU 1 2 VSNS_CPUAXG OUT 45 94
INA210 4.53K R5355 1% U4900.C1:10mm
94 SNS_P12VS0_GPUCORE_N 5 IN- SC70 OUT
94 6 ISNS_P12VS0_GPUCORE_R 1 2 ISNS_P12VS0_GPUCORE OUT 45 94 INA210 4.53K 1/16W
94 SNS_P12VS0_GPUUC_N 5 IN- SC70 OUT 6 94 ISNS_P12VS0_GPUUC_R 1 2 ISNS_P12VS0_GPUUNCORE OUT 45 94 MF LF 1 C5371
1% 402
CRITICAL 1/16W 1% 0.22UF
94 SNS_P12VS0_GPUCORE_P 4 IN+ REF 1 MF LF U4900.F1:10mm CRITICAL 1/16W 20%
4 IN+ 6 3V
402
1 94 SNS P12VS0 GPUUC P REF 1 MF LF U4900.F1:10mm 2 X5R
C5315 402
1 C5355 402
353S2073 GND 0.22UF
20%
353S2073 GND 0.22UF GND_SMC_AVSS 44 45 48 49
2
6 3V 20%
Gain: 200 V/V 2 X5R 94
2
6 3V
402 Gain: 200 V/V 2 X5R
402 =PP5V_S0_ISENSE
48 6
94 GND_SMC_AVSS 44 45 48 49
1
94 C5370
0.01UF
20%
16V
2 CERM
VMax = 0.9V R5372 402
10K 1 5 U4900.C2:10mm
96 62 IN REG_CPUAXG_IMON 1 2 94 ISNS_CPUAXG_P R5375
1%
4 5.1K
1/16W CRITICAL 1 2 ISNS_CPUAXG OUT 45 94
MF LF
402
3
5% U4900.C2:10mm
94 ISNS_CPUAXG_N 1/16W
1 C5375
2 U5370 MF LF
402
1 OPA348 0.22UF
R5373 SC70-5 10%
6 3V
10K 2 CERM X5R
1% 402
HDD S0 Highside sense for HDD
1/16W
MF LF
R5374
B PEAK:
TDP:
~1.2A
~0.9A
2 402 1
21K
2 94 ISNS_CPUAXG_FB
94 B
CRITICAL 1%
1/16W
R5320 MF LF
402
0.010 PPHDD_S0_SNS 6
1% OUT
1/4W
U4900.E2:10mm
MF R5321
0805 4.02K
6 =PPHDD S0 SNS R 1 2 1 2 VSNS HDDS0 OUT 45 94
3 4 1% U4900.E2:10mm
1/16W U4900.E2:10mm
MF LF
1
402
R5322 1 C5322
6.04K 0.22UF
1%
1/16W 20%
6 3V
MF LF 2 X5R
402 402
2
94
U5320
INA216 U4900.E1:10mm
WCSP-4 R5325
A1 B2 4.53K
94 SNS_HDD_P IN+ OUT 94 ISNS_HDDS0_R 1 2 ISNS_HDDS0 45 94
OUT
CRITICAL
1%
SNS_HDD_N A2 IN-OMIT_TABLE K 1/16W
94
DZ5320 MF LF U4900.E1:10mm
402
CDZ3.0B 1 C5325
GND SM 0.22UF
353S3597 B1 A 20%
6 3V
Gain: 200 V/V 2 X5R
402
94
A PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION SYNC MASTER=D7 DOUG SYNC DATE=01/06/2012 A
PAGE TITLE
353S3597 1 INA216A4 200V/V Current Sense U5320
I and V Sense(Production)
DRAWING NUMBER SIZE

REVISION
R
4.2.0
53 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
VDDQ S3 VDDQ lowside sense for SO-DIMM modules

Peak: ~12 A
TDP: ~6 A
C CRITICAL
R5440 SNS_VDDQS3_DDR:Y
C
0.0005 PPVDDQ_S3_SNS_DDR 6
1% OUT
1W
U4900.B4:10mm
MF R5441
0612 4.53K
6 =PPVDDQ_S3_SNS_DDR_R 1 2 1 2 VSNS_VDDQS3_DDR OUT 45 94
3 4 1% OMIT_TABLE
1/16W
MF LF U4900.B4:10mm
402
1 C5441
48 41 6 =PP3V3_S0_SENSE 0.22UF
50 SNS_VDDQS3_DDR:Y 20%
1 C5440 6 3V
2 X5R
0.22UF 402
20%
3
6 3V GND_SMC_AVSS
2 X5R 44 45 48 49
V+ 402 SNS_VDDQS3_DDR:Y 94
U4900.A4:10mm
U5440 R5445
INA211 4.53K
94 SNS_VDDQS3_DDR_N 5 IN- SC70 OUT 6 94 ISNS_VDDQS3_DDR_R 1 2 ISNS_VDDQS3_DDR OUT 45 94
SNS_VDDQS3_DDR:Y 1% OMIT_TABLE
1/16W
94 SNS_VDDQS3_DDR_P 4 IN+ REF 1 MF LF U4900.A4:10mm
402
1 C5445
353S2216 GND 0.22UF
20%
2
6 3V
Gain: 500 V/V 2 X5R
402
94
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
SSD S0 Highside sense for SSD

B SSD
Peak:
TDP:
~3 A(Connector Supports 5A)
~2.1 A
132S0080
116S0004
2
2
CAP,0.22UF,402
RES,0 OHM,402
C5441,C5445
C5441,C5445
SNS_VDDQS3_DDR:Y
SNS_VDDQS3_DDR:N
B
CRITICAL
R5420
0.002 PPSSD_S0_SNS 6
SSD
1% OUT
1W
U4900.E2:10mm
MF 1 R5421
0612 4.53K
6 =PPSSD S0 SNS R 2 1 1 2 VSNS SSDS0 OUT 45 94
4 3 1%
1/16W SSD
MF LF
402 U4900.E2:10mm
1 C5422
0.22UF
20%
6 3V
2 X5R
402
U5420 SSD
U4900.E1:10mm
94
INA216 R5425
WCSP-4
A1 4.53K
94 SNS_SSD_P IN+ CRITICALOUT B2 94 ISNS_SSDS0_R 1 2 ISNS_SSDS0 OUT 45 94
1%
94 SNS_SSD_N A2 IN- 1/16W SSD
MF LF U4900.E1:10mm
OMIT_TABLE 402
1
GND C5425
353S3597 0.22UF
B1 20%
6 3V
Gain: 200 V/V 2 X5R
402
94

PAGE TITLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
353S3597 1 INA216A4 200V/V Current Sense U5420 SSD

I and V Sense(Development)
DRAWING NUMBER SIZE

REVISION
R
4.2.0
54 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Temperature Sensor T1: Production Bound
GPU Proximity AC/DC Diode on supply
L5514
FERR-220-OHM
SNS T1 1 P 50 94
1 2 SNS T1 3 P 50
D 3
0402 D
Q5510.3:2MM L5514.2:2MM 50 49 48 41 6 =PP3V3_S0_SENSE
CRITICAL 94 6 IN SNS_ACDC_P
1 C5510 1 C5514
1 Q5510 94 6 SNS ACDC N
2.2PF IN 0.0022UF
BC846BLP +/-0.25PF L5515 10% 1 C5500 1
R5500
DFN1006H4-3 2 50V
C0G-CERM FERR-220-OHM 2 50V
CERM 1UF
2 402 402 10%
10K
5%
SNS_T1_1_N 50 94
1 2 SNS_T1_3_N 50 2 10V
X5R 1/16W
402-1 MF LF
PLACEMENT_NOTE=Place Q5510 near GPU and GDDR5 0402
2 402
1
VDD
CPU Proximity U5500

EMC1414-1-AIZL
SNS T1 2 P MSOP
50 94 2 DP1 7
GPU Prox 94 50 SNS_T1_1_P THERM*/ADDR NC
3 Q5512.3:2MM 94 50 SNS_T1_1_N 3 DN1 ALERT* 8 SNS1_ALERT_L
CRITICAL 1
1 C5512 4 DP2/DN3 9
Q5512 2.2PF CPU Prox 94 50 SNS T1 2 P SMDATA =SMB SNS1 SDA BI 47
BC846BLP +/-0.25PF MAKE_BASE=TRUE
DFN1006H4-3 50V
2 C0G-CERM 94 50 SNS T1 2 N 5 DN2/DP3 SMCLK 10 =SMB_SNS1_SCL 47
IN
2 402 MAKE_BASE=TRUE GND
SNS_T1_2_N 50 94 AC/DC 50 SNS_T1_3_P NOSTUFF NOSTUFF 6
PLACEMENT_NOTE=Place Q5512 in CPU socket cavity U5500.4:2MM U5500.5:2MM I2C Address (EMC1414-1):
50 SNS T1 3 N 1 1
C5504 C5505 0x98 (Write)
47PF 47PF 0x99 (Read)
5% 5%
50V 2 50V
CERM 2 CERM
402 402
Note:
C Make sure these caps are OK with U5500 Vendor!

Internal sensor of the EMC 1414
will be used as the ambient sensor.
C
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: Place U5500 at the coolest location
PART NUMBER
on the MLB.
372S0186 372S0185 ALL Alternate Temp Diode
Temperature Sensor T2: Development Only Temperature Sensor T3: LCD Remote Sensor(Dev4Now)
SO-DIMM Proximity 50 49 48 41 6 =PP3V3_S0_SENSE
SNS_T2_1_P 50 94
DIFFERENTIAL_PAIR=SNS_T2 TEMPSNSDEV
SIGNAL_MODEL=EMPTY 1 C5590
3 Q5560.3:2MM
B 1
CRITICAL
Q5560
1 C5560
2.2PF
0.01UF
10%
16V
2 CERM TEMPSNSDEV
B
BC846BLP +/-0.25PF
50V
402 1
R5590
DFN1006H4-3 2 C0G-CERM
2 402 SO-DIMM 94 50 SNS_T2_1_P 10K
A3
5%
SNS_T2_1_N 50 94 1/16W
DIFFERENTIAL_PAIR=SNS_T2 OMIT MF LF
SIGNAL_MODEL=EMPTY V+ 2 402
PLACEMENT_NOTE=Place Q5550 near SO-DIMM connectors U5550.4:2MM
XW5551 U5590
SM TMP0006AIYZER
50 49 48 41 6 =PP3V3_S0_SENSE C3 WCSP
94 50 SNS_T2_1_N 1 2 47 BI =SMB_SNS3_SDA SDA ADR0 C1
BLC Proximity B3 ADR1 B1
1 47 IN =SMB SNS3 SCL SCL
Skin 94 50 SNS_T2_2_P C5550
SNS T2 3 P 50 94
1UF DRDY* C2 TMP006 DRDY
DIFFERENTIAL_PAIR=SNS_T3 10%
OMIT 10V TEMPSNSDEV
3 SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 2 X5R I2C Address (TMP006):
Q5564.3:2MM U5550.4:2MM 402-1
DGND AGND
CRITICAL 0x8A (Write)
1 C5564 XW5552
A1
A2
1 Q5564 SM 0x8B (Read)
2.2PF
BC846BLP +/-0.25PF
50V 94 50 SNS T2 2 N 1 2
8
DFN1006H4-3 2 C0G-CERM
2 402 V+ NOTE - Follow TI layout guide(SBOU108.pdf) for this part!!!
SNS_T2_3_N BLC Prox SNS_T2_3_P
DIFFERENTIAL_PAIR=SNS_T3
50 94 94 50
U5550
OMIT 1 DXP1
TMP423
PLACEMENT_NOTE=Place Q5554 near BLC controller SIGNAL_MODEL=EMPTY SOT23-8 SCL 7 =SMB_SNS2_SCL IN 47
U5550.4:2MM 2 DXP2 SDA 6 =SMB_SNS2_SDA BI 47
XW5553 3 DXP3
SM
94 50 SNS T2 3 N 1 2 SNS T2 DXN 4 DXN I2C Address (TMP432B):
Skin 0x9A (Write)
GND
TEMPSNSDEV 5 0x9B (Read)
CRITICAL TEMPSNSDEV
A J5562
53780-8602
L5562
FERR-220-OHM SYNC MASTER=D7 DOUG SYNC DATE=12/13/2011 A
PAGE TITLE
M-RT-SM 1 2
3
DIFFERENTIAL_PAIR=SNS_SKIN 0402
SNS_T2_2_P
TEMPSNSDEV
50 94
Temperature Sensors
SIGNAL_MODEL=EMPTY DRAWING NUMBER SIZE
L5562.2:2MM
1 94 SNS_SKIN_P
1 C5562 Apple Inc. 051-9509 D
2 94 SNS_SKIN_N TEMPSNSDEV REVISION
0.0022UF R
DIFFERENTIAL_PAIR=SNS_SKIN L5563 10%
50V
2 CERM
4.2.0
4 FERR-220-OHM NOTICE OF PROPRIETARY PROPERTY: BRANCH
402
1 2 SNS T2 2 N 50 94 THE INFORMATION CONTAINED HEREIN IS THE
0402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
518S0698
SILK_PART=SkinTemp
55 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC Fan 0 (System)

CRITICAL
L5600
D Note:
The circuit for the PWM input to
6 =PP12V S0 FAN 220-OHM-1.4A
1 2
D
PP12V_S0_FAN_0_FILT
the fan acts as a non-inverting 0603 VOLTAGE=12V
1 1 MIN_LINE_WIDTH=0.5MM
level-shifter to protect the SMC. C5600 C5601 MIN_NECK_WIDTH=0.25MM
It is assumed there is a pull-up to 4.7UF 0.01UF
20% 20%
16V 16V
5V/12V inside the fan, otherwise 2 CERM 2 CERM
when the SMC PWM goes low and Q5610 1206-1 402 518S0730
turns on, there would be 5V/12V
present on the SMC pin! Then by
definition, the drain of Q5610 is 51 6 =PP3V3_S0_FAN
at common and the SMC sinks current
CRITICAL
when Q5610 is on. 1 CRITICAL
R5610 Q5610 J5600
This resembles an open-drain if 10K SSM3K15AMFVAPE 53780-8604
1
5% CRITICAL M-RT-SM
there is a pull-up, going to a Hi-Z 1/16W
G
VESM
MF-LF L5610 5
FET input. 2 402 FERR-220-OHM MIN_LINE_WIDTH=0.5MM
D
Otherwise, this is simply a pass-FET. 44 SMC_FAN_0_CTL FAN_0_PWM_FET 1 2 FAN_0_PWM_FILT 1
IN
3
2
0402 FAN_0_TACH_FILT 2 Tach
1 C5610 3 GND
100PF
5% 4 12V DC
50V
2 CERM
51 6 =PP3V3_S0_FAN 402
6
1
R5626
47K
5% CRITICAL
1/16W
MF-LF L5620
R5625 2 402 FERR-220-OHM
47K 1 2
C 44 OUT SMC_FAN_0_TACH 1
5%
1/16W
2 FAN_0_TACH_FET
1 C5620
0402 C
MF-LF
402 100PF
5%
2 50V
CERM
402
SMC Fan 1 (Unused)
44 IN SMC_FAN_1_CTL NC_SMC_FAN_1_CTL
44 OUT SMC_FAN_1_TACH NC_SMC_FAN_1_TACH

B B

PAGE TITLE
System Fan
DRAWING NUMBER SIZE

REVISION
R
4.2.0
56 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC PLACE C6200 AS CLOSE TO PIN 9 AS POSSIBLE
APPLE P/N 353S2592 PP5V_AUDIO_HPAMP 52 53
IN
VD MUST BE LESS THAN OR EQUAL TO VL_HD
6 =PP1V5 S0 AUD DIG
=PP3V3_S0_AUDIO IN 6 40 52 54 55 58
C6101 1 1 C6100
4.7UF 0.47UF
20%
4V
10% PP4V5 AUDIO ANALOG IN 52 56 58
X5R-1 2 2 10V
X5R CRITICAL
402 402
C6105 1 1 C6104C6106 C6107
C6108 1
1UF 0.47UF
1 1
10UF 10% 10% 0.47UF 10UF
20% C6102 1 1
C6103 10V 2
10V
2 X5R 10% 20%
D 59 58 56 52 GND_AUDIO_CODEC
16V 2
POLY-TANT
CASE-B2-SM
0.47UF
10%
10UF
20%
X5R
402-1 402
10V
X5R 2
402
10V
2 X5R-CERM
0402-1 D
24
46
25
10V 2 2 16V
9
PP4V5_AUDIO_ANALOG X5R POLY-TANT GND_AUDIO_CODEC
58 56 52 IN
C6109 1 1 C6110 VD VA_REF VA_HP VA
402 CASE-B2-SM
GND AUDIO CODEC
52 56 58 59
1 2.2UF 2.2UF 52 56 58 59
1
R6100 20%
6.3V
20%
6.3V
VBIAS DAC 29 VBIAS_DAC R6105
2.67K CERM 2 2 CERM 0
1% 402-LF 402-LF HPOUT_L 38 MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM TP AUD HP L NC 5%
1/16W CS4206_FP 44 VHP_FILT+ CRITICAL 1/16W
MF-LF HPOUT_R 40 MIN_LINE_WIDTH=0 1MM MIN_NECK_WIDTH=0 1MM TP_AUD_HP_R NC MF-LF
2 402
CS4206_FN 41 VHP_FILT- U6101 2 402
CS4206B HPREF 39 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM CS4206 HPREF
QFN
DMICS 1 & 2 40 AUD_DMIC_SDA1
OUT 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_L_P OUT 53 54 59
NC TP_DMIC_SDA2 12 GPIO1/DMIC_SDA2
/SPDIF_OUT2
LINEOUT_L1- 34 AUD_LO1_L_N OUT 53 54 59 HP AMP/LINE OUT RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT
HP AMP CNTRL 53 OUT AUD GPIO 2 14 GPIO2 LINEOUT_R1+ 36 AUD LO1 R P OUT 53 55 59 TWEETERS
15 GPIO3 LINEOUT_R1- 37 AUD LO1 R N OUT 53 55 59
Q6170_P_S
MAC SPKR AMP CNTRL
D6100
SOD-523 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_L_P OUT 54 59
DEVEL_AUDIO DEVEL_AUDIO
54 52 IN AUD_CODEC_MICBIAS A K CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 54 59 WOOFERS CRITICAL 1
CS4206 FLYC LINEOUT_R2+ 32 AUD LO2 R P OUT 55 59 Q6170 R6170
BAT54XV2T1 45 FLYP
DMC2400UV 0
LINEOUT_R2- 33 AUD LO2 R N 5%
4
C6111 1 1 C6112 43 FLYC OUT 55 59
SOT563 1/16W
MF-LF
WIN SPKR AMP CNTRL AUD_GPIO_3 2.2UF 2.2UF 42 FLYN
54 OUT 20% 20% 2 402
59 58 AUD_SENSE_A 6.3V 2 2 6.3V MICBIAS 16 AUD_CODEC_MICBIAS 52 54
IN CERM CERM OUT
402-LF 402-LF
S
Q6170 P G
3 VL_HD
P-CHN
5
CS4206 FLYN
G
VCOM 28 CS4206_VCOM MIN_NECK_WIDTH=0.15MM
D
1 VL_IF
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC
3
LINEIN_L+ 21 NO_TEST=TRUE NC_AUD_LI_P_L NC
92 18 IN HDA BIT CLK 6 BITCLK NC
LINEIN_C- 22 NO_TEST=TRUE NC_AUD_LI_COM NC
C 92 18 15 IN HDA_SYNC LINEIN_R+ 23 NO_TEST=TRUE NC_AUD_LI_P_R NC
6
NC
C
R6101 10 SYNC
HDA_SDIN0 1
22 2 AUD_SDI_R AUD_MIC_INL_P IN DEVEL_AUDIO
92 18 OUT 92 8 SDI MICIN_L+ 18 56 59 CRITICAL D
AUD_MIC_INL_N IN Q6170
N-CHN
5% 5 SDO MICIN_L- 17 56 59
1/16W
MF-LF MICIN_R+ 19 NO_TEST=TRUE NC_AUD_MIC_INP_R NC DMC2400UV
402 11 RESET* SOT563 G 2 Q6170_N_G
92 18 IN HDA SDOUT MICIN_R- 20 NO_TEST=TRUE NC AUD MIC INN R NC S
92 18 IN HDA_RST_L
DEVEL_AUDIO
98 81 IN DP_INT_SPDIF_AUDIO 47 SPDIF_IN
92 AUD_SPDIF_CHIP 48 SPDIF_OUT
VREF+_ADC 27 CS4206_VREF_ADC
NC 1
1
R6171
R6102 MIN_NECK_WIDTH=0.15MM R6104 0
5%
22 CS4206 DMIC SCL 22 1/16W
92 56 OUT AUD_SPDIF_OUT 1 2
1 DMIC_SCL 4 1 2 AUD_DMIC_CLK OUT 40 MF-LF
5% R6103 5% 2 402
1/16W 100K 1/16W
MF-LF 1% MF-LF Q6170_N_S
402 1/16W DGND THRM_PAD AGND 402
MF-LF
402 2
49
26
DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA
XW6100 CRITICAL CRITICAL
40 OUT GND_AUDIO_DMIC
C6113 1 1
C6114 C6115 1
DIFF FSINPUT= 2.45VRMS
0.47UF
1
MIN_NECK_WIDTH=0.15MM SM 1UF 10UF

VOLTAGE=0V 10%
20V 2
20%
2 16V
10%
10V SE FSINPUT= 1.22VRMS Q6171_P_S
TANT POLY-TANT X5R 2 DAC1 FSOUTPUT= 1.34VRMS
CASE-P3-HF CASE-B2-SM 402
DEVEL_AUDIO DEVEL_AUDIO
DAC2/3 FSOUTPUTDIFF= 2.67VRMS CRITICAL 1
DAC2/3 FSOUTPUTSE= 1.34VRMS Q6171 R6172
DMC2400UV 0
5%
4
SOT563 1/16W
MF-LF
59 58 56 52 GND_AUDIO_CODEC 2 402
S
Q6171_P_G
P-CHN
B
5
B
G
D
APPLE P/N 353S2456 PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS:
4.5V POWER SUPPLY FOR CODEC
3
127S0134 127S0111 C6113 THAILAND ALTERNATE
NC
NC
6
DEVEL_AUDIO
CRITICAL D
Q6171
N CHN
MIN NECK_WIDTH=0.20MM
L6111 VOLTAGE=4.5V
DMC2400UV
FERR-220-OHM SOT563
G 2 Q6171_N_G
1 2 PP5V_AUDIO_HPAMP S
OUT 52 53
0402 DEVEL_AUDIO
1
1 R6173
MIN_LINE_WIDTH=0.40MM 0
MIN NECK_WIDTH=0.20MM 5%
VOLTAGE=4.5V 1/16W
MF-LF
L6110 2 402
FERR-220-OHM VR6101
TPS71745 Q6171 N S
59 6 =PP5V_S0_AUDIO 1 2 4V5_REG_IN 6 IN SON 1 PP4V5 AUDIO_ANALOG 52 56 58
IN OUT OUT
0402 MIN_LINE_WIDTH=0.40MM
CRITICAL MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V
R6120 4V5_REG_EN 4 EN NR/FB 3 4V5_NR
0
55 54 52 40 6 IN =PP3V3 S0 AUDIO 1 2
GND NC 5 MIN_LINE_WIDTH=0.4MM
58 MIN_NECK_WIDTH=0.2MM
5%
1/16W
C6122 1
2
MF-LF 1UF C6123 1 1 C6124
402 10%
A 10V
X5R 2
402-1
XW6110 0.1UF
10%
16V
1UF
10%
2 10V
SYNC MASTER=D7 BREECE SYNC DATE=01/03/2012 A
X7R-CERM 2
1
X5R PAGE TITLE

SM 402 402-1
GND_AUDIO_CODEC 52 56 58 59
AUDIO: CODEC/REGULATORS
MIN_LINE_WIDTH=0.5MM DRAWING NUMBER SIZE
VOLTAGE=0V
XW6111 REVISION
GND_AUDIO_HPAMP 53 R
MIN_LINE_WIDTH=0.5MM 4.2.0
1
SM MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V NOTICE OF PROPRIETARY PROPERTY: BRANCH
PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
61 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SIGNAL_MODEL=EMPTY
C6262
220PF
1 2
5%
25V
CERM
402
R6262
7.87K2
1
R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
1%
1/20W
MF MAX97220_OUTR OUT 53 56 53 52 PP5V_AUDIO_HPAMP
201
D CRITICAL
C6261 R6261
SIGNAL_MODEL=EMPTY D
33UF
AUD_LO1_R_N 1 2 59 AUD_LO1_R_C_N 1
10K 2 MAX97220_INR_N C6250 1 1 C6251 C6252 1 1 C6253
59 55 52 IN OUT 53 59
0.1UF 10UF 1UF 1UF
1% 10% 20% 10% 10%
1/20W 16V 10V 10V 10V
20% X7R-CERM 2 2 X5R-CERM X5R 2 2 X5R
6.3V MF
201 402 0402-1 402-1 402-1
TANT
CASE-A
53 52 GND_AUDIO_HPAMP GND_AUDIO_HPAMP 52 53
CRITICAL
C6263 R6263
13
33UF
9
10K
59 55 52 IN AUD_LO1_R_P 1 2 59 AUD_LO1_R_C_P 1 2 MAX97220_INR_P OUT 53 59
PVDD
SVDD
SVDD2
1%
20% 1/20W R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL
6.3V MF
TANT 201
CASE-A
SIGNAL_MODEL=EMPTY 59 53 IN MAX97220 INR N 14 INL- OUTL 12 MAX97220 OUTR OUT 53 56
SIGNAL_MODEL=EMPTY 15 INL+ CRITICAL MIN_LINE_WIDTH=0.4MM
R62641 59 53 MAX97220_INR_P MIN_NECK_WIDTH=0.2MM
7.87K
1 C6264 IN
U6250 BIAS 11 MAX97220_BIAS
1% 220PF MAX97220AETE MIN_NECK_WIDTH=0.2MM
1/20W 5%
25V 59 53 IN MAX97220_INL_P 7 INR+ TQFN OUTR 10 MAX97220_OUTL OUT 53 56
MF 2 CERM MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
201 2 402 59 53 IN MAX97220_INL_N 8 INR- MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
2
C1P MAX97220_C1P
AUD_HP_PORT_REF MAX97220_SHDN_L 16 SHDN* C1N 4
THM_PAD
56 53 IN
1 C6255 1 C6256
PGND
SGND
PVSS
1UF 1UF NOSTUFF NOSTUFF
SIGNAL_MODEL=EMPTY 10% 10%
1 SIGNAL_MODEL=EMPTY 2 10V
X5R 2 10V
X5R R62531 1
R6254
R6274 1 C6274 402-1 402-1 2.0K 2.0K
17
7.87K 220PF 5% 5%
1% 1/16W 1/16W
1/20W
MF
5%
2 25V
MAX97220_C1N
C6257 1 1 C6258 MF-LF
402 2
MF-LF
201 2
CERM
MIN_NECK_WIDTH=0.2MM 0.1UF 0.1UF 2 402 NOSTUFF NOSTUFF
402 10% 10%
16V 16V CRITICAL CRITICAL
C CRITICAL
C6273
X7R-CERM 2
402
2 X7R-CERM
402 SOT23
MMBFJ201
SOT23
MMBFJ201
C
33UF R6273 NC MAX97220_OUTL_ZOBEL MAX97220_OUTR_ZOBEL NC
2 Q6250 2 Q6251
10K MAX97220 PVSS 53
59 54 52 IN AUD_LO1_L_P 1 2 59 AUD_LO1_L_C_P 1 2 MAX97220_INL_P OUT 53 59 MIN_LINE_WIDTH=0.5MM
1% VOLTAGE=0V S
S
20%
6.3V
1/20W
MF 1 C6254 R62511 1
R6252 G 3 3
G
TANT 201
1UF 33 33
CASE-A 10% 5% 5%
10V 1/16W 1/16W
2 X5R MF-LF MF-LF D
D
CRITICAL 402-1 402 2 2 402
C6271 R6271 1
33UF 1
10K
59 54 52 IN AUD_LO1_L_N 1 2 59 AUD_LO1_L_C_N 1 2 MAX97220_INL_N OUT 53 59
1%
20% 1/20W 53 52 GND_AUDIO_HPAMP
6.3V MF
TANT 201
CASE-A SIGNAL_MODEL=EMPTY
MAX97220_OUTL OUT 53 56
R6272
7.87K2 NOSTUFF
1
R6255
1% 0
1/20W 53 52 PP5V_AUDIO_HPAMP 1 2 HPOUT_JFET_G
MF
201 5%
1/16W
C6272 MF-LF
402
220PF
1 2 NOSTUFF
R6256
5% 0
25V 53 MAX97220_PVSS 1 2
CERM 5%
402 1/16W
SIGNAL_MODEL=EMPTY MF-LF
402
B L6250 B
FERR-220-OHM
PART NUMBER
52 IN AUD_GPIO_2 1 2 MAX97220_SHDN_L OUT 53
127S0135 127S0120 C6261 THAILAND ALTERNATE 0402

R62501
100K
5%
127S0135 127S0120 C6273 THAILAND ALTERNATE 1/20W
MF
201 2
A SYNC MASTER=D7 BREECE SYNC DATE=01/03/2012 A

PAGE TITLE
AUDIO: HEADPHONE AMP

DRAWING NUMBER SIZE

REVISION
R
4.2.0
62 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LEFT CH SPEAKER AMP
APPLE P/N 353S3163 SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
55 6 IN =PP12V S0 AUDIO SPKRAMP FC_HPF, TWEETERS = ~847 HZ (4700 PF)
CRITICAL
FC_HPF, WOOFERS = ~18 HZ (0.22 UF)
C6300 1 1 C6301 C6302 1 1 C6303 C6304 1 1 C6305 C6306 1
10UF 10UF 0.1UF 1UF 0.1UF 1UF 470UF
10% 10% 10% 10% 10% 10% 20%
25V 2 2 25V 25V 2 25V
2 X5R 25V 2 25V
2 X5R 16V 2
X5R X5R X5R X5R POLY
805 805 402 603-1 402 603-1 SM
D D
INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

L6303 C6308 OUTPUT POLARITY FLIP TO
FERR-1000-OHM 4700PF
AUD LO1 L N 1 2 AUD_LAMP_RINC_P 1 2 AUD_LAMP_RIN_P TP_AUD_LAMP_THERM NC MAKE LAYOUT MORE LOGICAL
34
35
36
37
59 53 52 59 59
IN
0402
5%
50V
NPO-C0G PVDD
C6313
805 20 INR+ 0.22UF SIGNAL_MODEL=EMPTY
THERM 17 1 2
AUD_LAMP_BOOTRP CRITICAL
L6302 C6309 19 INR- CRITICAL MIN_LINE_WIDTH=0.20MM
FERR-1000-OHM 4700PF WOOFERS & TWEETERS ON UNDER MAC OS U6300 BOOTR+ 30
AUD_LAMP_OUTPR
OUT L6305
54
110-OHM-3A
AUD_SPKR_LTWT_OUT_P OUT 57 59
25V MIN_NECK_WIDTH=0.25MM SIGNAL_MODEL=EMPTY
59 53 52 IN AUD LO1 L P 1 2 59 AUD_LAMP_RINC_N 1 2 59 AUD_LAMP_RIN_N 55 54 IN AUD_SPKRAMP_MAC_SHDN_L 22 STDNR* SSM3302 X5R
603 AUD_LAMP_OUTNR 4
DLY5ATN111SQ2
SYM VER-2 3 CRITICAL
0402
5%
LFCSP
OUTR+
28 54 IN 1 C6323
50V 29 1000PF
NPO-C0G 5%
805 54 AUD_LAMP_MONO 16 MONO 54 AUD_LAMP_OUTPR 1 2 25V
2 NP0-C0G
IN IN
L6300 C6310 26
C6314 402
FERR-1000-OHM 0.22UF ONLY WOOFERS ON UNDER WINDOWS OUTR- 27 0.22UF AUD_LAMP_OUTNR 54 AUD_SPKR_LTWT_OUT_N 57 59
OUT OUT
59 52 AUD_LO2_L_N 1 2 59 AUD LAMP LINC P 1 2 59 AUD LAMP LIN P 55 54 AUD SPKRAMP WIN SHDN L 9 STDNL* AUD LAMP BOOTRN 1 2 MIN_NECK_WIDTH=0.25MM
IN IN
0402
10% BOOTR- 25 MIN_NECK_WIDTH=0.15MM 20%
16V 11 INL+ 25V
CERM X5R
402 12 INL- EDGE 10 AUD_LAMP_EDGE 54
603
IN
L6301 C6311 C6315
FERR-1000-OHM 0.22UF BOOTL+ 1 0.22UF SIGNAL_MODEL=EMPTY
59 52 AUD LO2 L P 1 2 59 AUD_LAMP_LINC_N 1 2 59 AUD_LAMP_LIN_N 54 AUD_LAMP_GAIN 21 GAIN AUD_LAMP_BOOTLP 1 2 CRITICAL
IN IN
C 0402
10%
16V OUTL+
2
3
25V
AUD_LAMP_OUTPL
L6307
110-OHM-3A
AUD_SPKR_LWFR_OUT_N
SIGNAL_MODEL=EMPTY
OUT 57 59 C
CERM X5R DLY5ATN111SQ2 CRITICAL
402 AUD LAMP AVDD 8 VREG/AVDD 603 4 SYM VER-2 3

54
MIN NECK WIDTH=0.15MM 4
1 C6324
VOLTAGE=5V 1000PF
OUTL- 5 5%
1 2 25V
2 NP0-C0G
402
58 55 52 40 6 =PP3V3_S0_AUDIO 23 REGEN BOOTL- 6 C6316
0.22UF AUD_LAMP_OUTNL AUD_SPKR_LWFR_OUT_P OUT 57 59
AUD_LAMP_BOOTLN MIN_NECK_WIDTH=0.25MM
NC MIN_NECK_WIDTH=0.15MM
13 20%
NC NC 25V
C6317 1 14 X5R
603 OUTPUT POLARITY FLIP TO
2.2UF AGND PGND 15
20%
10V THRM PAD MAKE LAYOUT MORE LOGICAL CRITICAL CRITICAL
X5R-CERM 2
402
C6320 1 C6322 1
7
24
41
31
32
33
38
39
40
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
1000PF 1000PF
5% 5%
25V 25V
NP0-C0G 2 NP0-C0G 2
PINS 14 & 15 ARE TEST PINS AND 402 402
SHOULD BE TIED TO GND

CRITICAL CRITICAL
SIGNAL_MODEL=EMPTY 1 C6319 1 C6321 SIGNAL_MODEL=EMPTY
1000PF 1000PF
5% 5%
25V
2 NP0-C0G 2 25V
NP0-C0G
402 402
B B
L6308
FERR-1000-OHM
52 IN AUD_CODEC_MICBIAS1 2 AUD_SPKRAMP_MAC_SHDN_L OUT 54 55
0402 GAIN R6306 R6307
+9 DB NOSTUFF 0 OHM
NOSTUFF
EDGE RATE +12 DB NOSTUFF NOSTUFF
R63011 1 C6312 CONTROL R6304 R6305 AUD_RAMP_MONO NET: +15 DB 0 OHM NOSTUFF
100K
5% 100PF ON 0 OHM NOSTUFF HIGH = MONO OPERATION +18 DB NOSTUFF 47 KOHM
1/16W
MF-LF
5%
50V
2 CERM
OFF NOSTUFF 0 OHM LOW = STEREO OPERATION +24 DB 47 KOHM NOSTUFF
402 2 402
54 AUD_LAMP_AVDD
NOSTUFF
1 1
R6304 R6306
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
R6308 AUD_LAMP_EDGE OUT 54 AUD_LAMP_MONO OUT 54 AUD_LAMP_GAIN OUT 54
1
0 2
52 IN AUD_GPIO_3 AUD_SPKRAMP_WIN_SHDN_L OUT 54 55
NOSTUFF
5%
1 1 1
1/16W
MF-LF R6305 R6303 R6307
402 0 0 0
A R6309 1
1
NOSTUFF
C6318
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF SYNC MASTER=D7 BREECE SYNC DATE=01/03/2012 A
100K 2 402 2 402 2 402 PAGE TITLE
100PF
5%
1/16W
MF-LF
5%
50V
2 CERM
AUDIO: LEFT SPKR AMP
402 2 402 DRAWING NUMBER SIZE

REVISION
R
4.2.0
63 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RIGHT CH SPEAKER AMP
APPLE P/N 353S3163 SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
54 6 IN =PP12V S0 AUDIO SPKRAMP FC_HPF, TWEETERS = ~847 HZ (4700 PF)
CRITICAL
FC_HPF, WOOFERS = ~18 HZ (0.22 UF)
C6400 1 1 C6401 C6402 1 1 C6403 C6404 1 1 C6405 C6406 1
10UF 10UF 0.1UF 1UF 0.1UF 1UF 470UF
10% 10% 10% 10% 10% 10% 20%
25V 2 25V
2 X5R 25V 2 25V
2 X5R 25V 2 25V
2 X5R 16V 2
X5R X5R X5R POLY
805 805 402 603-1 402 603-1 SM
D D

L6400 C6408 OUTPUT POLARITY FLIP TO
FERR-1000-OHM 0.22UF
AUD LO2 R N 1 2 AUD_RAMP_RINC_P 1 2 AUD_RAMP_RIN_P TP_AUD_RAMP_THERM NC MAKE LAYOUT MORE LOGICAL
34
35
36
37
59 52 59 59
IN
0402
10%
16V
CERM PVDD
C6413
402 20 INR+ 0.22UF SIGNAL_MODEL=EMPTY
THERM 17 1 2
AUD_RAMP_BOOTRP CRITICAL
L6401 C6409 19 INR- CRITICAL MIN_LINE_WIDTH=0.20MM
FERR-1000-OHM 0.22UF ONLY WOOFERS ON UNDER WINDOWS U6400 BOOTR+ 30
AUD_RAMP_OUTPR
OUT L6405
55
110-OHM-3A
AUD_SPKR_RWFR_OUT_P OUT 57 59
25V MIN_NECK_WIDTH=0.25MM SIGNAL_MODEL=EMPTY
59 52 IN AUD LO2 R P 1 2 59 AUD_RAMP_RINC_N 1 2 59 AUD_RAMP_RIN_N 54 IN AUD_SPKRAMP_WIN_SHDN_L 22 STDNR* SSM3302 X5R
603 AUD_RAMP_OUTNR 4
DLY5ATN111SQ2
SYM VER-2 3 CRITICAL
0402
10%
LFCSP
OUTR+
28 55 IN 1 C6423
16V 29 1000PF
CERM 5%
402 55 AUD_RAMP_MONO 16 MONO 55 AUD_RAMP_OUTPR 1 2 25V
2 NP0-C0G
IN IN
L6402 C6410 26
C6414 402
FERR-1000-OHM 4700PF WOOFERS & TWEETERS ON UNDER MAC OS OUTR- 27 0.22UF AUD_RAMP_OUTNR 55 AUD_SPKR_RWFR_OUT_N 57 59
OUT OUT
1 2 1 2 9 STDNL* 1 2 MIN_LINE_WIDTH=0.6MM
59 53 52 IN AUD_LO1_R_P 59 AUD RAMP LINC P 59 AUD RAMP LIN P 54 IN AUD SPKRAMP MAC SHDN L AUD RAMP BOOTRN MIN_NECK_WIDTH=0.25MM
0402
5% BOOTR- 25 MIN_NECK_WIDTH=0.15MM 20%
50V 11 INL+ 25V
NPO-C0G X5R
805 12 INL- EDGE 10 AUD_RAMP_EDGE 55
603
IN
L6403 C6411 C6415
FERR-1000-OHM 4700PF BOOTL+ 1 0.22UF SIGNAL_MODEL=EMPTY
59 53 52 AUD LO1 R N 1 2 59 AUD_RAMP_LINC_N 1 2 59 AUD_RAMP_LIN_N 55 AUD_RAMP_GAIN 21 GAIN AUD_RAMP_BOOTLP 1 2 CRITICAL
IN IN
C 0402
5%
50V OUTL+
2
3
25V
AUD_RAMP_OUTPL
L6407
110-OHM-3A
AUD_SPKR_RTWT_OUT_P
SIGNAL_MODEL=EMPTY
OUT 57 59 C
NPO-C0G X5R DLY5ATN111SQ2 CRITICAL
805 AUD RAMP AVDD 8 VREG/AVDD 603 4 SYM VER-2 3
55
MIN NECK WIDTH=0.15MM 4
1 C6424
VOLTAGE=5V 1000PF
OUTL- 5 5%
1 2 25V
2 NP0-C0G
402
58 54 52 40 6 =PP3V3_S0_AUDIO 23 REGEN BOOTL- 6 C6416
0.22UF AUD_RAMP_OUTNL AUD_SPKR_RTWT_OUT_N OUT 57 59
AUD_RAMP_BOOTLN MIN_NECK_WIDTH=0.25MM
NC MIN_NECK_WIDTH=0.15MM
13 20%
NC NC 25V
C6417 1 14 X5R
603
2.2UF AGND PGND 15
20%
10V THRM PAD CRITICAL CRITICAL
X5R-CERM 2
402
C6420 1 C6422 1
7
24
41
31
32
33
38
39
40
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
1000PF 1000PF
5% 5%
25V 25V
NP0-C0G 2 NP0-C0G 2
PINS 14 & 15 ARE TEST PINS AND 402 402
SHOULD BE TIED TO GND

CRITICAL CRITICAL
SIGNAL_MODEL=EMPTY 1 C6419 1 C6421 SIGNAL_MODEL=EMPTY
1000PF 1000PF
5% 5%
25V
2 NP0-C0G 2 25V
NP0-C0G
402 402
B B
GAIN R6406 R6407

+9 DB NOSTUFF 0 OHM
EDGE RATE +12 DB NOSTUFF NOSTUFF
CONTROL R6404 R6405 AUD_RAMP_MONO NET: +15 DB 0 OHM NOSTUFF
ON 0 OHM NOSTUFF HIGH = MONO OPERATION +18 DB NOSTUFF 47 KOHM
OFF NOSTUFF 0 OHM LOW = STEREO OPERATION +24 DB 47 KOHM NOSTUFF
55 AUD_RAMP_AVDD
NOSTUFF
1 1
R6404 R6406
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402
AUD_RAMP_EDGE OUT 55 AUD_RAMP_MONO OUT 55 AUD_RAMP_GAIN OUT 55
NOSTUFF
1 1 1
R6405 R6403 R6407
0 0 0
A 5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF SYNC MASTER=D7 BREECE SYNC DATE=01/03/2012 A
2 402 2 402 2 402 PAGE TITLE
AUDIO: RIGHT SPKR AMP

DRAWING NUMBER SIZE

REVISION
R
4.2.0
64 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
58 52 PP4V5 AUDIO ANALOG
56 6 =PP3V3 S0 AUDIO DIG
CRITICAL
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=10.63KHZ
MIKEY RECEIVER
WRITE: 0X72 READ: 0X73
CKT
APN 353S2640
I2C ADDRESSES
MIKEY
MIKEY
U6751
U6751
READ
WRITE
0111
0111
0011
0010
0X73
0X72
R65621 C6555 1 1 C6560 CHS U6750 READ 0111 0111 0X77
10K 4.7UF 0.1UF
5% 20% 10% MIKEY 1A CHS U6750 WRITE 0111 0110 0X76
1/20W 10V 16V
X5R-CERM 2 2 X7R-CERM
MF 0402 402 APN:353S2640
201 2
MIKEY ADDRESS: WRITE=72H, READ=73H
AUDIO JACK: HP CONNECTOR WITH MIKEY
PLACE XWS 6500 & 6501 AT J6500 PINS
14
15
CRITICAL
D AVDD
U6551
D
I2C PULLUPS ON SOUTHBRIDGE PAGE CD3285A0
MQFN-RSV
47 =I2C MIKEY SCL 3 SCL MICBIAS 10 HS MIC BIAS 56
IN OUT
2 11 HS_SW_DET MIN_NECK_WIDTH=0.20MM
47 BI =I2C_MIKEY_SDA SDA DETECT
20 AUD I2C INT L 4 INT* BYPASS 9 HS RX BP

OUT
1 SIGNAL_MODEL=EMPTY
26 IN AUD IPHS SWITCH EN ENABLE
R65541 L6500
HS HDET 13 HDET 1K
NOSTUFF 5%
FERR-1000-OHM CRITICAL
1/16W
R6561 16 CS MF-LF 58 OUT AUD_TYPEDET_R 1 2 L6507
47K 1 C6556 402 2 0402 FERR-120-OHM-2.0A
58 IN AUD PORTD DET L 1 2
R65551 DGND AGND 0.01UF 1 2 MAX97220_OUTL
5% 100K 10%
2 25V
L6501 MIN_LINE_WIDTH=0.25MM
IN 53
5
6
7
8
12
1/16W 0402
MF-LF
5%
1/20W
X7R FERR-1000-OHM SIGNAL_MODEL=EMPTY
402 402
MF
201 2 59 56 OUT AUD_HS_MIC_N 1 2
J6500 L6508
0402 54722-0224 FERR-1000-OHM
F-ST-SM 1 2 AUD HP PORT REF
59 58 56 52 GND AUDIO CODEC L6502 AUD J1 TYPEDET R 1 2 AUD J1 HP OUTL 0402
OUT 53
FERR-1000-OHM
59 AUD J1 MIC N 3 4 AUD J1 HP PORT REF CRITICAL
AUD_HS_MIC_P 1 2
59 56 OUT
0402
59 AUD J1 MIC P 5 6 AUD J1 HP OUTR L6509
7 8 FERR-120-OHM-2.0A
CRITICAL 9 10 1 2
C6552 R6550 L6503 11 12 MIN_LINE_WIDTH=0.25MM
MAX97220 OUTR IN 53
0.1UF 2.2K 2 FERR-120-OHM-2.0A MIN_NECK_WIDTH=0.20MM 0402

2 1 59 AUD_HS_MIC_RC_P 1 13 14
OUT AUD_MIC_INL_P AUD_HS_MIC_P AUD_J1_MIC_BIAS
59 52
5%
IN 56 59
56 IN HS MIC BIAS 1 2
15 16 L6510
10% CRITICAL 1/16W CRITICAL 0402 MIN_LINE_WIDTH=0.25MM
FERR-1000-OHM
16V
C X7R-CERM R65561 1 C6550
MF-LF
402 1 C6558 CRITICAL
AUD J1 PP3V3 S0 17 18 =I2C CHS SCL IN 47
1 2 AUD TIPDET1 R OUT 58 C
402 100K 0.0082UF 27PF =I2C CHS SDA 19 20 AUD SPDIF OUT
5% 10% 5% L6504 47 IN
AUD J1 TIPDET2 R 21 22 AUD J1 TIPDET1 R
IN 52 92
0402
1/20W 25V 50V FERR-120-OHM-2.0A
C6553 MF
201 2
2 X7R
402 R6551
2 CERM
402 1 2
0.1UF 0 56 6 =PP3V3 S0 AUDIO DIG
2 1 0402 MIN_LINE_WIDTH=0.25MM
59 52 OUT AUD MIC INL N 59 AUD HS MIC RC N 1 2 AUD HS MIC N IN 56 59 MIN_NECK_WIDTH=0.20MM
5%
10%
16V
1/16W
MF-LF
L6505
X7R-CERM 402 FERR-1000-OHM
402
R/C6750 FILTER TO ADDRESS OUT-OF-BAND 58 AUD TIPDET2 R 1 2
OUT
NOISE ISSUE SEEN ON EARLY HEADSETS 0402
(SEE RADAR # 6210118)
NOSTUFF
SIGNAL_MODEL=EMPTY
R65531 R6506
1K 1
0 2
5% 59 58 56 52 IN GND AUDIO CODEC AUD J1 GND ANALOG
1/16W MIN_LINE_WIDTH=0.50MM
MF-LF 5% MIN_NECK_WIDTH=0.20MM
402 2 1/16W VOLTAGE=0V
MF-LF
402
59 58 56 52 GND AUDIO CODEC
B B

PAGE TITLE
AUDIO: Jack, Mikey, CHS Switch

DRAWING NUMBER SIZE

REVISION
R
4.2.0
65 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPEAKER CABLE CONNECTORS
APPLE P/N 998-4119 APPLE P/N 998-4119
CRITICAL CRITICAL
J6603 J6602
504050-0691 504050-0691
M-RT-SM M-RT-SM
7 7
WOOFER (BL) WOOFER (BR)
59 54 AUD_SPKR_LWFR_OUT_P 1 59 55 AUD_SPKR_RWFR_OUT_P 1
IN IN
59 54 AUD SPKR LWFR OUT N 2 59 55 AUD SPKR RWFR OUT N 2
D 59
IN
OUT AUD SPKR VENDOR ID L
3 59
IN
OUT AUD SPKR VENDOR ID R
3 D
4 4
59 54 IN AUD_SPKR_LTWT_OUT_P 5 59 55 IN AUD_SPKR_RTWT_OUT_P 5
59 54 AUD_SPKR_LTWT_OUT_N 6 59 55 AUD_SPKR_RTWT_OUT_N 6
IN IN
TWEETER (FL) 8
TWEETER (FR) 8
C C
B B

PAGE TITLE
Audio: Spkr/Mic Conn.

DRAWING NUMBER SIZE

REVISION
R
4.2.0
66 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IPHS HS Detect Debounce CKT

55 54 52 40 6 =PP3V3_S0_AUDIO
R67441
100K
5%
1/20W
MF
201 2 R6745
0
D
AUD IP PERPH DET DB 1
5%
2 AUD IP PERIPHERAL DET
OUT 20
D
1/16W
D 3 MF-LF
Q6741 402
SSM6N15AFE
SOT563
L6743 NC
FERR-1000-OHM
AUD_J1_DET_RC 1 2 AUD IP PERPH DET R 5 G S 4
58 IN
0402
Q6741 D 6
SSM6N15AFE
AUDIO CONNECTOR DETECT STATES SOT563
NOSTUFF
1 C6741 NOTHING SPDIF HEADPHONE
0.1UF 2 G S 1
10%
16V
AUD_J1_TYPEDET_R 1 1 0
2 X5R
402
AUD_J1_TIPDET_R 0 1 1
AUD_OUTJACK_INSERT_L 1 0 0
AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV
PORT D DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE)

59 58 52 OUT AUD_SENSE_A
C 1
C
R6795 1
R6796
58 56 52 PP4V5_AUDIO_ANALOG
1%
5.11K
1%
20.0K LI Insert Detect
1
1/16W
MF-LF
2 402
1/16W
MF LF
2 402
(DETECT A)
R6742
47K 59 58 52 IN AUD SENSE A
5% 1 AUD_PORTD_DET_L OUT 56 AUD_PORTB_DET_L NC
1/20W
MF 1
201 2
S R6743
47K
AUD_TIPDET1_R
SOT-563-HF
NTZD3152P
5%
1/20W
Q6796 D 3 Q6796 D 6
56 IN 2 MF SSM6N15AFE SSM6N15AFE 1
R6731
G Q6740 201 2 SOT563 SOT563
R67411 1%
39.2K
47K D 1/16W
5% 4 MF-LF
1/20W 6 5 G S 4 2 G S 1 2 402
MF
201 2
S AUD_J1_DET_RC OUT 58
AUD_OUTJACK_INSERT_L AUD_PORTA_DET_L NC
SOT-563-HF
56 IN AUD_TIPDET2_R NTZD3152P
5
G Q6740 APN:376S1032 TBT/DP Audio Enable
Q6797 D 3 Q6800 D 3
D SSM6N15AFE Q6797 D 6 SSM6N15AFE
3 SOT563 SOT563
SSM6N15AFE
SOT563 L6732
FERR-1000-OHM
R6792 5 G S 4 DP_GPU_TBT_SEL 1 2 AUD_LI_TIPDET 5 G S 4
82 21 IN
47K 2 G S 1 0402
AUD_TIPDET_INV 1 2
5%
1/16W R67301
R67911 MF LF AUD_OUTJACK_INSERT 10K
B 100K
5%
402 1
C6791
0.1UF
5%
1/20W
MF
B
1/20W 20% 10V 201 2
MF 2 CERM 402
201 2
59 58 56 52 GND_AUDIO_CODEC
59 58 56 52 GND_AUDIO_CODEC
PLACE C6700 CLOSE TO Q6700 PIN 4

58 56 52 PP4V5_AUDIO_ANALOG
C6700 1
0.1UF
10%
16V
R67011 1
R6703
X7R-CERM 2 270K 100K
402 5% 5%
1/20W
MF
Q6700 1/20W
201 2 DMC2400UV MF
4
59 58 56 52 GND_AUDIO_CODEC SOT563 2 201
AUD_TYPEDET_OD_INV
S
56 IN AUD TYPEDET R
P-CHN
5
6
D
D
Q6700
3
N-CHN
A AUD TYPEDET OD 2 G DMC2400UV

SOT563
SYNC MASTER=D7 BREECE SYNC DATE=01/03/2012 A
PAGE TITLE
S
AUDIO: Detects/Grounding
R67021 DRAWING NUMBER SIZE
100K 1 051-9509 D
5%
1/20W Apple Inc. REVISION
MF R
201 2 4.2.0
59 58 56 52 GND_AUDIO_CODEC NOTICE OF PROPRIETARY PROPERTY: BRANCH
67 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX MAC SHDN WIN SHDN DET ASSIGNMENT AUDIO * 0 1 MM ? AUDIODIFF * Y 0 1 MM 0 1 MM 10 MM 0 1 MM 0 1 MM
HP/LINE OUT 0X03 (3) 0X03 (3) 0X0A (10,D) GPIO_2 GPIO_2 0X0A (DET D)
SPKROUT * 0 2 MM ? SPKROUTDIFF * Y 0 6 MM 0 25 MM 10 MM 0 2 MM 0 2 MM
PRIMARY SPKRS (WFR) 0X04 (4) 0X04 (4) 0X0B (11) MICBIAS GPIO_3 N/A
SECONDARY SPKRS (TWT) 0X03 (3) 0X03 (3) 0X0A (10,V24) MICBIAS N/A N/A
SPDIF OUT N/A 0X08 (8) 0x10 (16) N/A N/A 0X0D (DET B) NET TYPE
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
ELECTRICAL CONSTRAINT SET PHYSICAL SPACING
AUDIODIFF * AUDIODIFF
CODEC INPUT SIGNAL PATHS
SPKROUTDIFF * SPKROUTDIFF
FUNCTION CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT AUD LO1 L P 52 53 54
D SPDIF IN
INTERNAL MIC ARRAY
0X07
0X06
(7)
(6)
0x0F
0X0E
(15)
(14,LEFT & RIGHT)
N/A
N/A
0X09 (DET A)
N/A
I215
I216
AUDIO DIFFPAIR
AUDIO DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIO
AUDIO AUD LO1 L N 52 53 54 D

0X05 (5) 0X12 (18,LEFT) I217 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 L C P 53
EXTERNAL MIC 0X06 (6) 0X0D (13,V22,B,LEFT) PANTHER POINT GPIO 16 PANTHER POINT GPIO 5 (RCVR INT) I218 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 L C N 53
PANTHER POINT GPIO 3 (PERIPH DET)
I211 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 R P 52 53 55
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 R N 52 53 55

I212
OTHER DETECT AUD LO1 R C P
I210 AUDIO DIFFPAIR AUDIODIFF AUDIO 53
FUNCTION CONVERTER PIN COMPLEX ENABLE/CONTROL DET ASSIGNMENT I209 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO1 R C N 53
MULTIPLE SPKR VENDORS N/A N/A N/A 0X0C (DET C) I208 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 L P 52 54
I206 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 L N 52 54
I207 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 R P 52 55
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LO2 R N 52 55

I204
I205 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LINC P 55
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LINC N 55

I203
I220 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP RINC P 55
I219 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP RINC N 55
AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LIN P 55

I222
I221 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP LIN N 55
I224 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP RIN P 55
I223 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD RAMP RIN N 55

59 52 6 =PP5V S0 AUDIO
I226 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP LINC P 54
I225 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP LINC N 54

SPEAKERID SPEAKERID
I227 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RINC P 54
R68101 1
R6811 I229 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RINC N 54
100K 100K AUD LAMP LIN P
1% 1% I228 AUDIO DIFFPAIR AUDIODIFF AUDIO 54
1/16W 1/16W
MF-LF MF-LF I230 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP LIN N 54
402 2 2 402
I264 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RIN P 54
C 57 IN AUD_SPKR_VENDOR_ID_L AUD_SPKR_VENDOR_ID_R IN 57 I263 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD LAMP RIN N 54
C
R68121 1
R6813
100K 100K
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402 PORT C DETECT(SPEAKER MISMATCH)
SPEAKERID SPEAKERID
58 52 OUT AUD_SENSE_A I236 AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INL P 53
AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INL N 53

I238
SPEAKERID
I237 AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INR P 53
R6816 SPEAKERID I239 AUDIO DIFFPAIR AUDIODIFF AUDIO MAX97220 INR N 53
100K 2
1
R68941 I240 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR RWFR OUT P 55 57
1% 10K I241 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR RWFR OUT N 55 57
1/16W 1%
MF-LF 1/16W I242 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR RTWT OUT P 55 57
402 MF-LF
402 2 I243 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR RTWT OUT N 55 57
I244 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LWFR OUT P 54 57
59 52 6 =PP5V S0 AUDIO I246 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LWFR OUT N 54 57
SPEAKERID I245 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LTWT OUT P 54 57
NC AUD_PORTC_DET_L
1 C6810 I247 SPKROUT DIFFPAIR SPKROUTDIFF SPKROUT AUD SPKR LTWT OUT N 54 57
0.1UF
10%
16V
2 X7R-CERM
402 AUD MIC INL P
I326 AUDIO DIFFPAIR AUDIODIFF AUDIO 52 56
Q6800 D 6
I327 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD MIC INL N 52 56
SSM6N15AFE I328 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD HS MIC RC P 56
SPEAKERID SOT563
CRITICAL I329 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD HS MIC RC N 56
SPEAKERID
U6800 SPEAKERID
L6802 I254 AUDIO DIFFPAIR AUDIODIFF AUDIO AUD HS MIC P 56
MAX9119_POS 3 5 MAX9119EXK-T R6820 FERR-1000-OHM 2 G S 1 AUD HS MIC N 56
B SC70-5
1 MAX9119 OUT 1
33 2 SPKR_MATCH_DRV_R 1 2 SPKR_MATCH_DRV
I255
I324
AUDIO DIFFPAIR
AUDIO DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIO
AUDIO AUD J1 MIC P 56 B

AUDIO DIFFPAIR AUDIODIFF AUDIO AUD J1 MIC N 56
5% 0402 I325
MAX9119 NEG 4 1/16W
2 MF-LF
402
59 52 6 =PP5V_S0_AUDIO
SPEAKERID
R68141
226K 58 56 52 GND_AUDIO_CODEC
1%
1/16W
MF-LF
402 2 SPEAKERID
R6817
37.4K2
1
1%
SPEAKERID 1/16W
SPEAKERID MF-LF
R68151 1 C6811
402
75K 2.2UF
1% 10%
1/16W 16V
MF-LF 2 X7R-CERM
402 2 805

PAGE TITLE
AUDIO: Speaker ID
DRAWING NUMBER SIZE

REVISION
R
4.2.0
68 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S5 Soft Enable S4 Enables S4 USB Enable

70 61 6 =PP12V_S5_PWRCTL 78 70 61 60 6 =PP3V3_S5_PWRCTL R6920
0
67 60 PM_PGOOD_REG_P5V_S4 1 2 PM_EN_USB_PWR 42 43
IN OUT
1 5%
R6990 1 C6900 1/16W
68K 0.1UF MF-LF NOSTUFF
5% 402
1/16W Note: 10% 1 C6920
16V
MF-LF 2 X5R 0.47UF
2 402 Halt power sequencing at S5
D PM_EN_REG_P3V3_S5 OUT 67
if there is no processor.
402 10%
6.3V
2 CERM-X5R
402
D
Remove Q6900 to circumvent
PLACE_SIDE=BOTTOM
1 or short gate to source.
R6991 14 74LVC08
33K 44 33 19 15 PM SLP S5 L 1 TSSOP-HF
IN
5% 3
1/16W U6900 PM EN S4
MF-LF 2
2 402 78 70 61 60 6 =PP3V3_S5_PWRCTL 08
1 1
7 R6910 R6911
R69001 R69011 33
5% 5%
33
S3 VDDQ Enable
100K 10K 1/16W 1/16W
5% 5% MF-LF MF-LF
1/16W 1/16W 2 402 2 402
MF-LF MF-LF
402 2 402 2
PM_EN_REG_P5V_S4 OUT 67 78 70 61 60 6 =PP3V3_S5_PWRCTL
CPU SKTOCC
PM EN FET P3V3 S4 OUT 70
D 3 PLACE_SIDE=BOTTOM 14 74LVC08
NOSTUFF NOSTUFF 4 TSSOP-HF
Q6900 1 1 44 19 15 IN PM_SLP_S4_L
C6910 C6911 6
S0 Enables SSM3K15AMFVAPE
VESM
0.47UF
10% 10%
0.47UF
67 60 IN PM_PGOOD_REG_P5V_S4 5
U6900
08
PM_EN_REG_VDDQ_S3 OUT 68
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
402 402 7
1 G S 2
78 70 61 60 6 =PP3V3_S5_PWRCTL 11 IN CPU_SKTOCC_L
tau (RC delay, ms): 0.0 0.0

14 74LVC08
45 44 38 28 19 15 PM_SLP_S3_L 10 TSSOP-HF
IN
8 PM_EN_FET_P12V_S0
U6900 OUT 70
68 PM_PGOOD_REG_VDDQ_S3 9 08
IN
7
C C
28 IN MEMVTT_EN PM_EN_LDO_DDRVTT S0 OUT 68

MAKE_BASE=TRUE
78 70 61 60 6 =PP3V3_S5_PWRCTL
R69021
33K
5%
1/16W
MF-LF
402 2
14 74LVC08
PU_U6900 13 TSSOP-HF R6930
11 100
PM_EN_S0_R 1 2 PM_EN_FET_P5V_S0
U6900 MAKE_BASE=TRUE OUT 70
70 IN PM_PGOOD_FET_P12V_S0 12 08 5% R6931
1/16W =TBT_S0_EN OUT 84 85 0
7
MF-LF 70 IN PM_PGOOD_FET_P5V_S0 1 2 PM_EN_FET_P3V3_S0 OUT 41 70
402
NOSTUFF 5%
1/16W
C6901 1 MF-LF
402
0.47UF
10%
6.3V
CERM-X5R 2
402
R6932 R6937
0 0
70 60 PM_PGOOD_FET_P3V3_S0 1 2 PM_EN_REG_P1V8_S0 68 70 60 PM_PGOOD_FET_P3V3_S0 1 2 PM_EN_REG_GPUCORE_S0 80
IN OUT IN OUT
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
B
402 402
R6933 R6938
0 0
68 IN PM_PGOOD_REG_P1V8_S0 1 2 PM_EN_FET_VDDQ_S0 OUT 70
GPU Sequencing 80 IN PM_PGOOD_REG_GPUCORE_S0 1 2 PM_EN_REG_GPU_VDDQ_S0 OUT 74
MAKE_BASE=TRUE
5% 5%
1/16W =PM EN REG P1V2 S0 OUT 40 1/16W
MF-LF MF-LF
402 402
R6934 R6939
0 0
PM_PGOOD_FET_VDDQ_S0 1 2 PM_EN_REG_P1V05_S0 74 IN PM_PGOOD_REG_GPU_VDDQ_S0 1 2 PM_EN_REG_GPU_P1V05_S0 OUT 74
CPU/PCH Sequencing 70 28 IN OUT 65
5%
5% 1/16W
1/16W MF-LF
MF-LF 402
402
R6935
0
65 IN PM_PGOOD_REG_P1V05_S0 1 2 PM_EN_REG_VCCSA_S0 OUT 66
5%
1/16W
MF-LF
402
R6936
0
66 61 IN PM_PGOOD_REG_VCCSA_S0 1 2 PM_EN_REG_CPUCORE_S0 OUT 62
5%
1/16W
MF-LF
402
Rail definitions
Platform: All processor non-Core and non-Graphics (5 V, 3.3 V, 1.8 V 1.5 V, PCH Core/PLL/VRM)
Uncore: VccSA, VDDQ, VccA (1.8 V), VccIO (VccSA, VccA, and VccIO must ramp within 50 ms of each other)
Notes on sequencing requirements

A Intel: SYNC MASTER=D7 NICK SYNC DATE=12/13/2011 A
PAGE TITLE
1. No hard specification on platform rails
2. SMC guarantees timing on PCH DPWROK and PWROK PM Regulator Enables
DRAWING NUMBER SIZE
NVIDIA:
1. 3V3_S0 must ramp first REVISION
R
2. IFPA/B_IOVDD (1.8 V) can ramp simultaneously or after 3V3_S0 (unused) 4.2.0
3. NVVDD (GPU_CORE) must ramp after IFPA/B_IOVDD NOTICE OF PROPRIETARY PROPERTY: BRANCH
4. VDDQ must ramp after CPU_CORE THE INFORMATION CONTAINED HEREIN IS THE
5. PEX_VDD with IFPC/D/E/F_IOVDD (1.05V) must ramp after VDDQ PROPRIETARY PROPERTY OF APPLE INC.
6. All rails must reach their target voltages in more than 40 uS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
69 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform and UnCore Power Good Derive SMC ALL_SYS_PWRGD Resume Reset
Note: GPU power goods are implicitly included because the power goods for VDDQ, DPVDDC, and GPU Core are wired-or together Intel Doc# 29517 Maho Bay PDG, Section 22.13
Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8
Note:
The iMac K70K72 designs does not support Deep Sx modes so both DPWROK and
RSMRST# signals are shorted together
D Requirements:
D
Power on:
Asserted at least 10 ms after all suspend well power is valid
Power off or loss of AC:
Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V
to allow PCH to switch suspend well to battery without excessive loading
78 70 61 60 6 =PP3V3 S5 PWRCTL Primary method:

The SMC guarantees proper assertion and de-assertion of RSMRST# for
normal operation.
1 C7000
0.1UF SMC de-asserts RSMRST# (PM_DSW_PWRGD) when S5_PWRGD input is asserted and
10% SMC_S5_PWRGD_VIN input is above comparator input level of 1.5 V.
16V
2 X5R
402
SMC asserts RSMRST# (PM_DSW_PWRGD) when SMC_S5_PWRGD_VIN input drops from
1.8 V to 1.5 V (as implemented) when 12 V S5 rail drops to 10 V.
PLACE_SIDE=BOTTOM 70 60 6 =PP12V_S5_PWRCTL
14 74LVC08 RSMRST:SMC
74 PM PGOOD REG P1V05 GPU 4 TSSOP-HF To SMC, for 99ms delay 1
IN R7030
6 ALL_SYS_PWRGD
U7000 OUT 5 44
68K
66 60 PM_PGOOD_REG_VCCSA_S0 5 08 5%
IN 1/16W
MF-LF
7 2 402 To SMC
SMC_S5_PWRGD_VIN OUT 44
RSMRST:SMC
1
R7031
C 5%
33K
1/16W
C
MF-LF
2 402
To SMC
67 61 IN PM_PGOOD REG_P3V3_S5 S5_PWRGD OUT 44
MAKE_BASE=TRUE
RSMRST:SMC
From SMC R7032 To PCH

0
61 45 44 IN PM_DSW_PWRGD 1 2 PM_RSMRST_PCH_L OUT 19 61
5%
1/16W
MF-LF
402
PCH Power Goods
NOSTUFF
R7022
0
1 2 Secondary method:
5% The SMC guarantees proper assertion and de-assertion of RSMRST# for
1/16W
MF-LF normal operation via PM_DSW_PWRGD.
402
B RSMRST# is asserted when power good from regulator is de-asserted in the

event AC is lost. Power good de-assertion should happen quickly enough
B
78 70 61 60 6 =PP3V3 S5 PWRCTL
to meet Intel spec.
PLACE_SIDE=BOTTOM
14 74LVC08
62 25 IN PM_PGOOD_REG_CPUCORE_S0 13 TSSOP-HF R7020 To PCH
11 0
SYS_PWROK_R 1 2 PM_PCH_SYS_PWROK
12
U7000 OUT 19 45
08 5% Third
1/16W NOSTUFF
MF-LF
7 402 1
R7023
0 78 70 61 60 6 =PP3V3_S5_PWRCTL
5%
1/16W
MF-LF
R7021 2 402 R7024 To PCH PLACE_SIDE=BOTTOM
0 1K From SMC RSMRST:GATE
45 44 36 IN SMC_DELAYED_PWRGD 1 2 1 2 PM_PCH_PWROK OUT 19 26 74LVC08
14
5% 5% 61 45 44 IN PM_DSW_PWRGD 1 TSSOP-HF R7035 To PCH
1/16W 1/16W Second 0
MF-LF MF-LF 3 PM_RSMRST_PCH_L_R 1 2 PM_RSMRST_PCH_L
402 To PCH 402 U7000 OUT 19 61
1 C7021 67 61 PM_PGOOD_REG_P3V3_S5 2 08 5%
PM_PCH APWROK IN 1/16W
19
MAKE_BASE=TRUE OUT 0.1UF MF-LF
First 10% 7 402
2 16V
X5R
=CAM RESET L 402
OUT 40

PAGE TITLE
PM Power Good
DRAWING NUMBER SIZE

REVISION
R
4.2.0
70 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
6 =PP5V_S0_REG_CPUCORE_S0
Pull-ups 1 Pull-ups 2
1
R7100
CPU Core S0 Regulator CPU AXG S0 Regulator 16 13 11 10 6 =PPVCCIO_S0_CPU
5%
2.2
96 62 REG_VCC_U7100
1/8W
Max avg current: ? A (design)/ 41.05 A (budget) Max avg current: ? A (design)/ 10 A (budget) C7117 1 NOSTUFF MF-LF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
Max peak current: ? A (design)/75.05 A (budget) Max peak current: ? A (design)/ 30 A (budget) 0.1UF 1 1 1 2 805 1 1 1 1 1
10% R7117 R7118 R7119 96 62 REG_VCC_U7100 R7120 R7121 R7122 R7123 R7124
OC trip point: ? A (nom)/? A (min) OC trip point: ? A (nom)/? A (min) 16V 2
X5R 1%
54.9
1%
90.9
1%
110
5%
0 0
5% 5%
0
5%
0
5%
0
402
Switching freq: 290 kHz Switching freq: 290 kHz 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1 C7100 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
AGND_CPU 10UF
96 64 63 62
2 402 2 402 2 402 10% 2 402 2 402 2 402 2 402 2 402
25V
2 X5R
Core compensation and feedback AXG compensation and feedback 96 62 13 CPU_VIDSCLK 805 96 62 REG_PWM_CPUAXG_R
96 62 13 CPU VIDALERT L 96 62 REG PWM CPUCORE 1 R
REG_CPUCORE_COMP REG_CPUAXG_COMP
D
35
D 96 62 96 62
96 62 13 CPU VIDSOUT 96 62
96 62
REG PWM CPUCORE 2 R
REG_PWM_CPUCORE_3_R
VCC
1 C7131 1 C7130 1 C7161 1 C7160 62 REG_PWM_CPUCORE_4_R
5%
82PF
10%
0.0012UF
5%
39PF
10%
0.001UF U7100
2 50V
CERM 2 50V
CERM
50V
2 CERM 2 50V
X7R-CERM ISL6364
402 402 402 0402
23 QFN 96
R7125 0
96 62 REG_CPUAXG_TM TMS PWMS 26 62 REG_PWM_CPUAXG_R 1 2 REG_PWM_CPUAXG OUT 64 96 (pu 2)
CPUCORE_COMP_RC 96 CPUAXG_COMP_RC 96
20 ISENS+ 24 REG_ISENAXG_PR IN 64 96 5% MF-LF
(axg vsen in) 96 62 REG CPUAXG VSEN VSENS 1/16W 402
1
R7130 1
R7160 ISENS- 25 REG_ISENAXG_NR IN 64 96
4.99K 8.06K (axg hf comp) REG_CPUAXG_HFCOMP 16 HFCOMPS/DVCS 0

1% 1%
96 62
PWM1 38
96
62 REG_PWM_CPUCORE_1_R R7126 1 2 REG_PWM_CPUCORE_1 OUT 63 96 (pu 2)
1/16W 1/16W 19
MF-LF MF-LF (axg fb in) 96 62 REG_CPUAXG_FB FBS ISEN1+ 46 REG_ISENCORE_1_P IN 63 96 5% MF-LF
To Core feedback To AXG feedback 1/16W 402
2 402 2 402
ISEN1- 45 REG_ISENCORE_1_NR
96 62 REG CPUAXG RGND 21 RGNDS
IN 63 96
REG_CPUCORE_FB REG_CPUAXG_FB 0
62 96 62 96
PWM2 36
96
62 REG PWM CPUCORE 2 R R7127 1 2 REG PWM CPUCORE 2 OUT 63 96 (pu 2)
(axg comp out) 96 62 REG_CPUAXG_COMP 18 COMPS
1
R7131 1 C7133 1
R7161 1 C7163 ISEN2+ 42 REG_ISENCORE_2_P IN 63 96 5% MF-LF
1/16W 402
1.21K 390PF 2.0K 390PF (pgood) 62 REG_CPUCORE_PGOOD 13 VR_RDY ISEN2- 41 REG_ISENCORE_2_NR 63 96
10% 10% IN
1% 50V 1% 50V
1/16W 2 CERM 1/16W 2 CERM 30 BTS_DES_TCOMPS 96
R7128 0
MF-LF 402 MF-LF 402 (straps 1) 96 62 REG CPUAXG TCOMP PWM3 39 62 REG PWM CPUCORE 3 R 1 2 REG PWM CPUCORE 3 OUT 63 96 (pu 2)
2 402 2 402 (straps 1) 96 62 REG_CPUCORE_SUTH 29 BT_FDVID_TCOMP ISEN3+ 48 REG_ISENCORE_3_P 63 96 5% MF-LF
CPUCORE_FB_R_1 CPUCORE_FB_RC CPUAXG_FB_R_1 CPUAXG_FB_RC IN 1/16W 402
96 96 96 96
(straps 1) 96 62 REG_CPUCORE_NPSI 28 NPSI_DE_IMAX ISEN3- 47 REG_ISENCORE_3_NR 63 96
IN
1 1 1 1 REG_CPUCORE_FDVID 27 ADDR_IMAXS_TMAX
R7132 R7133 R7162 R7163 (straps 1) 96 62
PWM4 37 REG PWM CPUCORE 4 R 62 (pu 2)
499 249 301 249 (pu 1) 96 62 13 CPU_VIDSCLK 12 SVCLK
IN
1% 1% 1% 1% 11 SVALERT* ISEN4+ 44 NC
1/16W 1/16W 1/16W 1/16W (pu 1) 96 62 13 OUT CPU_VIDALERT_L
MF-LF MF-LF MF-LF MF-LF 10 SVDATA ISEN4- 43 NC
(pu 1) CPU_VIDSOUT
2 402 2 402 2 402 2 402 96 62 13 BI
(core vsen in) 96 62 REG_CPUCORE_VSEN 4 VSEN FSS_DRPS 22 REG_CPUAXG_SW_FREQ 62 96 (straps 2)

96 CPUCORE FB R 2 96 CPUAXG FB R 2
REG CPUCORE RGND 3 RGND VR_RDYS 17 REG CPUAXG PGOOD (pgood)
C7134 To Core PSI comp
96 62 62
R7134 7
C 0.0033UF
1 2 96 CPUCORE_PSICOMP_RC 1
100
2 REG_CPUCORE_PSICOMP 62 96
(core fb in) 96
(core psi comp)

62
62
96
REG_CPUCORE_FB
REG_CPUCORE_PSICOMP 6
FB
PSICOMP
IMONS 14 REG_CPUAXG_IMON 48 62
96
(axg imon out)
PP12V_S0_CPUCORE_FLT 62 63 64 96
C
10%
1%
5 FS_DRP 34 REG_CPUCORE_SW_FREQ 62 96 (straps 2) 1
50V
1/16W (core hf comp) 96 62 REG CPUCORE HFCOMP HFCOMP R7197
MF-LF
CERM
402
402
8 RAMP_ADJ 2 REG_CPUCORE_RAMPADJ 62 96 (straps 2) 100K
(core comp out) 62 REG_CPUCORE_COMP COMP 5%
96 1/16W
R7135 To Core VSense R7136 To Core HF comp R7165 To AXG VSense R7166 To AXG HF comp 32 SICI EN_VTT 40 PM_EN_REG_CPUCORE_S0 IN 60 MF-LF
96 REG_CPUCORE_IAUTO 2 402
10 1.74K 10 2.26K
1 2 96 62 REG_CPUCORE_VSEN 1 2 REG_CPUCORE_HFCOMP 62 96 1 2 96 62 REG_CPUAXG_VSEN 1 2 REG_CPUAXG_HFCOMP 62 96
(core imon out)96 48 REG_CPUCORE_IMON 9 IMON EN_PWR 1 96 REG_CPUCORE_EN_PWR
1% 1% 1% NOSTUFF 1% 62
1/16W
1
1/16W 1/16W
1
1/16W
15 RSET 33 REG_CPUCORE_RSET 96
1 1
MF-LF
402
C7135 MF-LF
402
MF-LF
402
C7165 MF-LF
402
(vr hot out) 62 REG_CPUCORE_VRHOT_L VR_HOT* C7195 R7195
0.01UF 0.01UF 96 62 REG CPUCORE TM 31 TM 0.1UF 2.74K
20% 20% THRM 10% 1%
16V 16V 16V
2 CERM 2 CERM PAD X5R 2 1/16W
402 402 1 1 402 MF-LF
R7109 R7116 2 402
49
AGND_CPU 62 63 64 96 AGND_CPU 62 63 64 96 0 OMIT 12.1K
5% 1% CPUCORE_EN_PWR_R 96
1/16W U7100.49:1MM 1/16W
MF-LF MF-LF
402 2 XW7100 2 402
1
R7196
SM
6.65K
Core voltage sense input Core IMON output Core temp measurement 96 64 63 62 AGND_CPU 1 2 AGND_CPU 62 63 64 96 1%
1/16W
MF-LF
OMIT 2 402
R7230.2:10MM 96 62 REG_VCC_U7100 96 62 REG_VCC_U7100
AGND_CPU 62 63 64 96
=PPVCORE_S0_CPU
XW7142 R7142
16 13 6 SM NOSTUFF
48 1K 1 1
1 2 SNS VCORE XW P 1 2
96
R7152 R7190
5% 100K 1K
1/16W 5% 5%
MF-LF 1/16W 1/16W
402 SIGNAL_MODEL=EMPTY MF-LF MF-LF
Core sense from CPU R7140 R7141 To Core voltage sense 402 2 To sense amps 402 2
Straps 1 Straps 2 96 64 63 62 PP12V S0 CPUCORE FLT
0 10
96 13 IN SNS_CPU_VCORE_P 1 2 96 SNS_VCORE_R_P 1 2 REG_CPUCORE_VSEN 62 96 REG_CPUCORE_IMON OUT 48 62 96 REG_CPUCORE_TM 62 96
96 62 REG_VCC_U7100 96 62 REG_VCC_U7100
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF 1
NOSTUFF
C7148 R71501 1 C7150
0.082UF
1 1 C7190
0.1UF
B
402 402
0.0012UF 0 10% 10% NOSTUFF NOSTUFF
10% 5% 16V RT7190 16V 1 1 1 1 1 1 1
SIGNAL_MODEL=EMPTY 50V 1/16W 2 CERM-X7R 2 X5R R7101 R7103 R7105 R7107 R7110 R7112 R7114
R7145 R7146 2 CERM MF-LF 402 402
402 2 6.8K 953K 953K 23.2K 49.9K 0 0 1.18M
0 10 402
0603 1% 1% 1% 1% 5% 5% 1%
96 13 IN SNS_CPU_VCORE_N 1 2 96 SNS_VCORE_R_N 1 2 REG CPUCORE_RGND 62 96 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/16W
96 CPUCORE IMON R 2 MF MF MF MF MF MF MF
OMIT 5% 5%
1/16W 1/16W 1 C7141 1 C7146 2 201 2 201 2 201 2 201 2 201 2 201 2 402
XW7142.2:2MM MF-LF
402
MF-LF
402 0.0012UF 0.0012UF R71511 AGND_CPU 62 63 64 96 96 62 REG_CPUAXG_TCOMP 96 62 REG_CPUAXG_SW_FREQ
XW7147 R7147
10% 10% 12.4K 96 62 REG_CPUCORE_SUTH 96 62 REG_CPUCORE_SW_FREQ
SM 2 50V
CERM 2 50V
CERM 1%
1K 402 402 1/16W 96 62 REG_CPUCORE_NPSI 96 62 REG_CPUCORE_RAMPADJ
1 2 96 SNS_VCORE_XW_N 1 2 MF-LF
402 2 96 62 REG CPUCORE FDVID
5% AGND_CPU 62 63 64 96 NOSTUFF
1/16W AGND CPU 62 63 64 96
1 1 1 1 1 1 1
MF-LF
402 R7102 R7104 R7106 R7108 R7111 R7113 R7115
255K 255K 17.8K 12.4K 105K 124K 10K
1% 1% 1% 1% 1% 1% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF MF
AXG voltage sense input AXG IMON output AXG temp measurement 2 201 2 201 2 201 2 201 2 201 2 201 2 201
AGND_CPU 62 63 64 96 AGND_CPU 62 63 64 96
OMIT
L7330.2:10MM 96 62 REG_VCC_U7100 96 62 REG_VCC_U7100
=PPVAXG S0 CPU
XW7172 R7172
17 13 6 SM NOSTUFF
48 1K
1 2 96 SNS_VAXG_XW_P 1 2
R71821 R71921 Power goods VRHot to ProcHot
5% 100K 1K R7193
1/16W 5% 5% 74 68 66 65 62 6 =PP3V3_S0_VRD 0
MF-LF 1/16W 1/16W 62 REG_CPUCORE_VRHOT_L 1 2 CPU_PROCHOT_L 11 44 45
402 OUT
SIGNAL_MODEL=EMPTY MF-LF MF-LF
AXG sense from CPU To AXG voltage sense 402 2 To sense amps 402 2 5%
R7170 R7171 1
R7199 1/16W
0 10 MF-LF
96 13 IN SNS_CPU_VAXG_P 1 2 96 SNS_VAXG_R_P 1 2 REG_CPUAXG_VSEN 62 96 REG_CPUAXG_IMON OUT 48 62 96 REG_CPUAXG_TM 62 96 10K 402
5%
5% 5% NOSTUFF 1/16W
1/16W 1/16W
R71801 1 1 C7192
A MF-LF
402
MF-LF
402
1 C7178
0.0012UF 90.9
1%
1 C7180
0.082UF
0.1UF
10%
MF-LF
SIGNAL_MODEL=EMPTY 10%
50V 1/16W 10%
16V
RT7192 16V
2 X5R 62 REG CPUAXG PGOOD PAGE TITLE
R7175
0
R7176
10
2 CERM
402
MF-LF
402 2
2 CERM-X7R
402
6.8K
0603
402 VReg CPU Core/AXG Cntl
96 13 IN SNS_CPU_VAXG_N 1 2 96 SNS_VAXG_R_N 1 2 REG_CPUAXG_RGND 62 96 DRAWING NUMBER SIZE
CPUAXG IMON R =PP3V3 S0 VRD
OMIT 5%
1/16W
5%
1/16W 1 C7171 1 C7176
96
2 74 68 66 65 62 6

XW7172.2:2MM MF-LF MF-LF 1 AGND_CPU 1
402 402 0.0012UF 0.0012UF R7181 62 63 64 96
R7198 R
REVISION
XW7177
SM R7177
10%
50V
2 CERM
10%
50V
2 CERM
15.4K
1% 5%
1K 4.2.0
1 2 SNS_VAXG_XW_N 1
1K
2 402 402 1/16W 1/16W NOTICE OF PROPRIETARY PROPERTY: BRANCH
96 MF-LF MF-LF
402 2 2 402 To XDP THE INFORMATION CONTAINED HEREIN IS THE
5% AGND_CPU 62 63 64 96 PROPRIETARY PROPERTY OF APPLE INC.
1/16W AGND_CPU 62 63 64 96 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF-LF REG_CPUCORE_PGOOD PM_PGOOD REG_CPUCORE_S0
402
62
MAKE_BASE=TRUE OUT 25 61
71 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
96 64 63 62 PP12V_S0_CPUCORE_FLT CRITICAL
Filtered 12V Rail L7200
0.36UH-28A-0.66MOHM
6 =PP12V_S0_REG_CPUCORE_S0 1 2 PP12V_S0_CPUCORE_FLT 62 63 64 96
SDP110808MR36MF-TH
96 64 63 62 PP12V_S0_CPUCORE_FLT
EMC EMC
EMC EMC
CPU Phase 1 96 REG_LVCC_U7210
Q7210.7:3MM Q7210.8:3MM
CRITICAL CRITICAL CRITICAL CRITICAL Q7210.7:3MM Q7210.8:3MM
1 1 1 C7212 1 C7213 1 C7214 1 C7215
1 C7218 1 C7219 C7210 C7211
U7210.9:3MM U7210.8:3MM U7210.7:3MM 96 REG_BOOT_CPUCORE_1_RC 270UF 270UF 10UF 10UF 1UF 1UF
1000PF 1000PF 20% 20% 20% 20% 10% 10%
D
1 C7225
1UF
1 C7226
1UF
1 C7227
1UF R72161 1 C7216
5%
25V
2 NP0-C0G
5%
25V
2 NP0-C0G
2 16V
ELEC
2 16V
ELEC
2 25V
X5R-CERM
0603
2 25V
X5R-CERM
0603
2 25V
X5R
402
2 25V
X5R
402 D
7
8
CRITICAL 8X9-TH1 8X9-TH1
7
10% 10% 10% 1 0.22UF 402 402
16V 16V 16V
2 X5R 2 X5R VCC UVCC LVCC 2 X5R 5%
1/10W
20%
25V
2 X5R D Q7210
603 603 603 IRF6802SDTRPBF
U7210 MF-LF
603 2
603
2 G DIRECTFET-SA CRITICAL
ISL6622
DFN S CRITICAL
R7210
3 GDSEL BOOT 2 96 REG_BOOT_CPUCORE_1 0.0005
NC L7210 1%
3
CRITICAL 1W
UGATE 1 96 REG UGATE CPUCORE 1 0.24UH-30A-0.38MOHM MF
0612
1 2 96 PPCPUCORE S0 SENSE 1 1 2 PPCPUCORE S0 REG 6 63
OUT
PHASE 10 96 REG_PHASE_CPUCORE_1 SDP110808M-TH 3 4
NCNC REG_ISENCORE_1_P OUT 62 96
96 62 IN REG_PWM_CPUCORE_1 4 PWM LGATE 6 96 REG_LGATE_CPUCORE_1 1 C7217 SIGNAL_MODEL=EMPTY
THRML 0.0022UF U7100.46:3MM
GND 10% 1
PAD C7221
1
2
8
7
50V
2 CERM
11
CRITICAL SIGNAL_MODEL=EMPTY 220PF
D 402 C7221.2:2MM 10%
50V
Q7211 REG_SNUBBER_CPUCORE_1
2 X7R-CERM
IRF6892STR1PBF
96
R7221 402
4 G DIRECTFET_S3C 1.02K
96 REG ISENCORE 1 N 1 2 REG ISENCORE 1 NR OUT 62 96
1 SIGNAL_MODEL=EMPTY 1%
S R7217 C7221.1:2MM 1/16W
1 1
MF-LF
5% C7220 402
1/8W 0.1UF
5
6
3
CPUCOREDRV:ISL6612 MF-LF 10%
1 2 805 16V
R7247 2 X5R
10 402
5%
1/10W AGND_CPU 62 63 64 96
MF-LF
2 603
EMC EMC
EMC EMC
CPU Phase 2
C 96 REG_LVCC_U7230
1
Q7210.5:3MM
C7238 1
Q7210.6:3MM
C7239
1
CRITICAL
C7230 1
CRITICAL
C7232 1
CRITICAL
C7233 1
Q7210.5:3MM
C7234 1
Q7210.6:3MM
C7235 C
NC
U7230.9:3MM U7230.7:3MM 96 REG_BOOT_CPUCORE_2_RC 270UF 10UF 10UF 1UF 1UF

1000PF 1000PF 20% 20% 20% 10% 10%
1 C7245 1 C7247 5% 5% 2 16V 2 25V 2 25V 2 25V 2 25V
1UF 1UF R72361 1 C7236 2 25V
NP0-C0G
25V
2 NP0-C0G ELEC X5R-CERM
0603
X5R-CERM
0603
X5R
402
X5R
402
5
6
CRITICAL 8X9-TH1
9
10% 10% 1 0.22UF 402 402

2 16V
X5R VCC UVCC LVCC 2 16V
X5R 5%
1/10W
20%
25V
2 X5R D Q7210
603 603
U7230 MF-LF 603 IRF6802SDTRPBF
603 2
ISL6622
DFN S
CRITICAL
R7230
NC L7230 1%
4
CRITICAL 1W
UGATE 1 96 REG_UGATE_CPUCORE_2 0.24UH-30A-0.38MOHM MF
0612
OMIT_TABLE 1 2 96 PPCPUCORE_S0_SENSE_2 1 2 PPCPUCORE_S0_REG 6 63
OUT
PHASE 10 96 REG_PHASE_CPUCORE_2 SDP110808M-TH 3 4
THRML 0.0022UF U7100.42:3MM
GND 10% 1
PAD C7241
1
2
8
7
2 50V
5
11
CRITICAL CERM
SIGNAL_MODEL=EMPTY 220PF
D 402 10%
C7241.2:2MM
2 50V
X7R-CERM
IRF6892STR1PBF
96
R7241 402
96 REG_ISENCORE_2_N 1 2 REG_ISENCORE_2_NR 62 96
OUT
96 64 63 62 PP12V S0 CPUCORE FLT
S R7237 C7241.1:2MM 1/16W
1 1
MF-LF
5% C7240 402
1/8W 0.1UF
5
6
3
CPUCOREDRV:ISL6612 MF-LF 10%
1 2 805 2 16V
R7267 X5R
10 402
5%
1/10W AGND_CPU 62 63 64 96
B MF-LF
2 603
B
EMC EMC
EMC EMC
CPU Phase 3 96 REG_LVCC_U7250
Q7250.7:3MM Q7250.8:3MM
CRITICAL CRITICAL CRITICAL Q7250.7:3MM Q7250.8:3MM
1 1 C7252 1 C7253 1 C7254 1 C7255
1 C7258 1 C7259 C7250
NC
U7250.9:3MM U7250.7:3MM 96 REG_BOOT CPUCORE_3_RC 270UF 10UF 10UF 1UF 1UF

1000PF 1000PF 20% 20% 20% 10% 10%
1 1 5% 5% 25V 25V 25V 25V
C7265 C7267 2 16V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R
1UF 1UF R7256 1 1 C7256 2 25V
NP0-C0G
25V
2 NP0-C0G ELEC
0603 0603 402 402
7
8
CRITICAL 8X9-TH1
9
10% 10% 1 0.22UF 402 402

2 16V
X5R VCC UVCC LVCC 2 16V
X5R 5%
1/10W
20%
2 25V D Q7250
603 603 X5R
603 2
ISL6622
DFN S CRITICAL
R7250
NC L7250 1%
3
CRITICAL 1W
UGATE 1 96 REG_UGATE_CPUCORE_3 0.24UH-30A-0.38MOHM MF
0612
OMIT_TABLE 1 2 96 PPCPUCORE_S0_SENSE_3 1 2 PPCPUCORE_S0_REG 6 63
OUT
PHASE 10 96 REG PHASE CPUCORE 3 SDP110808M-TH 3 4
THRML 0.0022UF U7100.48:3MM
GND 10% 1
PAD C7261
1
2
8
7
2 50V
5
11
CRITICAL CERM SIGNAL_MODEL=EMPTY 220PF

D 402 10%
C7261.2:2MM
2 50V
X7R-CERM
IRF6892STR1PBF
96
R7261 402
96 REG_ISENCORE_3_N 1 2 REG_ISENCORE_3_NR 62 96
OUT
S R7257 C7261.1:2MM 1/16W
1 1
MF-LF
5% C7260 402
A 1/8W 0.1UF
A
3
5
6
MF-LF
CPU Output Decoupling 2 805
10%
2 16V
SYNC MASTER=D7 NICK SYNC DATE=01/04/2012
X5R PAGE TITLE
402
63 6 PPCPUCORE_S0_REG
AGND_CPU 62 63 64 96
VReg CPU Core Phases
DRAWING NUMBER SIZE
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

NOSTUFF
CRITICAL Apple Inc. 051-9509 D
1 1 1 1 1 1 REVISION
C7280 C7281 C7282 C7283 C7284 C7285 R
4.2.0
330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM
20% 20% 20% 20% 20% 20% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 2V 2 2V 2 2V 2 2V 2 2V 2 2V PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
POLY POLY POLY POLY POLY POLY THE INFORMATION CONTAINED HEREIN IS THE
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM PROPRIETARY PROPERTY OF APPLE INC.
353S1733 2 IC,ISL6612,FET DRV,DFN10,LF U7230,U7250 CRITICAL CPUCOREDRV:ISL6612 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
72 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
NOSTUFF
1
R7347
10
C 5%
1/10W
MF-LF 96 64 63 62 PP12V_S0_CPUCORE_FLT C
2 603
EMC EMC
EMC EMC
AXG Phase 96 REG_LVCC_U7330
Q7250.5:3MM Q7250.6:3MM
CRITICAL CRITICAL CRITICAL CRITICAL Q7250.5:3MM Q7250.6:3MM
1 1 1 C7332 1 C7333 1 C7334 1 C7335
1 C7338 1 C7339 C7330 C7331
U7330.9:3MM U7330.8:3MM U7330.7:3MM 96 REG_BOOT CPUAXG_RC 270UF 270UF 10UF 10UF 1UF 1UF
1000PF 1000PF 20% 20% 20% 20% 10% 10%
1 1 1 5% 5% 25V 25V 25V 25V
C7345 C7346 C7347 25V 25V 2 16V 2 16V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R
1UF 1UF 1UF R73361 1 C7336 2 NP0-C0G 2 NP0-C0G ELEC ELEC
0603 0603 402 402
5
6
CRITICAL 8X9-TH1 8X9-TH1
9
10% 10% 10% 1 0.22UF 402 402

16V 16V 16V
2 X5R 2 X5R VCC UVCC LVCC 2 X5R 5%
1/10W
20%
25V
2 X5R D
Q7250
603 603 603
603 2 1 G DIRECTFET-SA
ISL6622 CRITICAL
DFN S CRITICAL
R7330
3 GDSEL BOOT 2 96 REG_BOOT_CPUAXG 0.0005
NC L7330 1%
4
CRITICAL 1W
UGATE 1 96 REG_UGATE_CPUAXG 0.24UH-30A-0.38MOHM MF
0612
1 2 96 PPCPUAXG_S0_SENSE 1 2 PPCPUAXG_S0_REG 6 64
OUT
PHASE 10 96 REG_PHASE_CPUAXG SDP110808M-TH 3 4 SIGNAL_MODEL=EMPTY
4 PWM NCNC C7342.1:2MM
96 62 IN REG_PWM_CPUAXG LGATE 6 96 REG_LGATE_CPUAXG
1 C7337 R7342
THRML 0.0022UF 301
GND PAD 10%
1
2
8
7
96 REG_ISENAXG_P 1 2 REG_ISENAXG_PR 62 96
50V OUT
2 CERM
5
11
CRITICAL 1%
D 402 1/16W
SIGNAL_MODEL=EMPTY
Q7331 REG_SNUBBER_CPUAXG 96
R7342.1:2MM MF-LF
402
IRF6892STR1PBF 1 C7341
4 G DIRECTFET_S3C SIGNAL_MODEL=EMPTY 220PF
C7341.2:2MM 10%
1 50V
S R7337 R7341 2 X7R-CERM
402
1 1.02K
5% 96 REG_ISENAXG_N 1 2 REG_ISENAXG_NR 62 96
B 1/8W
OUT
B
3
5
6
MF-LF SIGNAL_MODEL=EMPTY 1% SIGNAL_MODEL=EMPTY
R7342.1:2MM 1/16W U7100.24:3MM
2 805 MF-LF
1 C7340 402 1 C7342
0.1UF 120PF
10% 5%
16V 50V
2 X5R 2 CERM
402 402
AGND CPU 62 63 64 96 AGND CPU 62 63 64 96
A AXG Phase SYNC MASTER=D7 NICK SYNC DATE=01/04/2012 A

PAGE TITLE
64 6 PPCPUAXG_S0_REG VReg CPU AXG Phases

DRAWING NUMBER SIZE
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL Apple Inc. 051-9509 D

1 1 1 1 1 1 1 1 REVISION
C7390 C7391 C7392 C7393 C7396 C7397 C7394 C7395 R
330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 10UF 10UF 4.2.0

20% 20% 20% 20% 20% 20% 20% 20% NOTICE OF PROPRIETARY PROPERTY: BRANCH
10V 10V
2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 X5R 2 X5R
POLY POLY POLY POLY POLY POLY THE INFORMATION CONTAINED HEREIN IS THE
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM 603 603 PROPRIETARY PROPERTY OF APPLE INC.
73 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VccIO/PCH (1.05V) S0 Regulator

Max avg current: ? A (design)/ 14.38 A (budget)
Max peak current: ? A (design)/ 18.38 A (budget)
OC trip point: ? A (min)/? A (max)
Switching freq: 500 kHz
D D
6 =PP12V_S0_REG_P1V05_S0
CRITICAL CRITICAL CRITICAL

6 =PP5V_S0_REG_P1V05_S0
1 1 C7411 1 C7412
C7410
270UF 10UF 10UF
20% 20% 20%
25V 25V
R74001 1
R7401 2 16V
ELEC
2 X5R-CERM 2 X5R-CERM
10 2.2 8X9-TH1 0603 0603
95 13 IN SNS_CPU_VCCIO_P 5% 5%
1/8W 1/8W
MF-LF MF-LF
95 13 IN SNS_CPU_VCCIO_N 805 2 2 805
95 REG_BOOT P1V05S0_RC
95 REG VCC U7400 REG PVCC U7400 95
U1000.AB3:1MM 22 U1000.AB4:1MM R74161 1 C7416
C7400 1 1 C7401 1 0.1UF
XW7430 XW7435 1% 10% EMC EMC
SM SM 1UF 2.2UF 1/8W 16V
2 X7R-CERM Q7410.2:3MM Q7410.2:3MM
10% 10% MF-LF
16V 16V 402 1 1
11 X5R 2 2 X5R 805 2 C7480 C7481
402 603 1UF 1UF
95 SNS_P1V05S0_XW_N SNS_P1V05S0_XW_P 95
10% 10%
2 25V 2 25V
C SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
X5R
402
X5R
402 C
13
14
<Ra> <Ra> 95 REG_UGATE P1V05S0_R
R74301 1
R7435 VCC PVCC 1
3.01K 3.01K R7411 CRITICAL
1%
1/16W
1%
1/16W
U7400 3.32
1%
MF-LF MF-LF ISL95870 1/8W Q7410
402 2 2 402 UTQFN
MF-LF
805 2
CSD58872Q5D
60 PM_EN_REG_P1V05_S0 3 EN BOOT 12 95 REG_BOOT_P1V05S0 SON5X6 VIN 1
IN 3 TG
6 CRITICAL CRITICAL
95 REG_P1V05S0_FB FB UGATE 11 95 REG_UGATE_P1V05S0 VSW 6 L7410
<Rb> 4 1.0UH-22A-1.15MOHM
1
95 REG P1V05S0 SREF SREF PHASE 10 95 REG PHASE P1V05S0 4 TGR 7
R7436 8 95 REG_PHASE_P1V05S0 L 1 2 PP1V05_S0_REG OUT 6
2.74K 95 65 REG_P1V05S0_VO 8 VO LGATE 15 95 REG_LGATE_P1V05S0
1% C7440 1 SDP1182-SM
1/16W 0.047UF 7 5 BG 1 1
MF-LF 10% 95 65 REG_P1V05S0_OCSET OCSET C7418 R7418 CRITICAL CRITICAL CRITICAL
2 402 16V 1000PF 200 1 1 1 1 C7423
X7R 2 65 REG_P1V05S0_PGOOD 9 PGOOD PGND 5% 5%
C7420 C7421 C7422
402 NOSTUFF 25V 330UF-0.009OHM 330UF-0.009OHM 330UF-0.009OHM 10UF
NP0-C0G 2 1/10W 20%
9
2 402 MF-LF 20% 20% 20% 6.3V
REG_P1V05S0_RTN RTN C7417 1 2 2V 2 2V 2 2V
2 603 2 X5R
95
POLY POLY POLY
0.001UF CASE-D2-HF CASE-D2-HF CASE-D2-HF 603
95 REG_P1V05S0_FSEL 5 FSEL 10%
50V
GND PGND CERM 2
<Rb> 402
R74311 R74601
1
16
C7430 1 1 C7435 95 REG_SNUBBER_P1V05S0 Note:

2.74K 10PF 10PF 0
1% 5% 5% 5% Regulator requires
1/16W 50V 50V 1/16W NOSTUFF
MF-LF CERM 2 2 CERM MF-LF a minimum load to
402 2 402 402 402 2 R74171 prevent noise in the
2.2
5% audio frequencies
95 AGND_P1V05S0 1/10W
MF-LF
603 2
U7400.3:1MM 2
B XW7400
SM
B
1
L7410.1:3MM
Vout = 0.5 * (1 + Ra / Rb) R74501
3.40K R7450.2:3MM
1%
1/16W C7450
MF-LF
402 2 0.22UF
1 2
L7410.2:3MM
10% 1
16V R7451
74 68 66 62 6 =PP3V3 S0 VRD X7R 3.40K
To regulator: 603 1%
1 1/16W
R7480 REG_P1V05S0_OCSET
MF-LF
20K
95 65
2 402
5%
1/16W 95 65 REG P1V05S0 VO
MF-LF
2 402
65 REG_P1V05S0_PGOOD PM_PGOOD_REG_P1V05_S0 OUT 60

MAKE_BASE=TRUE

PAGE TITLE
VReg CPU/PCH 1.05V S0

DRAWING NUMBER SIZE

REVISION
R
4.2.0
74 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VccSA (0.925V) S0 Regulator

Max avg current: ? A (design)/ 1.51 A (budget)
OC trip point: ? A (min)/? A (max)
D D
6 =PP12V_S0_REG_VCCSA_S0
CRITICAL
1
C7510
270UF
20%
2 16V
ELEC
8X9-TH1
6 =PP5V_S0_REG_VCCSA_S0
EMC EMC
Q7510.2:3MM Q7510.2:3MM
R75001 1
R7501 1 C7580 1 C7581
10 2.2 1UF 1UF
95 13 SNS_CPU_VCCSA 5% 5% 10% 10%
IN 25V 25V
1/8W 1/8W 2 X5R 2 X5R
MF-LF MF-LF 402 402
805 2 2 805
95 REG_BOOT VCCSAS0_RC
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 95 REG VCC U7500 95 REG PVCC U7500
XW7535.2:1MM 2 2 U1000.T2:1MM R75161 1 C7516
C7500 1 1 C7501 0 0.1UF
XW7530 XW7535 5% 10%
SM SM 1UF 2.2UF 1/10W 2 16V
10% 10% X7R-CERM
16V 16V MF-LF 402
1 1 X5R 2 2 X5R 603 2
402 603
95 SNS_VCCSAS0_XW_N SNS_VCCSAS0_XW_P 95 (reg_phase_vccsas0)
C SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
C
13
14
<Ra> <Ra>
R75301 1
R7535 VCC PVCC
2.32K 2.32K
1%
1/16W
1%
1/16W
U7500 2
CRITICAL
MF-LF
402 2
MF-LF ISL95870
2 402 UTQFN Q7510
60 PM_EN_REG_VCCSA_S0 3 EN BOOT 12 95 REG_BOOT_VCCSAS0 CRITICAL
IN FDMS3602S
6 CRITICAL POWER56 L7510
95 REG_VCCSAS0_FB FB UGATE 11 95 REG_UGATE_VCCSAS0 1
1.0UH-20%-15A-0.0065OHM
<Rb> 4
1
95 REG VCCSAS0 SREF SREF PHASE 10 95 REG PHASE VCCSAS0 PHASE 7 1 2 PPVCCSA S0 REG OUT 6
R7536 PIC0605H-SM
2.74K 95 66 REG_VCCSAS0_VO 8 VO LGATE 15 95 REG_LGATE_VCCSAS0 NOSTUFF
C7540 1 C7518 1 1
1%
1/16W 1 C7517 R7518 CRITICAL CRITICAL
0.047UF REG_VCCSAS0_OCSET 7 6 1000PF 200 1 1 1 C7522
MF-LF 10% 95 66 OCSET 0.001UF 5% C7520 C7521
2 402 16V 10% 25V 5%
330UF-0.009OHM 330UF-0.009OHM 10UF
X7R 2 66 REG_VCCSAS0_PGOOD 9 PGOOD 2 50V NP0-C0G 2 1/10W
MF-LF 20% 20% 20%
402 CERM 402 2 2V 2 2V 2 6.3V
402 2 603 POLY POLY X5R
95 REG_VCCSAS0_RTN 2 RTN 3 4 5 CASE-D2-HF CASE-D2-HF 603
REG_SNUBBER_VCCSAS0 95
95 REG_VCCSAS0_FSEL 5 FSEL
GND PGND NOSTUFF
<Rb> 1
R7517 Note:
R75311 R75601
16
C7530 1 1 C7535 2.2 Regulator requires
2.74K 10PF 10PF 0 5%
1% 5% 5% 5% 1/10W a minimum load to
1/16W 50V 50V 1/16W MF-LF
MF-LF CERM 2 2 CERM MF-LF 2 603 prevent noise in the
402 2 402 402 402 2
audio frequencies
95 AGND_VCCSAS0 L7510.1:3MM
R75501
U7500.3:1MM 2 12.1K R7550.2:3MM
B XW7500
SM
1%
1/16W
MF-LF C7550 B
402 2 0.012UF
1 1 2
L7510.2:3MM
Vout = 0.5 * (1 + Ra / Rb) 10% 1
50V R7551
CER-X7R 12.1K
To regulator: 603 1%
1/16W
MF-LF
95 66 REG VCCSAS0 OCSET 2 402
95 66 REG_VCCSAS0_VO
74 68 65 62 6 =PP3V3 S0 VRD
1
R7580
20K
5%
1/16W
MF-LF
2 402
66 REG_VCCSAS0_PGOOD PM_PGOOD_REG_VCCSA_S0 OUT 60 61

MAKE_BASE=TRUE

PAGE TITLE
VReg CPU VccSA S0

DRAWING NUMBER SIZE

REVISION
R
4.2.0
75 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S5 Regulator 5V S4 Regulator

Max avg current: 6 A (design)/ 4.85 A (budget) Max avg current: 10 A (design)/ 6.08 A (budget)
Max peak current: ? A (design)/ 6.6 A (budget) Max peak current: ? A (design)/ 6.9 A (budget)
OC trip point: ? A (nom)/? A (min) OC trip point: ? A (nom)/? A (min)
Switching freq: 350 kHz Switching freq: 350 kHz
D 6 =PP12V_S5_REG_P3V3P5V_S5
D
CRITICAL CRITICAL CRITICAL
C7610 1 1
C7650 1
C7651
270UF 270UF 270UF
20% 20% 20%
16V 2 2 16V 2 16V
ELEC ELEC ELEC
8X9-TH1 8X9-TH1 8X9-TH1
1
R7603
1
5%
1/8W
MF-LF
2 805
EMC EMC EMC EMC

Q7610.2:3MM Q7610.2:3MM Q7650.5:3MM Q7650.5:3MM
1 1 97 REG_VIN_U7600 1 1
C7642 C7643 C7682 C7683
1UF 1UF 1UF 1UF
10% 10% 10% 10%
25V 2 25V 2 2 25V 2 25V
X5R X5R PP5V S5 LDO X5R X5R
402 402 OUT 6 CRITICAL 402 402
5
1 Q7650
1 C7601 R7602 FDMC0223
2.2 MLP3.3X3.3 D
EMC EMC 4.7UF 5% EMC EMC
20% 1/8W
L7610.1:3MM L7610.1:3MM 6.3V
2 CERM MF-LF 4 G L7650.2:3MM L7650.2:3MM
C7640 1 C7641 1 603 2 805 1 C7680 1 C7681
C 1000PF
5%
25V
1000PF
5%
25V 2
97 REG_VCC2_U7600
1 C7602 1 C7603 S 5%
1000PF
2 25V
5%
1000PF
25V
C
NP0-C0G 2 NP0-C0G 2 CRITICAL 97 REG_VCC1_U7600 97 REG_BOOT_P5VS4_RC NP0-C0G 2 NP0-C0G
402 402 1UF 1UF 402 402
CRITICAL
Q7610 C7600 1
10%
2 16V
10%
2 16V
1 2 3
CRITICAL
FDMS3602S X5R X5R 1
R7656 1 C7656
L7610 POWER56 1UF 402 402 L7650
1 10% 0 0.1UF
2.2UH-10A-12.5MOHM 16V 10% 2.2UH+/-20%-0.0069OHM-16A
X5R 2 5% 25V
1 2 (reg_phase_p3v3s5) 7 402 1/10W 2 X5R (reg_phase_p5vs4) 1 2
6 OUT PP3V3_S5_REG PHASE MF-LF 402
PP5V_S4_REG OUT 6
PAB0705AR-SM 2 603 PIC1005H-SM
4
CRITICAL CRITICAL NOSTUFF NOSTUFF CRITICAL CRITICAL
VCC1
VCC2
1
C7622 C7621 1 C7620 1 C7618 C7617 1 1 C7616 6
1 C7657 C7658
1
C7660 1
C7661 1 C7662
10UF 150UF 150UF 0.01UF R7618 0.001UF 0.1UF 18 LDO5 VIN 17 0.001UF R7658 27.0NF 330UF 330UF 10UF
20% 20% 20% 15.8K 10% 10% 10% 9.76K 20% 20% 20%
6.3V 2 1 2 50V 2 25V 50V 1 2 6.3V
X5R
6.3V 2
POLY
6.3V 2
POLY
1 2
CERM 2 X5R U7600 FCCM 3 REG_U7600_FCCM 67
CRITICAL 5 2 CERM 1 2 2 6.3V
POLY-TANT
2 6.3V
POLY-TANT
2 X5R
603 B1A-SM B1A-SM
10%
1%
1/16W
402 402
5 4 3 ISL62383CRTZ Q7655 402 1%
1/16W 10%
CASE-D3L-SM CASE-D3L-SM 603
16V
CERM
MF-LF 67 REG_P3V3S5_PGOOD 7 PGOOD1 QFN PGOOD2 1 REG_P5VS4_PGOOD 67 FDMC0223S D MF-LF 10V
X5R
402
402 REG_BOOT_P3V3S5_RC 97 MLP3.3X3.3 REG_SNUBBER_P5VS4 97 402
402
97 REG_SNUBBER_P3V3S5 97 REG_UGATE_P3V3S5 14 UGATE1 UGATE2 22 97 REG_UGATE_P5VS4 4 G
NOSTUFF
NOSTUFF 1 REG_BOOT_P3V3S5 15 BOOT1 CRITICAL BOOT2 21 REG_BOOT_P5VS4 1
OMIT R7616 97 97
R7657 OMIT
1 0 0.499
L7610.1:1MM 2 1
R7619 R7617 5% 97 REG_PHASE_P3V3S5 13 PHASE1 PHASE2 23 97 REG_PHASE_P5VS4
S
1% R76591 2 L7650.2:1MM
0.499 1/10W 1/10W
XW7610 15.8K 1% MF-LF
16 LGATE1 20 MF 9.76K XW7650
SM 1% 1/10W 2 603
97 REG_LGATE_P3V3S5 LGATE2 97 REG_LGATE_P5VS4 1 2 3 2 603 1% SM
1/16W MF 1/16W
MF-LF 603 2 MF-LF
1 2 402
97 REG_P3V3S5_ISEN 10 ISEN1 ISEN2 26 97 REG_P5VS4_ISEN 402 2 1
97 REG_P3V3S5_OCSET 11 OCSET1 OCSET2 25 97 REG_P5VS4_OCSET

(reg_p3v3s4_isen) (reg_p5vs4_isen)
97 REG_P3V3S5_VOUT 9 VOUT1 VOUT2 27 97 REG_P5VS4_VOUT
(reg_p3v3s4_ocset) (reg_p5vs4_ocset)
97 REG_P3V3S5_FB 8 FB1 FB2 28 97 REG_P5VS4_FB
(reg_p3v3s4_vout) (reg_p5vs4_vout)
B <Ra>
97 REG_P3V3S5_FSET 6 FSET1 FSET2 2 97 REG_P5VS4_FSET
<Ra> B
R76301 R76321 12 EN1 EN2 24 1
R7672 1
R7670
45.3K 976 THRM
976 75K
1% 1% PAD PGND NOSTUFF 1% 1%
1/16W 1/16W 1 1 1 1 1 1/16W 1/16W
MF-LF MF-LF C7633 R7633 C7673 R7673 C7675 MF-LF MF-LF
29
19
402 2 402 2 0.01UF 0.01UF 0.001UF 2 402 2 402
10% 16.5K 10% 16.5K 10%
16V 1% 16V 1% 50V
REG P3V3S5 VOUT R 97 2 CERM 1/16W 2 CERM 1/16W 2 CERM 97 REG P5VS4 VOUT R
<Rb> 402 MF-LF 402 MF-LF 402 <Rb>
2 402 2 402
R76311 C7632 1 1 C7672 1
R7671
10.0K 1000PF 1000PF 10K
0.5% 5% 5% 1%
1/16W 25V 2 25V
MF NP0-C0G 2 NP0-C0G 1/16W
MF-LF
402 402
402 2 2 402
Vout = 0.6 * (1 + Ra / Rb) Vout = 0.6 * (1 + Ra / Rb)

60 IN PM EN REG P3V3 S5
NOSTUFF
R7600 60 IN PM_EN_REG_P5V_S4
1K
NOSTUFF 2 1 REG_U7600_FCCM 67
5%
Q7600 1/16W
SSM6L36FE MF-LF
402
SOT563 D 3 REG_U7600_FCCM_R 68 67 6 =PP3V3_S5_VRD
P-CH
=PP5V_S5_PWRCTL 6 67 70
1
NOSTUFF R7680
This circuit toggles the Vreg 20K
between PWM and ultrasonic DCM R76011 5%
10K 1/16W
modes based on load requirements 67 BURSTMODE EN 5 G 5% MF-LF
1/16W 2 402
A 70 67 6 =PP5V_S5_PWRCTL 4 S
MF-LF
402 2 67 REG P5VS4 PGOOD PM PGOOD REG P5V S4
MAKE_BASE=TRUE OUT 60 SYNC MASTER=D7 NICK SYNC DATE=01/04/2012 A
D 6 PAGE TITLE
67 BURSTMODE_EN
BURSTMODE_EN_L Vreg Mode 68 67 6 =PP3V3_S5_VRD
VReg 3.3V S5/5V S4
DRAWING NUMBER SIZE
0 PWM 1
R7640 Apple Inc. 051-9509 D
1 DCM 2 G 20K REVISION
45 6 IN BURSTMODE EN L 5% R
1/16W
MF-LF
4.2.0
1 S 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
N-CH THE INFORMATION CONTAINED HEREIN IS THE
67 REG_P3V3S5_PGOOD PM_PGOOD REG_P3V3_S5 OUT 61 PROPRIETARY PROPERTY OF APPLE INC.
MAKE_BASE=TRUE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
76 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VDDQ (1.5V) S3 Regulator

Max avg current: ? A (design)/ 8 A (budget)
OC trip point: ? A (nom)/? A (min) 6 =PP12V_S5_REG_VDDQ_S3
CRITICAL CRITICAL
C7710 1 C7711 1
270UF 270UF
D
20%
16V 2
ELEC
20%
16V 2
ELEC
D
8X9-TH1 8X9-TH1
EMC EMC
6 =PP5V_S4_REG_VDDQ_S3
Q7710.1:3MM Q7710.1:3MM
6 =PPVDDQ_S3_LDO_DDRVTT 1 1
C7742 C7743
R77001 1UF 1UF
2.2 C7701 1 10% 10%
5% 10UF 2 25V
X5R 2 25V
X5R
1/8W 20% 402 402
MF-LF 6.3V 2
805 2 X5R
603 95 REG_BOOT_VDDQS3_RC 95 REG_UGATE_VDDQS3_R
EMC EMC
R77161 1 C7716 R77111 L7710.2:3MM Q7710.1:3MM
C7700 1 0 0.1UF 3.9 CRITICAL 1 C7740 1 C7741
5% 10% 5%
2.2UF 25V 1000PF 1000PF
2
1/10W 2 X5R 1/10W
10%
16V 2 MF-LF 402 MF-LF Q7710 5%
25V
5%
25V
X5R VLDOIN 603 2 603 2 CSD58872Q5D 2 NP0-C0G 2 NP0-C0G
603 SON5X6 VIN 1 402 402
3 TG
95 REG_V5IN_U7700 12 V5IN CRITICAL VBST 15 95 REG_BOOT_VDDQS3 CRITICAL
DRVH 14 95 REG UGATE VDDQS3 VSW 6 L7710
60 PM EN LDO DDRVTT S0 17 S3
U7700 SW 13 95 REG PHASE VDDQS3 4 TGR 7 1.0UH-22A-1.15MOHM
IN
PM_EN_REG_VDDQ_S3
TPS51916 8 REG_PHASE_VDDQS3_L 1 2 PPVDDQ_S3_REG
60 IN 16 S5 QFN
95
OUT 6
DRVL 11 95 REG_LGATE_VDDQS3 SDP1182-SM CRITICAL CRITICAL

95 REG_VDDQS3_VREF 6 VREF 5 BG NOSTUFF 1 1 1
PGOOD 20 REG_VDDQS3_PGOOD 68
1 C7720 C7721 C7722
9 REG_VDDQS3_VDDQSNS
C7717 330UF-0.009OHM 330UF-0.009OHM 10UF
VDDQSNS 95
1000PF 20%
95 REG VDDQS3 REFIN 8 REFIN PGND 5%
20% 20% 6.3V
<Ra> VTT 3 PPDDRVTT_S0_LDO OUT 6 2 2V 2 2V 2 X5R
2 25V POLY POLY
9
1 1 NP0-C0G 603
C7730 R7730 95 REG_VDDQS3_MODE 19 MODE VTTSNS 1 95 LDO_DDRVTTS0_SNS 402
CASE-D2-HF CASE-D2-HF
0.1UF REG VDDQS3 TRIP 1 2
10% 10K 95 18 TRIP CRITICAL
16V 1% SM 1
REG_SNUBBER_VDDQS3 95
X7R-CERM 2 1/16W VTTREF 5 6 PPDDRVTT S3 LDO C7725
402 MF-LF
402 2 10mA (max)
XW7725 22UF Critical: NOSTUFF
C7725.1:3MM 20%
VTT THRM 2 6.3V 1
C PGND GND GND PAD OMIT X5R-CERM-1
603
Need copper around Q7710
to sink heat
R7717
0.499
67 6 =PP3V3_S5_VRD C
10
21
<Rb> 1% 1
CRITICAL 1/10W R7740
R77311 1 C7731 1
R7735 R77361 C7727 1 C7726 1 MF
OMIT 20K
49.9K 0.01UF 1K 75K 2 603 5%
1% 10% 1% 1% 0.22UF 22UF L7710.2:1MM 1/16W
50V 10% 20%
1/16W 2 X7R 1/16W 1/16W 16V 6.3V MF-LF
MF-LF 402 MF-LF MF-LF CERM 2 X5R-CERM-1 2 XW7710 2 402
402 2 2 402 402 2 402 603 SM
1 2 68 REG_VDDQS3_PGOOD PM_PGOOD REG_VDDQ_S3 OUT 60
95 AGND_VDDQS3 MAKE_BASE=TRUE
OMIT
Vout = 1.8 * (Ra / (Ra + Rb))
2 U7700.21:1MM
XW7700
SM
1.8V S0 Regulator
Max avg current: 3 A (design)/ 0.61 A (budget)
OC trip point: ? A (nom)/? A (min)
Switching freq: ? kHz
B 6 =PP5V_S0_REG_P1V8_S0
B
EMC EMC
Q7750.1:3MM Q7750.1:3MM
1 C7750 1 C7751 1 C7752 1 C7753
10UF 10UF 1UF
20% 20% 10% 1UF
6.3V 6.3V 25V 10%
2 X5R 2 X5R 2 X5R 25V
603 603 2 X5R
402 402
1
VIN 2
3
VDD
CRITICAL
=PP5V_S0_VRD
6
U7750 L7750
ISL8014A 1.0UH-4.5A
R77701 60 IN PM_EN_REG_P1V8_S0 5 EN QFN
LX 14 97 REG_PHASE_P1V8S0 1 2 PP1V8_S0_REG OUT 6
100K PCMB042T-IHLP1616BZ
5% CRITICAL LX 15 <Ra>
1/16W 1 1
MF-LF 68 REG_P1V8S0_PGOOD 7 PG C7758 R7758
402 2 1 C7760 1 C7761
VFB 8 97 REG P1V8S0 VFB 47PF 59.0K
5% 1% 22UF 22UF
REG P1V8S0 SYNCH 4 SYNCH 50V 20% 20%
97 2 CERM 1/16W
17 THRM_PAD
16
NC 402 MF-LF 2 6.3V
X5R-CERM-1 2 6.3V
X5R-CERM-1
NOSTUFF PU: PWM 2 402 603 603
PD: PFM (SKIP mode) 6
NC NC
R77711
12 PGND
10 SGND
13
100K NC <Rb>
5% 1
1/16W R7759
9
11
MF-LF
402 2 47.0K
1%
1/16W
MF-LF
A 2 402 Vout = 0.8 * (1 + Ra / Rb)
PAGE TITLE
VReg VDDQ and 1.8V S0

74 66 65 62 6 =PP3V3_S0_VRD DRAWING NUMBER SIZE
1 Apple Inc. 051-9509 D

R7780 REVISION
10K R
5%
1/16W
4.2.0
MF-LF NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 402 THE INFORMATION CONTAINED HEREIN IS THE
68 REG_P1V8S0_PGOOD PM_PGOOD REG_P1V8_S0 OUT 60 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
77 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
3.425V "G3Hot" Regulator

Max avg current: ? A (design)/ 0 A (budget)
6 =PP12V_G3H_REG_3V42_G3H Switching freq: ? kHz
1 C7806 1 C7807 1 C7802 97 P3V42G3H_BOOST
1UF 1UF 10UF 1
10%
25V
10%
25V
10%
25V R7801
2 X5R 2 X5R 2 X5R 6.98K 1 C7803
3
402 402 0805 1% 0.22UF
1/16W VIN BOOST 10%
MF-LF
2 16V
2 402 U7800 CERM
402 L7801
LT3470A 33UH PP3V42 G3H REG 6
DFN Vout = 3.425
97 P3V42G3H SHDN L 8 SHDN* SW 4 97 P3V42G3H SW 1 2 250mA max output
(Switcher limit)
NOSTUFF NOSTUFF BIAS 2 CDPH4D19FHF-SM
7 NC
1 NC
R7802 1 C7801 FB 1
2.1K 1000PF THRM
1%
1/16W
MF-LF
5%
25V
2 NP0-C0G
GND PAD 1 C7804 1
R7803 1 C7805
22PF 22UF
9
2 402 402 5%
348K 20%
50V <Ra> 1% 6.3V
2 CERM 1/16W 2 X5R-CERM1
402 MF-LF 0603
2 402
97 P3V42G3H_FB
C 1
R7804
200K
C
<Rb> 1%
1/16W
MF-LF
2 402
Vout = 1.25V * (1 + Ra / Rb)
12V S5 FET
Max avg current: 7.03 A (budget)
Max peak current: 9.69 A (budget)
Q7870
B 6 =PP12V G3H FET P12V S5 IRFH3702TRPBF
PQFN
B
R7870
100
S
1 2 FET_VCC_U7970 PP12V_S5_FET
1
OUT 6
5%
1/10W
MF-LF
G
603 1 C7870
1UF
10%
4
1
2 16V
X5R
603 VCC
U7870
SLG5AP026
Input: 2.4V to 5.5V 2 TDFN 5
45 44 IN SMC PM G2 EN ON D1
3 NC D2 6
1 NC
R7871
100K G 7 FET_EN_P12V_S5
5%
1/16W
MF-LF PG 8 NC PM PGOOD FET P12V S5
2 402 THRM NO_TEST=TRUE
GND PAD
4

PAGE TITLE
VReg G3Hot
DRAWING NUMBER SIZE

REVISION
R
4.2.0
78 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S4 FET 3.3V S0 FET 3V3 S0 SSD 5V S0 FET

Max avg current: 0.85 A (budget) Max avg current: 1.7 A (budget) Max avg current: 2.12 A (budget) Max avg current: 1.26 A (budget)
Max peak current: 1.48 A (budget) Max peak current: 1.82 A (budget) Max peak current: 3.03 A (budget) Max peak current: 2.08 A (budget)
78 70 61 60 6 =PP3V3 S5 PWRCTL 6 =PP5V S4 PWRCTL

67 6 =PP5V_S5_PWRCTL
SSD
D 1 C7900
1 C7910
0.1UF
1 C7920
0.1UF
D
0.1UF 10% 10%
10% 16V 16V
2 X5R 2 X5R
2 16V
X5R 402 402
402
1
VDD VDD
U7910 U7920
4
5_VDD SLG5AP304V SLG5AP304V
TDFN TDFN
P3V3_S0_SSD_FET_RAMP 7 CAP D 3 =PP3V3_S5_FET_P3V3_S0 P5V_S0_FET_RAMP 7 CAP D 3 =PP5V_S4_FET_P5V_S0
U7900 CRITICAL 6 70
CRITICAL 6
SLG5AP439 70 60 41 IN PM_EN_FET_P3V3_S0 2 ON SSD S 5 PP3V3_S0_SSD_FET OUT 6 60 IN PM_EN_FET_P5V_S0 2 ON S 5 PP5V_S0_FET OUT 6 70

TDFN 70
PM_EN_FET_P3V3_S4 3 ON_MOS1 ON_MOS2 5 PM_EN_FET_P3V3_S0 SSD
60 IN IN 41 60 70 GND GND
12 CAP_MOS2 10
C7911 1 C7921 1
8
FET_RAMP_P3V3_S4 CAP_MOS1 FET_RAMP_P3V3_S0
0.0047UF 0.0047UF
10% 10%
6 OUT PP3V3 S4 FET 13 MOS1_S MOS2_S 8 PP3V3 S0 FET OUT 6 70
25V
CERM 2 4nF corresponds to
25V
CERM 2 4nF corresponds to
6 =PP3V3_S5_FET_P3V3_S4 1 MOS1_D MOS2_D 6 =PP3V3_S5_FET_P3V3_S0 6 70
402
2.2V / ms ramp rate
402 2.2V / ms ramp rate
IN IN
1
THRM 1 C7902
C7901 GND PAD
0.01UF 0.01UF
10%
11
15
10% 25V
25V 2 X7R
X7R 2 402
402
C C
5V / 3V3 S0 PGOODs
78 70 61 60 6 =PP3V3 S5 PWRCTL
1 C7940
0.1UF
10%
16V
2 X5R
8 402
VCC
U7940
SOT833
08
74LVC2G08GT
PM_EN_FET_P5V_S0 1 7 PM_PGOOD_FET_P5V_S0 OUT
70 60 IN
2
A1 Y1 60
70 6 PP5V_S0_FET
B1
70 60 41 PM_EN_FET_P3V3_S0 5 3 PM_PGOOD_FET_P3V3_S0 OUT 60
IN
6
A2 Y2
70 6 PP3V3_S0_FET
B2
GND
4
B B
1.5V S0 FET
Max avg current: 1.27 A (budget)
Max peak current: 4.8 A (budget)
12V S0 FET
61 60 6 =PP12V_S5_PWRCTL Max avg current: 14.3 A (budget)
Q7930 1 C7930 Max peak current: 23 A (budget) Q7950
IRF6892STR1PBF 0.1UF IRF6892STR1PBF
10%
DIRECTFET_S3C 2 16V
X5R DIRECTFET_S3C
402
7 6 =PP12V_G3H_FET_P12V_S0 7
8 6 MIN_LINE_WIDTH=0.3mm 8 6
R7950 MIN_NECK_WIDTH=0.15mm
VOLTAGE=12V
2 5 100 2 5
D
D
=PPVDDQ S3 FET VDDQ S0 PP1V5 S0 FET 1 2 FET VCC U7950 PP12V S0 FET
S
S
6 3 OUT 6 3 OUT 6
1 1
5%
G
G
1/10W
MF-LF
80 6 =PP3V3_S0_PWRCTL 603 1 C7950
4
4
1UF
1
10%
16V
1
1 VCC 2 X5R
R7930 603 VCC
5%
10K U7930 U7950
1/16W SLG5AP004 =PP3V3 S4 PWRCTL
A MF-LF
2 402 5D DFN
ON 2 PM EN FET VDDQ S0 IN 60
60 PM_EN_FET_P12V_S0
Input: 2.4V to 5.5V 2
ON
SLG5AP026
TDFN
D1 5
6

IN 1 PAGE TITLE
7G S6 R7952
P1V5_S0_FET_GATE
8 PG
CRITICAL
1
R7951 NC
3 NC D2 6 10K
5%
FET-Controlled S0 and S4
60 28 OUT PM_PGOOD_FET_VDDQ_S0 NC 3 NC 7 1/16W DRAWING NUMBER SIZE
100K G P12V S0 FET GATE MF-LF
THRM
5%
1/16W
402 2
PAD GND MF-LF PG 8 PM_PGOOD_FET_P12V_S0 60 REVISION
OUT
9
2 402 THRM
R
4.2.0
GND PAD
NOTICE OF PROPRIETARY PROPERTY:
4
BRANCH
79 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT TABLE
Page Notes
U8000
- PP3V3 GPU VDD33
NV-GK107
BGA
(1 OF 10)
AN12 AK14
89 71 PEG R2D P<0> PEX_RX0 PEX_TX0 PEG D2R C P<0> 71 89
AM12 AJ14
89 71 PEG R2D N<0> PEX_RX0* PEX_TX0* PEG D2R C N<0> 71 89
(NONE)
Polarity swaps intended on Lanes 0, 5, 8, 9, and 11.
AN14 AH14
(NONE)
AM14 AG14
D D
AP14 AK15
C8020 0.22UF
1 2
C8036 0.22UF
1 2
89 9 IN PEG R2D C P<0> PEG R2D N<0> 71 89 89 9 IN PEG R2D C P<8> PEG R2D N<8> 71 89 AP15 AJ15
GND VOID=TRUE 20% 6 3V X5R 0201 GND VOID=TRUE 20% 6 3V X5R 0201 89 71 PEG R2D N<2> PEX_RX2* PEX_TX2* PEG D2R C N<2> 71 89
Polarity swapped!! Polarity swapped!!
C8021 0.22UF C8037 0.22UF
PEG R2D C N<0> 1 2 PEG R2D P<0> PEG R2D C N<8> 1 2 PEG R2D P<8>
89 9 IN 71 89 89 9 IN 71 89
GND VOID=TRUE 20% 6 3V X5R 0201 GND VOID=TRUE 20% 6 3V X5R 0201
AN15 AL16
C8022 0.22UF
1 2
C8038 0.22UF
1 2
89 9 IN PEG R2D C P<1> PEG R2D P<1> 71 89 89 9 IN PEG R2D C P<9> PEG R2D N<9> 71 89
AM15 AK16
GND VOID=TRUE 20% 6 3V X5R 0201
GND VOID=TRUE 20% 6 3V X5R 0201 89 71 PEG R2D N<3> PEX_RX3* PEX_TX3* PEG D2R C N<3> 71 89
Polarity swapped!!
C8023 0.22UF C8039 0.22UF
PEG R2D C N<1> 1 2 PEG R2D N<1> PEG R2D C N<9> 1 2 PEG R2D P<9>
89 9 IN 71 89 89 9 IN 71 89
AN17 AK17
C8024 0.22UF
1 2
C8040 0.22UF
1 2
89 9 PEG R2D C P<2> PEG R2D P<2> 71 89 89 9 PEG R2D C P<10> PEG R2D P<10> 71 89
IN IN AM17 AJ17
C8025 0.22UF C8041 0.22UF

PEG R2D C N<2> 1 2 PEG R2D N<2> PEG R2D C N<10> 1 2 PEG R2D N<10>
89 9 IN 71 89 89 9 IN 71 89
AP17 AH17
C8026 0.22UF
1 2
C8042 0.22UF
1 2
89 9 IN PEG R2D C P<3> PEG R2D P<3> 71 89 89 9 IN PEG R2D C P<11> PEG R2D P<11> 71 89
AP18 AG17
C8027 0.22UF C8043 0.22UF

89 9 IN 71 89 89 9 IN 71 89
AN18 AK18
C8028 0.22UF
1 2
C8044 0.22UF
1 2
89 9 IN PEG R2D C P<4> PEG R2D P<4> 71 89 89 9 IN PEG R2D C P<12> PEG R2D P<12> 71 89
AM18 AJ18
C8029 0.22UF C8045 0.22UF

89 9 IN 71 89 89 9 IN 71 89
AN20 AL19
C8030 0.22UF
1 2
C8046 0.22UF
1 2
89 9 PEG R2D C P<5> PEG R2D N<5> 71 89 89 9 PEG R2D C P<13> PEG R2D N<13> 71 89
IN IN AM20 AK19
C 89 9 PEG R2D C N<5>

GND VOID=TRUE
C8031 0.22UF
1
20%
2
6 3V X5R 0201
Polarity swapped!!
PEG R2D P<5> 71 89 89 9 PEG R2D C N<13>
GND VOID=TRUE
C8047 0.22UF
1
20%
2
6 3V X5R 0201
Polarity swapped!!
PEG R2D P<13> 71 89
C
IN 20% 6 3V X5R 0201
IN 20% 6 3V X5R 0201
GND VOID=TRUE GND VOID=TRUE
AP20 AK20
C8032 0.22UF
1 2
C8048 0.22UF
1 2
IN IN AP21 AJ20
C8033 0.22UF C8049 0.22UF

89 9 IN 71 89 89 9 IN 71 89
AN21 AH20
C8034 0.22UF
1 2
C8050 0.22UF
1 2
IN IN AM21 AG20
C8035 0.22UF C8051 0.22UF

89 9 IN 71 89 89 9 IN 71 89
AN23 AK21
AM23 AJ21
C8055 0.22UF C8071 0.22UF

1 2 1 2 AP23 AL22
89 71 PEG D2R C N<0>
20% 6 3V X5R 0201
PEG D2R P<0>
OUT 9 89 89 71 PEG D2R C N<8>
20% 6 3V X5R 0201
PEG D2R P<8>
OUT 9 89 89 71 PEG R2D P<11> PEX_RX11 PEX_TX11 PEG D2R C P<11> 71 89
GND VOID=TRUE GND VOID=TRUE AP24 AK22
Polarity swapped!! Polarity swapped!! 89 71 PEG R2D N<11> PEX_RX11* PEX_TX11* PEG D2R C N<11> 71 89
C8056 0.22UF C8072 0.22UF
PEG D2R C P<0> 1 2 PEG D2R N<0> PEG D2R C P<8> 1 2 PEG D2R N<8>
89 71 OUT 9 89 89 71 OUT 9 89
C8057 0.22UF C8073 0.22UF

1 2 1 2 AN24 AK23
89 71 PEG D2R C P<1>
20% 6 3V X5R 0201
PEG D2R P<1>
OUT 9 89 89 71 PEG D2R C N<9>
20% 6 3V X5R 0201
PEG D2R P<9>
GND VOID=TRUE GND VOID=TRUE AM24 AJ23
Polarity swapped!! 89 71 PEG R2D N<12> PEX_RX12* PEX_TX12* PEG D2R C N<12> 71 89
C8058 0.22UF C8074 0.22UF
PEG D2R C N<1> 1 2 PEG D2R N<1> PEG D2R C P<9> 1 2 PEG D2R N<9>
89 71 OUT 9 89 89 71 OUT 9 89
C8059 0.22UF C8075 0.22UF

1 2 1 2 AN26 AH23
89 71 PEG D2R C P<2> PEG D2R P<2> 9 89 89 71 PEG D2R C P<10> PEG D2R P<10> 9 89 89 71 PEG R2D P<13> PEX_RX13 PEX_TX13 PEG D2R C P<13> 71 89
B GND VOID=TRUE
C8060 0.22UF
1
20%
2
6 3V X5R 0201
OUT
GND VOID=TRUE
C8076 0.22UF
1
20%
2
6 3V X5R 0201
OUT
89 71 PEG R2D N<13> AM26
PEX_RX13* PEX_TX13* AG23 PEG D2R C N<13> 71 89 B
89 71 PEG D2R C N<2> PEG D2R N<2> OUT 9 89 89 71 PEG D2R C N<10> PEG D2R N<10> OUT 9 89
C8061 0.22UF C8077 0.22UF

1 2 1 2 AP26 AK24
89 71 PEG D2R C P<3>
20% 6 3V X5R 0201
PEG D2R P<3>
OUT 9 89 89 71 PEG D2R C P<11>
20% 6 3V X5R 0201
PEG D2R N<11>
GND VOID=TRUE GND VOID=TRUE AP27 AJ24
Polarity swapped!! 89 71 PEG R2D N<14> PEX_RX14* PEX_TX14* PEG D2R C N<14> 71 89
C8062 0.22UF C8078 0.22UF
PEG D2R C N<3> 1 2 PEG D2R N<3> PEG D2R C N<11> 1 2 PEG D2R P<11>
89 71 OUT 9 89 89 71 OUT 9 89
C8063 0.22UF C8079 0.22UF

1 2 1 2 AN27 AL25
89 71 PEG D2R C P<4> PEG D2R P<4> OUT 9 89 89 71 PEG D2R C P<12> PEG D2R P<12> OUT 9 89 89 71 PEG R2D P<15> PEX_RX15 PEX_TX15 PEG D2R C P<15> 71 89
AM27 AK25
C8064 0.22UF C8080 0.22UF
PEG D2R C N<4> 1 2 PEG D2R N<4> PEG D2R C N<12> 1 2 PEG D2R N<12>
89 71 OUT 9 89 89 71 OUT 9 89
R8002
200
C8065 0.22UF C8081 0.22UF PEX TSTCLK O PL 1 2
1 2 1 2 AL13 AJ26
89 71 PEG D2R C N<5>
20% 6 3V X5R 0201
PEG D2R P<5>
OUT 9 89 89 71 PEG D2R C P<13>
20% 6 3V X5R 0201
PEG D2R P<13>
OUT 9 89 89 18 IN PEG CLK100M P PEX_REFCLK PEX_TSTCLK_OUT NOSTUFF
GND VOID=TRUE GND VOID=TRUE AK13 AK26
1% MF
Polarity swapped!! 89 18 IN PEG CLK100M N PEX_REFCLK* PEX_TSTCLK_OUT* 1/20W 201
C8066 0.22UF C8082 0.22UF PEX TSTCLK O NG

89 71 PEG D2R C P<5> 1 2 PEG D2R N<5> 9 89 89 71 PEG D2R C N<13> 1 2 PEG D2R N<13> 9 89
R8000 R8005
OUT OUT GPU RESET L GPU RESET R L
GND VOID=TRUE 20% 6 3V X5R 0201 GND VOID=TRUE 20% 6 3V X5R 0201 0 AJ12 AP29
2.49K
78 26 IN
1 2 PEX_RST* PEX_TERMP GPU PEX TERMP 1 2
C8067 0.22UF C8083 0.22UF MF 5% 1/20W 201 1%

PEG D2R C P<6> 1 2 PEG D2R P<6> PEG D2R C P<14> 1 2 PEG D2R P<14> 1/20W
89 71 OUT 9 89 89 71 OUT 9 89 AK12
18 15 OUT PEG CLKREQ L PEX_CLKREQ* MF
201
C8068 0.22UF C8084 0.22UF

1 2 1 2 AG12
89 71 PEG D2R C N<6> PEG D2R N<6>
OUT 9 89 89 71 PEG D2R C N<14> PEG D2R N<14>
OUT 9 89
AJ11 PEX_SVDD_3V3 =PP3V3 GPU VDD33 6 77 78 79
NC PEX_WAKE*
C8069 0.22UF C8085 0.22UF

PEG D2R C N<7> 1 2 PEG D2R N<7> PEG D2R C P<15> 1 2 PEG D2R P<15>
89 71 OUT 9 89 89 71 OUT 9 89
C8070 0.22UF C8086 0.22UF

PEG D2R C P<7> 1 2 PEG D2R P<7> PEG D2R C N<15> 1 2 PEG D2R N<15>
89 71 OUT 9 89 89 71 OUT 9 89
20% 6 3V X5R 0201 20% 6 3V X5R 0201
GND VOID=TRUE GND VOID=TRUE
A SYNC MASTER=D7 TONY SYNC DATE=01/10/2012 A

PAGE TITLE
KEPLER PCI-E
DRAWING NUMBER SIZE
DP TBTSNK0 EG AUXCH P DP TBTSNK0 AUXCH C P DP TBTSNK1 EG AUXCH P DP TBTSNK1 AUXCH C P
77
MAKE_BASE=TRUE
34 98 77
MAKE_BASE=TRUE
34 98

77 DP TBTSNK0 EG AUXCH N DP TBTSNK0 AUXCH C N 34 98 77 DP TBTSNK1 EG AUXCH N DP TBTSNK1 AUXCH C N 34 98
MAKE_BASE=TRUE MAKE_BASE=TRUE REVISION
R
4.2.0
80 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
OMIT TABLE Power aliases required by this page:
- PPVCORE GPU
- PP1V35 GPU FBVDDQ
=PPVCORE GPU U8000 =PPVCORE GPU

79 72 6
NV-GK107 6 72 79
BGA
(10 OF 10)
AA12 V17
AA14 V18
AA16 V20
(NONE)
AA19 V22
AA21 W12
D
=PPVCORE GPU 6 72 79
EDP = 30 A AA23 W14
(NONE) D
AB13 W16
VDD
AB15 W19
AB17 W21
AB18 W23
AB20 Y13
AB22 Y15
AC12 Y17
1 1 1 1 1 1 1 1
C8161 C8184 C8162 C8174 C8179 C8166 C8167 C8168
AC14 Y18
47UF 47UF 22UF 22UF 22UF 4 7UF 4 7UF 4 7UF
20% 20% 20% 20% 20% 20% 20% 20%
AC16 Y20
6 3V 4V 6 3V 4V 4V 6 3V 6 3V 6 3V
2 X5R CERM 2 X6S
2 X5R 2 X6S-CERM
2 X6S-CERM
2 X5R-CERM1
2 X5R-CERM1
2 X5R-CERM1
0805 0805 0603 0603 0603 402 402 402
AC19 Y22
AC21
U1
AC23 NC
U2
M12 NC
U3
M14
U4
NC
M16 NC
U5
M19 NC
U6
1
C8169 1
C8170 1
C8171 1
C8172 1
C8173 1
C8175 1
C8176 1
C8177 1
C8178 1
C8180 M21 NC
U7
4 7UF 4 7UF 4 7UF 4 7UF 4 7UF 4 7UF 4 7UF 4 7UF 4 7UF 4 7UF M23 NC
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% U8
2
6 3V
2
6 3V
2
4V
2
4V
2
4V
2
4V
2
4V
2
4V
2
4V
2
4V N13 NC
X5R-CERM1 X5R-CERM1 X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM V1
402 402 0603 0603 0603 0603 0603 0603 0603 0603 N15 NC
V2
N17
VDD NC
V3
N18 NC
V4
N20 NC
V5
N22 NC
V6
P12
V7
NC
C 1
C8181
4 7UF
1
C8185
4 7UF
P14
P16
V8
W2
NC
NC
C
10% 10% P19 NC
4V 4V W3
2 2
X6S-CERM X6S-CERM P21 NC
0603 0603 W4
P23 NC
W5
R13 NC
W7
R15 XVDD NC
W8
R17 NC
Y1
R18 NC
Y2
R20 NC
Y3
R22 NC
Y4
1 1 1 1 1 1 1 1
C8191 C8192 C8193 C8194 C8182 C8183 C8198 C8199 T12 NC
Y5
0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF
10% 10% 10% 10% 10% 10% 10% 10%
T14 NC
Y6
2
16V
X7R-CERM
2
16V
X7R-CERM
2
16V
X7R-CERM
2
16V
X7R-CERM
2
16V
X7R-CERM
2
16V
X7R-CERM
2
16V
X7R-CERM
2
16V
X7R-CERM
T16 NC
Y7
402 402 402 402 402 402 402 402
T19 NC
Y8
T21 NC
AA1
T23 NC
AA2
U13 NC
AA3
GPU VCORE DE-COUPLING U15 NC
AA4
U17 NC
AA5
U18 NC
AA6
U20 NC
AA7
U22 NC
AA8
V13 NC
V15
B B
GPU FB DE-COUPLING
OMIT TABLE
76 75 72 6 =PP1V35 GPU FBVDDQ
EDP = 6500 MA
1 1
U8000
C8125 C8126 1
C8101 1
C8102
=PP1V35 GPU FBVDDQ
NV-GK107 =PP1V35 GPU FBVDDQ
76 75 72 6 6 72 75 76
22UF 22UF 10UF 10UF BGA
20% 20%
4V 4V
20% 20% (7 OF 10)
2 2 4V 4V
AA27 H18
X5R X5R 2 X5R
2 X5R
0402 0402
402 402
AA30 H19
AB27 H20
AB33 H21
AC27 H22
AD27 H23
AE27 H24
1 C8105 1 C8106 1 C8107 1 C8132 1
C8111 1
C8112 1
C8113 1
C8131 AF27 H8
4 7UF 4 7UF 4 7UF 4 7UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 10% 10% 10% 10% AG27 H9
6 3V 6 3V 6 3V 6 3V 25V 25V 25V 16V
2 X5R-CERM1
2 X5R-CERM1
2 X5R-CERM1
2 X5R-CERM1
2 X7R
2 X7R
2 X7R
2 X5R B13 L27
402 402 402 402 0603 0603 0603 603
B16 M27
FBVDDQ FBVDDQ
B19 N27
E13 P27
E16 R27
E19 T27
A 1
C8122 1
C8123 1
C8124 1
C8130 H10 T30
SYNC MASTER=D7 TONY SYNC DATE=01/10/2012 A
0 1UF 0 1UF 0 1UF 0 1UF H11 T33 PAGE TITLE
2
10%
16V
X7R-CERM
402
2
10%
16V
X7R-CERM
402
2
10%
16V
X7R-CERM
402
2
10%
16V
X7R-CERM
402
H12
H13
V27
W27
KEPLER CORE/FB POWER
DRAWING NUMBER SIZE
H14 W30
H15 W33
REVISION
R
H16 Y27
4.2.0
81 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
NOTE GDDR5 MODE H MAPPING
99 75 73 FB A0 RESET L 99 75 73 FB A1 RESET L Power aliases required by this page:
- PP1V35 GPU S0 FB
- PP1V05 GPU PEX IOVDD
OMIT TABLE
1 1
R8250 R8251
U8000 10K 10K OMIT TABLE Signal aliases required by this page:
NV-GK107 1%
1/20W
1%
1/20W (NONE)
BGA MF MF
(3 OF 10) 2
201
2
201 U8000
L28
MEM INTERFACE A U30
NV-GK107
99 75 BI FB A0 DQ<0> FBA_D0 FBA_CMD0 FB A0 CS L OUT 75 99 BGA (NONE)
99 75 FB A0 DQ<1> M29
FBA_D1 FBA_CMD1 T31 FB A0 A<3> 75 99
(4 OF 10)
BI OUT MEM INTRERFACE B
L29 U29 G9 D13
99 75 BI FB A0 DQ<2> FBA_D2 FBA_CMD2 FB A0 A<2>
OUT 75 99 99 76 BI FB B0 DQ<0> FBB_D0 FBB_CMD0 FB B0 CS L
OUT 76 99
D 99 75
99 75
BI
BI
FB A0 DQ<3>
FB A0 DQ<4>
M28
N31
FBA_D3
FBA_D4
FBA_CMD3
FBA_CMD4
R34
R33
FB A0 A<4>
FB A0 A<5>
OUT
OUT
75 99
75 99 =PP1V35 GPU S0 FB 6 73
99 76
99 76
BI
BI
FB B0 DQ<1>
FB B0 DQ<2>
E9
G8
FBB_D1
FBB_D2
FBB_CMD1
FBB_CMD2
E14
F14
FB B0 A<3>
FB B0 A<2>
OUT
OUT
76 99
76 99
L8201
30-OHM-25%-5A-0.01-OHM MIN LINE WIDTH 0 6 MM
D
P29 U32 F9 A12 MIN NECK WIDTH 0 2 MM
99 75 BI FB A0 DQ<5> FBA_D5 FBA_CMD5 FB A0 WE L
OUT 75 99 99 76 BI FB B0 DQ<3> FBB_D3 FBB_CMD3 FB B0 A<4> OUT 76 99 =PP1V05 GPU PEX IOVDD 1 2 VOLTAGE 1 05V PP1V05 GPU FB PLL AVDD
R29 U33 F11 B12 6 73
OUT 75 99
1 1
99 76 BI FB B0 DQ<4> FBB_D4 FBB_CMD4 FB B0 A<5>
OUT 76 99 73
79 0603
P28 U28 R8252 R8253 G11 C14 CRITICAL
99 75 BI FB A0 DQ<7> FBA_D7 FBA_CMD7 FB A0 A<6> OUT 75 99 99 76 BI FB B0 DQ<5> FBB_D5 FBB_CMD5 FB B0 WE L OUT 76 99
10K 10K ESR = 0 05OHM
J28 V28 F12 B14 1 1 1 1
99 75 BI FB A0 DQ<8> FBA_D8 FBA_CMD8 FB A0 ABI L
OUT 75 99 1% 1% 99 76 BI FB B0 DQ<6> FBB_D6 FBB_CMD6 FB B0 A<7> OUT 76 99 C8201 C8202 C8203 C8204
1/20W 1/20W
H29 V29 G12 G15 22UF 1UF 0 1UF 0 1UF
99 75 BI FB A0 DQ<9> FBA_D9 FBA_CMD9 FB A0 A<8> OUT 75 99 MF MF 99 76 BI FB B0 DQ<7> FBB_D7 FBB_CMD7 FB B0 A<6> OUT 76 99
20% 20% 10% 10%
201 201
J29 V30 2 2 G6 F15 4V 6 3V 16V 16V
99 75 BI FB A0 DQ<10> FBA_D10 FBA_CMD10 FB A0 A<0> OUT 75 99 99 76 BI FB B0 DQ<8> FBB_D8 FBB_CMD8 FB B0 ABI L OUT 76 99 2 X5R
2 X5R
2 X7R-CERM
2 X7R-CERM
H28 U34 F5 E15 402 0201 402 402
99 75 BI FB A0 DQ<11> FBA_D11 FBA_CMD11 FB A0 A<1> OUT 75 99 99 76 BI FB B0 DQ<9> FBB_D9 FBB_CMD9 FB B0 A<8> OUT 76 99
G29 U31 E6 D15
99 75 BI FB A0 DQ<12> FBA_D12 FBA_CMD12 FB A0 RAS L
OUT 75 99 99 75 73 FB A0 CKE L 99 76 BI FB B0 DQ<10> FBB_D10 FBB_CMD10 FB B0 A<0>
OUT 76 99
E31 V34 F6 A14
99 75 BI FB A0 DQ<13> FBA_D13 FBA_CMD13 FB A0 RESET L
OUT 73 75 99 99 76 BI FB B0 DQ<11> FBB_D11 FBB_CMD11 FB B0 A<1>
OUT 76 99
E32 V33 F4 D14
99 75 BI FB A0 DQ<14> FBA_D14 FBA_CMD14 FB A0 CKE L
OUT 73 75 99 99 76 BI FB B0 DQ<12> FBB_D12 FBB_CMD12 FB B0 RAS L
OUT 76 99
F30 Y32 99 75 73 FB A1 CKE L G4 A15
99 75 BI FB A0 DQ<15> FBA_D15 FBA_CMD15 FB A0 CAS L OUT 75 99 99 76 BI FB B0 DQ<13> FBB_D13 FBB_CMD13 FB B0 RESET L
OUT 73 76 99
C34 AA31 E2 B15
99 75 BI FB A0 DQ<16> FBA_D16 FBA_CMD16 FB A1 CS L OUT 75 99 99 76 BI FB B0 DQ<14> FBB_D14 FBB_CMD14 FB B0 CKE L
OUT 73 76 99
D32 AA29 F3 C17
OUT 75 99 99 76 BI FB B0 DQ<15> FBB_D15 FBB_CMD15 FB B0 CAS L
OUT 76 99 L8202
B33 AA28 C2 D18 30-OHM-25%-5A-0.01-OHM MIN LINE WIDTH 0 6 MM
99 75 BI FB A0 DQ<18> FBA_D18 FBA_CMD18 FB A1 A<2> OUT 75 99 99 76 BI FB B0 DQ<16> FBB_D16 FBB_CMD16 FB B1 CS L OUT 76 99 MIN NECK WIDTH 0 2 MM
=PP1V05 GPU PEX IOVDD VOLTAGE 1 05V
99 75 FB A0 DQ<19> C33
FBA_D19 FBA_CMD19 AC34 FB A1 A<4> 75 99 99 76 FB B0 DQ<17> D4
FBB_D17 FBB_CMD17 E18 FB B1 A<3> 76 99 79 73 6
1 2 PP1V05 GPU FB DLL AVDD 73
BI OUT BI OUT
F33 AC33 D3 F18 0603
OUT 75 99 99 76 BI FB B0 DQ<18> FBB_D18 FBB_CMD18 FB B1 A<2>
OUT 76 99 CRITICAL
F32 AA32 C1 A20
99 75 BI FB A0 DQ<21> FBA_D21 FBA_CMD21 FB A1 WE L
OUT 75 99 =PP1V35 GPU S0 FB 6 73 99 76 BI FB B0 DQ<19> FBB_D19 FBB_CMD19 FB B1 A<4> OUT 76 99 ESR = 0 05OHM
1 1 1
H33 AA33 B3 B20 C8208 C8209 C8205
OUT 75 99
1
NOSTUFF 99 76 BI FB B0 DQ<20> FBB_D20 FBB_CMD20 FB B1 A<5> OUT 76 99
22UF 1UF 0 1UF
99 75 FB A0 DQ<23> H32
FBA_D23 FBA_CMD23 Y28 FB A1 A<6> 75 99
R8258 99 76 FB B0 DQ<21> C4
FBB_D21 FBB_CMD21 C18 FB B1 WE L 76 99
20% 20% 10%
BI OUT PLACE_NEAR U8000 H26 8 4MM BI OUT 4V 6 3V 16V
P34 1 33K 2 2 2
Y29 B5 B18 X5R X5R X7R-CERM
99 75 BI FB A0 DQ<24> FBA_D24 FBA_CMD24 FB A1 ABI L
OUT 75 99 1% 99 76 BI FB B0 DQ<22> FBB_D22 FBB_CMD22 FB B1 A<7>
OUT 76 99 402 0201 402
1/20W
P32 W31 C5 G18
OUT 75 99 MF PLACE_NEAR U8000 H26 8 4MM 99 76 BI FB B0 DQ<23> FBB_D23 FBB_CMD23 FB B1 A<6>
OUT 76 99
201
P31 Y30 2 A11 G17
99 75 BI FB A0 DQ<26> FBA_D26 FBA_CMD26 FB A1 A<0> OUT 75 99 99 76 BI FB B0 DQ<24> FBB_D24 FBB_CMD24 FB B1 ABI L
OUT 76 99
FB VREF 73
P33 AA34 C11 F17
OUT 76 99
L31 Y31 D11 D16
99 75 BI FB A0 DQ<28> FBA_D28 FBA_CMD28 FB A1 RAS L
OUT 76 99
L34 Y34 NOSTUFF NOSTUFF B11 A18
1
99 75 BI FB A0 DQ<29> FBA_D29 FBA_CMD29 FB A1 RESET L
OUT 73 75 99 R8259 99 76 BI FB B0 DQ<27> FBB_D27 FBB_CMD27 FB B1 A<1>
OUT 76 99
FB PLL & DLL VDD
C 99 75
99 75
BI FB A0 DQ<30>
FB A0 DQ<31>
L32
L33
FBA_D30
FBA_D31
FBA_CMD30
FBA_CMD31
Y33
V31
FB A1 CKE L
FB A1 CAS L
OUT 73 75 99
75 99
1 33K
1%
1
C8260
0 1UF
10%
99 76
99 76
BI FB B0 DQ<28>
FB B0 DQ<29>
D8
A8
FBB_D28
FBB_D29
FBB_CMD28
FBB_CMD29
D17
A17
FB B1 RAS L
FB B1 RESET L
OUT 76 99
73 76 99
C
BI OUT 1/20W
6 3V BI OUT
MF 2
AG28 X5R C8 B17
99 75 BI FB A1 DQ<0> FBA_D32 R30 2
201
201
99 76 BI FB B0 DQ<30> FBB_D30 FBB_CMD30 FB B1 CKE L OUT 73 76 99
AF29 FBA_CLK0 FB A0 CLK P
OUT 75 99 B8 E17
99 75 BI FB A1 DQ<1> FBA_D33 R31 99 76 BI FB B0 DQ<31> FBB_D31 FBB_CMD31 FB B1 CAS L
OUT 76 99
AG29 FBA_CLK0* FB A0 CLK N
OUT 75 99 F24
99 75 BI FB A1 DQ<2> FBA_D34 AB31 99 76 BI FB B1 DQ<0> FBB_D32 D12 99 76 73 FB B0 RESET L 99 76 73 FB B1 RESET L
AF28 FBA_CLK1 FB A1 CLK P
OUT 75 99 PLACE_NEAR U8000 H26 8 4MM
G23 FBB_CLK0 FB B0 CLK P
OUT 76 99
99 75 BI FB A1 DQ<3> FBA_D35 AC31 99 76 BI FB B1 DQ<1> FBB_D33 E12
AD30 FBA_CLK1* FB A1 CLK N OUT 75 99
E24 FBB_CLK0* FB B0 CLK N
OUT 76 99
99 75 BI FB A1 DQ<4> FBA_D36 99 76 BI FB B1 DQ<2> FBB_D34 E20 1 1
AD29 G24 FBB_CLK1 FB B1 CLK P
OUT 76 99 R8254 R8255
99 75 BI FB A1 DQ<5> FBA_D37 P30 99 76 BI FB B1 DQ<3> FBB_D35 F20
AC29 FBA_DQM0 FB A0 DBI L<0>
BI 75 99
D21 FBB_CLK1* FB B1 CLK N
OUT 76 99 10K 10K
99 75 BI FB A1 DQ<6> FBA_D38 F31 FB VREF GEN (TEST ONLY) 99 76 BI FB B1 DQ<4> FBB_D36 1% 1%
AD28 FBA_DQM1 FB A0 DBI L<1>

BI 75 99
E21 1/20W 1/20W
99 75 BI FB A1 DQ<7> FBA_D39 F34 99 76 BI FB B1 DQ<5> FBB_D37 E11 MF MF
AJ29 FBA_DQM2 FB A0 DBI L<2>

BI 75 99 G21 FBB_DQM0 FB B0 DBI L<0> BI 76 99
2
201
2
201
99 75 BI FB A1 DQ<8> FBA_D40 M32 99 76 BI FB B1 DQ<6> FBB_D38 E3
AK29 FBA_DQM3 FB A0 DBI L<3>
BI 75 99
F21 FBB_DQM1 FB B0 DBI L<1>
BI 76 99
99 75 BI FB A1 DQ<9> FBA_D41 AD31 99 76 BI FB B1 DQ<7> FBB_D39 A3
AJ30 FBA_DQM4 FB A1 DBI L<0> BI 75 99
G27 FBB_DQM2 FB B0 DBI L<2>
BI 76 99
99 75 BI FB A1 DQ<10> FBA_D42 AL29 99 76 BI FB B1 DQ<8> FBB_D40 C9
AK28 FBA_DQM5 FB A1 DBI L<1> BI 75 99
D27 FBB_DQM3 FB B0 DBI L<3> BI 76 99
99 75 BI FB A1 DQ<11> FBA_D43 AM32 99 76 BI FB B1 DQ<9> FBB_D41 F23
AM29 FBA_DQM6 FB A1 DBI L<2>
BI 75 99
G26 FBB_DQM4 FB B1 DBI L<0>
BI 76 99
99 75 BI FB A1 DQ<12> FBA_D44 AF34 99 76 BI FB B1 DQ<10> FBB_D42 F27
AM31 FBA_DQM7 FB A1 DBI L<3> BI 75 99 E27 FBB_DQM5 FB B1 DBI L<1>
BI 76 99 =PP1V35 GPU S0 FB 6 73
99 75 BI FB A1 DQ<13> FBA_D45 99 76 BI FB B1 DQ<11> FBB_D43 C30
AN29 E29 FBB_DQM6 FB B1 DBI L<2>
BI 76 99
99 75 BI FB A1 DQ<14> FBA_D46 M30 99 76 BI FB B1 DQ<12> FBB_D44 A24
AM30 FBA_DQS_RN0 NC F29 FBB_DQM7 FB B1 DBI L<3>
BI 76 99
99 75 BI FB A1 DQ<15> FBA_D47 H30 99 76 BI FB B1 DQ<13> FBB_D45 1 1
AN31 FBA_DQS_RN1 NC E30
R8256 R8257
99 75 BI FB A1 DQ<16> FBA_D48 E34 99 76 BI FB B1 DQ<14> FBB_D46 D9 10K 10K
AN32 FBA_DQS_RN2 NC D30 FBB_DQS_RN0 NC 1% 1%
99 75 BI FB A1 DQ<17> FBA_D49 M34 99 76 BI FB B1 DQ<15> FBB_D47 E4 1/20W 1/20W
AP30 FBA_DQS_RN3 NC A32 FBB_DQS_RN1 NC MF MF
99 75 BI FB A1 DQ<18> FBA_D50 AF30 99 76 BI FB B1 DQ<16> FBB_D48 B2 201 201
AP32 FBA_DQS_RN4 NC C31 FBB_DQS_RN2 NC 2 2
99 75 BI FB A1 DQ<19> FBA_D51 AK31 99 76 BI FB B1 DQ<17> FBB_D49 A9
AM33 FBA_DQS_RN5 NC C32 FBB_DQS_RN3 NC
99 75 BI FB A1 DQ<20> FBA_D52 AM34 99 76 BI FB B1 DQ<18> FBB_D50 D22
AL31 FBA_DQS_RN6 NC B32 FBB_DQS_RN4 NC 99 76 73 FB B0 CKE L
99 75 BI FB A1 DQ<21> FBA_D53 AF32 99 76 BI FB B1 DQ<19> FBB_D51 D28
AK33 FBA_DQS_RN7 NC D29 FBB_DQS_RN5 NC
99 75 BI FB A1 DQ<22> FBA_D54 99 76 BI FB B1 DQ<20> FBB_D52 A30
AK32 A29 FBB_DQS_RN6 NC
99 75 BI FB A1 DQ<23> FBA_D55 M31 99 76 BI FB B1 DQ<21> FBB_D53 B23 99 76 73 FB B1 CKE L
FBA_DQS_WP0 FB A0 EDC<0> 75 99 FBB_DQS_RN7 NC
B 99 75
99 75
BI
BI
FB A1 DQ<24>
FB A1 DQ<25>
AD34
AD32
FBA_D56
FBA_D57
FBA_DQS_WP1 G31
E33
FB A0 EDC<1>
IN
IN 75 99 =PP1V35 GPU S0 FB 6 73
99 76
99 76
BI
BI
FB B1 DQ<22>
FB B1 DQ<23>
C29
B29
FBB_D54
FBB_D55 D10
B
AC30 FBA_DQS_WP2 FB A0 EDC<2> IN 75 99
B21 FBB_DQS_WP0 FB B0 EDC<0>
IN 76 99
99 75 BI FB A1 DQ<26> FBA_D58 M33 99 76 BI FB B1 DQ<24> FBB_D56 D5
AD33 FBA_DQS_WP3 FB A0 EDC<3>
IN 75 99 C23 FBB_DQS_WP1 FB B0 EDC<1> IN 76 99
99 75 BI FB A1 DQ<27> FBA_D59 AE31 99 76 BI FB B1 DQ<25> FBB_D57 C3
AF31 FBA_DQS_WP4 FB A1 EDC<0>
IN 75 99
A21 FBB_DQS_WP2 FB B0 EDC<2>
IN 76 99 MEM VREFC & VREFD SWITCH
99 75 BI FB A1 DQ<28> FBA_D60 AK30 1
NOSTUFF 1
NOSTUFF 99 76 BI FB B1 DQ<26> FBB_D58 B9
AG34 FBA_DQS_WP5 FB A1 EDC<1> IN 75 99
R8203 R8202 C21 FBB_DQS_WP3 FB B0 EDC<3> IN 76 99
99 75 BI FB A1 DQ<29> FBA_D61 AN33 99 76 BI FB B1 DQ<27> FBB_D59 E23
AG32 FBA_DQS_WP6 FB A1 EDC<2>
IN 75 99 60 4 60 4
IN 76 99
99 75 BI FB A1 DQ<30> FBA_D62 AF33 1% 1% 99 76 BI FB B1 DQ<28> FBB_D60 E28
AG33 FBA_DQS_WP7 FB A1 EDC<3>
IN 75 99 1/20W 1/20W
C24 FBB_DQS_WP5 FB B1 EDC<1>
IN 76 99
99 75 BI FB A1 DQ<31> FBA_D63 MF MF 99 76 BI FB B1 DQ<29> FBB_D61 B30 76 75 OUT FB SW LEG
K27 2
201
2
201
IN 76 99
K31 FB_DLL_AVDD PP1V05 GPU FB DLL AVDD 73 99 76 BI FB B1 DQ<30> FBB_D62 A23 CRITICAL
99 75 OUT FB A0 WCLK P<0> FBA_WCK01 U27 C26 FBB_DQS_WP7 FB B1 EDC<3> IN 76 99
L30 FBA_PLL_AVDD PP1V05 GPU FB PLL AVDD 73 99 76 BI FB B1 DQ<31> FBB_D63 Q8265
99 75 OUT FB A0 WCLK N<0> FBA_WCK01*
FBA_DEBUG R28 GPU FBA DEBUG0 99 76 FB B0 WCLK P<0> F8
FBB_WCK01 3 D SSM3K15AMFVAPE
H34 1 OUT H17 VESM
99 75 OUT FB A0 WCLK P<1> FBA_WCK23 AC28 R8270 E8 FBB_PLL_AVDD 73 PP1V05 GPU FB PLL AVDD
J34 FBA_DEBUG GPU FBA DEBUG1 99 76 OUT FB B0 WCLK N<0> FBB_WCK01*
99 75 OUT FB A0 WCLK N<1> FBA_WCK23* 100 G14
J27 5% A5 FBB_DEBUG0 GPU FBB DEBUG0 73
AG30 FB_CAL_PD_VDDQ FB CAL PD VDDQ 73 1/20W 99 76 OUT FB B0 WCLK P<1> FBB_WCK23 G20
99 75 OUT FB A1 WCLK P<0> FBA_WCK45 H27 MF A6 FBB_DEBUG1 GPU FBB DEBUG1 73
1 1
AG31 FB_CAL_PU_GND FB CAL PU GND 73
R8201 2
201 99 76 OUT FB B0 WCLK N<1> FBB_WCK23* C8206 C8207
99 75 OUT FB A1 WCLK N<0> FBA_WCK45* H25 1 2
PLACE_NEAR U8000 H25 8 4MM
H26 1UF 0 1UF 2 S G 1
FB_CAL_TERM_GND FB CAL TERM GND
NOSTUFF D24 FB_VREF FB VREF 73
20% 10%
AJ34 99 76 OUT FB B1 WCLK P<0> FBB_WCK45 6 3V 6 3V
GPU ALT VREF IN 78
99 75 OUT FB A1 WCLK P<1> FBA_WCK67 E1
60 4 1% 1/20W MF 201
D25 C12 2 X5R
2 X5R
AK34 FB_CLAMP FB CLAMP 99 76 OUT FB B1 WCLK N<0> FBB_WCK45* FBB_CMD_RFU0 NC 0201 201
99 75 OUT FB A1 WCLK N<1> FBA_WCK67* R8261 C20 1
R32 1
10K
2 B27 FBB_CMD_RFU1 NC R8260
J30 FBA_CMD_RFU NC 99 76 OUT FB B1 WCLK P<1> FBB_WCK67
NC FBA_WCKB01 AC32 C27
10K
J31 FBA_CMD_RFU NC MF 1% 1/20W 201 99 76 OUT FB B1 WCLK N<1> FBB_WCK67* 5%
NC FBA_WCKB01* 1/20W
F1 D6 MF
J32 FB_VDDQ_SENSE SNS GPUVDDQ P
OUT 74 97
NC FBB_WCKB01 2 201
NC FBA_WCKB23 D7
J33 F2 NC FBB_WCKB01*
NC FBA_WCKB23* FB_GND_SENSE SNS GPUVDDQ N OUT 74 97
C6
AH31 NC FBB_WCKB23
NC FBA_WCKB45 B6
AJ31 NC FBB_WCKB23*
NC FBA_WCKB45* PLACE CLOSE TO BGA
F26
A NC
AJ32
AJ33
FBA_WCKB67
FBA_WCKB67*
73 FB CAL PU GND =PP1V35 GPU S0 FB 6 73
1
R8271
100
NC
NC
E26
FBB_WCKB45
FBB_WCKB45*
=PP1V35 GPU S0 FB 6 73

NC 5% PAGE TITLE
A26
1
R8204
1
R8205 2
1/20W
MF
201
NC
NC
A27
FBB_WCKB67
FBB_WCKB67* 1
NOSTUFF 1
NOSTUFF
KEPLER FRAME BUFFER I/F
NOSTUFF R8206 R8207 DRAWING NUMBER SIZE
40 2 40 2
PLACE_NEAR U8000 H27 8 4MM 1%
1/20W
1%
1/20W
PLACE_NEAR U8000 J27 8 4MM 60 4
1%
60 4
1% Apple Inc. 051-9509 D
MF MF 1/20W 1/20W REVISION
R
2
201
2
201
2
MF
201
2
MF
201 4.2.0
FB CAL PD VDDQ 73 THE INFORMATION CONTAINED HEREIN IS THE
73 GPU FBB DEBUG0 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
73 GPU FBB DEBUG1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
82 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
6 =PP12V_S0_REG_GPU_VDDQ_S0
6 =PP5V_S0_REG_GPU_VDDQ_S0
CRITICAL
1
R83501 1
R8351 C8360
270UF
97 73 IN SNS_GPUVDDQ_P 5%
10
5%
2.2 20%
2 16V
GPU VDDQ SUPPLY
1/8W 1/8W ELEC
MF-LF MF-LF 8X9-TH1 VOUT = 1.5V / 1.35V
97 73 IN SNS_GPUVDDQ_N 805 2 2 805
97 REG_BOOT_GPUVDDQ_RC 10 A MAX OUTPUT
97 REG_VCC_U8350 97 REG_PVCC_U8350
SIGNAL_MODEL=EMPTY
<Ra>
SIGNAL_MODEL=EMPTY
<Ra> R83661 1 C8366 F = ??? KHZ
1 C8351 2.2 0.1UF
1 1 10%
R8380 R8385 5%
D 2.32K
1% 1%
2.32K 10%
16V
2 X5R
2.2UF 1/10W
MF-LF
603 2
2 16V
X7R-CERM
402
EMC
Q8360.2:3MM
EMC
Q8360.2:3MM D
1/16W
MF-LF
1/16W
MF-LF C8350 1 603 1 C8361 1 C8362
402 2 2 402 1UF 1UF 1UF
10% 10% 10%
16V 25V 25V
2 X5R 2 X5R
19
20
X5R 2 402 402
402
GPIO_16 VID 1 VID 0 GPU VDDQ
VCC PVCC
0 0 1.5 V
U8350 2
CRITICAL
1 0 1.35 V
ISL95870AH
60 PM_EN_REG_GPU_VDDQ_S0 15 EN UTQFN
BOOT 18 97 REG_BOOT_GPUVDDQ
Q8360 CRITICAL
IN FDMS3602S
CRITICAL POWER56 L8360
REG GPUVDDQ FB 10 FB UGATE 17 REG UGATE GPUVDDQ 1
97 97
1.0UH-20%-15A-0.0065OHM
97 REG_GPUVDDQ_SREF 7 SREF PHASE 16 97 REG_PHASE_GPUVDDQ PHASE 7 1 2 PP1V5R1V35_S0_GPU_REG OUT 6
PIC0605H-SM
97 74 REG_GPUVDDQ_VO 12 VO LGATE 1 97 REG_LGATE_GPUVDDQ NOSTUFF
C8390 1 R83871 1 C8367
C8368 1 1
R8368 CRITICAL CRITICAL
0.047UF 301K REG GPUVDDQ OCSET 11 OCSET 6 1000PF 200 1 1 1 C8372
10% 1%
97 74
0.001UF 5% 5%
C8370 C8371
16V 1/16W 10% 25V 330UF-0.009OHM 330UF-0.009OHM 10UF
X7R 2 MF-LF 74 REG_GPUVDDQ_PGOOD 14 PGOOD 2 50V NP0-C0G 2 1/10W
MF-LF 20% 20% 20%
402 402 2 CERM 402 2 2V 2 2V 6.3V
402 2 603 POLY POLY
2 X5R
97 REG_GPUVDDQ_RTN 4 RTN 3 4 5 CASE-D2-HF CASE-D2-HF 603
REG_SNUBBER_GPUVDDQ
97 REG GPUVDDQ FSEL 13 FSEL
NOSTUFF NOSTUFF NOSTUFF
<Rb> <Rb> REG_GPUVDDQ_SET0 8 SET0 1
97
R8367
C8380 1 R83811 1
R8386 1 C8385 9 SET1 2.2 L8360.1:3MM
10PF 2.74K 2.74K 10PF 97 REG_GPUVDDQ_SET1 5%
5%
50V
1%
1/16W
1%
1/16W
5%
50V R83881 1 6 VID0
1/10W
MF-LF
R83911
CERM 2
402
MF-LF MF-LF 2 CERM
402 150K
R8390 2 603 12.1K R8391.2:3MM
402 2 2 402 0 1%
1% 5% 5 VID1 1/16W C8391
1/16W 1/16W MF-LF
C MF-LF
402 2 MF-LF
2 402 R8394
402 2 0.012UF
1 2
L8360.2:3MM
74 68 66 65 62 6 =PP3V3_S0_VRD C
0 GND PGND
97 REG_GPUVDDQ_SET1_R 1 2 10% 1 1
25V R8392 R8393
2
5% X7R 12.1K 20K
R83891 1/16W
MF-LF To regulator: 402 1% 5%
27K 402 1/16W 1/16W
1% MF-LF MF-LF
1/16W 97 74 REG_GPUVDDQ_OCSET 2 402 2 402
MF
402 2
78 IN FBVDD ALTVO XW8350
SM 97 74 REG_GPUVDDQ_VO 74 REG_GPUVDDQ_PGOOD PM_PGOOD_REG_GPU_VDDQ_S0 OUT 60
97 AGND GPUVDDQ 2 1 MAKE_BASE=TRUE
Vout = 0.5 * (1 + Ra / Rb) U8360.3:1MM
6 =PP12V_S0_REG_GPU_P1V05_S0
6 =PP5V_S0_REG_GPU_P1V05_S0
97 79 IN SNS_GPU_PEX_IOVDD_P
EMC EMC
CRITICAL Q8310.1:3MM Q8310.1:3MM
CRITICAL
1 1 C8301 97 REG_BOOT_GPU_P1V05S0_RC C8310 1 1 C8311 1 C8312
R8300 180UF 1UF 1UF
2.2
5%
10UF
20% 20%
16V 2
10%
2 25V
10%
2 25V
GPU 1V05 SUPPLY
SNS_GPU_PEX_IOVDD_N 1/16W 2 10V
X5R POLY X5R
402
X5R
402
97 79 IN MF-LF TH VOUT = 1.05V
603
402 2 1 C8316
0.1UF
97 REG_VCC_U8300 R83161 10%
3.43 A MAX OUTPUT
1 2 16V
X5R F = 500 KHZ
5% 402
13
14
1/16W
C8300 1 MF-LF
B SIGNAL_MODEL=EMPTY
1
R8330 1
SIGNAL_MODEL=EMPTY
R8335
2.2UF
10%
VCC PVCC
402 2
CRITICAL CSD598873D
Q8310 B
3.01K 3.01K
16V 2
X5R U8300 SON
603 376S1038
1% 1% ISL95870
1/16W 1/16W OMIT_TABLE VIN 1
MF-LF MF-LF 3 UTQFN
402 2 2 402 60 IN PM_EN_REG_GPU_P1V05_S0 EN BOOT 12 97 REG_BOOT_GPU_P1V05S0 R8311
<Ra> <Ra> 6 CRITICAL 1
97 REG_GPU_P1V05S0_FB FB UGATE 11 97 REG_UGATE_GPU_P1V05S0_R 2 1 97 REG_UGATE_GPU_P1V05S0 3 TG CRITICAL
REG GPU P1V05S0 SREF 4 SREF PHASE 10 REG PHASE GPU P1V05S0
5%
1/10W
6 L8310 PP1V05 S0 GPU_REG
1
97 97
MF-LF 4 TGR VSW 7 1.0UH-20%-15A-0.0065OHM 6
R8336 REG_GPU_P1V05S0_VO 8 VO LGATE 15

603 8 REG_PHASE_GPU_P1V05S0_L 1 2
2.74K 97 74 97
1% PIC0605H-SM
1/16W 97 74 REG_GPU_P1V05S0_OCSET 7 OCSET NOSTUFF
MF-LF
2 402 9 PGOOD 5
1 C8317 CRITICAL CRITICAL
PGND
REG_GPU_P1V05S0_PGOOD REG_LGATE_GPU_P1V05S0 BG
<Rb> 74 97
0.001UF R83201 C8320 1
C8321 1 1
C8322
10% 200 1000PF
97 REG GPU P1V05S0 RTN 2 RTN 50V
2 CERM 1% 5%
330UF 0 009OHM 330UF 0 009OHM
25V 2 20% 20%
9 402 1/16W 2V 2 2 2V
5 FSEL MF-LF NP0-C0G POLY POLY
97 REG_GPU_P1V05S0_FSEL 402 2 402 CASE-D2-HF CASE-D2-HF
R83311 C8330 1 GND PGND
REG SNUBBER GPU P1V05S0 XW8302 2 PLACE NEAR L8310 2:3MM PLACE NEAR L8310 2:3MM
2.74K 10PF SM
1
16
1% 5% NOSTUFF
1/16W 50V NOSTUFF
MF-LF CERM 2 1
1
R8317 PLACE NEAR L8310 2 1 5MM
402 2 402 1 C8335 1 C8340 R8340 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
2.2
1 2 XW8301
10PF 0.047UF 0 5%
REG_GPU_P1V05S0_OCSET_R SM
<Rb> 5% 10% 5% 1/10W 97
2 50V
CERM 2 16V
X7R
1/20W
MF 110S0568 1 RES MF 3 32 OHM 1/10W 1 603 LF R8311 CRITICAL MF-LF
2 603
402 402 2 201 XW8300
SM
1
P1V05_GPU_AGND 1 2
R83411
97
6.98K
PLACE NEAR U8310 1 1mm
1%
1/20W
Vout = 0.5V * (1 + Ra / Rb) MF
201 2 C8341 97 REG_GPU_P1V05S0_VO_R
=PP3V3 S0 VRD 0.022UF
A 74 68 66 65 62 6
PAGE TITLE
10%
16V
X5R-X7R-CERM 1
R8342
1V05 GPU POWER SUPPLY
R83431 0402
6.98K DRAWING NUMBER SIZE
10K 1% 051-9509 D
5%
1/16W 1/20W
MF
Apple Inc. REVISION
MF-LF
402 2 97 74 REG_GPU_P1V05S0_OCSET 2 201 R
4.2.0
97 74 REG_GPU_P1V05S0_VO
74 REG_GPU_P1V05S0_PGOOD PM_PGOOD_REG_P1V05_GPU OUT 61
83 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
U8400 U8450
Power aliases required by this page
This memory device is in Mirrored Mode. 32MX32-1.5GHZ-MFH
PP1V5R1V35 S0 FB VDD 32MX32-1.5GHZ-MFL BGA
BGA K4G10325FG-HC03
Signal aliases required by this page K4G10325FG-HC03
K11 (1 OF 2) P13
(NONE)
H11 D2 99 73 IN FB A1 A<2> BA0/A2 DBI1* FB A1 DBI L<1>
BI 73 99
99 73 IN FB A0 A<2> BA0/A2 DBI0* FB A0 DBI L<0> BI 73 99
H10 D13
K10 (1 OF 2) D13 99 73 IN FB A1 A<5> BA1/A5 DBI2* FB A1 DBI L<2> BI 73 99
BOM options provided by this page 99 73 IN FB A0 A<5> BA1/A5 DBI1* FB A0 DBI L<1> BI 73 99
H11 P2
K11 P13 99 73 IN FB A1 A<4> BA2/A4 DBI0* FB A1 DBI L<0> BI 73 99
99 73 IN FB_A0_A<4> BA2/A4 DBI2* FB_A0_DBI_L<2> BI 73 99
K10 D2
H10 P2 99 73 IN FB A1 A<3> BA3/A3 DBI3* FB A1 DBI L<3> BI 73 99
99 73 IN FB A0 A<3> BA3/A3 DBI3* FB A0 DBI L<3> BI 73 99
PLACE NEAR=U8400 J11 8 4MM 99 73 IN FB A1 A<7> H4 A8/A7 DQ0 U4 FB A1 DQ<0> BI 73 99

CK TERMINATION - A0 99 73 IN FB A0 A<7> K4 A8/A7 DQ0 A4 FB A0 DQ<0> BI 73 99
99 73 FB_A1_A<1> K5 A9/A1 DQ1 U2 FB_A1_DQ<1> 73 99
D FB_A0_CLK_P
R8401
40.2 FBA0_CK_MID
R8402
40.2 FB_A0_CLK_N
99 73
99 73
IN
IN
FB A0 A<1>
FB A0 A<0>
H5
H4
A9/A1
A10/A0
DQ1
DQ2
A2
B4
FB A0 DQ<1>
FB A0 DQ<2>
BI
BI
73 99
73 99
99 73
IN
IN FB_A1_A<0> K4
H5
A10/A0 DQ2 T4
T2
FB_A1_DQ<2>
BI
BI 73 99 D
75 73 1 2 1 2 73 75 99 99 73 FB A1 A<6> A11/A6 DQ3 FB A1 DQ<3> 73 99
K5 B2 76 75 72 6 =PP1V35 GPU FBVDDQ IN BI
99 99 73 IN FB A0 A<6> A11/A6 DQ3 FB A0 DQ<3> BI 73 99
J3 N4
1% FBA 1% FBA J3 E4 99 73 IN FB A1 CKE L CKE* DQ4 FB A1 DQ<4> BI 73 99
1/20W 1/20W 99 73 IN FB_A0_CKE_L CKE* DQ4 FB_A0_DQ<4>
BI 73 99
N2
MF
FBA MF
E2 OMIT_TABLE DQ5 FB A1 DQ<5> BI 73 99
201 201 OMIT_TABLE DQ5 FB_A0_DQ<5> BI 73 99
J12 M4
PLACE_NEAR U8400 J12 8 4MM
1 C8490 J12 F4 1 99 75 73 IN FB A1 CLK P CK DQ6 FB A1 DQ<6>
BI 73 99
0.01UF 99 75 73 IN FB_A0_CLK_P CK DQ6 FB_A0_DQ<6> BI 73 99 R8454 J11 M2
10% J11 F2 99 75 73 IN FB A1 CLK N CK* DQ7 FB A1 DQ<7> BI 73 99
99 75 73 IN FB A0 CLK N CK* DQ7 FB A0 DQ<7> BI 73 99 1K
2
10V
5% 99 73 IN FB A1 CS L L12 CS* DQ8 U11 FB A1 DQ<8> BI 73 99
X5R
PLACE_NEAR U8400 J11 8 4MM 99 73 IN FB A0 CS L G12 CS* DQ8 A11 FB A0 DQ<8> BI 73 99 1/20W
201
MF 99 73 IN FB_A1_WE_L G12 WE* DQ9 U13 FB_A1_DQ<9> BI 73 99
99 73 IN FB A0 WE L L12 WE* DQ9 A13 FB A0 DQ<9> BI 73 99 201
2 99 73 FB_A1_CAS_L G3 CAS* DQ10 T11 FB_A1_DQ<10> 73 99
L3 B11 IN BI
99 73 IN FB A0 CAS L CAS* DQ10 FB A0 DQ<10> BI 73 99 FBA L3 T13
G3 B13 99 73 IN FB A1 RAS L RAS* DQ11 FB A1 DQ<11> BI 73 99
99 73 IN FB A0 RAS L RAS* DQ11 FB A0 DQ<11> BI 73 99
J13 N11
J13 E11
FB A1 ZQ ZQ DQ12 FB A1 DQ<12> BI 73 99
FB_A0_ZQ ZQ DQ12 FB_A0_DQ<12>
BI 73 99
J1 N13
J1 E13
FB A1 MF MF (MF=1) DQ13 FB A1 DQ<13> BI 73 99
1
FB_A0_MF MF (MF=0) DQ13 FB_A0_DQ<13> BI 73 99
J10 M11
R8400 J10 F11
FB A1 SEN SEN DQ14 FB A1 DQ<14>
BI 73 99
FB_A0_SEN SEN DQ14 FB_A0_DQ<14> BI 73 99
J2 M13
120 FBA 99 73 IN FB A1 RESET L RESET* DQ15 FB A1 DQ<15> BI 73 99
1% 1 99 73 FB A0 RESET L J2 RESET* DQ15 F13 FB A0 DQ<15> 73 99
1 1
1/20W
R8404 1 IN BI R8450 R8453 DQ16 A11 FB A1 DQ<16> 73 99
MF 120 FBA R8403 DQ16 U11 FB A0 DQ<16> 73 99 120 120 BI
BI J4 ABI* A13
201 2 1% 120 FBA 1% 1% 99 73 IN FB_A1_ABI_L DQ17 FB_A1_DQ<17>
BI 73 99
1/20W 1% 99 73 IN FB A0 ABI L J4 ABI* DQ17 U13 FB A0 DQ<17> BI 73 99 1/20W 1/20W
MF 1/20W MF MF DQ18 B11 FB_A1_DQ<18> BI 73 99
201 2 MF DQ18 T11 FB A0 DQ<18> 73 99 201 201 2
BI R2 B13
201
2 C2 T13 FBA 2 FBA 99 73 BI FB A1 EDC<0> EDC0 DQ19 FB A1 DQ<19> BI 73 99
99 73 BI FB A0 EDC<0> EDC0 DQ19 FB A0 DQ<19> BI 73 99
R13 E11
C13 N11 99 73 BI FB A1 EDC<1> EDC1 DQ20 FB A1 DQ<20> BI 73 99
99 73 BI FB A0 EDC<1> EDC1 DQ20 FB A0 DQ<20> BI 73 99
C13 E13
R13 N13 99 73 BI FB A1 EDC<2> EDC2 DQ21 FB A1 DQ<21> BI 73 99
99 73 BI FB_A0_EDC<2> EDC2 DQ21 FB_A0_DQ<21> BI 73 99
C2 F11
R2 M11 99 73 BI FB A1 EDC<3> EDC3 DQ22 FB A1 DQ<22> BI 73 99
99 73 BI FB_A0_EDC<3> EDC3 DQ22 FB_A0_DQ<22> BI 73 99
F13
M13 DQ23 FB A1 DQ<23> BI 73 99
DQ23 FB A0 DQ<23>
BI 73 99
A4
U4 DQ24 FB A1 DQ<24> BI 73 99
DQ24 FB A0 DQ<24> BI 73 99
P4 WCK01 A2
CK TERMINATION - A1 PLACE_NEAR U8450 J11 8 4MM
D4 WCK01 U2 99 73 IN FB_A1_WCLK_P<0> DQ25 FB_A1_DQ<25>
BI 73 99
99 73 IN FB A0 WCLK P<0> DQ25 FB A0 DQ<25> BI 73 99
P5 WCK01* B4
R8451 R8452 D5 WCK01* T4 99 73 IN FB_A1_WCLK_N<0> DQ26 FB_A1_DQ<26> BI 73 99
99 73 IN FB A0 WCLK N<0> DQ26 FB A0 DQ<26>
BI 73 99
B2
FB_A1_CLK_P 40.2 FBA1_CK_MID 40.2 FB_A1_CLK_N DQ27 FB_A1_DQ<27> BI 73 99
99
73 1 2 1 2 99
73 DQ27 T2 FB A0 DQ<27> BI 73 99
D4 WCK23 E4
C 75
FBA 1%
1/20W
MF
1%
1/20W
MF
FBA
75
99 73
99 73
IN FB A0 WCLK P<1>
FB_A0_WCLK_N<1>
P4 WCK23
P5 WCK23*
DQ28
DQ29
N4
N2
FB A0 DQ<28>
FB_A0_DQ<29>
BI 73 99
73 99
99 73
99 73
IN
IN
FB A1 WCLK P<1>
FB A1 WCLK N<1> D5 WCK23*
DQ28
DQ29 E2
FB A1 DQ<28>
FB A1 DQ<29>
BI
BI
73 99
73 99
C
IN BI F4
201
1
FBA 201
M4 DQ30 FB A1 DQ<30> BI 73 99
PLACE_NEAR U8450 J12 8 4MM C8491 DQ30 FB_A0_DQ<30> BI 73 99
F2
0.01UF M2 DQ31 FB A1 DQ<31> BI 73 99
10%
DQ31 FB A0 DQ<31> BI 73 99
10V
2 X5R
201
U8400 NC A5
U8450 NC A5 NC
NC 32MX32-1.5GHZ-MFH A12/RFU/NC J5 FB_A1_A<8> IN 73 99
32MX32-1.5GHZ-MFL A12/RFU/NC J5 FB A0 A<8>
IN 73 99
BGA NC U5
BGA NC U5 K4G10325FG-HC03 NC
K4G10325FG-HC03 NC
=PP1V35 GPU FBVDDQ C5 (2 OF 2) B5
76 75 72 6
72 6 =PP1V35_GPU_FBVDDQ C5 B5
76 75 (2 OF 2) L11 L5
C10 B10
76 75 72 6 =PP1V35 GPU FBVDDQ L14 L10 76 75 72 6 =PP1V35 GPU FBVDDQ
D11 D10 FBA FBA FBA
FBA FBA FBA 1
C8450 1
C8451 1
C8452 P11 P10
1 1 1 G1 G5
1 FBA
C8400 C8401 C8402 4.7UF 4.7UF 4.7UF R5 T5 1
FBA
4.7UF 4.7UF 4.7UF G4 G10 R8430 20% 20% 20% R8480
20% 20% 20% 549 PLACE_NEAR U8400 J14 8 4MM 2
6 3V
2
6 3V
2
6 3V R10 T10 549
2
6 3V
2
6 3V
2
6 3V G11 H1 1%
X5R X5R X5R
MIN LINE WIDTH=0 25 MM 1% PLACE_NEAR U8450 J14 8 4MM
X5R X5R X5R
MIN LINE WIDTH=0 25 MM 1/20W
402 402 402 C10 B10 MIN NECK WIDTH=0 1 mm 1/20W
402 402 402 G14 H14 MIN NECK WIDTH=0 1 mm MF MF
VDD VSS 201 D11 VSS D10 201
L1 K1 2 VDD 2
G1 G5
L4 K14
FB_A0_VREFC FBA FBA FBA G4 G10 FB_A1_VREFC
FBA FBA FBA L11 L5 75
1
C8453 1
C8454 1
C8455 75
FBA
1
C8403 1
C8404 1
C8405 G11 OMIT_TABLE H1
L14 L10 PLACE_NEAR U8400 J14 8 4MM
4.7UF 4.7UF 4.7UF
4.7UF 4.7UF 4.7UF 20% 20% 20% G14 H14
20% 20% 20% P11 P10 PLACE_NEAR U8400 J14 8 4MM 2
6 3V
2
6 3V
2
6 3V FBA
2
6 3V
2
6 3V
2
6 3V
FBA 1 X5R X5R X5R L1 K1 FBA 1
X5R X5R X5R R5 T5 1
C8431 R8431 1 402 402 402 1
C8481 R8481 1
402 402 402
1.33K R8434 L4 K14 1.33K R8484
R10 T10 820PF 1% 931 820PF 1% 931
10% 10%
50V 1/20W 1% 50V 1/20W 1%
2 MF 1/20W 2 MF 1/20W
OMIT_TABLE CERM
201 MF B1 CERM
201 MF
B1 402 2 FBA FBA FBA FBA 402 2
FBA 2 201 1 1 1 1 E10 2 201
1
FBA 1
FBA 1
FBA 1
FBA B3 FBA C8456 C8457 C8458 C8459
C8406 C8407 C8408 C8409 1UF 1UF 1UF 1UF F1
FB_SW_LEG 73 75 76 FB_SW_LEG 73 75 76
B 2
1UF
20%
6 3V
X5R 2
1UF
20%
6 3V
X5R 2
1UF
20%
6 3V
X5R 2
1UF
20%
6 3V
X5R
B12
B14 PLACE_NEAR U8400 J14 8 4MM
IN
2
20%
6 3V
X5R
0201
2
20%
6 3V
X5R
0201
2
20%
6 3V
X5R
0201
2
20%
6 3V
X5R
0201
F3
F12 A1
PLACE NEAR=U8450 J14 8 4MM
IN
B
0201 0201 0201 0201 D1 A1
F14 C14 PLACE CLOSE TO U8450
D3 A3
G2 E1
D12 A12
FBA FBA FBA FBA G13 E3 =PP1V35_GPU_FBVDDQ
FBA FBA FBA FBA D14 A14 PLACE CLOSE TO U8400 1
C8460 1
C8461 1
C8462 1
C8463 76 75 72 6
1
C8410 1
C8411 1
C8412 1
C8413 H3 E12
E5 C1 1UF 1UF 1UF 1UF
1UF 1UF 1UF 1UF 20% 20% 20% 20% H12 E14
20% 20% 20% 20% E10 C3 2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V X5R X5R X5R X5R K3 F5
X5R X5R X5R X5R F1 C4 0201 0201 0201 0201 FBA
PLACE_NEAR U8450 U10 8 4MM
0201 0201 0201 0201 B3 F10
F3 C11 MIN LINE WIDTH=0 25 MM
K12 H2 1 R8482
F12 C12 MIN NECK WIDTH=0 1 mm
=PP1V35_GPU_FBVDDQ
76 75 72 6
L2 H13 549
F14 C14 1%
FBA FBA FBA FBA L13 K2 1/20W
FBA FBA FBA FBA G2 E1 1
C8464 1
C8465 1
C8466 1
C8467 MF
1 C8414 1 C8415 1 C8416 1 C8417 M1 A3 FB_A1_VREFD 201
G13 E3 1UF 1UF 0.1UF 0.1UF VDDQ 75
2
1UF 1UF 0.1UF 0.1UF VDDQ FBA
20% 20% 10% 10% M3 K13
20% 20% 10% 10% H3 E12 2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
MIN LINE WIDTH=0 25 MM
X5R X5R X5R X5R M12 M5
X5R X5R X5R X5R H12 E14 1 R8432 0201 0201 201 201 PLACE_NEAR U8450 U10 8 4MM
0201 0201 201 201 MIN NECK WIDTH=0 1 mm M14 M10 PLACE_NEAR U8450 A10 8 4MM
K3 F5 549
1% N5 N1
K12 F10 1/20W PLACE_NEAR U8450 U10 8 4MM
MF N10 N3 1
L2 VSSQ H2 FB_A0_VREFD R8483 1
2 201 FBA FBA FBA FBA P1 N12 1 C8482 1 C8483 1.33K R8485
75
FBA FBA FBA FBA L13 H13 1
C8468 1
C8469 1
C8470 1
C8471 1% 931
1 C8418 1 C8419 1 C8420 1 C8421 B12 N14 0.01UF 820PF 1/20W 1%
M1 K2 0.1UF 0.1UF 0.1UF 0.1UF VSSQ 10% 10% MF 1/20W
0.1UF 0.1UF 0.1UF 0.1UF 10% 10% 10% 10% P3 R1 2
10V
2
50V
201 MF
10% 10% 10% 10% M3 K13 2
6 3V
2
6 3V
2
6 3V
2
6 3V X5R CERM 2 201
2
6 3V
2
6 3V
2
6 3V
2
6 3V X5R X5R X5R X5R P12 R3 201 402 FBA 2
FBA
X5R X5R X5R X5R M12 M5 201 201 201 201 FBA FBA
201 201 201 201
FBA FBA P14 R4 FB SW LEG 73 75 76
M14 M10 1
PLACE_NEAR U8400 U10 8 4MM IN
FBA R8433 1 T1 A12
N5 N1 1 1 FBA R8435 PLACE NEAR=U8450 U10 8 4MM
C8432 C8433 1.33K T3 R11
0.01UF 820PF 1% 931
N10 N3 1/20W 1%
10% 10% T12 R12
A 1 FBA
C8422 1 FBA
C8423 1 FBA
C8424 1 FBA
C8425
P1
P3
N12
N14
2
10V
X5R
201
2
50V
CERM
402
MF
2 201
2
1/20W
MF
201
1 FBA
C8472
0.1UF
1 FBA
C8473
0.1UF
1 FBA
C8474
0.1UF
1 FBA
C8475
0.1UF
T14 R14 SYNC MASTER=D7 TONY SYNC DATE=12/13/2011 A
0.1UF 0.1UF 0.1UF 0.1UF 10% 10% 10% 10% B14 U1 PAGE TITLE
P12 R1 6 3V 6 3V 6 3V 6 3V
2
10%
6 3V
X5R
201
2
10%
6 3V
X5R
201
2
10%
6 3V
X5R
201
2
10%
6 3V
X5R
201
P14 R3 PLACE_NEAR U8400 A10 8 4MM
FB_SW_LEG IN 73 75
76
2 X5R
201
2 X5R
201
2 X5R
201
2 X5R
201
D1
D3
U3
U12
GDDR5 Frame Buffer A
T1 R4 DRAWING NUMBER SIZE
T3 R11 PLACE_NEAR U8400 U10 8 4MM

D12 U14
D14 A14 REVISION
T12 R12 R
T14 R14
E5 C1 4.2.0
C3 NOTICE OF PROPRIETARY PROPERTY: BRANCH
U1
75 FB A1 VREFC J14 VREFC C4 THE INFORMATION CONTAINED HEREIN IS THE
75 FB A0 VREFC J14 VREFC U3 PROPRIETARY PROPERTY OF APPLE INC.
75 FB_A1_VREFD A10 C11 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
FB A0 VREFD A10 U12
75
U10 VREFD U14
U10 VREFD C12 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
84 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
U8500 U8550
Power aliases required by this page
This memory device is in Mirrored Mode. 32MX32-1.5GHZ-MFH
PP1V5R1V35 S0 FB VDD 32MX32-1.5GHZ-MFL BGA
BGA K4G10325FG-HC03
Signal aliases required by this page K4G10325FG-HC03
K11 (1 OF 2) P13
(NONE)
H11 D2 99 73 IN FB B1 A<2> BA0/A2 DBI1* FB B1 DBI L<1>
BI 73 99
99 73 IN FB B0 A<2> BA0/A2 DBI0* FB B0 DBI L<0> BI 73 99
H10 D13
K10 (1 OF 2) D13 99 73 IN FB B1 A<5> BA1/A5 DBI2* FB B1 DBI L<2> BI 73 99
BOM options provided by this page 99 73 IN FB B0 A<5> BA1/A5 DBI1* FB B0 DBI L<1> BI 73 99
H11 P2
K11 P13 99 73 IN FB B1 A<4> BA2/A4 DBI0* FB B1 DBI L<0> BI 73 99
(NONE) 99 73 IN FB_B0_A<4> BA2/A4 DBI2* FB_B0_DBI_L<2> BI 73 99
K10 D2
H10 P2 99 73 IN FB B1 A<3> BA3/A3 DBI3* FB B1 DBI L<3> BI 73 99
99 73 IN FB B0 A<3> BA3/A3 DBI3* FB B0 DBI L<3> BI 73 99
99 73 IN FB B1 A<7> H4 A8/A7 DQ0 U4 FB B1 DQ<0> BI 73 99

CK TERMINATION - B0 PLACE_NEAR U8500 J11 8 4MM 99 73 IN FB B0 A<7> K4 A8/A7 DQ0 A4 FB B0 DQ<0> BI 73 99
99 73 FB_B1_A<1> K5 A9/A1 DQ1 U2 FB_B1_DQ<1> 73 99
D FB_B0_CLK_P
R8501
40.2 FBB0_CK_MID
R8502
40.2 FB_B0_CLK_N
99 73
99 73
IN
IN
FB B0 A<1>
FB B0 A<0>
H5
H4
A9/A1
A10/A0
DQ1
DQ2
A2
B4
FB B0 DQ<1>
FB B0 DQ<2>
BI
BI
73 99
73 99
99 73
IN
IN FB_B1_A<0> K4
H5
A10/A0 DQ2 T4
T2
FB_B1_DQ<2>
BI
BI 73 99 D
76 73 1 2 1 2 73 76 99 99 73 FB B1 A<6> A11/A6 DQ3 FB B1 DQ<3> 73 99
K5 B2 IN BI
99 99 73 IN FB B0 A<6> A11/A6 DQ3 FB B0 DQ<3> BI 73 99
J3 N4
FBB 1% 1%
FBB J3 E4 99 73 IN FB B1 CKE L CKE* DQ4 FB B1 DQ<4> BI 73 99
1/20W 1/20W 99 73 IN FB_B0_CKE_L CKE* DQ4 FB_B0_DQ<4>
BI 73 99
76 75 72 6 =PP1V35 GPU FBVDDQ OMIT_TABLE N2
MF MF OMIT_TABLE E2 DQ5 FB B1 DQ<5> BI 73 99
201
1 FBB 201 DQ5 FB_B0_DQ<5> BI 73 99
J12 M4
PLACE_NEAR U8500 J12 8 4MM C8590 J12 F4 99 76 73 IN FB B1 CLK P CK DQ6 FB B1 DQ<6>
BI 73 99
0.01UF 99 76 73 IN FB_B0_CLK_P CK DQ6 FB_B0_DQ<6> BI 73 99
J11 M2
10% J11 F2 1 99 76 73 IN FB B1 CLK N CK* DQ7 FB B1 DQ<7> BI 73 99
99 76 73 IN FB B0 CLK N CK* DQ7 FB B0 DQ<7> BI 73 99 R8554
2
10V
99 73 FB B1 CS L L12 CS* DQ8 U11 FB B1 DQ<8> 73 99
X5R
99 73 FB B0 CS L G12 CS* DQ8 A11 FB B0 DQ<8> 73 99
1K IN BI
FBB 201 PLACE_NEAR U8500 J11 8 4MM IN BI 5% G12 U13
L12 A13 1/20W
99 73 IN FB_B1_WE_L WE* DQ9 FB_B1_DQ<9> BI 73 99
99 73 IN FB B0 WE L WE* DQ9 FB B0 DQ<9> BI 73 99
MF G3 T11
L3 B11 201
99 73 IN FB_B1_CAS_L CAS* DQ10 FB_B1_DQ<10> BI 73 99
99 73 IN FB B0 CAS L CAS* DQ10 FB B0 DQ<10> BI 73 99 2
L3 T13
G3 B13 FBB 99 73 IN FB B1 RAS L RAS* DQ11 FB B1 DQ<11> BI 73 99
99 73 IN FB B0 RAS L RAS* DQ11 FB B0 DQ<11> BI 73 99
J13 N11
J13 E11
FB B1 ZQ ZQ DQ12 FB B1 DQ<12> BI 73 99
FB_B0_ZQ ZQ DQ12 FB_B0_DQ<12>
BI 73 99
J1 N13
J1 E13
FB B1 MF MF (MF=1) DQ13 FB B1 DQ<13> BI 73 99
FBB
1
FB_B0_MF MF (MF=0) DQ13 FB_B0_DQ<13> BI 73 99
J10 M11
R8500 J10 F11
FB B1 SEN SEN DQ14 FB B1 DQ<14>
BI 73 99
FB_B0_SEN SEN DQ14 FB_B0_DQ<14> BI 73 99
J2 M13
120 FBB 99 73 IN FB B1 RESET L RESET* DQ15 FB B1 DQ<15> BI 73 99
1% 1 FBB 99 73 FB B0 RESET L J2 RESET* DQ15 F13 FB B0 DQ<15> 73 99
1 1
1/20W
R8504 1 IN BI R8550 R8553 DQ16 A11 FB B1 DQ<16> 73 99
MF 120 R8503 DQ16 U11 FB B0 DQ<16> 73 99 120 120 BI
BI J4 ABI* A13
201 2 1% 120 1% 1% 99 73 IN FB_B1_ABI_L DQ17 FB_B1_DQ<17>
BI 73 99
1/20W 1% 99 73 IN FB B0 ABI L J4 ABI* DQ17 U13 FB B0 DQ<17> BI 73 99 1/20W 1/20W
MF 1/20W MF MF DQ18 B11 FB_B1_DQ<18> BI 73 99
201 2 MF DQ18 T11 FB B0 DQ<18> 73 99 201 201
BI R2 B13
201
2 C2 T13 FBB 2 FBB 2 99 73 BI FB B1 EDC<0> EDC0 DQ19 FB B1 DQ<19> BI 73 99
99 73 BI FB B0 EDC<0> EDC0 DQ19 FB B0 DQ<19> BI 73 99
R13 E11
C13 N11 99 73 BI FB B1 EDC<1> EDC1 DQ20 FB B1 DQ<20> BI 73 99
99 73 BI FB B0 EDC<1> EDC1 DQ20 FB B0 DQ<20> BI 73 99
FBB C13 E13
FBB R13 N13 99 73 BI FB B1 EDC<2> EDC2 DQ21 FB B1 DQ<21> BI 73 99
99 73 BI FB_B0_EDC<2> EDC2 DQ21 FB_B0_DQ<21> BI 73 99
C2 F11
R2 M11 99 73 BI FB B1 EDC<3> EDC3 DQ22 FB B1 DQ<22> BI 73 99
99 73 BI FB_B0_EDC<3> EDC3 DQ22 FB_B0_DQ<22> BI 73 99
F13
M13 DQ23 FB B1 DQ<23> BI 73 99
DQ23 FB B0 DQ<23>
BI 73 99
A4
U4 DQ24 FB B1 DQ<24> BI 73 99
DQ24 FB B0 DQ<24> BI 73 99
P4 WCK01 A2
CK TERMINATION - B1 PLACE_NEAR U8550 J11 8 4MM
D4 WCK01 U2 99 73 IN FB_B1_WCLK_P<0> DQ25 FB_B1_DQ<25>
BI 73 99
99 73 IN FB B0 WCLK P<0> DQ25 FB B0 DQ<25> BI 73 99
P5 WCK01* B4
R8551 R8552 D5 WCK01* T4 99 73 IN FB_B1_WCLK_N<0> DQ26 FB_B1_DQ<26> BI 73 99
99 73 IN FB B0 WCLK N<0> DQ26 FB B0 DQ<26>
BI 73 99
B2
FB_B1_CLK_P 40.2 FBB1_CK_MID 40.2 FB_B1_CLK_N DQ27 FB_B1_DQ<27> BI 73 99
99
73 1 2 1 2 99
73 DQ27 T2 FB B0 DQ<27> BI 73 99
D4 WCK23 E4
C 76
FBB 1%
1/20W
MF
1%
1/20W
MF
FBB
76
99 73
99 73
IN FB B0 WCLK P<1>
FB_B0_WCLK_N<1>
P4 WCK23
P5 WCK23*
DQ28
DQ29
N4
N2
FB B0 DQ<28>
FB_B0_DQ<29>
BI 73 99
73 99
99 73
99 73
IN
IN
FB B1 WCLK P<1>
FB B1 WCLK N<1> D5 WCK23*
DQ28
DQ29 E2
FB B1 DQ<28>
FB B1 DQ<29>
BI
BI
73 99
73 99
C
IN BI F4
201
1
FBB 201
M4 DQ30 FB B1 DQ<30> BI 73 99
C8591 DQ30 FB_B0_DQ<30> BI 73 99
F2
0.01UF M2 DQ31 FB B1 DQ<31> BI 73 99
10%
DQ31 FB B0 DQ<31> BI 73 99
10V
FBB
2 X5R
201
U8500 NC A5
U8550 NC A5 NC
NC 32MX32-1.5GHZ-MFH A12/RFU/NC J5 FB_B1_A<8> IN 73 99
32MX32-1.5GHZ-MFL A12/RFU/NC J5 FB B0 A<8>
IN 73 99
BGA NC U5
BGA NC U5 K4G10325FG-HC03 NC
K4G10325FG-HC03 NC
=PP1V35 GPU FBVDDQ C5 (2 OF 2) B5
76 75 72 6
72 6 =PP1V35_GPU_FBVDDQ C5 B5
76 75 (2 OF 2) L11 L5
C10 B10 76 75 72 6 =PP1V35 GPU FBVDDQ
L14 L10
D11 D10 76 75 72 6 =PP1V35 GPU FBVDDQ FBB FBB FBB FBB
FBB FBB FBB 1
C8550 1
C8551 1
C8552 P11 P10
1
C8500 1
C8501 1
C8502 G1 G5 FBB 1
4.7UF 4.7UF 4.7UF R5 T5 R8580
4.7UF 4.7UF 4.7UF G4 G10 1 20% 20% 20%
MIN LINE WIDTH=0 25 MM 549
20% 20% 20% R8530 2
6 3V
2
6 3V
2
6 3V R10 T10 1%
6 3V 6 3V 6 3V G11 H1 X5R X5R X5R MIN NECK WIDTH=0 1 mm
2 X5R 2 X5R 2 X5R 549 402 402 402 C10 B10 1/20W
1% MF
402 402 402 G14 H14 1/20W
VDD VSS MIN LINE WIDTH=0 25 MM D11 VSS D10 2 201
MIN NECK WIDTH=0 1 mm MF
L1 K1 VDD
2 201 G1 G5
L4 K14 FB_B1_VREFC
FBB FBB FBB G4 G10 76
FBB FBB FBB L11 L5 FB_B0_VREFC 1
C8553 1
C8554 1
C8555 FBB
1
C8503 1
C8504 1
C8505 OMIT_TABLE 76 G11 H1
L14 L10 FBB
4.7UF 4.7UF 4.7UF
4.7UF 4.7UF 4.7UF 20% 20% 20% G14 H14 FBB
20% 20% 20% P11 P10 2
6 3V
2
6 3V
2
6 3V
FBB 1
2
6 3V
2
6 3V
2
6 3V X5R X5R X5R L1 K1 1
C8581 R8581 1
X5R X5R X5R R5 T5 FBB 1
FBB 402 402 402 PLACE_NEAR U8550 J14 8 4MM
1.33K R8584
402 402 402 1
C8531 R8531 1 L4 K14 820PF 1% 931
R10 T10 1.33K R8534 10%
1/20W 1%
820PF 1% 931 OMIT_TABLE 2
50V
MF 1/20W
10% CERM
1/20W 1%
2 201
MF
2
50V
MF 1/20W B1 402
201
B1 CERM
FBB FBB FBB FBB 2
2 201
MF
FBB FBB FBB FBB 402 1
C8556 1
C8557 1
C8558 1
C8559 E10 FBB
1 1 1 1 B3 2 201
C8506 C8507 C8508 C8509 1UF 1UF 1UF 1UF F1 FBB FB SW LEG IN 73 75 76
B 2
1UF
20%
6 3V
X5R 2
1UF
20%
6 3V
X5R 2
1UF
20%
6 3V
X5R 2
1UF
20%
6 3V
X5R
B12
B14
FBB
FBB
FB SW LEG

IN 73 75 76
2
20%
6 3V
X5R
0201
2
20%
6 3V
X5R
0201
2
20%
6 3V
X5R
0201
2
20%
6 3V
X5R
0201
F3
F12 A1
B
0201 0201 0201 0201 D1 A1
F14 C14 PLACE CLOSE TO U8550
D3 A3
G2 E1
D12 A12 PLACE CLOSE TO U8500
FBB FBB FBB FBB G13 E3
FBB FBB FBB FBB D14 A14 1
C8560 1
C8561 1
C8562 1
C8563 =PP1V35_GPU_FBVDDQ
1
C8510 1
C8511 1
C8512 1
C8513 H3 E12 76 75 72 6
E5 C1 1UF 1UF 1UF 1UF
1UF 1UF 1UF 1UF =PP1V35_GPU_FBVDDQ 20% 20% 20% 20% H12 E14
20% 20% 20% 20% E10 C3 76 75 72 6 2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V X5R X5R X5R X5R K3 F5
X5R X5R X5R X5R F1 C4 0201 0201 0201 0201
0201 0201 0201 0201 B3 F10
F3 C11 MIN LINE WIDTH=0 25 MM
FBB
K12 H2 MIN NECK WIDTH=0 1 mm
F12 C12 1
FBB L2 H13 R8582
F14 C14 MIN LINE WIDTH=0 25 MM 549
1
FBB FBB FBB FBB L13 K2 1%
FBB FBB FBB FBB G2 E1 R8532 1
C8564 1
C8565 1
C8566 1
C8567 1/20W
1 C8514 1 C8515 1 C8516 1 C8517 549 M1 A3 MF
G13 E3 1% 1UF 1UF 0.1UF 0.1UF VDDQ FB_B1_VREFD 201
1UF 1UF 0.1UF 0.1UF VDDQ 1/20W
20% 20% 10% 10% M3 K13 76
2
20% 20% 10% 10% H3 E12 MF 2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V
2
6 3V FB_B0_VREFD X5R X5R X5R X5R M12 M5
X5R X5R X5R X5R H12 E14 2 201 0201 0201 201 201 FBB
76 PLACE_NEAR U8550 U10 8 4MM
0201 0201 201 201 M14 M10
K3 F5
FBB
N5 N1
K12 F10
N10 N3 FBB
L2 VSSQ H2 FBB 1
FBB FBB FBB FBB P1 N12 FBB R8583 1
FBB FBB FBB FBB L13 H13 1
C8568 1
C8569 1
C8570 1
C8571 1
C8582 1
C8583 1.33K R8585
1 C8518 1 C8519 1 C8520 1 C8521 FBB 1 FBB B12 N14 1% 931
M1 K2 FBB R8533 1 0.1UF 0.1UF 0.1UF 0.1UF VSSQ 0.01UF 820PF 1/20W 1%
0.1UF 0.1UF 0.1UF 0.1UF 1
C8532 1
C8533 1.33K R8535 10% 10% 10% 10% P3 R1 10% 10%
MF 1/20W
10% 10% 10% 10% M3 K13 1% 931 2
6 3V
2
6 3V
2
6 3V
2
6 3V PLACE_NEAR U8550 A10 8 4MM
2
10V
2
50V
201 MF
2
6 3V
2
6 3V
2
6 3V
2
6 3V 0.01UF 820PF 1/20W 1%
X5R X5R X5R X5R P12 R3 X5R CERM 2
X5R X5R X5R X5R M12 M5 10% 10% MF 1/20W
201 201 201 201 201 402 2 201
201 201 201 201
2
10V
2
50V
201 MF P14 R4 FBB
M14 M10 X5R CERM 2 201 FB_SW_LEG IN 73 75 76
201 402 2 T1 A12 PLACE_NEAR U8550 U10 8 4MM
FBB
N5 N1
FB SW LEG 73 75 76
T3 R11
N10 N3 FBB IN
T12 R12
A 1 FBB
C8522 1 FBB
C8523 1 FBB
C8524 1 FBB
C8525
P1
P3
N12
N14
PLACE_NEAR U8500 A10 8 4MM

1 FBB
C8572
0.1UF
1 FBB
C8573
0.1UF
1 FBB
C8574
0.1UF
1 FBB
C8575
0.1UF
T14 R14 SYNC MASTER=D7 TONY SYNC DATE=12/13/2011 A
0.1UF 0.1UF 0.1UF 0.1UF 10% 10% 10% 10% B14 U1 PAGE TITLE
P12 R1 6 3V 6 3V 6 3V 6 3V
2
10%
6 3V
X5R
201
2
10%
6 3V
X5R
201
2
10%
6 3V
X5R
201
2
10%
6 3V
X5R
201
P14 R3
2 X5R
201
2 X5R
201
2 X5R
201
2 X5R
201
D1
D3
U3
U12
GDDR5 Frame Buffer B
T1 R4 DRAWING NUMBER SIZE
FBB T3 R11
FBB D12 U14
D14 A14 REVISION
T12 R12 R
T14 R14
E5 C1 4.2.0
C3 NOTICE OF PROPRIETARY PROPERTY: BRANCH
U1
76 FB_B1_VREFC J14 VREFC C4 THE INFORMATION CONTAINED HEREIN IS THE
76 FB B0 VREFC J14 VREFC U3 PROPRIETARY PROPERTY OF APPLE INC.
76 FB B1 VREFD A10 C11 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
FB B0 VREFD A10 U12
76
U10 VREFD U14
U10 VREFD C12 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
85 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU IFPA IOVDD GPU IFPB IOVDD GPU IFPC IOVDD GPU TESTMODE
PD FOR AUX CHANNELS (FOR NVIDIA) DISABLE PHYs A, B & C FOR K70 77 77 77 77 Page Notes
98 82 77 DP INT EG AUX P Power aliases required by this page:
DP INT EG AUX N 1 1 1 1
98 82 77 R8601 R8602 R8603 R8608 - PP3V3 GPU IFPB IOVDD - PP1V05 GPU IFPCD IOVDD
10K 10K 10K 10K - PP1V8 GPU IFPA IOVDD - PP1V05 GPU IFPEF IOVDD
1 1
OMIT TABLE 1% 1% 1% 1%
DP TBTSNK0 EG AUXCH P 71 77
R8614 R8613 CRITICAL
1/20W
MF
1/20W
MF
1/20W
MF
1/20W
MF
- PP1V8 GPU DPLL - PP3V3 GPU VDD33
100K 100K 201 201 201 201 - PP1V05 GPU DPLL

DP TBTSNK0 EG AUXCH N 2 2 2 2
71 77 1% 1%
1/20W
MF
1/20W
MF
U8000 - PP3V3 GPU IFPX PLLVDD
2
201
2
201 NV-GK107 Signal aliases required by this page:
1 1 BGA
R8615 R8616 (5 OF 10) (NONE)
100K 100K GPU IFPA IOVDD PD FOR RSET
AG8 AM6
1% 1% 77 IFPA_IOVDD IFPA_TXC NC
D 2
1/20W
MF
201
2
1/20W
MF
201
77 71
77 71
DP TBTSNK1 EG AUXCH P
DP TBTSNK1 EG AUXCH N
77
77
GPU IFPB IOVDD
GPU IFPC IOVDD

AG9
AF6
IFPB_IOVDD
IFPC_IOVDD
IFPA_TXC* AN6
AP3
NC
GPU IFPAB PLLVDD
77
GPU IFPX PLLVDD
77
IFPD RSET
77
IFPEF RSET
77
- J31:YES D
PP1V05 GPU IFPD IOVDD AG6 IFPA_TXD0 NC PLACE_NEAR U8000 AN2 5MM PLACE_NEAR U8000 AD6 5MM - J5:YES
77 IFPD_IOVDD AN3 1 1 1 1
PP1V05 GPU IFPEF IOVDD AC7 IFPA_TXD0* NC R8604 R8619 R8606 R8607
1 1
77 IFPE_IOVDD AN5
R8617 R8618 PP1V05 GPU IFPEF IOVDD AC8 IFPA_TXD1 NC 10K 10K 1K 1K
77 IFPF_IOVDD AM5 1% 1% 1% 1%
100K 100K IFPA_TXD1* NC 1/20W 1/20W 1/20W 1/20W
1% 1% MF MF MF MF
AH8 AL6
1/20W 1/20W 77 GPU IFPAB PLLVDD IFPAB_PLLVDD IFPA_TXD2 NC 2
201
2
201
2
201
2
201
MF MF 79 77 PP1V05 GPU SP PLLVDD PP1V05 GPU VID PLLVDD
AJ8 AK6
2
201
2
201
NC IFPAB_RSET IFPA_TXD2* NC 77
MAKE BASE TRUE
AJ6
AF7 IFPA_TXD3 NC
77 GPU IFPX PLLVDD IFPC_PLLVDD AH6
AF8 IFPA_TXD3* NC
NC IFPC_RSET
AJ9
PP3V3 GPU IFPX PLLVDD AG7 IFPB_TXC NC
79 78 77 71 6 =PP3V3 GPU VDD33 77 IFPD_PLLVDD AH9
IFPD RSET AN2 IFPB_TXC* NC
77 IFPD_RSET
1 1 1 1 AP6
R8624 R8623 R8625 R8626 PP3V3 GPU IFPX PLLVDD AB8 IFPB_TXD4 NC
4 7K 4 7K 100K 100K 77 IFPEF_PLLVDD AP5
1% 1% 5% 5% IFPEF RSET AD6 IFPB_TXD4* NC
1/20W 1/20W 1/20W 1/20W
77 IFPEF_RSET AM7
MF MF MF MF
IFPB_TXD5 NC
201 201
NOSTUFF 201 201 AL7
2 2 2 2 IFPB_TXD5* NC
NOSTUFF AN8
IFPB_TXD6 NC
R4 AM8
83 OUT DP TBTSNK0 DDC CLK I2CA_SCL IFPB_TXD6* NC
R5 AK8
83 BI DP TBTSNK0 DDC DATA I2CA_SDA IFPB_TXD7 NC
AL8
IFPB_TXD7* NC OMIT TABLE
AG3
IFPC_AUX_I2CW_SCL NC U8000
AG2
IFPC_AUX_I2CW_SDA* NC NV-GK107
R2 ote PP3 3 GPU M SC and p 3v3 GPU DD33 ha e to be solated from each other
BGA
GPU SSC SMB CLK I2CC_SCL AK1
R3 IFPC_L0 NC 80 77 6 =PP3V3 GPU MISC (6 OF 10)
GPU SSC SMB DAT I2CC_SDA AJ1 J8 P6
IFPC_L0* NC GPIO0 GPU GPIO 0
BI 78
AJ3 K8 M3
IFPC_L1 NC GPIO1 GPU GPIO 1
BI 78
AJ2 79 78 77 71 6 =PP3V3 GPU VDD33
L8 L6
C IFPC_L1*
IFPC_L2 AH3
NC
NC
M8
VDD33 GPIO2
GPIO3 P5
GPU GPIO 2
GPU GPIO 3
BI
BI
78
78
C
T4 AH4 P7
99 78 OUT GPU SMB CLK I2CS_SCL IFPC_L2* NC GPIO4 GPU GPIO 4
BI 78
T3 AG5 H6 L7
99 78 BI GPU SMB DAT I2CS_SDA IFPC_L3 NC 78 OUT GPU ROM CS L ROM_CS* GPIO5 GPU GPIO 5 BI 78
AG4 H4 M7
IFPC_L3* NC 78 OUT GPU ROM SCLK ROM_SCLK GPIO6 GPU GPIO 6
BI 78
H5 N8
79 78 77 71 6 =PP3V3 GPU VDD33 AK3 78 IN GPU ROM SI ROM_SI GPIO7 GPU GPIO 7
BI 78
IFPD_AUX_I2CX_SCL DP INT EG AUX P BI 77 82 98 H7 M1
AK2 PLACE_NEAR U8000 J1 5MM 78 OUT GPU ROM SO ROM_SO GPIO8 GPU GPIO 8 BI 78
1 1 IFPD_AUX_I2CX_SDA* DP INT EG AUX N
BI 77 82 98
R8609 M2
CRITICAL R8627 R8628 GPIO9 GPU GPIO 9
BI 78
100K 100K AM1 40 2K J1 L1
L8604 5% 5%
IFPD_L0 DP INT EG ML P<0>
OUT 82 98 1 2 MULTI STRAP REF MULTI_STRAP_REF0_GND GPIO10 GPU GPIO 10
BI 78
330-OHM-1 2A 1/20W 1/20W AM2 M5
MF MF
IFPD_L0* DP INT EG ML N<0>
OUT 82 98 0 1% GPIO11 GPU GPIO 11 BI 78
1/20W
6 =PP3V3 GPU IFPX PLLVDD
1 2 PP3V3 GPU IFPX PLLVDD 77 NOSTUFF 2
201
2
201
IFPD_L1 AM3 DP INT EG ML P<1> 82 98 MF 77
GPU TESTMODE AK11
TESTMODE GPIO12 N3 GPU GPIO 12 78
OUT BI
0603 MIN LINE WIDTH 0 5 MM NOSTUFF AM4
0201
M4
MIN NECK WIDTH 0 2 mm IFPD_L1* DP INT EG ML N<1>
OUT 82 98 GPIO13 GPU GPIO 13
BI 78
VOLTAGE 3 3V AL3 PP1V05 GPU SP PLLVDD AE8 N4
R7 IFPD_L2 DP INT EG ML P<2>
OUT 82 79 77 SP_PLLVDD GPIO14 GPU GPIO 14
BI 78
83 OUT DP TBTSNK1 DDC CLK I2CB_SCL AL4 P2
R6 IFPD_L2* DP INT EG ML N<2> OUT 82 PP1V05 GPU PLLVDD AD8 GPIO15 GPU GPIO 15 BI 78
83 BI DP TBTSNK1 DDC DATA I2CB_SDA AK4 77 PLLVDD R8
IFPX PLLVDD IFPD_L3 DP INT EG ML P<3> OUT 82 GPIO16 GPU GPIO 16 BI 78
AK5 PP1V05 GPU VID PLLVDD AD7 M6
IFPD_L3* DP INT EG ML N<3>
OUT 82 77 VID_PLLVDD GPIO17 GPU GPIO 17
BI 78
1 1 1
C8619 C8615 C8617 1
C8618 1
C8612 DDC MAPPING GPIO18 R1 GPU GPIO 18 78
AB3 BI
4 7UF 1UF 0 1UF
0 1UF 0 1UF
IFPE_AUX_I2CY_SCL DP TBTSNK0 EG AUXCH P BI 71 77 H3 P3
10% 10% 10%
10% 10%
I2CA > IFPE DDC AB4 78 IN GPU OSC 27M XTALIN XTAL_IN GPIO19 GPU GPIO 19
BI 78
2
6 3V
2
25V
2
16V
16V 16V
IFPE_AUX_I2CY_SDA* DP TBTSNK0 EG AUXCH N
BI 71 77
H2 P4
X5R-CERM X5R X7R-CERM 2 X7R-CERM
2 X7R-CERM
I2CB > IFPF DDC 78 OUT GPU OSC 27M XTALOUT XTAL_OUT GPIO20 GPU GPIO 20
BI 78
603 402 402
402 402 AD2 P1
I2CC > Not used IFPE_L0 DP TBTSNK0 ML C P<0>
OUT 34 98 GPIO21 GPU GPIO 21
BI 78
(was ext SSC cntl) AD3 J4
IFPE_L0* DP TBTSNK0 ML C N<0> OUT 34 98 GPU XTAL OUTBUFF XTAL_OUTBUFF
AD1 AM10
IFPE_L1 DP TBTSNK0 ML C P<1>
OUT 34 98 H1 JTAG_TCK GPU JTAG TCK IN 78
AC1
GPU XTAL SSIN XTAL_SSIN AM11
IFPE_L1* DP TBTSNK0 ML C N<1>
OUT 34 98 JTAG_TDI GPU JTAG TDI
IN 78
AC2 AP12
IFPE_L2 DP TBTSNK0 ML C P<2>
OUT 34 98
J2 JTAG_TDO GPU JTAG TDO
OUT 78
AC3 78 IN GPU MLS STRAP0 STRAP0 AP11
L8605 IFPE_L2* DP TBTSNK0 ML C N<2>
OUT 34 98
1 1 J7 JTAG_TMS GPU JTAG TMS
IN 78
AC4 R8620 R8622 78 IN GPU MLS STRAP1 STRAP1 AN11
FERR 220 OHM 2A IFPE_L3 DP TBTSNK0 ML C P<3>
OUT 34 98
J6 JTAG_TRST* GPU JTAG TRST L
IN 78
AC5 10K 10K 78 IN GPU MLS STRAP2 STRAP2
1 2 IFPE_L3* DP TBTSNK0 ML C N<3> 34 98
B 6 =PP1V05 GPU IFPCD IOVDD
CRITICAL
0603
PP1V05 GPU IFPD IOVDD 77
MIN LINE WIDTH 0 5MM
MIN NECK WIDTH 0 2mm
IFPF_AUX_I2CZ_SCL AF3 DP TBTSNK1 EG AUXCH P
OUT
BI 71 77
2
5%
1/20W
MF
201
2
5%
1/20W
MF
201
78
78
IN
IN
GPU MLS STRAP3
GPU MLS STRAP4

J5
J3
STRAP3
STRAP4
THERMDP K3
K4
GPU TDIODE P
IN 8
1
R8610
B
ESR = 0 05OHM
VOLTAGE 1 05V
AF2 THERMDN GPU TDIODE N OUT 8
IFPF_AUX_I2CZ_SDA* DP TBTSNK1 EG AUXCH N
BI 71 77 10K
5%
1/20W
AE3
IFPF_L0 DP TBTSNK1 ML C P<0>
OUT 34 98 MF
201
AE4 2
IFP CD IOVDD
IFPF_L0* DP TBTSNK1 ML C N<0> OUT 34 98
AF4
1 1 1 1
IFPF_L1 DP TBTSNK1 ML C P<1> OUT 34 98
C8625 C8656 C8657 C8658 AF5
4 7UF 1UF 0 1UF 0 1UF
IFPF_L1* DP TBTSNK1 ML C N<1>
OUT 34 98
20% 20% 10% 10% AD4
6 3V 6 3V 16V 16V
2 X5R-CERM1
2 X5R
2 X7R-CERM
2 X7R-CERM AD5
402 0201 402 402
AG1 GPU PLL VDD
AF1
L8607
FERR 220 OHM 2A
L8606 DAC AVDD
AG10 AK9 1 2
FERR 220 OHM 2A DACA_VDD DACA_RED NC 79 6 =PP1V05 GPU PEX PLLVDD PP1V05 GPU PLLVDD 77
AL10 MIN LINE WIDTH 0 41MM
6 =PP1V05 GPU IFPEF IOVDD
1 2 PP1V05 GPU IFPEF IOVDD 77 DACA_GREEN NC
0603
MIN NECK WIDTH 0 2MM
AL9 CRITICAL VOLTAGE 1 05V
MIN LINE WIDTH 0 5MM
0603
MIN NECK WIDTH 0 2mm
DACA_BLUE NC ESR = 0 05OHM
1 1
CRITICAL C8651 C8654
ESR = 0 05OHM
VOLTAGE 1 05V
AP9 AM9 GPU 3V3 VDD 22UF 0 1UF
NC DACA_VREF DACA_HSYNC NC 20% 10%
IFP EF IOVDD AP8 AN9 4V 16V
NC DACA_RSET DACA_VSYNC NC 2 X5R
2 X7R-CERM
0402 402
79 78 77 71 6 =PP3V3 GPU VDD33
1 1 1 1
C8633 C8634 C8635 C8636
4 7UF 4 7UF 1UF 1UF
20% 20% 20% 20%
1 1 1
2
6 3V
2
6 3V
2
6 3V
2
6 3V C8642 C8643 C8644
X5R-CERM1 X5R-CERM1 X5R X5R
402 402 0201 0201
1 1UF 0 1UF 0 1UF
R8600 10% 10% 10%
25V 16V 16V
10K L3 2 2 2
1%
CEC NC X5R X7R-CERM X7R-CERM
402 402 402
1/20W
MF
A
201
2
SYNC MASTER=D7 TONY

PAGE TITLE
SYNC DATE=12/13/2011 A
80 77 6 =PP3V3 GPU MISC
1
C8637 1
C8638
1
C8631
0 1UF
1
C8632
0 1UF
KEPLER EDP/DP/GPIO
0 1UF 0 1UF 10% 10% 1 1 1
DRAWING NUMBER SIZE
C8646 C8649 C8650
2
10%
16V
X7R-CERM
2
10%
16V
X7R-CERM
2
16V
X7R-CERM
2
16V
X7R-CERM 4 7UF 0 1UF 0 1UF Apple Inc. 051-9509 D
402 402 20% 10% 10%
402 402
6 3V 16V 16V
REVISION
2 2 2 R
X5R-CERM1
402
X7R-CERM
402
X7R-CERM
402
4.2.0
86 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Unused signals
Native Func TP GPU JTAG TCK GPU JTAG TCK 77

Native Func GPIOs GPIOs ISOLATION R’s for GPU Int Temp Sense MAKE BASE TRUE
TP GPU JTAG TDI GPU JTAG TDI 77

GPU GPIO 0 GP GPU VCORE VID4 GPU GPIO 14 GP NC DP EXTA CA DET EG
77 80 77 MAKE BASE TRUE
MAKE BASE TRUE MAKE BASE TRUE
TP GPU JTAG TDO GPU JTAG TDO 77
77 GPU GPIO 1 GP GPU VCORE VID3 80 77 GPU GPIO 15 GP NC DP EXTB CA DET EG R8780 MAKE BASE TRUE
MAKE BASE TRUE MAKE BASE TRUE 0
99 77 GPU SMB DAT 1 2 GPU SMB DAT R 47 99 TP GPU JTAG TMS GPU JTAG TMS 77
GPU GPIO 2 GP GPU LCD BKLT PWM GPU GPIO 16 GP FBVDD ALTVO MAKE BASE TRUE
77 82 77 74 78
MAKE BASE TRUE MAKE BASE TRUE 5%
1/20W TP GPU JTAG TRST L GPU JTAG TRST L 77
GPU GPIO 3 GP EG LCD PWR EN GPU GPIO 17 GP DP INT EG HPD MF
77 8 78 77 82 MAKE BASE TRUE
MAKE BASE TRUE MAKE BASE TRUE 201
GPU GPIO 4 GP EG BKLT EN GPU GPIO 18 GP DP TBTSNK0 HPD

77 78 77 34
MAKE BASE TRUE MAKE BASE TRUE
R8781
0
GPU GPIO 5 GP GPU VCORE VID1 GPU GPIO 19 GP DP TBTSNK1 HPD GPU SMB CLK 1 2 GPU SMB CLK R
77 80 77 34 99 77 47 99
D 77 GPU GPIO 6 GP
MAKE BASE TRUE
GPU VCORE VID2 80 77 GPU GPIO 20 GP

MAKE BASE TRUE
NC GPU GPIO 20 RSVD

5%
1/20W
D
MAKE BASE TRUE MAKE BASE TRUE NO TEST TRUE MF
201
GPU GPIO 7 GP FB CLAMP TOGGLE REQ L GPU GPIO 21 GP NC GPU GPIO 21 RSVD
77 77
MAKE BASE TRUE MAKE BASE TRUE NO TEST TRUE
GPU GPIO 8 GP SMC GFX OVERTEMP R L

77 78
MAKE BASE TRUE 1
GP
R8791
77 GPU GPIO 9 SMC GFX THROTTLE R L 78 10K
MAKE BASE TRUE
GP
5%
1/20W
GPU XTAL 27 MHZ
77 GPU GPIO 10 GPU ALT VREF 73
MF
MAKE BASE TRUE
201
GPU GPIO 11 GP GPU VCORE VID0 GPU OSC 27M XTALIN
77 80 2 NOSTUFF OUT 77
MAKE BASE TRUE
GPU OSC 27M XTALOUT 77
GPU GPIO 12 GP NC HDMI EG HPD IN
77
MAKE BASE TRUE
77 GPU GPIO 13 GP GPU VCORE VID5 80 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
MAKE BASE TRUE
998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8704 CRITICAL GPU:107GTX
118S0409 1 RES,MF,4.99k ,1,1/20W,0201 R8704 CRITICAL GS
Y8700 998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8704 CRITICAL GPU:107EGE

CONFIG STRAPS - MLPS SM-2 5X2 0MM
27MHZ 15PPM 18PF 118S0280 1 RES,MF,30.1k ,1,1/20W,0201 R8705 CRITICAL GPU:107GTX

=PP3V3 GPU VDD33 =PP3V3 GPU VDD33 1 3
77 71 6
79 78
79 78 77 71 6 CRITICAL 998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8705 CRITICAL GS
2 4
NOSTUFF
1 1
118S0409 1 RES,MF,4.99k ,1,1/20W,0201 R8705 CRITICAL GPU:107EGE
C8700 C8701
NC
NC
1 1
R8700 R8708 18PF 18PF 998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8710 CRITICAL FB:BOTH_SAMSUNG
5% 5%
45 3K 3 24K
25V 25V
1% 1% 2 2
1/20W 1/20W
NP0-C0G
201
NP0-C0G
201
998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8710 CRITICAL FB:BOTH_HYNIX
MF MF
201 201
2 2
998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8710 CRITICAL FB CH1 SAMSUNG
OUT 77 OUT 77
R8710
C GPU MLS STRAP0 GPU MLS STRAP4
998-3824
998-3824
1
1
RES,MF,NOSTUFF,1,1/20W,0201
RES,MF,NOSTUFF,1,1/20W,0201 R8710
CRITICAL
CRITICAL
FB CH2 SAMSUNG
FB CH1 HYNIX
C
1 1
R8701 R8709 998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8710 CRITICAL FB CH2 HYNIX
5 62K 45 3K
1% 1%
1/20W 1/20W 118S0175 1 RES,MF,20.0k ,1,1/20W,0201 R8711 CRITICAL FB BOTH SAMSUNG
MF MF
201 201
2 2
118S0105 1 RES,MF,15.0k ,1,1/20W,0201 R8711 CRITICAL FB BOTH HYNIX
NOSTUFF GPU VBIOS ROM
118S0013 1 RES,MF,10.0k ,1,1/20W,0201 R8711 CRITICAL FB CH1 SAMSUNG
=PP3V3 GPU VDD33

118S0013 1 RES,MF,10.0k ,1,1/20W,0201 R8711 CRITICAL FB CH2 SAMSUNG
79 78 77 71 6
=PP3V3 GPU VDD33 =PP3V3 GPU VDD33

GPU ROM YES
118S0230 1 RES,MF,24.9k ,1,1/20W,0201 R8711 CRITICAL FB CH1 HYNIX
77 71 6 79 78 77 71 6
79 78 GPU ROM YES GPU ROM YES 1
C8721
1 1 0 1UF 118S0230 1 RES,MF,24.9k ,1,1/20W,0201 R8711 CRITICAL FB CH2 HYNIX
NOSTUFF OMIT TABLE R8720 R8721
R8723 10%
1 1
R8714
8
6 3V
R8702 R8710 GPU ROM SI
1
33
2
10K 0 2
X5R
118S0409 1 RES,MF,4.99k ,1,1/20W,0201 CRITICAL GPU 107GTX
77 5% 5%
201
3 24K 3 24K 78 1/20W VCC 1/20W
1% 1%
GPU ROM YES 5%
1/20W
MF MF 118S0409 1 RES,MF,4.99k ,1,1/20W,0201 R8714 CRITICAL GS
1/20W
MF
1/20W
MF MF
201
2
U8701 201
2
2
201
2
201 201
1MBIT 998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8714 CRITICAL GPU:107EGE
R8726 MX25V1005C
OUT 77 OUT 77 78 33 998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8715 CRITICAL GPU:107GTX
GPU ROM SI 77 GPU ROM SO 1 2 USON
78 5 SI
GPU MLS STRAP1 5%
1/20W
MF
201
GPU ROM SI R OMIT TABLE 998-3824 1 RES,MF,NOSTUFF,1,1/20W,0201 R8715 CRITICAL GS
GPU ROM YES 2 SO 3
GPU ROM SO R CRITICAL GPU ROM WP L
1 1 R8725 WP* 118S0105 1 RES,MF,15.0k ,1,1/20W,0201 R8715 CRITICAL GPU:107EGE
R8703 R8711 GPU ROM YES 33
34 8K 25 5K 77 GPU ROM CS L 2 1 GPU ROM CS L R 1
CS* HOLD* 7
1% 1% 5% MF NO STUFF
1/20W 1/20W 1/20W 201 1
MF MF GPU ROM SCLK R 6 SCLK R8722
33 THRM
201 201
2 2 77 GPU ROM SCLK 2 1
GND PAD 0
78 MF 5% 5%
OMIT TABLE 201 1/20W
9
GPU ROM YES R8724 1/20W
MF
B 2
201
B
77 71 6 79 78 77 71 6
79 78
OMIT TABLE
1 1
R8704 R8712
10K 10K
1% 1%
1/20W 1/20W
MF MF
201 201
2 2 =PP3V3_GPU_VDD33
77 77 78
79 78 77 71 6 GPU overtemp masking
OUT OUT
79 78 77 71 6 =PP3V3 GPU VDD33
GPU MLS STRAP2 GPU ROM SO
1
1 1 R8752 1 1
R8705 R8713 10K 70 61 60 6 =PP3V3 S5 PWRCTL
R8796 R8797
15K 10K 5% 10K 10K
1% 1% 1/20W 5% 5%
1/20W 1/20W MF 1/20W 1/20W
MF MF 201 MF MF
2
2
201
2
201 PLACE_SIDE=BOTTOM 201 201
NOSTUFF
OMIT TABLE 14 74LVC08 2 2
NO STUFF
SMC GFX OVERTEMP Q 10 TSSOP-HF 78 SMC GFX OVERTEMP R L R8798 0 1 2 SMC GFX OVERTEMP 44 45 78
OUT
5% 1/20W MF 201
8 78
U7000 OUT 44
45 78 SMC GFX THROTTLE R L R8799 0 1 2 SMC GFX THROTTLE L
Q8701 9 08 SMC_GFX_OVERTEMP 5% 1/20W MF 201
BI 44

SSM3K15AMFVAPE D 3 EG LCD PWR EN OUT 8 78
77 71 6 79 78 77 71 6 VESM 7
79 78
EG BKLT EN OUT 78
OMIT TABLE
1 1 FBVDD ALTVO 74 78
R8706 R8714 OUT
10K 35 7K 1 G S 2 Quad AND gate from .csa70
A 1%
1/20W
MF
201
1%
1/20W
MF
201
NO STUFF SYNC MASTER=D7 TONY SYNC DATE=01/10/2012 A
2 2 1 1 1 1 PAGE TITLE
R8792 R8793 R8794 R8790
OUT 77 OUT 77 78 10K
5%
10K
5%
10K
5%
10K
5%
KEPLER GPIOS,CLK & STRAPS
1/20W 1/20W 1/20W 1/20W DRAWING NUMBER SIZE
GPU MLS STRAP3 GPU ROM SCLK
78
MF
201
2
MF
201
2
MF
201
2
201
MF
2
1 1 SMC_GFX_OVERTEMP_R_L
R8707 R8715 REVISION
R
5 62K
1%
45 3K
1%
4.2.0
1/20W 1/20W GPU RESET L NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF MF 26 IN
201 201 71 THE INFORMATION CONTAINED HEREIN IS THE
2 2
OMIT TABLE
NOSTUFF I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
87 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
GPU SP PLLVDD - PP3V3 GPU VDD33

OMIT TABLE L8804 - PP1V05 GPU PEX IOVDD
- PP1V05 GPU PEX PLLVDD
FERR 220 OHM 2A
U8000 6
=PP1V05 GPU PEX PLLVDD 1 2 77 PP1V05 GPU SP PLLVDD
=PP1V05 GPU PEX IOVDD 77
NV-GK107 6 73 79
79 0603
MIN LINE WIDTH 0 6 MM
MIN NECK WIDTH 0 25 MM
BGA CRITICAL VOLTAGE 1 05V
(2 OF 10) ESR = 0 05OHM
1 1 1 1
P8 AG19 C8830 C8831 C8836 C8837
NC NC PEX_IOVDD 22UF 4.7UF 0 1UF 0 1UF
AC6 AG21 20% 20% 10% 10%
NC NC PEX_IOVDD 4V 6 3V 16V 16V
AJ28 AG22 2 X5R

2 X5R CERM1
2 X7R-CERM
2 X7R-CERM
NC NC PEX_IOVDD XW8801 402 402 402 402
(NONE)
AJ4 AG24 SM
NC NC PEX_IOVDD
D NC
AJ5
AL11
NC PEX_IOVDD AH21
AH25
1 2 GND GPU SP PLLVDD
MIN LINE WIDTH 0 3 MM
MIN NECK WIDTH 0 2 MM
(NONE)
D
NC NC PEX_IOVDD VOLTAGE 0V
C15
NC NC =PP1V05 GPU PEX IOVDD OMIT TABLE
D19 6 73 79 OMIT TABLE
NC NC
D20
NC PEX_IOVDDQ AG13 U8000
NC
D23 AG15
U8000 NV-GK107
NC NC PEX_IOVDDQ NV-GK107 BGA
D26
NC PEX_IOVDDQ AG16 BGA (9 OF 10)
NC (8 OF 10)
H31 AG18 C7 N7
NC NC PEX_IOVDDQ AG11 AK7
T8 AG25 D2 P13
NC NC PEX_IOVDDQ A2 AL12
NC
V32
NC PEX_IOVDDQ AH15
A33
GND AL14
D31
GND P15
AH18 D33 P17
PEX_IOVDDQ AA13 AL15
AH26 E10 P18
AH27 E22 P20
AJ27 E25 P22
PEX_IOVDDQ AA18 AL2
AK27 E5 R12
AL27 E7 R14
72 6 =PPVCORE GPU
AM28 F28 R16
PEX_IOVDDQ AB12 AL23
AN28 F7 R19
PEX_IOVDDQ AB14 AL24
G10 R21
AB16 AL26
G13 R23
AB19 AL28
1 G16 T13
R8810 =PP1V05 GPU PEX PLLVDD 6 77 79 AB2 AL30
G19 T15
100 AB21 AL32
5% G2 T17
1/20W AB23 AL33
MF G22 T18
1 1 1
2
201 C8827 C8828 C8829 AB28 AL5
4.7UF 1UF 0.1UF G25 T2
NOSTUFF 20% 20% 10% AB30 AM13
6 3V 6 3V 16V G28 T20
2 X5R CERM1 2 X5R
2 X7R CERM AB32 AM16
G3 T22
C C16
GND_OPT
402 0201 402
1
XW8802
SM
2
AB5
AB7
AM19
AM22
G30 T28 C
W32 G32 T32
GND_OPT GND GPU PEX PLLVDD AC13 AM25
MIN LINE WIDTH 0 3 MM G33 T5
MIN NECK WIDTH 0 2 MM AC15 AN1
VOLTAGE 0V G5 T7
L4 AC17 AN10
97 80 OUT SNS GPU CORE P VDD_SENSE G7 U12
AG26 AC18 AN13
PEX_PLLVDD K2 U14
AC20 AN16
L5 K28 U16
97 80 OUT SNS GPU CORE N GND_SENSE AC22 AN19
K30 U19
AH12 AE2 AN22
PEX_PLL_HVDD =PP3V3 GPU VDD33 6 71 77 78
K32 U21
L2 AE28 AN25
GPU BUFRSTN BUFRST* K33 U23
1 1 1 AE30 AN30
C8822 C8823 C8825 K5 V12
4 7UF 4 7UF 0.1UF AE32 AN34
20% 20% 10% K7 V14
6 3V 6 3V 6 3V AE33 AN4
2 2 2 M13 V16
1 X5R-CERM1 X5R-CERM1 X5R
XW8803
R8800 402 402 201
SM
AE5 AN7
M15 V19
10K AE7 AP2
1% 1 2
M17 V21
1/20W AH10 AP33
MF GND GPU PEX PLL HVDD
M18 V23
201 MIN LINE WIDTH 0 3 MM
2 AH13 B1
MIN NECK WIDTH 0 2 MM M20 W13
VOLTAGE 0V AH16 B10
1 M22 W15
R8811 AH19 B22
N12 W17
100 AH2 B25
5% N14 W18
1/20W AH22 B28
MF N16 W20
201 AH24 B31
2
N19 W22
NOSTUFF AH28 B34
N2 W28
AH29 B4
N21 Y12
AH30 B7
N23 Y14
AH32 C10
N28 Y16
B AH33
AH5
C13
C19
N30
N32
Y19
Y21
B
AH7 C22
N33 Y23
AJ7 C25
N5 AH11
AK10 C28
PLACE XW8800 & XW8804 CLOSE TO C8803

XW8804
SM
1 2 SNS GPU PEX IOVDD P 74 97

OUT
PLACE NEAR C8803 1 2MM
SIGNAL MODEL EMPTY
EDP = 2000 MA
79 73 6 =PP1V05 GPU PEX IOVDD
1 1 1 1 1 1 1
C8803 C8804 C8805 C8815 C8816 C8809 C8810
22UF 22UF 4 7UF 10UF 1UF 10UF 1UF
20% 20% 20% 20% 10% 20% 10%
4V 4V 6 3V 4V 25V 4V 25V
2 X5R
2 X5R
2 X5R-CERM1
2 X5R
2 X7R
2 X5R
2 X7R
402 402 402 402 0603 402 0603
XW8800
SM
1 2 SNS GPU PEX IOVDD N

OUT 74 97
PLACE NEAR C8803 2 2MM

SIGNAL MODEL EMPTY
79 73 6 =PP1V05 GPU PEX IOVDD
A EDP = 1100MA
1 1 1 1 1 1 1
C8800 C8801 C8802 C8812 C8813 C8806 C8807 PAGE TITLE
2
22UF
20%
4V
2
22UF
20%
4V
2
4 7UF
20%
6 3V
2
10UF
20%
4V
2
1UF
10%
25V
2
10UF
20%
4V
2
1UF
10%
25V
KEPLER PEX PWR/GNDS
X5R X5R X5R-CERM1 X5R X7R X5R X7R DRAWING NUMBER SIZE
402 402 402 402 0603 402 0603

REVISION
R
4.2.0
PEX IOVDD & PEX IOVDDQ THE POSESSOR AGREES TO THE FOLLOWING: PAGE
88 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU Core Phases
80 6 =PP12V_S0_REG_GPUCORE_S0
=PP12V_S0_REG_GPUCORE_S0
GPU Core S0 Regulator 6 =PP5V_S0_REG_GPUCORE_S0
80 6
Max avg current: ? A (design)/? A (budget) R89001 1

R8901 EMC EMC
Max peak current: ? A (design)/? A (budget) 4.7
5% 5%
4.7 Q8910.5:3MM Q8910.6:3MM CRITICAL
OC trip point: ? A (nom)/? A (min) 1/8W
MF-LF
1/8W
MF-LF
1 C8918 1 C8919 1
C8910
Switching freq: 290 kHz 805 2 2 805 1UF
10%
1UF
10%
270UF
20%
25V 25V
97 80 REG_VCC_U8900 97 REG_PVCC_U8900 2 X5R 2 X5R 2 16V
ELEC
402 402 8X9-TH1
GPU Core current sense R8940 1 1
80.6
C8900 C8901
D 97 80 REG_GPUCORE_ICOMP 1
1%
2 REG_GPUCORE_OCSET 80 97
1UF
10%
25V
X7R 2
1UF
10%
25V
2 X7R
D
1/16W
MF-LF 805 805
402
15
97 REG_BOOT_GPUCORE_1_RC
7
8
CRITICAL
VCC PVCC R89161 1 C8916 D Q8910
R8941 1 1 C8941 U8900 0
5%
0.22UF
10% IRF6802SDTRPBF
0.012UF ISL6568 1/10W 2 16V 2 G DIRECTFET-SA
42.2K 10% MF-LF
X7R
1% 603
1/10W 2 25V QFN 603 2 S
MF-LF X7R CRITICAL
402
603 2 11 ICOMP OCSET 10 L8910
3
(icomp out) 97 80 REG_GPUCORE_ICOMP REG_GPUCORE_OCSET 80 97 REG BOOT GPUCORE 1
97 80
MIN_LINE_WIDTH=0.4mm 0.36UH-28A-0.66MOHM
97 GPUCORE_ICOMP_R 12 ISUM REG UGATE GPUCORE 1 MIN_NECK_WIDTH=0.2mm
(isum in) 97 80 REG_GPUCORE_ISUM PGOOD 28 REG_GPUCORE_PGOOD 80
97 80
1 2 PPGPUCORE_S0_REG 6 80
13 IREF REG PHASE GPUCORE 1
R89421 (iref in) 97 80 REG_GPUCORE_IREF
ENLL 20 PM EN REG GPUCORE S0 IN 60
97 80
REG_LGATE_GPUCORE_1 MIN_LINE_WIDTH=0.4mm
SDP110808MR36MF-TH
1.5K 8 RGND
97 80
MIN_NECK_WIDTH=0.2mm
NCNC
1% 97 80 REG GPUCORE RGND 24 REG_ISEN_GPUCORE_1 1 C8917
1/16W 9 VSEN BOOT1 REG_BOOT_GPUCORE_1 80 97
97 80
1
MF-LF (vsense in) 97 80 REG_GPUCORE_VSEN 25 REG_UGATE_GPUCORE_1
R8915 0.001UF
402 2 UGATE1 10%
1
2
8
7
80 97 1.0K 50V
(vdiff out) 97 80 REG GPUCORE VDIFF 7 VDIFF PHASE1 23 REG PHASE GPUCORE 1 80 97
1% 2 CERM
1/10W CRITICAL 402
27 REG LGATE GPUCORE 1 MF-LF D
22 LGATE1 80 97
Q8911
R8945 (straps) 97 80 REG_GPUCORE_VID4 VID4 2 603 REG SNUBBER GPUCORE 1 97
200K (straps) 97 80 REG_GPUCORE_VID3 21 VID3 FS 29 REG_GPUCORE_FS 97
IRF6892STR1PBF
97 80 REG_PHASE_GPUCORE_1 1 2 REG_GPUCORE_ISUM 80 97
30 4 G DIRECTFET_S3C
(straps) 97 80 REG_GPUCORE_VID2 VID2 18
1% 31 BOOT2 REG_BOOT_GPUCORE_2 80 97 1
1/10W (straps) 97 80 REG GPUCORE VID1 VID1
S R8917
MF-LF
R8946 32 UGATE2 17 REG_UGATE_GPUCORE_2 80 97 1.02
603 (straps) 97 80 REG GPUCORE VID0 VID0
200K 1 PHASE2 19 REG_PHASE_GPUCORE_2 80 97
1%
1/8W
97 80 REG_PHASE_GPUCORE_2 1 2 (straps) 97 80 REG_GPUCORE_MODE VID12.5
3
5
6
LGATE2 14 REG_LGATE_GPUCORE_2 80 97
MF-LF
1%
2 REF 2 805
NOSTUFF NOSTUFF 1/10W 97 REG GPUCORE REF
1 1
MF-LF 6 FB ISEN1 26 REG_ISEN_GPUCORE_1 80 97
C8945 C8946 603 (fb in) 97 80 REG GPUCORE FB
1000PF 1000PF ISEN2 16 REG_ISEN_GPUCORE_2 80 97
5% 5% (comp out) 97 80 REG_GPUCORE_COMP 5 COMP
25V 2 25V
C NP0-C0G 2
402
NP0-C0G
402
1 C8947
97 REG_GPUCORE_OFS 3 OFS
80 6 =PP12V_S0_REG_GPUCORE_S0
C
0.01UF 97 80 REG VCC U8900
10%
2 25V
THRM_PAD
R8947 X7R
402
EMC EMC
4.99 R89951 1
33
80 6 PPGPUCORE_S0_REG 1 2 REG_GPUCORE_IREF 80 97
R8997 Q8910.7:3MM Q8910.8:3MM CRITICAL
11K 64.9K 1 C8938 1 C8939 1
1%
1 1% 1% C8930
1/16W
MF-LF
NOSTUFF C8948 1/16W 1/16W 1UF 1UF 270UF
R8948 100PF MF-LF MF-LF 10% 10% 20%
402 402 2 25V 25V
10 5% 2 402 2 X5R 2 X5R 2 16V
1 2 50V ELEC
2 CERM 402 402 8X9-TH1
1% 402
1/16W
MF-LF R89961 1 C8990
402 28K 0.022UF
1% 10%
1/16W 16V
MF-LF 2 CERM-X5R
402 2 402 97 REG_BOOT_GPUCORE_2_RC
5
6
NOSTUFF CRITICAL
R89361 1 C8936 D Q8910
0 0.22UF IRF6802SDTRPBF
5% 10%
16V 1 G DIRECTFET-SA
1/10W 2 X7R
MF-LF 603
Straps & VID inputs GPU Core compensation and feedback 603 2 S
CRITICAL
77 6 =PP3V3_GPU_MISC =PP1V8_S0_GPUVID 6 L8930
4
97 80 REG_GPUCORE_COMP REG_BOOT_GPUCORE_2
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF 97 80
MIN_NECK_WIDTH=0.2mm 0.36UH-28A-0.66MOHM
1 REG_UGATE_GPUCORE_2 MIN_LINE_WIDTH=0.4mm
R8960 1R8962 1R8964 1R8966 1R8968 1R8992 97 80
REG_PHASE_GPUCORE_2
1 2 PPGPUCORE_S0_REG 6 80
97 80
1K 1K 1K 1K 1K 1K 1 1 C8981 1 C8980 SDP110808MR36MF-TH
1%
1/20W
1%
1/20W
1%
1/20W
1%
1/20W
1%
1/20W
1%
1/20W
R8994 R8998 1
27PF 0.022UF 97 80 REG LGATE GPUCORE 2 MIN_NECK_WIDTH=0.2mm
NCNC
MF MF MF MF MF MF 10K 1K 5% 10% MIN_LINE_WIDTH=0.4mm 1
R8954 50V 16V 97 80 REG_ISEN_GPUCORE_2 C8937
0 2 201 2 201 2 201 2 201 2 201 2 201 5%
1/20W
1%
1/20W 2 CERM 2 CERM-X5R 1
R8935 0.001UF
GPU_VCORE_VID4 1 2 97 80 REG_GPUCORE_VID4 MF MF 402 402 10%
1
2
8
7
78 IN 1.0K 50V
5% MF R8953 2 201 201
2 1% 2 CERM
GPUCORE COMP RC
B 78 IN
1/20W
GPU_VCORE_VID3
201
1
5%
0
2
MF R8952
97 80 REG_GPUCORE_VID3 REG_GPUCORE_MODE_B
1
97 1/10W
MF-LF
2 603
D
CRITICAL
Q8931
402
REG_SNUBBER_GPUCORE_2
B
1/20W 201 1 R8980 IRF6892STR1PBF
97
GPU VCORE VID2 1

0
2 REG GPUCORE VID2
C8991 4.99K
78 IN 97 80
100PF 1% 4 G DIRECTFET_S3C
R8951 5%
1/20W
MF
201
5%
25V
1/16W 1
0 2 CERM MF-LF S R8937
78 IN GPU_VCORE_VID1 1 2 97 80 REG_GPUCORE_VID1 201 2 402 1.02
5%
1/20W
MF
201
R8950 To Core feedback 1%
0 1 1/8W
5
6
3
78 GPU_VCORE_VID0 1 2 97 80 REG_GPUCORE_VID0 MF-LF
IN REG_GPUCORE_FB 80 97
2 805
5%
1/20W
MF
201
R8955
0 2 3
78 GPU_VCORE_VID5 1 2 97 80 REG_GPUCORE_MODE REG_GPUCORE_MODE_PU 1
IN R8983
5%
1/20W
Q8990 100
MF NOSTUFF MMBT2222AM3T5G 1%
1
201
R8961 1R8963 1R8965 1R8967 1R8969 1
R8993 SOT723 1/16W
MF-LF
1K 1K 1K 1K 1K 1K 2 402
1% 1% 1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W GPUCORE VDIFF RC 97
MF MF MF MF MF MF GPU Core Output Decoupling
2 201 2 201 2 201 2 201 2 201 2 201 1
R8986 1 C8983 PPGPUCORE_S0_REG
1.0K 80 6
1% 0.0015UF
1/10W 10%
50V
MF-LF 2 CERM-X7R
2 603 402 CRITICAL CRITICAL CRITICAL CRITICAL
GPU Core voltage sense input 97 GPUCORE VDIFF R
1
C8920 1
C8921 1
C8922 1
C8923
330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM 330UF-0.006OHM
20% 20% 20% 20%
2 2V 2 2V 2 2V 2 2V
R8985 POLY
CASE-D2-SM
POLY
CASE-D2-SM
POLY
CASE-D2-SM
POLY
CASE-D2-SM
0
97 80 REG_GPUCORE_VDIFF 1 2
R8971 To Core voltage sense 1/16W
MF-LF
10 402
SNS GPU CORE P 1 2 REG GPUCORE VSEN
A 97 79 IN
5% NOSTUFF
80 97

1/16W
MF-LF 1 C8978 Power goods PAGE TITLE
Core sense from GPU

402
1000PF
25V 70 6 =PP3V3_S0_PWRCTL
VReg GPU Core
R8976 2 NP0-C0G DRAWING NUMBER SIZE
97 79 SNS GPU CORE N 1

10
2
402
REG GPUCORE RGND 80 97 1 Apple Inc. 051-9509 D
IN
5%
R8910 REVISION
NOSTUFF NOSTUFF 10K R
1/16W
MF-LF 1 C8971 1 C8976 5% 4.2.0
402 1/20W NOTICE OF PROPRIETARY PROPERTY: BRANCH
100PF 100PF MF
5% 5% 2 201 THE INFORMATION CONTAINED HEREIN IS THE
2 50V
CERM
50V
2 CERM PROPRIETARY PROPERTY OF APPLE INC.
402 402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
80 REG GPUCORE PGOOD PM PGOOD REG GPUCORE S0 OUT 60 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 89 OF 113
MAKE_BASE=TRUE II NOT TO REPRODUCE OR COPY IT
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Internal DP Connector Backlight Control
U9000 output Y2 is a non-inverted, delayed version of input A

518S0829 The delay applies only on a L->H transition on A. This guarantees video is valid before the backlight is enabled.
On a H->L transition of A, Y2 follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video
CRITICAL
Y1 is simply an inverted version of A, with no delay
J9100
C 20525-130E-01
F-RT-SM
C
83 47 6 =PP3V3 S0 DP
L9100 31
FERR-250-OHM
6 =PP12V S0 LCD 1 2 PP12V LCD 1
VOLTAGE=12V 2 1
SM MIN LINE WIDTH=0 4 mm C9106
MIN NECK WIDTH=0 1 mm 1 C9120 1 C9101 3 0.1UF
10UF 0.001UF 20%
10% 20% 4 10V
16V 50V 2 CERM
2 2
1
X5R CERM CERM 5 402
0805 402
6 VCC
7
8
U9100
SN1105002 To Diag LED
9 SC70
81 VIDEO ON 3 A Y1 5 VIDEO ON L 5
10 IN OUT
11 6 NC Y2 4 BKLT EN OUT 86
NC CRITICAL To BLC
12
GND
94 47 SMB DP TCON SDA 13
BI
2
Display TCon Master 14
94 47 OUT SMB DP TCON SCL
47 SMB DP TCON SLA SDA 15
BI
Display TCon Slave 16
47 IN SMB DP TCON SLA SCL
98 52 DP INT SPDIF AUDIO 17
OUT
82 DP INTPNL HPD 18
OUT
19
98 82 DP_INTPNL_AUX_N 20
BI
98 82 DP INTPNL AUX P 21
BI
22
B 98 82 IN DP INTPNL ML P<0> 23
24
B
98 82 IN DP INTPNL ML N<0>
25
98 82 DP INTPNL ML P<1> 26
IN
98 82 DP INTPNL ML N<1> 27
IN
28
81 VIDEO ON 29
OUT
86 BKLT_VSYNC 30
OUT
33
34
35
36
37
38
39
40
41
32

PAGE TITLE
Internal DP Support
DRAWING NUMBER SIZE

REVISION
R
4.2.0
91 OF 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TP to DP aliases
34 IN
TP DP TBTSRC ML CP<0> DP TBTSRC ML P<0> 82 98
MAKE BASE TRUE
34 IN
TP_DP_TBTSRC_ML_CN<0> DP_TBTSRC_ML_N<0> 82 98
MAKE BASE TRUE
TP_DP_TBTSRC_ML_CP<1> DP_TBTSRC_ML_P<1>
D
34
34
IN
TP DP TBTSRC ML CN<1> DP TBTSRC ML N<1>

MAKE BASE TRUE
82 98
82 98
D
IN
MAKE BASE TRUE
34 BI
TP_DP_TBTSRC_AUXCH_CP DP_TBTSRC_AUXCH_P 82 98
MAKE BASE TRUE
34 BI
TP DP TBTSRC AUXCH CN DP TBTSRC AUXCH N 82 98
MAKE BASE TRUE
=PP3V3_S0_INTDPMUX 6 82
NC aliases
TP DP TBTSRC ML CP<2> NC DP TBTSRC ML P<2>

1 C9268 1 C9269
34 IN
NO TEST TRUE MAKE BASE TRUE
0.1UF 0.1UF
10% 10%
34 IN TP_DP_TBTSRC_ML_CN<2> NC_DP_TBTSRC_ML_N<2> 6.3V
2 X5R
6.3V
2 X5R
NO TEST TRUE MAKE BASE TRUE 201 201
29
20
16
12
TP_DP_TBTSRC_ML_CP<3> NC_DP_TBTSRC_ML_P<3>
9
3
34 IN
34 IN
TP DP TBTSRC ML CN<3> NC DP TBTSRC ML N<3> 98 77 IN DP_INT_EG_ML_P<0> 31 D0+A VDD
DP INT EG ML N<0> 30
98 77 IN D0-A U9200
DP INT EG ML P<2> NC DP INT EG ML P<2> DP_INT_EG_ML_P<1> 27 PI3VEDP212 C9200 1 2
77 IN 98 77 IN D1+A
NO TEST TRUE MAKE BASE TRUE TQFN 0.1UF 201 10% DP_INTPNL_ML_P<0> OUT 81 98
98 77 DP_INT_EG_ML_N<1> 26 D1-A CRITICAL D0+ 1 98 DP_INTPNL_ML_C_P<0> X5R 6 3V
DP_INT_EG_ML_N<2> NC_DP_INT_EG_ML_N<2> IN DP_INTPNL_ML_N<0>
77 IN
NO TEST TRUE MAKE BASE TRUE 98 77 BI DP INT EG AUX P C9208 1 2 D0- 2 98 DP INTPNL ML C N<0> C9201 1 2 OUT 81 98
0.1UF 201 10% 98 DP_INT_EG_AUX_C_P 19 AUX+A 0.1UF 201 10%

X5R 6 3V X5R 6 3V
98 DP_INT_EG_AUX_C_N 18 AUX-A
77 IN
DP INT EG ML P<3> NC DP INT EG ML P<3> 98 77 BI DP INT EG AUX N C9209 1 2 C9202 1 2
NO TEST TRUE MAKE BASE TRUE 0.1UF 201 10%
17 0.1UF 201 10% DP_INTPNL_ML_P<1> OUT 81 98
D1+ 4
C 77 IN
DP INT EG ML N<3> NC DP INT EG ML N<3>
X5R 6 3V
82 78 OUT DP_INT_EG_HPD HPD_A
D1- 5
98
98
DP_INTPNL_ML_C_P<1>
DP_INTPNL_ML_C_N<1> C9203 1
0.1UF
X5R 6 3V
2
201 10%

LB 820-3302 Schematic Diagram - LSS

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8 7 6 5 4 3 2 1

LAST_MODIFIED=Thu Jan 12 10:24:09 2012

D Page Contents Sync Page Contents Sync D

A 100 BLC Constraints D7 DAVE

Schematic / PCB #’s SCH,D7,MLB

System Block diagram can be found on Kismet

A SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A

System Block Diagram

Apple Inc. 051-9509 D

Power Block Diagram

en S0 Reg S0 IOVDD PP1V05_S0_GPU

639-3566 PCBA,MLB,D7,GSA,GOOD D7_COMMON,CPU:GOOD,GPU:GSA,GS,FBA,SSD:N,EEEE:DF98 377S0107 377S0126 ALL USB diodes

511S0073 1 SOCKET,MOLEX,LGA1155,CPU-LF U1000 CRITICAL

825-7122 1 MLB LABEL,48.0X4.8 EEEE_DF98 CRITICAL EEEE:DF98

511S0071 511S0073 ALL TYCO SOCKET

Add ’K70_PRODUCTION’ at RevA release 607-9435 K70,GDDR5,HYNIX FB:BOTH_HYNIX

D7_DEVEL XDP_CONN,LPCPLUS,VREFMRGN:EXT,BKLT_PWM,DEVEL_SENSORS,DEVEL_AUDIO 607-9433 K70,GDDR5,SAMSUNG_CH1 FB:CH1_SAMSUNG

C DEVEL_SENSORS SNS_VDDQS0_GPU:Y,SNS_VDDQS3:Y,TEMPSNSDEV 607-9436 K70,GDDR5,HYNIX_CH1 FB:CH1_HYNIX

607-9437 K70,GDDR5,HYNIX_CH2 FB:CH2_HYNIX

333S0631 2 IC SGRAM GDDR5 64MX32 4 2GBPS D DIE HF U8400,U8450 CRITICAL FB:CH1_SAMSUNG

333S0630 2 U8400,U8450 CRITICAL FB:CH1_HYNIX

333S0631 2 IC SGRAM GDDR5 64MX32 4 2GBPS D DIE HF U8500,U8550 CRITICAL FB:CH2_SAMSUNG

338S1047 1 IC TBT CR 4C ES1 288 FCBGA 12X12MM U3600 CRITICAL

337S4221 1 IC,GPU,NV,GK107-GS-2/1-QS-A U8000 CRITICAL GPU:GSA

337S4220 1 IC,GPU,NV,GK107-GS-2/1-QS-A U8000 CRITICAL GPU:GSB

607-9432 VRAM GDDR5_BOTH

341S3487 1 IC,ENET 1MBITFLASH,CIV,PVT,J40 U3990 CRITICAL CIVROM:PROG

GPU GOOD Led VIDEO ON Led

61 44 ALL SYS PWRGD 5 G S SOT 363

A SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A

Apple Inc. 051-9509 D

MLB to AC-DC Supplemental Signal Connector S0 Rails Ground/Common

5% 2 =PP12V_S0_SNS_GPUUNCORE_R 48 PPDDRVTT_S0 PPDDRVTT_S0_LDO

SMC_ACDC_ID 97 PP12V_S0_GPUCORE PP12V_S0_SNS_GPUCORE 48 PPDDRVREF DQ_MEM_A_S3 PPDDRVREF_DQ_MEM_A

=PP12V_S0_REG_GPU_VDDQ_S0 97 PPDDRVREF_CA_MEM_A_S3 PPDDRVREF_CA_MEM_A 32

4 =PP5V_S0_REG_GPU_VDDQ_S0 74 95 PP1V05_S0 PP1V05_S0_REG 65

1 1 1 =PP5V S0 CAMERA =PP1V05 S0 PCH

10UF 1000PF 1000PF =PP5V_S0_ISENSE 48 =PP1V05_S0_PCH_VCC_ADPLL 17

G3H Rails =PP5V_S4_FET_P5V_S0 70 =PP3V3_S0_AUDIO_DIG 56

=PP5V S4 MEMRESET 28 =PP3V3 S0 BT =PPVCCIO_S0_SMC 45

=PP12V_G3H_FET_P12V_S5 69 97 PP3V3_S4 PP3V3_S4_FET 70 =PP3V3_S0_LED 5

=PP3V3_S4_PWRCTL 70 =PP3V3_S0_PCH =PPVAXG_S0_CPU 13 17 48 62

97 PP3V42_G3H PP3V42_G3H_REG 69 =PP3V3_S4_ALS 40 =PP3V3_S0_PCH_GPIO 15 19 20 36

=PP3V3_G3H_SMC =PP3V3_S4_LED =PP3V3_S0_PCH_STRAPS 95 PPVCCSA_S0 PPVCCSA_S0_REG 66

=PPVIN_G3H_SMCVREF 45 =PP3V3_S4_PCH 15 =PP3V3_S0_PCH_VCC_ADAC 17

=PP3V3_G3H_SMC_USBMUX =PP3V3_S4_PM =PP3V3_S0_PCH_VCC_GPIO

=PP3V3_S4_TBTBPWRSW =PP3V3_S0_SMBUS =PPVDDIO_TBT_CLK 26

PP5V_S5 PP5V_S5_LDO =PP3V3_S0_BKLT_VDDIO 86 95 PP1V05_TBTCIO =PP1V05_TBTCIO_FET 36

97 PP3V3 ENET PP3V3_ENET_FET 38 =PP3V3_GPU_VDD33 71 77 78 79

97 PP3V3 S5 PP3V3 S5 REG 67

=PP3V3_S5_VRD 95 PPVDDQ_S3 PPVDDQ_S3_REG 68

CPU Heatsink WIRELESS CARD MTG HOLES

OMIT OMIT OMIT OMIT

GPU HEATSINK MOUNTING FEATURES

CRITICAL POGO PINS

USB Can holes

A SYNC MASTER=K70 MLB SYNC DATE=11/30/2011 A

Apple Inc. 051-9509 D

A 22 PP1V05 S0 PCH VCCAPLL SATA NC PP1V05 S0 PCH VCCAPLL SATA