8086 Microprocessor

By

Lecture 3
 C lo c k D a ta
N a m e D a te T r a n si s to r s M ic ro n s M IP S
sp e e d w id th
808 0 197 4 6 ,0 0 0 6 2 M H z 8 b it s 0 .6 4
1 6 b it s
808 8 197 9 2 9 ,0 0 0 3 5 M H z 8 -b it 0 .3 3
bus
802 86 198 2 1 3 4 ,0 0 0 1 .5 6 M H z 1 6 b it s 1
803 86 198 5 2 7 5 ,0 0 0 1 .5 16 M H z 3 2 b it s 5
804 86 198 9 1 ,2 0 0 , 0 0 0 1 25 M H z 3 2 b it s 20
3 2 b it s
P e n t iu m 199 3 3 ,1 0 0 , 0 0 0 0 .8 60 M H z 6 4 - b it 100
bus
3 2 b it s
233
P e n t iu m II 199 7 7 ,5 0 0 , 0 0 0 0 .3 5 6 4 - b it ~ 300
M H z
bus
3 2 b it s
450
P e n t iu m III 199 9 9 ,5 0 0 , 0 0 0 0 .2 5 6 4 - b it ~ 510
M H z
bus
3 2 b it s
P e n t iu m 4 200 0 4 2 ,0 0 0 ,0 0 0 0 .1 8 1 .5 G H z 6 4 - b it ~ 1 ,7 0 0
bus
3 2 b it s
P e n t iu m 4
200 4 1 2 5 ,0 0 0 ,0 0 0 0 .0 9 3 .6 G H z 6 4 - b it ~ 7 ,0 0 0
" P re s c o tt"
bus
 Overview: Intel 8086
• Introduced in 1978
• Performance < 0.5 MIPS
• 16-bit architecture
• “Assembly language” compatible with 8080
• Designed using HMOS technology
• 29,000 transistors
• Includes memory protection, support for Floating Point
coprocessor
• In 1981, IBM introduces PC
• Based on 8088--8-bit bus version of 8086
 8086 Features
• Manufacturing process 3 micron N-channel, silicon gate technology (HMOS)
• 29,000 transistors
• Data bus width: 16 bit
• Address bus width: 20 bit
• Physical memory: 1MB
• Package 40-pin side-brazed ceramic DIP
• Speed: 5 MHz
• Floating Point Unit: 8087
• V core (V): 5 ± 10%
• Min/Max operating temperature (°C): 0 – 70
 8086 Features

• 20-bit address bus - 220 = 1,048,576 = 1 meg

• The address refers to a byte in memory.

• In the 8088, these bytes come in on the 8-bit data bus.

• In the 8086, bytes at even addresses come in on the low half of the data bus (bits 0-7)
and bytes at odd addresses come in on the upper half of the data bus (bits 8-15).

• The 8086 can read a 16-bit word at an even address in one operation and at an odd
address in two operations. The 8088 needs two operations in either case.

The least significant byte of a word on an 8086 family microprocessor is at the lower
address.
8086 Architecture
 8086 Architecture

• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

• The BIU fetches instructions, reads and writes data, and computes
the 20-bit address.

• The EU decodes and executes the instructions using the 16-bit ALU.
Bus Interface Unit (BIU)

• The BIU contains the following registers:

• IP - the Instruction Pointer
• CS - the Code Segment Register
• DS - the Data Segment Register
• SS - the Stack Segment Register
• ES - the Extra Segment Register
• The BIU fetches instructions using the CS and IP, written CS:IP,
to construct the 20-bit address.
• Data is fetched using a segment register (usually the DS) and
an effective address (EA) computed by the EU depending on
the addressing mode.
• Instruction Queue
• The BIU’s instruction queue is a First-In-First-Out (FIFO) group of registers, in which up to six
bytes of instruction can be pre-fetched from memory ahead of execution.
• This mechanism is called pipelining.
• If the queue is not full and empty by two bytes, the BIU may pre-fetch instructions.
• The queue allows the BIU to keep the EU supplied with pre-fetched instructions without tying
up the system bus.
 Execution Unit
The EU contains the following 16-bit registers:
AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer \ defaults to stack segment
BP - the Base Pointer /
SI - the Source Index Register
DI - the Destination Index Register

These are referred to as general-purpose registers, although,

as seen by their names, they often have a special-purpose use
for some instructions.
General purpose Registers of 8086

• The AX, BX, CX, and DX registers can be considered as

two 8-bit registers, a High byte and a Low byte.
• This allows byte operations and compatibility with the
previous generation of 8-bit processors, the 8080 and
8085.
• 8085 source code could be translated in 8086 code
and assembled.
• The 8-bit registers are:
• AX --> AH,AL
• BX --> BH,BL
• CX --> CH,CL
• DX --> DH,DL
 8086 Programmer’s Model
ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
14
8086/88 internal registers 16 bits (2 bytes each)

AX, BX, CX and DX are two

bytes wide and each byte can
be accessed separately

These registers are used as

memory pointers.

Flags will be discussed later

Segment registers are used

as base address for a segment
in the 1 M byte of memory