Digital VLSI Design

Lecture 10:
I/O and Pad Ring
Semester A, 2018-19
Lecturer: Dr. Adam Teman

3 February 2019
 Lecture Outline

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Packaging IOs System-in-Package

A bit about Packaging

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 How do we get outside the chip?
• It’s actually a pretty long road…
• I/O Circuits
• Bonding
• Package
• Board
• Once we get out of the chip
• Long wires mean a lot of delay, capacitance, inductance.
• We can use fat wires for low resistance.
• But we have a lot more room to play around.

• The interface between the chip and

the outer world is the IC package.
4 © Adam Teman, 2019
 Main Properties of Package
• The package provides the physical, temperature and electrical protection.
• Electrical connection from chip to board Package

• Physical connection from chip to board Chip Bond Wire Lead Frame Board

• VDD VDD

Signal Pins

Signal Pads
Protection from high voltages (outside) Package
Chip
• Physical protection Chip
Capacitor
Board

• Thermo isolation GND GND

• Requirements of a package are:

• Electrical: Capacitance, Resistance, Inductance, Impedance Tuning
• Interface: A large number of I/O pins
• Mechanical: Die/Bond protection, Compatibility with PCB
• Thermal: Heat Removal
• Cost: As low cost as possible (without fan, heat sink, etc.)
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© Adam Teman, 2019
 Package to Board Connection

QFP
(Quad Flat Package)
DIP
(Dual Inline Package)

PGA
(Pin Grid Array)
BGA (Ball Grid Array)
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 IC to Package Connection
Mold Compound

Two main approaches: Wire Bond

• Wire bonding
Die

• All pads are around Die Attach or Sn Plating

Solder or Sn Planting
chip edges (~100um pitch). Exposed Die Pad

• Slow, serial bonding process.

• Long, high RLC wires
(~5nH, 1pF per wire).
• Flip Chip
• Pads on top of IC core.
• High pin count.
• Short, low RLC bonds (0.1nH)
• Fast parallel bonding process.
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• But… Expensive! © Adam Teman, 2019
 Some Bond Wire Requirements
When designing a wire bond package,
you need to pay attention to:
• No crossing of bond wires
• Minimum spacing
• Maximum angle of wires
• Maximum length of wires

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 To summarize

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Packaging IOs System-in-Package

Input/Output Circuits (I/Os)

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 So how do we interface to the package?
• We need to create a physical connection to the bonding wire.
• For wire bond packaging:
• Use a landing pad.
• Basically a big (100µm X 100µm) piece of metal.
• Many stacking layers for physical robustness.

• For flip chip packaging:

• Use solder bumps.
• Route to bumps with
Redistribution Layer
(RDL)

11 © Adam Teman, 2019

 But what connects to the bonding pads?
I/O Circuits! Goals of I/O Design:
• Reduce delay to and from
• Requirements of I/O Circuits: outside world (PCB)
• High drive current capability
• Availability to drive big loads
• Match impedance to load
• Due to package and transmission lines
• ESD Protection
• Voltage Consistency • Level shifting of voltages
• Due to different supply voltages on the board (i.e.1.2V inside/3.3V outside)
• Low switching noise • Meet specifications of
• Due to package and transmission line Interfaces
inductance • Reduce power (short circuit
• ESD protection current through output buffers)
• Due to high potential difference of external • High voltage tolerance
devices

12 © Adam Teman, 2019

 Types of I/O Cells I/O Libraries

There are several types of basic I/O cells: Standard Special

• Digital I/O Buffers
• Provide high drive Digital Analog Power SSTL HSTL LVDS …
up-level shifting output
• Provide down-level shifting
and ESD protection for inputs
• Analog I/O Cells
• Provide ESD protected analog inputs/outputs
• Power supplies
• Provide power to the I/O and Core supplies
• Provide the basis for ESD protection

13 © Adam Teman, 2019

 Digital I/O Buffer DIN
VDD VDDIO PAD
RX
OEN
• Digital I/O
• Output buffer needs to drive pF, not fF
• Requires increasing fanout inverter chain DOUT TX
VSS VSSIO
• Short circuit current is unacceptable!

DOUT
E

DIN

R_EN

PADIN ESD

PULLUP/ PUE
30K PULL
DOWN

PDE

VDD VSS IOVDD IOVSS

14 © Adam Teman, 2019
 ESD Protection
• Electrostatic discharge (ESD)
• One of the most important reliability problems in the IC industry. Junction
Metal/Via
Damage
• ESD protection circuits divert high currents away from the Breakdown Gate oxide
damage
internal circuitry and clamp high voltages during an ESD stress.
• Diode clamps Diode
• Diodes turn on if pad voltage: R Clamps
• Exceeds VDD +0.7V PAD
• Drops below VDD -0.7V
• Formation: Current Limiting Thin
• P+ diffusion in n-well Resistor Gate Oxides
• N+ diffusion in p-substrate
• Resistor Wide, but turn
on slowly
First protection until
primary turns on
• Limits the current
• Protects secondary protection
• Formation: Primary Current Secondary
PAD Internal
• Diffusion ESD Limiting ESD circuits
• Polysilicon Elements resistor Elements
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 Analog I/O Cell
• Analog I/O
• Used for passing “analog” signals to/from the chip.
• Basically, “a wire”, but should have some degree of ESD
protection.

IOVDD ESD

PAD PADNORES
Metal resistor 0.3
Ohm

IOVSS ESD

16 © Adam Teman, 2019

 Power Supply Cells and ESD Protection
• Power supply cells are analog cells Corner
(i.e., just a wire).
IO Cell
• But these cells supply the I/O rings for:
• Power distribution
• ESD Protection VSS VDD
VSSIO VDDIO
• Generally, digital (core) and I/O power/ground
supplies are separate: VDDIO
• I/Os sink a lot of current → Power supply noise Digital PAD
• I/Os usually run at a higher voltage level Input

(i.e., 2.5V vs. 1.2V)

• All (four) types of supplies connect to rings
under the I/O circuits. VSSIO
17 © Adam Teman, 2019
 Simultaneously Switching Outputs
• Simultaneously Switching Outputs (SSO) is a metric describing the period of
time during which the switching starts and finishes.
• Consider a 64 bit output bus. If all transition from high to low, lots of current
must driven/sunk leading to extensive voltage drop.
• Problem is independent of frequency
• The SSO metric indicates how many I/O Power supplies are needed.
SSO-2

Vdrop=Lpackagedi/dt

18 © Adam Teman, 2019

 Design Guidelines for Power
• Follow these guidelines during I/O design:
• Put as many mutual capacitances as possible between IC supply voltages.
• Put as many supply voltage pins as possible.
Put supply and ground supply voltages as close to each other as possible.
• Provide separate supply voltages for the core and I/Os.
• Reduce inductances as much as possible by using as short transmission
lines as possible.
• Reduce signal rate as much as possible. But be careful as the reduction of
signal rate leads to signal weakening,
and experiments show that
those noises can have definite
affect on the given I/O cells.

19 © Adam Teman, 2019

 Pad Configurations
• In-line: logic
• Pads are placed next to each other, Bonding pad
with the corresponding bond pads
lined up against each other having
a small gap in between.
Corner
• Staggered: Cell
• Useful technique if design is
“Pad Limited”.
• A larger number of pads
can be accommodated in
the design, but the overall
height of the pad structure
increases significantly
In-Line Staggered (non-CUP)
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 Pad Configurations logic
Bonding pad

• Circuit Under Pad (CUP):

• CUP I/O is has the bonding pad over the I/O body itself.
• Bonding pad has to be placed over the I/O body and is
connected to the PAD pin of the I/O.
• CUP I/O can substantially reduce the die size since the
bonding pad does not take any extra space in addition to the
I/O body itself.
• Flip Chip with RDL:
• In the Flip Chip methodology, I/O bumps and driver cells
may be placed in the peripheral or in the core area.
• Signals and power are connected to the bumps through
a top aluminum layer called the Redistribution Layer (RDL).
21 © Adam Teman, 2019
 The Chip Hall of Fame
• Most chips are covered by a package.
But that was not exactly the case for the

Source: Kodak

• The chip that brought digital photography outside the lab.

• The imager of the DCS 100, the first commercially available DSLR.
• Release date: 1991 Technology: CCD
• Resolution: 1.3 MegaPixel
• Initial cost of Kodak DCS 100: $25,000
• The image sensor was mounted on a Nikon F3 Body.
• Required a 5kg external data storage unit that users
had to carry on a shoulder strap.
• Had a 200MB HDD that could store 156 images
2017 Inductee to the IEEE Chip Hall of Fame Source: Kodak
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Packaging IOs System-in-Package

System in Package (SiP)

 SoC vs. SiP
• SoC – System-on-Chip
• Integration of several IPs on a single silicon substrate.
• SiP – System-in-Package
• Integration of several silicon devices (chips) in a single package.
• Why SiP?
• Smaller chips → Improved yield
• Mix several process nodes
• i.e., 7nm for high speed logic, 45nm for analog.
• Close integration with non-CMOS device
• Flash
• Silicon Photonics
• SiGe
• High Bandwidth Memory (HBM DRAM)
24 © Adam Teman, 2019
 MCM – Multi Chip Module
• Assembly of several silicon devices
on Organic Substrate (PCB)
• Very mature technology
• Routing pitch ~30um
• Bump Pitch > 160um

AMD Radeon E4690:

GPU + DRAM in MCM
Source: PC Magazine Source: AnandTech

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 Silicon Interposer
TSMC CoWoS Technology
• Several silicon devices on Passive Silicon Carrier
• Substrate is a chip (No Transistors)
• Silicon Carrier is later assembled on organic substrate
• Use TSVs (Through Silicon Vias) to cross interposer
• Much more dense bonding
• Routing Pitch ~1µm (65nm Silicon Mature Technology)
• Bump Pitch (µBump) – 40µm
• Usage of Silicon Manufacturing equipment
• Reticle size limitation (32x26mm)
• TSMC has a stitching process for large devices
• Relatively New technology
• Hence, more expensive
• Early Production since 2011
• Simpler than 3D technology
• Heat removal and Power delivery are almost
the same as MCM
26 Source: siliconsemiconductor.net © Adam Teman, 2019
 HBM – High Bandwidth Memory
• Memory standard designed for needs of
future GPU and HPC systems

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 Main References
• AMMOS – CDNLive 2007
• IDESA
• CMOS VLSI Design
• Ido Burstein – Mellanox Technologies

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