Sukanya Pandey Resume

Sukanya
Bengaluru (India)
(+91) 7004838620
Pandey
sukanyapandey989@gmail.com
www.linkedin.com/in/sukanya-pandey/
Career Summary___________________________________________________________
• Semiconductor Product engineer • M.Tech - IIT Delhi • Digital circuit design
• M.Tech from IIT-Delhi with 2.5 years of experience in Semiconductor domain working as a Senior Engineer
in Micron Technology for Datacenter and Automotive SSD System Validation and Data Analysis.
• Have strong educational background in Digital Design, Circuits, Device physics, Hardware Modeling using
Verilog, Signal Processing.
• Demonstrated ability to solve and drive critical customer issues with high end to end ownership working
collaboratively with global cross-functional teams such as Firmware, Hardware and Media Architecture
Group. Self-motivated, determined, consistent and focused achiever looking forward to extend these key
strengths in the digital circuit domain
Work Experience_____________________________________________________________
MICRON TECHNOLOGY Bengaluru, India
Senior Product Engineer, NVM QRA July 2021- Present
• Responsible for product qualification and reliability analysis on different design approaches and device
parameter characterization for SSD in automotive and data center applications.
• Reviewed drive level TSM (Technical specification matrix) Requirements to verify that the current test
cases validate all the design requirements, propose new test cases, and validate with data analysis.
• Analyzed multiple performance parameters like NAND health, component level analysis, performance
thruputs on various extrinsic tests like Reliability demonstration, Environmental stress, Power cycling,
cross temperature tests. This led to successful launch of Enterprise Data Center SSD products with fewer
abnormalities at customer end.
• Initiated regular temperature characterization which led to stabilization of drive temperatures with
respect to the test environment and resolved the critical “thermal throttling” issue that was increasing
the overall runtime for testing and delayed qualification cycle to the customer.
• Performance analysis of the Reliability Requirements encompassing NAND endurance, Read/Write
Disturb, Program Erase Cycles, End-of-life cycling and power cycling in alignment with TSM and JEDEC spec
• Drove and analyzed failure signatures, completed failure categorization, created and owned workflow
processes in JIRA for critical issues that led to early failure detection and firmware maturity and release.
• Summarizing the system validation data analysis and generating customer reports for product release.
• Analysis and risk assessment to identify potential failure mode and recommend remedial strategy.
• Demonstrated success in the automation of test data analysis, statistics, and failure prediction in JMP
using JSL scripting thereby increasing process efficiency.
• SSD System Validation Data Analysis resulted in the better understanding of the SSD as a system, Front-
end, FTL, Backend and NAND Flash.
Education____________________________________________________________________
IIT DELHI 99.14 percentile in GATE
MTech in RF Design and Technology (Specialized in Signal Processing and MOS VLSI) CGPA: 8.76/10
JECRC UDML COLLEGE OF ENGINEERING Jaipur, India

B. Tech in Electronics and Communication Engineering Overall score: 78.15%
Academic projects___________________________________________________________
DETECTION OF ACOUSTICALLY RADIATING SOURCE IN NON-GAUSSIAN NOISE: Developed a M.Tech Thesis
noise analysis algorithm to detect acoustically radiating source that consists of both narrowband
and broadband signal components in the presence of non-Gaussian noise and low SNR
conditions
DESIGN OF LOW POWER 8 BIT BINARY TO GRAY CODE CONVERTER USING, TRANSMISSION May – June
GATES, DOMINO LOGIC, STATIC CMOS: Comparison of different types of logic has been done 2020
based on power delay product and number of transistors used
DESIGN AND VERIFICATION OF BASIC DIGITAL CIRCUITS USING VERILOG: Various digital Summer
circuits have been designed and verified using Verilog like counters, registers, flip-flops, latches Project 2020
on EDA playground tool
DESIGN AND VERIFICATION OF A SIMPLE TRAFFIC LIGHT USING VERILOG: Simplified form of Summer
Moore machine-based traffic light design has been created and then later was verified on EDA Project 2020
playground tool
DESIGN OF AN AREA EFFICIENT LOW POWER MULTIPLIER USING APPROXIMATE 15-4 Oct 2020-Jan
COMPRESSOR: The project presented designing of a multiplier using 15-4 approximate 2021
compressor which shows significant improvement in terms of power than that of an accurate
15-4 compressor
Courses and Skills___________________________________________________________

Special Courses : Digital Electronics, MOS VLSI Design, Basics of statistical signals, CAD of RF and microwave
devices, Selected advanced topics in RFDT, RF and microwave measurement lab, Sensor array
signal processing, Architectures and algorithms for DSP systems, Human & machine speech
communication
Languages: Verilog, MATLAB, C, Assembly language (8085 microprocessor), Python
Tools: Cadence Virtuoso, Serenade, Icarus Verilog, GTKWave, Intellicad, Raspberry-Pi(3B+), PC-104,
Pycharm, JMP
Honors and Awards___________________________________________________________

EXCELLENT EXECUTION AWARD
2022 Awarded by Director, System Design Engineering for tenacity in data analysis on an Micron Global
enterprise SSD product qualification. This was a pioneering effort for the India team on award
completely owning an enterprise SSD qual program for the first time.

2021 Awarded by Vice President, Global Quality for spearheading data analysis on critical Micron Global
issues in a team effort to achieve qualification of a leading enterprise SSD product with award
maximum NAND flash layers

2021 Awarded by Manager for quick assimilation on data analysis and finding critical issues Micron,
that were instrumental towards product qualification for multiple programs India
COLLABORATION AWARD
2022 Awarded by Director, Global Quality for effective training and knowledge transfer to Micron Global
new engineers in the US team award

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Sukanya

JECRC UDML COLLEGE OF ENGINEERING Jaipur, India

Courses and Skills___________________________________________________________

Honors and Awards___________________________________________________________

EXCELLENT EXECUTION AWARD

EXCELLENT EXECUTION AWARD

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