8 7 6 5 4 3 2 1

315mA MAX
R1703

NAND
24.9
PP1V8 1 2 PP1V8_NAND_AVDD
1%
1/32W
Alimenta??o da PMU Buck03 MF
01005
ROOM=NAND
1
C1726
2.2UF
1
C1710
0.1UF
20% 20%
6.3V 6.3V
2 X5R-CERM 2 X5R-CERM
0201-1 01005
ROOM=NAND ROOM=NAND
NAND_AGND
PROBE POINTS
17

D D
1
C1701
15UF
1
C1707
15UF
1
C1729
15UF
1
C1730
15UF 17 8 90_PCIE_AP_TO_NAND_REFCLK_P 1
SM
PP1701
PP
20% 20% 20% 20% P2MM-NSM
6.3V 6.3V 6.3V 6.3V ROOM=NAND
2 X5R
0402-1
ROOM=NAND
2 X5R
0402-1
ROOM=NAND
2 X5R
0402-1
ROOM=NAND
2 X5R
0402-1
ROOM=NAND
17 8 90_PCIE_AP_TO_NAND_REFCLK_N 1
SM
PP PP1702
P2MM-NSM
ROOM=NAND

1 C1739 1 C1741 1 C1743 1 C1745 1 C1747

1.0UF 1.0UF 1.0UF 1.0UF 1.0UF
20% 20% 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X5R X5R X5R X5R X5R
0201-1 0201-1 0201-1 0201-1 0201-1
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

1
C1708 1
C1711 1
C1717 1
C1723 1
C1712
100PF
220PF 22PF 68PF 39PF 5%
5% 5% 5% 5% 16V
2 10V
C0G-CERM 2 16V
CERM 2 16V
NP0-C0G 2 16V
NP0-C0G 2 NP0-C0G
01005 01005 01005 01005 01005
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

Tens?o regulada PP0V9_NAND

da PMU LVDO10 1007mA MAX
1
C1704 1
C1702 1
C1705 1 C1722 1 C1727
15UF 15UF 15UF 15UF 15UF
20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
C 0402-1
ROOM=NAND
0402-1
ROOM=NAND
0402-1
ROOM=NAND
0402-1
ROOM=NAND
0402-1
ROOM=NAND #24543147:10uF for 32GB
#26326159:10uF for C1719 1230mA MAX (1us peak power) C
PP3V0_NAND
OMIT OMIT OMIT OMIT OMIT

1 C1737 1 C1738 1 C1740 1 C1742 1 C1744 1 C1746

1 C1748 1 C1713 1 C1716 1 C1719 1 C1721 1 C1733
15UF 15UF 15UF 10UF 15UF 15UF
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 20%
6.3V
20% 20% 20% 20% 20%
20% 20% 20% 20% 20% 20% 2 X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
X5R 2 6.3V
X5R
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 0402-1 0402-1 0402-1 0402-9 0402-1 0402-1
X5R X5R X5R X5R X5R X5R
0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

C1703 C1706 C1709 C1714 C1720 C1728

1 C1749 1 C1750 1 C1751 1 C1752 1 C1753 1 C1754
1 1 1 1 1 1 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF
220PF 22PF 100PF 220PF 100PF 68PF 20% 20% 20% 20% 20% 20%
5% 5% 5% 5% 5% 5% 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
2 10V
C0G-CERM 2 16V
CERM 2 16V 2 10V
C0G-CERM 2 16V 2 16V
NP0-C0G
X5R
0201-1
X5R
0201-1
X5R
0201-1
X5R
0201-1
X5R
0201-1
X5R
0201-1
01005 01005 NP0-C0G 01005 NP0-C0G 01005
01005 01005 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

PP1V8
1 C1715 1 C1718 1 C1731 1 C1732 1 C1734 1 C1735 1 C1736
220PF 22PF 68PF 39PF 100PF 220PF 100PF
5% 5% 5% 5% 5% 5% 5%
2 10V 2 16V 2 16V 2 16V 2 16V 10V 2 16V
1
C1724
0.01UF
C0G-CERM
01005
CERM
01005
NP0-C0G
01005
NP0-C0G
01005
NP0-C0G
01005
2 C0G-CERM
01005
NP0-C0G
01005
10% ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
6.3V
2 X5R NAND_VREF 0
0 0 0 0
4 5 7 4 6 3 5 3 7 2 1 9 3 7 5 B0 B1 F0 F1 5 A0 A1 D0 D1 G0 G1
01005
ROOM=NAND M J J K K C E A A F J J R R A O O O O R O O O O O O
1 DD2 1 EF D D D D D D D
_DHDD IODIODIODIODIODIOCCCCCCCCCCCC
C1725

LK 1
D VD VD VD VD VD VD

2
D

_C LK
1
D D R V V V V V V V
B D_VI_AVV V VD VD VD VD VD VD B

DD_C
0.01UF VI
A

AV D
I_PC PC
10%

I_ VD
2 6.3V
C

PCI_A
X5R
01005 P

PC
ROOM=NAND PP0V9_NAND PP1V8 PP3V0_NAND

A CPU envia um pulso

D2
U1701 G3
de Clock pra NAND AP_TO_NAND_SYS_CLK CLK_IN EXT_D0 PMU_TO_NAND_LOW_BATT_BOOT_L
THGBX6T1T82LFXF
20

EXT_D1 J3 AP_TO_NAND_FW_STRAP CPU inicia o firmware

A CPU envia o pulso de Clock requisitado H8 12

para ativa??o da comunica??i PCIE

90_PCIE_AP_TO_NAND_REFCLK_P PCIE_REFCLK_P VLGA H2 para comunica??o
H6 EXT_D2 NC
90_PCIE_AP_TO_NAND_REFCLK_N PCIE_REFCLK_M VER-1 E3
NAND solicita pulso de clock EXT_D3 NC
ROOM=NAND
para o barramento PCIE PCIE_NAND_BI_AP_CLKREQ_L G9 PCIE_CLKREQ* EXT_D4 E7
BOMOPTION=OMIT_TABLE NC
Refer?ncia de n?vel l?gico baixo EXT_D5 F6
PCIE_NAND_RESREF M6 PCI_RESREF NC
CRITICAL EXT_D6 C7 Malha de sincronismo entre entre
NC

{
1 90_PCIE_AP_TO_NAND_TXD_P M8 PCIE_RX0_P EXT_D7 B8 SYSTEM_ALIVE PROC., NAND, PMU e TIGRIS
R1704
3.01K 90_PCIE_AP_TO_NAND_TXD_N K8 PCIE_RX0_M
CPU reseta o barramento PCIE
PULL DOWN 1% EXT_NCE G1 PCIE_AP_TO_NAND_RESET_L 8 Comunica??o de dados entre
Elimina n?vel l?gico flutuante 1/32W N5
da malha de RESET do barramento MF Comunica??o PCIE entre NC PCIE_RX1_P F4 ROOM=NAND 0.00 R1702 a CPU e mem?ria NAND
PCIE da NAND 01005 CPU e NAND liberada N3 EXT_NRE SWD_AP_BI_NAND_SWDIO_R 1 2 SWD_AP_BI_NAND_SWDIO
13
2 ROOM=NAND NC PCIE_RX1_M 1/32W 0% 01005 MF
C5 ROOM=NAND 0.00 R1707 Malha de clock CPU para NAND
P8 EXT_NWE SWD_AP_NAND_SWCLK_R 1 2 SWD_AP_TO_MANY_SWCLK
13 36 53
90_PCIE_NAND_TO_AP_RXD_P PCIE_TX0_P 1/32W 0% 01005 MF e para o setor da Base Band
90_PCIE_NAND_TO_AP_RXD_N N7 PCIE_TX0_M EXT_RNB G5
NC
M2 PCIE_TX1_P EXT_CLE H4
NC NC
K2 PCIE_TX1_M
NC EXT_ALE D4

A CPU envia um pulso F8

de RESET pra NAND
7 AP_TO_NAND_RESET_L RESET*

A NC
D8 TRST*
SYNC_MASTER=Sync SYNC_DATE=06/06/2016
A
Auto calibra??o da NAND NAND_ZQ D6 ZQ PAGE TITLE

S SA SS SS SS SS SS SS SS SS SS SS SS SS SS
V V V V V V V V V V V V V V
NAND
1 R1701 DRAWING NUMBER SIZE

34.8 107 L3 L5 L7 P2 P4 P6 C0 C10E0

B2 B4 B6 EG Apple Inc.
051-00482 D
PULL DOWN 0.5%
1/32W O O O O REVISION
MF
01005
2 ROOM=NAND
17 NAND_AGND
R
8.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
17 OF 53
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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