Intel 8085 Reference Card Data Transfer Instruction Group Arithmetic & Logical Instruction Group Arith &

Arithmetic & Logical Instruction Group Arith & Logic Stack Branch
MOV A, A 7F MOV E, A 5F MVI A, b 3E ADD* A 87 INR‡ A 3C ORA* A B7 Rotate PUSH B C5 Jump
X1 1 VCC A, B 78 E, B 58 B, b 06 B 80 B 04 B B0 RLC† 07 D D5 JMP a C3
X2 HOLD C 81 C 0C C B1 RRC† 0F H E5 JNZ a C2
RESET OUT
Intel HLDA
A,
A,
C
D
79
7A
E,
E,
C
D
59
5A
C,
D,
b
b
0E
16 D 82 D 14 D B2 RAL† 17 PSW F5 JZ a CA
RAR† 1F JNC a D2
SOD 8085 CLK OUT A,
A,
E
H
7B
7C
E,
E,
E
H
5B
5C
E,
H,
b
b
1E
26
E
H
83
84
E
H
1C
24
E
H
B3
B4 [AHRL] [10]
POP B
D
C1
D1 JC a DA
SID Vcc: 5.0V±10% /RESET IN L 85 L 2C L B5 JPO a E2
A, L 7D E, L 5D L, b 2E Immediate H E1
TRAP VIH: 2.0→ READY A, M 7E E, M 5E M, b 36 M 86 M 34 M B6 PSW* F1 JPE a EA
ADI b C6 JP a F2
RST 7.5 Vcc+0.5V IO/M ACI b CE XTHL E3
MOV B, A 47 MOV H, A 67 XCHG EB ADC* A 8F DCR‡ A 3D CMP* A BF JM a FA
RST 6.5 VIL: -0.5V→0.8V S1 SUI b D6 SPHL F9
VOH: ≤ 0.45V B, B 40 H, B 60 LXI B, d 01 B 88 B 05 B B8 PCHL E9
RST 5.5 /RD SBI b DE
VOL: ≥ 2.4V B, C 41 H, C 61 D, d 11 C 89 C 0D C B9
ANI b E6
Branch [JNUI] [DD]
INTR /WR D 8A D 15 D BA Restart [JUI] [FD]
Icc: ≤ 200mA B, D 42 H, D 62 H, d 21 XRI b EE
/INTA ALE B, E 43 H, E 63 E 8B E 1D E BB RST 0 C7
tclk max: 2uS SP,d 31 ORI b F6
AD0 S0 B, H 44 H, H 64 H 8C H 25 H BC RST 1 CF Call
tclk min: 125- Load/Store CPI b FE CALL a CD
AD1 A15 B, L 45 H, L 65 L 8D L 2D L BD [LDHI b][28] RST 2 D7
320nS B, M 46 H, M 66 LDAX B 0A M 8E M 35 M BE RST 3 DF CNZ a C4
AD2 A14
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LDAX D 1A [LDSI b][38] CZ a CC

Icc and tclk vary RST 4 E7
AD3 A13 LHLD a 2A SUB* A 97 ANA* A A7 16 Bit CNC a D4
by version. MOV C, A 4F MOV L, A 6F Specials RST 5 EF
AD4 A12 C, B 48 L, B 68 LDA a 3A B 90 B A0 DAD† B 09 DAA* 27 RST 6 F7 CC a DC
AD5 A11 C, C 49 L, C 69 [LHLX] [ED] C 91 C A1 D 19 CMA 2F RST 7 FF CPO a E4
AD6 A10 C, D 4A L, D 6A D 92 D A2 H 29 STC† 37 [RST V] [CB] CPE a EC
STAX B 02
AD7 A9 C, E 4B L, E 6B STAX D 12 E 93 E A3 SP 39 CMC† 3F Restart Vector CP a F4
C, H 4C L, H 6C SHLD a 22 H 94 H A4 INX B 03 RST 0 0000H CM a FC
VSS A8 I/O & Control
C, L 4D L, L 6D STA a 32 L 95 L A5 D 13 RST 1 0008H
C, M 4E L, M 6E M 96 M A6 OUT b D3 Return
Register Organization [SHLX] [D9] H 23 RST 2 0010H
SP 33 IN b DB RST 3 0018H RET C9
A(8) F(8) PSW(16) B(8) C(8) B/C(16) MOV D, A 57 MOV M, A 77 arguments: SBB* A 9F XRA* A AF RST 4 0020H RNZ C0
DCX B 0B RIM 20
Flags D, B 50 M, B 70 b = byte data B 98 B A8 TRAP 0024H RZ C8
D(8) E(8) D/E(16) D 1B SIM 30
D, C 51 M, C 71 d = 16b data C 99 C A9 RST 5 0028H RNC D0
S Z [UI] AC - P [V] C H 2B
H(8) L(8) H/L(16) D, D 52 M, D 72 a = 16b address D 9A D AA Control RST 5.5 002CH RC D8
SP 3B
Aux Carry

Parity
Zero

Carry
Sign

D, E 53 M, E 73 flags: E 9B E AB DI F3 RST 6 0030H RPO E0

[UI]

Program Counte
ounter PC (16)
[V]

D, H 54 M, H 73 * = affects all H 9C H AC [DSUB] [08] EI FB RST 6.5 0034H RPE E8

Stack Pointer
ter SP (16) D, L 55 M, L 75 † = carry only L 9D L AD Arith & Logic NOP 00 RST 7 0038H RP F0
D, M 56 ‡ = all but M 9E M AE RM F8
continued --> HLT 76 RST 7.5 003CH
Note: [ ]=Undocumented/80C85B only carry

00 NOP 2C INR L ‡ 58 MOV E,B 83 ADD E * AF XRA A * DB IN b Instruction Timing (T States) Accumulator Operations
01 LXI B,d 2D DCR L ‡ 59 MOV E,C 84 ADD H * B0 ORA B * DC CC a Data Transfer CMP r 4 Control
02 STAX B 2E MVI L,b 5A MOV E,D 85 ADD L * B1 ORA C * DD [JNUI] Instruction Code Function
03 INX B 2F CMA 5B MOV E,E 86 ADD M * B2 ORA D * DE SBI b * MOV rd,rs 4 CMP M 7 DI 4
XRA A AF Clear A and Clear Carry
04 INR B ‡ 30 SIM 5C MOV E,H 87 ADD A * B3 ORA E * DF RST 3 MOV M,r 7 EI 4
05 DCR B ‡ 31 LXI SP,d 5D MOV E,L 88 ADC B * B4 ORA H * E0 RPO 16 bit CMA 2F Complement Accumulator
MOV r,M 7 NOP 4
06 MVI B,b 32 STA a 5E MOV E,M 89 ADC C * B5 ORA L * E1 POP H DAD x 10 ORA A B7 Clear Carry
XCHG 4 HLT 5
07 RLC † 33 INX SP 5F MOV E,A 8A ADC D * B6 ORA M * E2 JPO a INX x 6
08 [DSUB] * 34 INR M ‡ 60 MOV H,B 8B ADC E * B7 ORA A * E3 XTHL MVI r 7 CMC 3F Complement Carry
DCX x 6 Stack
09 DAD B † 35 DCR M ‡ 61 MOV H,C 8C ADC H * B8 CMP B * E4 CPO a MVI M 10 STC 37 Set Carry
0A LDAX B 36 MVI M,b 62 MOV H,D 8D ADC L * B9 CMP C * E5 PUSH H PUSH 12
LXI x 10 Rotate RLC 7 Rotate Left, MSB=CY
0B DCX B 37 STC † 63 MOV H,E 8E ADC M * BA CMP D * E6 ANI b POP 10
0C INR C ‡ 38 [LDSI] 64 MOV H,H 8F ADC A * BB CMP E * E7 RST 4 RLC 4
Load/Store RRC 0F Rotate Right, LSB=>CY
0D DCR C ‡ 39 DAD SP 65 MOV H,L 90 SUB B * BC CMP H * E8 RPE RRC 4 Branch
LDAX x 7 RAL 17 Rotate Ledt Thru Carry
0E MVI C,b 3A LDA a 66 MOV H,M 91 SUB C * BD CMP L * E9 PCHL RAL 4 RST x 12
0F RRC † 3B DCX SP 67 MOV H,A 92 SUB D * BE CMP M * EA JPE a LDA 13 RAR 1F Rotate Right Thru Carry
RAR 4 JMP 10
10 [AHRL] † 3C INR A ‡ 68 MOV L,B 93 SUB E * BF CMP A * EB XCHG STAX x 7
11 LXI D,d 3D DCR A ‡ 69 MOV L,C 94 SUB H * C0 RNZ EC CPE a Jx 7/10 After RIM:
SHLD 16 Immediate
12 STAX D 3E MVI A,b 6A MOV L,D 95 SUB L * C1 POP B ED [LHLX] CALL 18
6B MOV L,E 96 SUB M C2 JNZ a EE XRI b STA 13 ADI 7 SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5
13 INX D 3F CMC † * * Cx 9/18
14 INR D ‡ 40 MOV B,B 6C MOV L,H 97 SUB A * C3 JMP a EF RST 5 ACI 7
Arith & Logic RET 10 SID = Serial In Data
15 DCR D ‡ 41 MOV B,C 6D MOV L,L 98 SBB B * C4 CNZ a F0 RP SUI 7
16 MVI D,b 42 MOV B,D 6E MOV L,M 99 SBB C * C5 PUSH B F1 POP PSW * ADD r 4 Rx 6/12 Ix.5 = Interrupt Pending
SBI 7
17 RAL † 43 MOV B,E 6F MOV L,A 9A SBB D * C6 ADI b * F2 JP a ADD M 7 IE = Interrupt Enable Flag
18 [RDEL]CY,V 44 MOV B,H 70 MOV M,B 9B SBB E * C7 RST 0 F3 DI ANI 7 T-State Time
ADC r 4 Mx.5 = Interrupt Masks for external lines
19 DAD D † 45 MOV B,L 71 MOV M,C 9C SBB H * C8 RZ F4 CP a XRI 7 CPU f tCYC
72 MOV M,D 9D SBB L * C9 RET F5 PUSH PSW ADC M 7
1A LDAX D 46 MOV B,M ORI 7 8.0MHz 125nS
1B DCX D 47 MOV B,A 73 MOV M,E 9E SBB M * CA JZ a F6 ORI b * SUB r 4 Before SIM:
CPI 7 6.0 166.7
1C INR E ‡ 48 MOV C,B 74 MOV M,H 9F SBB A * CB [RSTV] F7 RST 6 SUB M 7 SOD SOE --- R7.5 MSE M7.5 M6.5 M5.5
1D DCR E ‡ 49 MOV C,C 75 MOV M,L A0 ANA B * CC CZ a F8 RM SBB r 4 Specials 5.0 200
1E MVI E,b 4A MOV C,D 76 HLT A1 ANA C * CD CALL a F9 SPHL SBB M 7 DAA 4 4.0 250 SOD = Serial Out Data
1F RAR † 4B MOV C,E 77 MOV M,A A2 ANA D * CE ACI b * FA JM a 3.58 279 SOE = Serial Out Enable (enable SOD output)
20 RIM 4C MOV C,H 78 MOV A,B A3 ANA E * CF RST 1 FB EI INR R 4 CMA 4
21 LXI H,d 4D MOV C,L 79 MOV A,C A4 ANA H * D0 RNC FC CM a INR M 10 STC 4 3.125 320 R7.5= Reset (clear) RST 7.5 Interrupt
22 SHLD a 4E MOV C,M 7A MOV A,D A5 ANA L * D1 POP D FD [JUI] DCR r 4 CMC 4 3.072 325.5 MSE = Mask Set Enable (1 to set new masks)
23 INX H 4F MOV C,A 7B MOV A,E A6 ANA M * D2 JNC a FE CPI b * 3.0 333.3 Mx.5= New RSTx.5 Mask Setting (1 to enable)
24 INR H ‡ 50 MOV D,B 7C MOV A,H A7 ANA A * D3 OUT b FF RST 7 DCR M 10
I/O 2.5 400
25 DCR H ‡ 51 MOV D,C 7D MOV A,L A8 XRA B * D4 CNC a b = byte data ANA r 4 Note: RST5.5, RST6.5, RST7.5 are masked by
52 MOV D,D 7E MOV A,M A9 XRA C * D5 PUSH D d = 16b data OUT 10 2.0 500
26 MVI H,b a = 16b address
ANA M 7 default. Masks must be cleared before use.
27 DAA * 53 MOV D,E 7F MOV A,A AA XRA D * D6 SUI b * IN 10 1.25 800
flags: XRA r 4
28 [LDHI] 54 MOV D,H 80 ADD B * AB XRA E * D7 RST 2 * = affects all RIM 4 1.2 833.3
29 DAD H † 55 MOV D,L 81 ADD C * AC XRA H * D8 RC † = carry only
XRA M 7
SIM 4 1.0 1000
2A LHLD a 56 MOV D,M 82 ADD D * AD XRA L * D9 [SHLX] ‡ = all but ORA r 4
2B DCX H 57 MOV D,A 83 ADD E * AE XRA M * DA JC a carry ORA M 7 0.75 1333 Visit http://saundby.com/ for more 8085 info.