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ARM Assembly Programming

Textbook ARM Assembly Language Programming & Architecture by Mazidi, et al.

1. ARM and Microcontrollers

2. ARM Architecture and Assembly Language Programming
3. Arithmetic and Logic Instructions and Programs
4. Branch, Call, and Looping in ARM
5. Signed Integer Numbers Arithmetic
6. ARM Memory Map, Memory Access, and Stack

ARM emulator – Coding Environment

EECE416 Microcontroller Fundamentals

i. Background:
• Specific microprocessor core for embedded-systems
and System-on-chip (SoC):

• ARM architecture:

• ARM processors are embedded in products:

• Goal of the class:

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ii. ARM Embedded Systems

RISC Design Philosophy
• ARM core uses RISC (Reduced Instruction Set Computer) architecture
• cf. CISC (Complex Instruction Set Architecture) of Intel X86
architecture
• RISC Aim:
• Delivering simple but powerful instructions  executes within a single
cycle at a high clock speed
• Reducing the complexity of instructions (performed by hardware) by
providing flexibility and intelligence in software  greater demand on
compiler.
• Cf. CISC – relies more on hardware for instruction functionality and
instructions are more complicated

ii. ARM Embedded Systems

Four (4) Major Design Rules of RISC Philosophy
1. Instructions
1. Reduced number of instruction classes.
2. Each instruction executes
3. Programmer or compiler synthesizes
4. Each instruction

2. Pipelines
1. Instruction processing is broken down into smaller units
2. executed in parallel by pipeline.
3. Registers
1. RISC machines have
2. Any register can contain
3. Acts as the fast
4. Load-Store Architecture – for memory access
1. RISC processor operates on data held in registers
2. Cf. CISC – relies more on hardware for instruction functionality and
instructions are more complicated

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iii. ARM Design Philosophy

Physical Features which have driven ARM processor design
Portable embedded Systems (Target)
1. Battery power:

2. High code density:

3. Ability to use slow

4. Reduce the area of the die

iv. Embedded System Hardware

1. Embedded Systems – controls
2. Four (4) main hardware components of microcontroller
1. The ARM Processor
2. Controllers
3. Peripherals
4. Bus

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iv. Embedded System Hardware - Packaging

v. Memory and trade-off

1. Hierarchy (of off-chip
memory)
1. Storage trade-offs
2. Cache:
3. Secondary storage:
2. Width
1. 8, 16, 32, or 64 bits
3. Types
1. ROM

2. Flash ROM –

3. DRAM –

4. SRAM –

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vi. Peripherals & Controllers

1. Peripherals
1. Outside world an embedded system interacts with

2. Input-output functions for the chip by connecting to other

devices or sensors that are off-chip

3. Range: From simple serial communication device to more

complex 802.11 wireless device

4. ARM peripherals are memory-mapped.

1. Programming interface is a set of memory-addressed registers.

ARM Processor Fundamentals

1. Overview of the
process core
2. Von Neumann (Cf.
Harvard) Architecture
3. Rn & Rm – Source Reg
4. Rd – Destination Reg
5. MAC (Multiply-
accumulate unit)
6. ALU (Arithmetic logic
unit)
7. Load-Store
Instruction: ALU
generates address (of
memory)
8. Rm can be pre-
processed by Barrel
Shifter

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Registers
1. R0 – R12: General purpose
registers hold either data or
address
2. R13: stack pointer (sp) and
stores the head of the stack
in the current processor mode
3. R14: link register (lr) and is
where the core puts the return
address whenever it calls a
subroutine
4. R15: program counter (pc) and
contains the address of the
next instruction to be fetched
by the processor
5. Cpsr: (current program status
register)

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Cpsr (Current Program Status Register)

1. ARM uses cpsr to monitor and control internal operations
2. 32-bit register
3. Basic layout of a generic program status register

4. M4-M0: Processor modes

1. Seven (7) processor modes including user (nonprivileged) mode – fast interrupt
request; abort; interrupt request; supervisor; system; undefined; user.

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ARM Core Family and Architecture

Revision Example Core ISA Enhancement

Implementation
ARMv4T ARM7DTMI, ARM9T Thumb
ARMv5TE ARM9E, ARM10E Extra instructions added
for changing state between
ARM and Thumb
ARMv5TEJ ARM7EJ, ARM926EJ Java Acceleration
ARMv6 ARM11 Unaligned and mixed endian
data handling; new
multimedia instructions 13

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Numbering System
Decimal numbers

Binary Numbers

32-bit binary
number

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Numbering System
N-bit computer
and accessible
memory

Conversion

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Numbering System

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Numbering System

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Numbering System

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Numbering System

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Numbering System

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Numbering System

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Numbering System

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Numbering System

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Character Representation

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