1

CONTENTS
1. Mission and Vision.
2. Guiding Principles and PEO’s.
3. Overview.
4. Faculties
5. Academic Programs
6. Grading Policy
7. Instructions for Lab Reports
8. Resources
9. Experiments with 8086 Microprocessor
10. Introduction to 8051 Microcontroller
11. Experiments with 8051 Microcontroller
12. FPGA based experiments
13. XA Zynq UltraScale+ MPSoC Data Sheet: Overview
14. Xilinx Artix Nexys4 DDR™ FPGA Board Reference
Manual
15. TM4C123G LaunchPad Evaluation Kit

2
National Institute of Technology Rourkela

Rourkela, Odisha, Indio 769008

First Published 2013,

Second Edition 2021,

Third Edition 2022,

Copyright ©2022, Embedded System & Real Time Lab, Dept., Of EE, Nit Rourkela

All Right Reserved.

3
4
 Guiding Principles
• Build an environment that is conductive to academic
pursuit, nurturing creative thoughts and inculcating a spirit
of inquiry.
• Promote free exchange of knowledge and experience with
others, while respecting each other’s right to intellectual
property.
• Ensure quality, speech, economy and transparency in all
spheres of our activities.
• Create a truly multicultural community and promote
cultural bonding and teamwork among all.
• Provide opportunity to every member of the lab for
achieving academic excellence, developing all round
personality and realizing his or her full potential.
• Adopt state of the art technology in all endeavors.

Program Educational Objectives (PEOs)

To prepare student to,

 Get employment in industry related to Embedded system
or allied domains.
 Able to carry out higher studies or research in Embedded
system or allied domain.
 Able to utilize the Embedded system knowledge in
establishing start-ups.

5
1. 6
2.

7
 Academic Programs

Following courses are conducted in ESRT Lab,

Subject {L-T-P / C}: EE6174: Real-Time Systems Laboratory{0-0-3 / 2}

Subject Nature: Practical
Coordinator: Prof. Supratim Gupta

Course Objectives:
To expose the students in order to

1. Learn to use modern circuit design tools, software, and equipment to develop digital circuit in
embedded systems
2. Learn coding in VHDL/Verilog, simulation and testing
3. Learn to design and implement embedded system with optimal computational complexity

Experiment Modules

Essential Reading:
1. Douglas L. Perry, VHDL: Programming by Example, Tata McGraw-Hill, 4th Ed., 2002 or latest Ed.
2. D. M. Harris & S. L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, 2007 or latest Ed.

Supplementary Reading:
1. Anonymous, Data Sheets of Various components by respective manufacturer, latest release
2. M. Morris Mano, Computer System Architecture, PHI, 3rd Ed., 2007 or latest Ed.

8
Course Outcomes:

CO1: Learn modern EDA Tools for Design and Simulation of Real-time Embedded
System
CO2: Learn VHDL/Verilog code for developing basic digital circuit components

CO3: Learn peripheral interfacing with FPGA/SoC based embedded system

CO4: Design, implement, and test the Digital Filters like FIR, IIR, and Adaptive Filters

CO5: Learn reporting the performance analysis of the embedded systems effectively

Program Outcomes:

PO1: An ability to independently carry out research /investigation and development work
to solve practical problems
PO2: An ability to write and present a substantial technical report/document

PO3: Students should be able to demonstrate a degree of mastery over the area as per
the specialization of the program. The mastery should be at a level higher than the
requirements in the appropriate bachelor program

PO4: Students will be able to independently carry out system design, testing, verification
and realization under real-time constraints in the field of communication systems,
signal and image processing, and embedded system.

PO5: Students will be competent to serve different industries and able to take up
challenging problems in the field of electronic systems and communication.

PO6: Students will be broadly educated and will have an understanding of the impact of
engineering on society and demonstrate awareness of contemporary issues. They
also understand and commit to professional ethics and responsibilities and norms
of engineering technology and practice.

Course Outcome and Program Objectives Mapping:

PO1 PO2 PO3 PO4 PO5 PO6
CO1: L L L H H L
CO2: L L M H H L
CO3: M L H H H L
CO4: H L H H H L
CO5: H H L L L H
Average 2 1 2 3 3 1
Value
Average M L M H H L
M=2; H=3; L=1

9
Following courses are conducted in ESRT Lab,(For UG)
Subject {L-T-P / C} : EE3704 : Embedded Systems Laboratory {0-0-2 / 1}
Subject Nature : Practical
Coordinator : Dr. Supratim Gupta
Course Objectives:
Prepare students ,
1. To understand extraction of information from datasheets
2. To develop circuits with processor in an Integrated Development Environment (IDE)
3. To able to design digital filters with software tool
4. To debug hardware and firmware of a digital filter in a simulator
5. To realize hardware and test digital filters with embedded system

Syllabus:

Module 1: Introduction / Practice Session

• Motivation of the work and design procedures and components to be used through the laboratory
sessions.
• Learning Proteus Environment for simulation of circuits with microcontroller
• Learning Filter Design & Analysis (FDA) toolbox of MATLAB
Module 2: ADC-0808 and DAC-0808 interfacing
• Input Sinusoidal Signal of variable amplitude & frequency
• Develop RTOS to measure the input & output (after DAC) amplitude & frequency
• Tabulate at least 20 reading and find the limitation of your system
Module 3: Design Low pass (LP) with FIR structure of 2nd order
• Cut-off frequencies for LP is last 4-digit of lowest Roll number of your group in Hz.
• Develop RTOS–with FIFO structure for signal access–to realize the filters in the circuit developed in
Task-1
• Consider integer, fixed point precision for computation
• Tabulate readings for each of the occasions and each type of filters to get frequency response and
compare it with
the frequency responses obtained in MATLAB FDA tool
• Measure latency of your system i.e. time delay between occurrence i/p to o/p
• Analyse and comment if the filter specification is met
Draw RTL schematic for this design.
Module 4: Design Low pass (LP) with IIR structure of order higher than 4
• Cut-off frequencies for LP is last 4-digit of lowest Roll number of your group in Hz
• Develop RTOS–with FIFO structure for signal access–to realize the filters in the circuit developed in
Task-1-2
• Consider integer, fixed point precision for computation
• Consider full order realization & cascaded 2nd order filters realization
• Tabulate readings for each of the occasions of filter precision and structure (full & cascaded) to get
frequency
response and compare it with the frequency responses obtained in MATLAB FDA tool
• Measure latency of your system i.e. time delay between occurrence i/p to o/p
• Analyse your system if the filter specification is met and is stable, what is the minimum precision
required, if the
stability depends on order
• Draw RTL schematic for this design.

10
 Module 5: Hardware realization
Hardware realization of either of the filters designed in Tasks 2-5 on system developed in Task 1 on bread
boards

Essential Reading:

1. Anonymous, DATA SHEETs of various ICs,, Software, Simulator etc.

Course Outcomes:

At the end of the course, students will be able to

CO1. Apply Filter Design Tool of MATLAB for designing FIR & IIR filters with given specification
CO2. Write compact Real-time Operating System (RTOS) for Digital Signal Processing (DSP) System
CO3. Simulate digital filters with signal interfaces with embedded processor 8051 in Proteus IDE
CO4. Determine performance of FIR & IIR digital filter with the simulator
CO5. Realize stable digital filter of 2nd & higher order FIR/IIR filter & signal interfaces on hardware

CO-PO&PSO mapping:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

CO1 3 0 0 0 3 0 0 2 2 0 0 0 3 1 1
CO2 2 0 0 0 3 0 0 2 2 1 0 0 3 1 1
CO3 3 3 3 0 3 0 0 2 2 0 0 0 3 1 1
CO4 3 3 3 3 3 0 0 2 2 1 0 0 3 1 1
CO5 3 3 3 0 3 0 0 2 3 1 1 0 3 1 1
CO 3 2 2 1 3 0 0 2 3 1 1 0 3 1 1

11
 Grading policy
Total grade consists of Mid- Semester grade (50%) and End-Semester grade (50%).

Grading for the course will be based primarily on the results of the laboratory projects and
the quality of the lab reports (20%). Lecture attendance with active participation will
account for 10% of the course grade, and the remaining 20% of the grade will be based
on the student’s viva voce performance.

Instructions for Lab Reports: -

1. Report must be well organized and concise.
2. Clearly state the objectives/purpose of design problem.
3. Emphasize the problem faced during implementation and methods used to
overcome them.
4. Present codes in understandable way with proper comments.
5. Figures and Table captions should include the figure number (e.g., Figure 1,
or Table 1.), a title, and enough of a description to understand the figure
without referring back to the text.
6. In case of graphs, label both the X and Y axis.
7. Captions usually go above tables and below figures.
8. Briefly summarize results.
9. Compare obtained results to those found in concepts and relate them to the literature.
10. References must be relevant and refer the article properly within the text
of formal report.

Structure of Report:

1) Cover Page should have

a. Name of the course with course code
b. Group number, name of the students in group with roll number
2) Table of contents
3) List of problems.
4) Structure of each experiment has to be as follows,
a. Title
b. Objective of project/design
c. Software used
d. Theory
e. Code with comments
f. Result (Comparison between obtained output and theoretical output)
g. Problem faced during experimental deign. (Optional)
h. Conclusion

12
 Template & Instruction For Each Design Problem: -

General Style

To make a report readable

1. Type using a 10-point standard font, such as Times New Roman.
2. Text should be ‘1.5’ spaced with 1-inch margin.
3. Number pages consecutively.
4. Start each new section on a new page with font size 10 and bold face.
5. Present your point in logical order.
Mistakes to avoid
1. Placing a heading of a section at the bottom of the page with the following
text on the next page.
2. Dividing a table or figure in two pages.

Structure of each design problem: -

1. Title
Top-middle of each experiment. Bold face with font size 14.
2. Objective/Aim of the experiment.
Define the objective of the experiment with maximum two or three lines concisely.
3. Software used
Mention the software packages used for your experiment in bullet or
numbering format.
4. Theory
The following approach can produce an effective theory section:
a. Your theory should be precise.
b. Description of working principle of each design with proper block diagram and
mathematical formula (if required).
c. State some of the applications of the design.
5. Code with comments
a. Code shouldn’t be plagiarized.
b. Comments at the beginning of code must contain the following points:
 In one or two line write the objective of the code.
 Authors (if working in group).
 Date of creation and current version.
c. Write comments either above or on the right hand side of the code.
6. Results
The objective of the result section is to illustrate and present the experimental
findings with a brief comparison between obtained and theoretical output.
7. Conclusion
It summarizes the study and presents the results in nutshell. It should be
concise; economy of words is again very important here. Make sure that all
the important findings or questions that follow from the ‘Objective/Aim of the
experiment’ are included. They can be given in bulleted form or in a
paragraph.

13
Resources
Xilinx Artix 7 Nexys 4 DDR Board
The Nexys4 DDR board is a complete, ready-to-use
digital circuit development platform based on the latest Artix-7™
Field Programmable Gate Array (FPGA) from Xilinx®. With its
large, high-capacity FPGA (Xilinx part number XC7A100T-
1CSG324C), generous external memories, and collection of
USB, Ethernet, and other ports, the Nexys4 DDR can host
designs ranging from introductory combinational circuits to
powerful embedded processors. Several built-in peripherals,
including an accelerometer, temperature sensor, MEMs digital
microphone, a speaker amplifier, and several I/O devices allow
the Nexys4 DDR to be used for a wide range of designs without
needing any other components.

MIMAS V2Spartan 6 FPGA Development Board

MIMAS V2 is a feature-packed yet low-

cost FPGA Development board featuring
Xilinx Spartan-6 FPGA. MIMAS V2 is
specially designed for experimenting and
learning system design with FPGAs. This
development board features SPARTAN
XC6SLX9 CSG324 FPGA with onboard
512Mb DDR SDRAM. The USB 2.0 interface
provides fast and easy configuration
download to the onboard SPI flash. No need
to buy an expensive programmer or special
downloader cable to download the bitstream
to the board.

14
TM4C123G LaunchPad Evaluation Kit

The universal VLSI trainer consists of

a Main board with many peripheral devices
like LED, parallel printer port, VGA port etc.
The main board has 4 Nos. of 48 pin Euro
connector for plugging in the Daughter
boards, which contains the FPGA or CPLD of
any manufacturer.

15
Xilinx Zynq UltraScale+ MPSoC ZCU104
Evaluation kit.

The XA Zynq® UltraScale+™ MPSoC family is

based on the Xilinx® UltraScale™ MPSoC
architecture. This family of products integrates a
feature-rich 64-bit quad-core Arm® Cortex™-
A53 and dual-core Arm Cortex-R5 based
processing system (PS) and Xilinx programmable
logic (PL) UltraScale architecture in a single
device. Also included are on-chip memory,
multiport external memory interfaces, and a rich set
of peripheral connectivity interfaces.

Mojo FPGA Development Board

Mojo is an FPGA board which lets you FPGA will start talking to the
get the pleasure of configuring the digital microcontroller; giving you access to the
circuits on Mojo v3 to your own serial port and the analog inputs.
specifications. What separates this FPGA
from the others is the ease of use. The
goal of Mojo v3 is to get you up and
running with FPGA as easily as
possible.The Mojo v3 FPGA Board uses
the Spartan 6 and a high performance
ATmega32U4 microcontroller. This board
has high processing power. The
ATmega32U4 microcontroller comes with
a USB (DFU) bootloader which allows
you to install new versions of the
firmware without the need for a
programmer. Once the board is powered
on, the ATmega32U4 configures the
FPGA from the flash memory. After the
FPGA is successfully configured, your

Universal Burner for Microcontroller

SuperPro 610P is a high performance and low cost
48 pin programmer with USB2. 0 interface which comes
with free software updates. Application and target
customers: Low to medium volume programming, electronic
repair, car repair shop, students .

16
 Arduino Mega

The Arduino Mega 2560 is a

microcontroller board based on the
ATmega2560. It has 54 digital
input/output pins (of which 15 can be
used as PWM outputs), 16 analog
inputs, 4 UARTs (hardware serial ports),
a 16 MHz crystal oscillator, a USB
connection, a power jack, an ICSP
header, and a reset button.

Components & Tools

Resistors Thermistors
Capacitors Diodes
Transistors 20 pin flat cable connectors
ADC/DAC Bread boards
Microcontrollers Signal Generators
Op-Amp’s DSOs
Rectifiers Power suppliesUSB cables
LEDs & Timers Voltage Regulators Stepper motors
Heat sinks Relay, Buzzers,
Crystal Oscillators,
Pushbuttons, LDR,
LCD’s

17
EXPERIMENT WITH MICROPROCESSOR
(8085)/MICROCONTROLLER (8051)

18
19
 National Institute of Technology, Rourkela
Department of Electrical Engineering,
B.Tech Programme
Embedded Systems Laboratory (EE 3704)

TASK 1:-

Introduction / Practice Session.

 Learn motivation of the work and design procedures and components to be used through the laboratory
sessions.
 Learn Proteus Environment for simulation of circuits with microcontroller.
 Learn Filter Design & Analysis (FDA) toolbox of MATLAB.
TASK 2 :-
ADC-0808 and DAC-0808 interfacing with 8051-µC/8085-µP

 Input Sinusoidal Signal of variable amplitude & frequency.

 Develop RTOS to measure the input & output (after DAC) amplitude & frequency.
 Tabulate at least 20 reading and find the limitation of your system.
TASK 3 :-
Design Low pass (LP) with FIR structure of 2nd order.

 Cutoff frequencies for LP is last 4-digit of lowest Roll number of your group in Hz..
 Develop RTOS–with FIFO structure for signal access–to realize the filters in the circuit developed in
Task-1.
 Consider integer, fixed point precision for computation.
 Tabulate readings for each of the occasions and each type of filters to get frequency response and
compare it with the frequency responses obtained in MATLAB FDA tool.
 Measure latency of your system i.e. time delay between occurrence i/p to o/p.
 Analyze and comment if the filter specification is met.
 Draw RTL schematic for this design.

TASK 4 :-
Design Low pass (LP) with IIR structure of order higher than 4

 Cutoff frequencies for LP is last 4-digit of lowest Roll number of your group in Hz.
 Develop RTOS–with FIFO structure for signal access–to realize the filters in the circuit developed in
Experiment-1-2.
 Consider integer, fixed point precision for computation.
 Consider full order realization & cascaded 2nd order filters
 realization
 Tabulate read.ings for each of the occasions of filter precision and structure (full & cascaded) to get
frequency response and compare it with the frequency responses obtained in MATLAB FDA tool
 Measure latency of your system i.e. time delay between occurrence i/p to o/p
 Analyze your system if the filter specification is met and is stable, what is the minimum precision
required, if the stability depends on order.
 Draw RTL schematic for this design.

TASK 5 :-
Hardware realization of either of the filters designed in Tasks 2-5 on system developed in Task 1.
20
TASK 1

21
 TASK - 1
Aim: Learn proteus environment for simulation of circuits with microcontroller and learn FDA
toolbox of matlab
Theory:
Proteus:

 Proteus is used to simulate design and drawing of electronic circuits, it was invented by lab
center electronics.
 By using Proteus we can prepare two-dimensional Circuit design as well.
 With the use of this emerging software, we can construct and simulate different electrical and
electronic circuits on our PC.
 There are numerous benefits to simulate circuits on proteus before making them practically.
 Designing of circuit on proteus take much less time.
 The electronic tool that are very expensive can easily get in proteus such as Oscilloscope.
 Using proteus we can find different parents of a circuit such as current and voltage value of any
component and resistance at any instant which is very difficult in a practical circuit.

Features of Proteus:

 There are two main parts of proteus first is used to design and draw different circuits and
second is for designing of PCB layout.
 The first is ‘ISIS’ that is used to design and simulate circuit and second is ‘ARES’ that is used for
designing of a printed circuit board.
 It also provides features related to the three-dimensional view of a design in PCB.
 It contains a panel to write source code if we are simulating microcontroller related tasks.
Proteus layout:

Proteus window has many sections some of them are as under:

1. Editing window
2. overview window
3. object selector
4. zoom option
5. tool option
6. Run buttons

22
Layouts of Proteus:

Fig.1 Schematic capture layout of Proteus

Fig.2 Source code layout of Proteus

23
 Fig.3 PCB layout in Proteus

FDA Tool:

 The filter design and analysis tool FDA tool is a powerful user interface for designing and
analysing filters quickly appropriate tools enable us to design digital FIR or IR filter by setting
required filter specifications by importing filters from matlab workspace or why adding moving or
deleting poles and zeros
 FDA tool also provide tools for analysing filters such as magnitude and phase response and
pole-zero plot
 When we type FD a tool or filter designer at the MATLAB Command Prompt the GUI displays
with a default filter

24
 Fig.4 GUI of FDA tool in MATLAB

The GUI has three main regions:

 The Current Filter Information region
 The Filter Display region and
 The Design panels
The upper half of the GUI displays information on filter specifications and responses for the
current filter. The current Filter Information region, in the upper left, displays filter properties,
namely the filter structure, order, number of sections used and whether the filter is stable or not.
It also provides access to the Filter manager forworking with multiple filters.
The Filter Display region, in the upper right, displays various filter responses, such as,
magnitude response, group delay and filter coefficients.
The lower half of the GUI is the interactive portion of FDATool. The Design Panel, in the lower
half is wherewe define our filter specifications. It controls what is displayed in the other two
upper regions. Other panels can be displayed in the lower half by using the sidebar buttons.

25
Fig.5 Filter Specifications window

Fig.6 Magnitude Response

Fig.7 Magnitude (in dB) Response

26
Fig.8 Phase Response

Fig.9 Filter information

27
TASK 2

28
 TASK-2
AIM:
To develop an Embedded system in Proteus interfacing ADC-0808 and DAC-0808 with
8051-MC. Structured RTOS code is developed to measure the input & output (after DAC).

Components used: -
1. 8051 microcontrollers (AT89C52)
2. Crystal oscillator (11.059 MHz)
3. DAC (DAC0808)
4. ADC (ADC0808)
5. Op-Amp (LF347)
6. Sine wave generator
7. Not gate
8. Digital oscilloscope
9. Resistors
10. capacitors
11. Resistors packs
12. DC source
Description of lables used in circuit diagram:
1. ADCO - ADC outputs
2. DACI - DAC inputs
Circuit Diagram:

Fig.1 Circuit Diagram in Proteus

29
 Assembly Code:
;====================================================================
; Main.asm file generated by New Project wizard
; Created: Mon Jan 24 2022
; Processor: AT89C52
; Compiler: ASEM-51 (Proteus)
;====================================================================

$NOMOD51
$INCLUDE (80C52.MCU)

;====================================================================
; DEFINITIONS
;====================================================================
ADop equ P0 ;Port 0 as ADC output
ALE equ P1.2 ; Port 1.2 as ALE for ADC
SOC equ P1.3 ; Port 1.3 as Start conversion (SC) for ADC
EOC equ P3.3 ; external interrupt 0
DAip equ P2 ; Port 2 as DAC input
Exedge equ TCON.2 ; setting external interrupt 1 as edge
trigger OE equ P3.0
;====================================================================
; VARIABLES
;====================================================================
IEvalue equ 84h ;Enabling interrupts globally and external interrupt 1
T2modval equ 02h ;to set as up programmable clock output and T2OE enable
RCAP_L equ 0FCh ;lower byte of count value for 640kHz clock out at T2 pin with 11.059MHz clock
RCAP_H equ 0FFh ;higher byte of count value
;====================================================================
; RESET and INTERRUPT VECTORS
;====================================================================

; Reset Vector
org 0000h
jmp Start

org 0013h ; For external interrupt

1 sjmp READ_ADC_ISR

;====================================================================
; CODE SEGMENT
;====================================================================
Start:

mov RCAP2H, #RCAP_H ;higher byte of count value for 640kHz clock out at T2 pin with 11.059MHz
clock
mov RCAP2L, #RCAP_L ;lower byte of count value
mov T2MOD , #T2modval ;to set as up programmable clock output and T2OE
enable
clr T2CON.0 ;setting timer 2 in 16bit Autoreload mode
clr T2CON.1 ;In timer mode
setb TR2 ;Start the timer

mov IE, #IEvalue ;to enable external interrupt 1

mov ADop , #0FFh ;Configure P0 as an input port for recieving data of ADC
mov DAip , #00h ;Configure P2 as an output port for sending data to DAC
setb Exedge ;setting external interrupt 1 as edge trigger

30
 mov R1, #0FFh ;Initialise R1 to compare and check the maximum value
mov R0 , #00h ;Initialise R0 to store maximum value

Start ADC conversion for 1st sample

setb ALE ;Set ALE to start conversion and selecting channel 1 input
setb SOC ;Set SC to start the conversion of ADC
clr ALE
clr SOC

Loop:
jmp Loop

READ_ADC ISR:

Push ACC ;set Output Enable to take the data

push PSW
setb OE
mov B , ADop ;Store data in B register to check whether the coming data is
mov A , R1
maximum value or not

cjne A, B, Back
mov R0,B
mov DAip ,B ;Send data to DAC
Back:

; Start ADC conversion for next sample

setb ALE
setb SOC
clr ALE
clr SOC
pop PSW
pop ACC
reti
;===========================================================
========= END

31
Readings:

S.No. ADC INPUT DAC OUTPUT

Amplitude Frequnecy Amplitude Frequnecy
1. 1V 20Hz 5V 20Hz

2. 1V 30Hz 5V 30Hz

3. 1V 50Hz 4.99V 50Hz

4. 1V 75Hz 4.99V 75Hz

5. 1V 100Hz 4.99V 100Hz

6. 1V 150Hz 4.98V 150Hz

7. 1V 200Hz 4.98V 200Hz

8. 1V 250Hz 4.98V 250Hz

9. 1V 300Hz 4.98V 300Hz

10. 1V 400Hz 4.98V 400Hz

11. 0.5V 20Hz 2.5V 20Hz

12. 0.5V 30Hz 2.5V 30Hz

13. 0.5V 50Hz 2.49V 50Hz

14. 0.5V 75Hz 2.49V 75Hz

15. 0.5V 100Hz 2.49V 100Hz

16. 0.5V 150Hz 2.49V 150Hz

17. 0.5V 200Hz 2.48V 200Hz

18. 0.5V 250Hz 2.48V 250Hz

19. 0.5V 300Hz 2.48V 300Hz

20. 0.5V 400Hz 2.48V 400Hz

32
 Waveforms:

Input Amplitude =
1V Offset = 1V

1. At 50Hz

Fig.1
At 100 Hz

Fig.3

33
2. At 200Hz

Fig.4

3. At 400 Hz

Fig.5

34
Input Amplitude = 0.5V
Offset = 0.5V

4. At 50Hz

Fig.6

5. At 100 Hz

35
6. At 200Hz

Fig.8

7. At 400 Hz

Fig.9

Limitations of the System:

1. The amplitude of input sinusoid must be less than or equal to 1V.

2. Frequencies above and around 400 Hz, significant distortions are observed in the recovered
sinusoid so frequency of the input sinusoid must be kept below 400Hz.
3. The Frequency of clock input to ADC must be kept greater than or equal to 640kHz.

36
TASK -3

37
 TASK -3
AIM: To Design Low pass (LP) with FIR structure of 2nd order for a given Cut-off frequency.
RTOS Structured code is developed with FIFO structure for signal access–to realize the filters
in the circuit developed in Task-1. Latency of designed system is determined.

Components used: -
1. 8051 microcontrollers (AT89C52)
2. Crystal oscillator (11.059 MHz)
3. DAC (DAC0808)
4. ADC (ADC0808)
5. Op-Amp (LF347)
6. Sine wave generator
7. Not gate
8. Digital oscilloscope
9. Resistors
10. capacitors
11. Resistors packs
12. DC source
Description of lables used in circuit diagram:

1. ADCO - ADC outputs

2. DACI - DAC inputs

Circuit Diagram:
38
Circuit Diagram in Proteus

39
Cut off frequency = 638 Hz
Sampling frequency = 4000 Hz

Filter specifications:

Filter Coefficients:

40
Assembly Code:
;====================================================================

$NOMOD51
$INCLUDE (80C52.MCU)

;====================================================================
; DEFINITIONS
;====================================================================
ADOP EQU P0 ;port 0 as adc output
ALE EQU P1.2 ;port 1.2 as ale for adc
SOC EQU P1.3 ;port 1.3 as start conversion (sc) for ADC
EOC EQU P3.3 ; external interrupt 0
DAIP EQU P2 ;port 2 as dac input
EXEDGE EQU TCON.2 ; setting external interrupt 1 as edge trigger
OE EQU p3.0
;====================================================================
; VARIABLES
;====================================================================
IEVALUE equ 84h
T2MODVAl equ 02h ;to set as up programmable clock output and T2OE enable
RCAP_L equ 0FCh ;lower byte of count value for 640kHz clock out at T2 pin with 11.059MHz clock
RCAP_H equ 0FFh ;higher byte of count value
;====================================================================
; FILTER COEFFICIENTS
;=====================================================
=====An equ 4Eh ; 0.30629553*2^(8)
An_1 equ 63h ; 0.38740894*2^(8)
An_2 equ 4Eh ; 0.30629553*2^(8)
;====================================================================
; RESET and INTERRUPT VECTORS
;====================================================================

; Reset Vector
ORG 0000h
JMP Start

ORG 0013h ;For external interrupt 1

SJMP READ_ADC_ISR

;====================================================================
; CODE SEGMENT
;====================================================================

Start:
MOV RCAP2H, #RCAP_H ; higher byte of count value for 640kHz clock out at T2 pin with 11.059MHz clock
MOV RCAP2L, #RCAP_L ; lower byte of count value
MOV T2MOD , #T2modval ;to set as up programmable clock output and T2OE enable
CLR T2CON.0 ;16bit Autoreload
CLR T2CON.1 ;In timer mode
SETB TR2 ;Start the timer

MOV IE, #IEvalue ;to enable external interrupt 1

MOV ADop , #0FFh ;Configure P0 as an input port for recieving data of ADC
MOV DAip , #00h ;Configure P2 as an output port for sending data to DAC

41
 MOV R0 ,#00H ;
MOV R1 , #00H
MOV R2 , #00H
MOV R3 , #00H
MOVR5, #00H
SETB EXEDGE ; setting external interrupt 1 as edge trigger

; Start ADC conversion for 1st sample

SETB ALE ; Set ALE to start conversion and selecting channel 1 input.
SETB SOC ; Set SC to start the conversion of ADC.
CLR ALE
CLR SOC
Loop:
JMP Loop

READ_ADC_ISR:
PUSH ACC
PUSH PSW
SETB OE ;set Output Enable to take the data
MOV A , ADOP ;Store data in B register to check whether the coming data is maximum value or
not
MOV R3,A ;storing current sample in R3
MOV A,R1 ;storing the previous x[n-1] In A
MOV R0,A ;shifting the previous x[n-1] in R0
MOV A,R2 ;Store the previous x[n] in A
MOV R1,A ;Store it in R1
MOV A,R3;Store current sample value in A
MOV R2,A ;Store current sample in R2
MOVA,R0
MOVB,#n
MUL AB ;performing An*x[n]
MOV R5,B ;Storing in R5
MOV A,R1
MOV B,#An_1
MUL A_B ;performing An_1*x[n-1]
MOV A,B
ADD A,R5 ;Adding and storing in R5
MOV R5,A
MOV A,R2
MOVB,#A2
MUL AB ;performing An_2*x[n-2]
MOV A,B
ADD A,R5
MOV R5,A ;storing An*x[n] + An_1*x[n-1] + An_2*x[n-2] in R5
MOV DAip,R5 ;To send the contents to DAC
Start ADC conversion for next sample
SETB ALE
SETB SOC
CLR ALE
CLR SOC
POP PSW
POP ACC
RETI
END

42
Readings:

Input Output Latency Gain in

Gai
Frequency Amplitude (V) Amplitude (V) (ms) dB
n
(Hz)
50 1 4.75 4.75 10.00 13.533
100 1 4.70 4.70 5.00 13.442

150 1 4.68 4.68 3.33 13.405

200 1 4.60 4.60 2.50 13.255

250 1 4.52 4.52 2.00 13.103

300 1 4.50 4.50 1.67 13.064

350 1 4.45 4.45 1.43 12.967

400 1 4.42 4.42 1.25 12.908

450 1 4.30 4.30 1.11 12.669

500 1 4.22 4.22 1.00 12.506

550 1 3.90 3.90 0.91 11.821

600 1 3.88 3.88 0.83 11.777

650 1 2.61 2.6 0.77 8.333

1
700 1 2.30 2.30 0.71 7.235

800 1 1.63 1.6 0.63 4.244

3
1000 1 0.45 0.45 0.50 -6.936

1500 1 0.42 0.42 0.33 -7.535

2000 1 0.40 0.40 0.25 -7.959

43
Frequency response using above table:

Fig.2

Frequency response using FDA tool:

Fig.3

44
Waveforms:

Input Amplitude = 1V
Offset = 1V

1. At 50Hz

Fig.4

At 100 Hz

Fig.5

45
2. At 200Hz

Fig.6

3. At 400 Hz

Fig.7

46
4. At 600 Hz

Fig.8

5. At 1000Hz

Fig.9

Conclusion:

From the above waveforms, it is clear that with the increase in frequency of input sinusoid,
there is decrease in amplitude of output waveforms is significant above cutoff frequency. As it
is a low pass FIR filter, decrease in the amplitude is justified and the frequency response of
output is also similar to that of response obtained in FDA tool. The output waveforms become
more distorted as we increase the frequency closer to 2000Hz.

47
TASK 4-5

48
 TASK - (4-5)
AIM:
To Design Low pass (LP) with IIR structure of order 5 for a given Cut-off frequency. RTOS
Structured code is developed with FIFO structure for signal access–to realize the filters in the
circuit developed in Task-1-2. Latency of designed system is determined.

Components used: -

1. 8051 microcontrollers (AT89C52)

2. Crystal oscillator (11.059 MHz)
3. DAC (DAC0808)
4. ADC (ADC0808)
5. Op-Amp (LF347)
6. Sine wave generator
7. Not gate
8. Digital oscilloscope
9. Resistors
10. capacitors
11. Resistors packs
12. DC source

Description of lables used in circuit diagram:

1. ADCO - ADC outputs

2. DACI - DAC inputs

49
Circuit Diagram:
Fig.1 Circuit Diagram in Proteus

RP1
RESPACK-8

2
3
4
5
6
7
8
9
Vcc

ADCO0
ADCO1
ADCO2
ADCO3
ADCO4
ADCO5
ADCO6
ADCO7
ADCIP
GND Vcc U2
10 26 ADCIP
C3 CLOCK IN0
6 27
START IN1
28
IN2
7 1
EOC IN3
33uF 2
U1 IN4
ADCO7 21 3
1

OUT1 IN5
19 39 ADCO0 ADCO6 20 4
XTAL1 P0.0/AD0 OUT2 IN6
X1 38 ADCO1 ADCO5 19 5
P0.1/AD1 OUT3 IN7
37 ADCO2 ADCO4 18
CRYSTAL P0.2/AD2 OUT4
18 36 ADCO3 ADCO3 8 25
XTAL2 P0.3/AD3 OUT5 ADD A
2

35 ADCO4 ADCO2 15 24 GND

C4 P0.4/AD4 OUT6 ADD B
34 ADCO5 ADCO1 14 23
C1 P0.5/AD5 OUT7 ADD C
33 ADCO6 ADCO0 17 22
P0.6/AD6 OUT8 ALE
Vcc 9 32 ADCO7
RST P0.7/AD7
33uF 12 Vcc
VREF(+)
1nF 21 DAI0 9 16 GND
P2.0/A8 OE VREF(-)
22 DAI1
P2.1/A9
23 DAI2 ADC0808
P2.2/A10
29 24 DAI3
PSEN P2.3/A11
30 25 DAI4
ALE P2.4/A12
31 26 DAI5
EA P2.5/A13
27 DAI6
P2.6/A14 U3
28 DAI7 R1(2)
P2.7/A15
DAI7 5 14
R1
A1 VREF+
1 10 DAI6 6
P1.0/T2 P3.0/RXD A2 5k R2
2 11 U4 DAI5 7 15 GND
P1.1/T2EX P3.1/TXD A3 VREF-
3 12 DAI4 8
P1.2 P3.2/INT0 A4 5k
4 13 DAI3 9 4
P1.3 P3.3/INT1 A5 IOUT
5 14 DAI2 10
P1.4 P3.4/T0 A6
6 15 DAI1 11 16 C2(2)
P1.5 P3.5/T1 NOT A7 COMP
7 16 DAI0 12 3
P1.6 P3.6/WR A8 VEE
8 17 0.1uF
P1.7 P3.7/RD
DAC0808
AT89C52 C2
U5:A(V+)

U5:A
4 A
GND 3
1
B
2
C
11

R3 LF347 +88.8 D
AC Volts
5k
U5:A(V-)

Last four digit of roll no. = 0638

Cut off frequency = 638 Hz
Sampling frequency = 2000 Hz

Filter specifications:

50
Filter Coefficients (Full order realization):

Filter Coefficients (Cascaded 2nd order realization):

51
Assembly Code:
;====================================================================

$NOMOD51
$INCLUDE (80C52.MCU)

;====================================================================
; DEFINITIONS
;====================================================================
ADOP equ P0 ;Port 0 as ADC output
ALE equ P1.2 ;Port 1.2 as ALE for ADC
SOC equ P1.3 ;Port 1.3 as Start conversion (SC) for ADC

EOC equ P3.3 ; external interrupt 0

DAIP equ P2 ;Port 2 as DAC input
EXEDGE equ TCON.2 ; setting external interrupt 1 as edge trigger
OE equ P3.0
;====================================================================
; VARIABLES
;====================================================================
IEVALUE equ 84h ;
T2MODVAL equ 02h ; to set as up programmable clock output and T2OE enable
RCAP_L equ 0FCh ; lower byte of count value for 640kHz clock out at T2 pin with
11.059MHz CLOCK
RCAP_H equ 0FFh ; higher byte of count value
;====================================================================
; RESET and INTERRUPT VECTORS
;====================================================================
; Reset Vector
ORG 0000h
JMP Start

ORG 0013h ; For external interrupt 1

SJMP READ_ADC_ISR

;====================================================================
; CODE SEGMENT
;====================================================================

Start:

MOV RCAP2H, #RCAP_H ;higher byte of count value for 640kHz clock out at T2 pin with
11.059MHz clock
MOV RCAP2L, #RCAP_L ;lower byte of count value
MOV T2MOD , #T2modval ;to set as up programmable clock output and T2OE enable
CLR T2CON.0 ;16bit Autoreload
CLR T2CON.1 ;In timer mode
SETB TR2 ;Start the timer

MOV IE, #IEvalue ;to enable external interrupt 1

MOV ADop , #0FFh ;Configure P0 as an input port for recieving data of ADC
MOV DAip , #00h ;Configure P2 as an output port for sending data to DAC
MOV R0 , #00h ;
MOV R1 , #00h
mOV R2 , #00h
MOV R3 , #00h
MOV R5, #00h
MOV R6, #00h
SETB EXEDGE ;setting external interrupt 1 as edge trigger

; Start ADC conversion for 1st sample

SETB ALE ;Set ALE to start conversion and selecting channel 1 input
SETB SOC ;Set SC to start the conversion of ADC
CLR ALE
CLR SOC

52
Loop:

JMP LOOP

READ_ADC_ISR: PUSH ACC

PUSH PSW
SETB OE ;set Output Enable to take the data
;Section 1:
mov A,ADop ; Taking data from ADC after conversion
MOV R0,A ; Storing the sample x[n] in R0
MOV B,#80H ;Storing Ao in B (1 * 128 = 80H)
MUL AB ;Performing Ao*x[n]
MOV R5,B ;Storing result in R5

MOV A,R1 ;shifting x[n-1] Storinin R1 to A

MOV B,#0FFH ;Storing A1 in B ( 2*128 = FFh)
MUL AB ;performing A1*x[n-1]
MOV R6,B ;Storing result n R6
MOV A,R6 ;Storing from R6 to A
ADD A,R5 ;performing Ao*x[n]+A1*x[n-1]
MOV R5,A ;Storing it in R5
MOV A,R2 ;moving x[n-2] in A
MOV B,#80H ;storing A2 in B (1 * 128 = 80H)
MUL AB ;Performing A2*x[n-2]
MOV R6,B
MOV A,R6
ADD A,R5
MOV R5,A ; performing Ao*x[n]+A1*x[n-1]+A2*x[n-2]
MOV A,R3
MOV B,#53H ;Storing b1 in B (0.65616448*128) = 53H
MUL AB ;Performing b1*y[n-1]
MOV R6,B ;
MOV A,R5 ;moving it to A
SUBB A,R6 ;performing Ao*x[n]+A1*x[n-1]+A2*x[n-2]-b1*y[n-1]
MOV R5,A ;Storing it in R5
MOV A,R4 ;
MOV B,#47H ;Storing b2 in B (0.56197758*128) = 47H
MUL AB ;Performing b2*y[n-2]
MOV R6,B ;
MOV A,R5
SUBB A,R6 ;performing Ao*x[n]+A1*x[n-1]+A2*x[n-2]-b1*y[n-1]-b2*y[n-2]
RLC A
MOV R5,A ;Storing it in R5
MOV A,R3
MOV R4,A ;Storing y[n-1] in R4
MOV A,R2
MOV R3,A ;Storing y[n] in R3
MOV A,R1
MOV R2,A ; ;
mov A,R0
MOV R1,A ; Storing x[n] in R1

Section 2:-
MOV A,R0 ;taking x[n] in A from R0
MOV B,#80H ;storing Ao in B (1 * 128 = 80H)
MUL AB ;performing Ao*x[n]
MOV R5,B ;Storing Ao*x[n] in R5
MOV A,R1 ;Taking x[n-1] in A
MOV B,#0FFH ;Storing A1 ( 2*128 = 0FFh)
MUL AB ;Performing A1*x[n-1]
MOV R6,B ;Storing it in R6
MOV A,R6 ;move from R6 to A
ADD A,R5 ; Ao*x[n]+A1*x[n-1]
MOV R5,A ;Storing it in R5
MOV A,R2 ;R2 has x[n-2]
MOV B,#80H ;taking A2 in B (1 * 128 = 80H)

53
 MUL AB ;Performing A2*x[n-2]
MOV R6,B

MOV A,R6
ADD A,R5
MOV R5,A ; performing Ao*x[n]+A1*x[n-1]+A2*x[n-2]
MOV A,R3 ; Taking y[n-1] in A
MOV B,#3EH ;Storing b1(0.48448035 * 128 = 3EH)
MUL AB ;performing b1*y[n-1]
MOV R6,B
MOV A,R5 ;moving it to A
SUBB A,R6 ;Performing Ao*x[n]+A1*x[n-1]+A2*x[n-2]-b1*y[n-1]
MOV R5,A ;Storing it in R5
MOV A,R4
MOV B,#13H ;Storing b2 in B (0.15328925*128 = 13H)
MUL AB ;performing b2*y[n-2]
MOV R6,B ;
MOV A,R5

SUBB A,R6 ;performing Ao*x[n]+A1*x[n-1]+A2*x[n-2]-b1*y[n-1]-b2*y[n-2]

RLC A
MOV R5,A ;Storing it in R5
MOV A,R3
MOV R4,A ;Storing y[n-1] sample to R4
MOV A,R2
MOV R3,A ; Storing y[n] sample to R3
MOV A,R1
MOV R2,A ;
MOV A,R0
MOV R1,A ;Storing x[n] sample to R1

Section 3:-

MOV A,R0 ;Taking x[n] in A from R0

MOV B,#80H ;Taking Ao in B( 1*128 = 80h)
MUL AB ;performing Ao*x[n]
MOV R5,B ;storing result in R5
MOV A,R1 ;Taking x[n-1]
MOV B,#80H ;Storing A1 ( 1*128 = 80h)
MUL AB ;Performing of A1*x[n-1]
MOV R6,B ;Storing it in R6
MOV A,R6 ;
ADD A,R5 ;performing Ao*x[n]+A1*x[n-1]
MOV R5,A ;STORING IT IN R5
MOV A,R3 ; taking y[n-1] from R3 in A
MOV B,#1CH ;Storing b1 ( 0.22023022*128 = 1CH)
MUL AB ;performing b1*y[n-1]
MOV R6,B ;
MOV A,R5 ;moving it to A
SUBB A,R6 ;performing Ao*x[n]+A1*x[n-1]+A2*x[n-2]-b1*y[n-1]
RLC A
MOV R5,A ;Storing it in R5
MOV A,R3 ;taking y[n-1] in A
MOV R4,A ;Storing y[n-1] in R4
MOV A,R2 ; taking y[n] in A
MOV R3,A ;Storing y[n] sample to R3
MOV A,R1
MOV R2,A ;
MOV A,R1
MOV R1,A ; Storing x[n] sample in R1
MOV DAIP,A ; Sending output to y[n] of 5th order filter to DAC

54
 ; Start ADC conversion for next sample

SETB ALE
SETB SOC
CLR ALE
CLR SOC
POP PSW
POP ACC
RETI

;====================================================================
END

Readings:

55
Frequency response using above table:

Fig.2

Frequency response using FDA tool:

Fig.3

56
 Waveforms:

Input Amplitude = 1V
Offset = 1V

1. At 50 Hz

Fig.4

2.At 200 Hz

Fig.5

57
 3.At 400Hz

Fig.6

2. At 600Hz

Fig.7

58
 3.At 800Hz

Fig.8

Conclusion:
All the Coefficients of the IIR filter were obtained from FDA tool of MATLAB for Cascade and
2nd order section realisation. By using the value of samples and coefficients the output was calculated
and send to DAC .With increase in frequency, it was observed that the amplitude of the output
decreased and distortion increased with increasing input frequency beyond cut-off frequency (638
Hz). Since it is a LPF the decrement in output amplitude is justified and the output frequency
response is also quite similar to that of response obtained in FDA tool of MATLAB. From graphs we
observed that as the frequency reached half of the sampling frequency (1.0KHz), the distortion
increased very rapidly by satisfying Nyquist theorem (f s >2fm).

59
TASK 6

60
 Interfacing 8051 with ADC and DAC
Learning outcome
 Learn to implement regulated power supply and square wave generator
using 555 timer
 Understand specifications of ADC and DAC
 Learn to write code for interfacing 8051 with ADC and DAC
 Learn how to implement the interfacing circuit

Aim

To interface ADC0808 and DAC0808 with AT89C51 Microcontroller

Equipment’s and components required

AT89C51 Microcontroller, Crystal Oscillator(11.059 Mhz),

Universal Programmer, Square Wave Generator(600 Khz),
ADC0808, DAC0808, 5V Regulated Resistors,
Power Supply, Capacitors

Theory

In most of the digital system micro controller needs to take input from analog sensor or
transducer. Analog signal are most common input signal for embedded system. Hence before
feeding to microcontroller the analog input has to be converted to digital data by using an Analog to
Digital Converter(ADC).The digital data is converted back to analog using a digital to analog
converter.

5V Regulated Power Supply

Fig.1.– Circuit for 5V regulated power supply

61
Square wave generation using 555 timer.

(Fig-Circuit for square wave generation using 555 timer)

ADC0808 :-

ADC 0808 is an 8-bit analog to digital converter which is of successive approximation type. Its
important specifications are:
 Resolution is 8-bit
 Conversion time is 100 us
 Clock frequency range is 10 kHz to 1 MHz

It has 8 analog data channels, which are selected using A, B and C. The control signals are:
 ALE (Address Latch Enable) – with a high pulse it selects the corresponding data channel
according to the address in A,B and C
 START – a high pulse starts the conversion
 EOC (End of Conversion) - There is a low to high transition when the conversion is done
 OE (Output Enable) – Setting it latches the output to its output channel

62
 Fig. – Timing diagram for ADC0808
Minimum start pulse width = 100 ns
Minimum ALE pulse width = 100ns
Minimum address set up time = 50 ns
Minimum address hold time = 50 ns
DAC0808 :-

DAC 0808 is an 8-bit digital to analog converter. The analog output is sinking current.
Important specifications are
 Resolution – 8-bit
 Slew rate – 8mA/us

63
Procedure :-

1. Design, simulate and implement 5V regulated power supply with 1% ripple.

2. Design, simulate and implement square wave generator using 555 timer (600kHz).
3. Write assembly code to interface ADC0808 with 8051 so as to detect a sinusoidal input. Verify
it using 8051 simulator software. Compile the code into machine language.
4. Burn the code into the 8051 chip.
5. Implement the circuit of interfacing 8051, ADC0808 and DAC0808.
6. Display the original sine input and output of DAC in a DSO.

64
Hardware Implementation:-

65
FPGA BASED EXPERIMENTS

66
National Institute of Technology, Rourkela
Department of Electrical Engineering,
M. Tech Programme
Real-Time Systems Laboratory (EE 6174)

MODULE 1 (TASK 1)
Introduction / Practice Session

 Realize the AND, OR & NOT gate by using dataflow and behavioural modelling with VHDL and
Verilog HDL.

MODULE 2 (TASK 2-4)

Realization of Digital circuits using VHDL/Verilog HDL (structural modelling).

 4:1 MUX by using 2:1 MUX and JK Flip-flop in structural modelling

 8-bit fixed point Multiplier
 8-bit fixed point Adder

MODULE 3 (TASK 5-7)

Realization of Counter and FIFO as IP core using VHDL /Verilog HDL

 Counter with auto-reset signal

 Asynchronous FIFO
 Convert the FIFO designed into IP core and compare it with inbuilt FIFO IP

MODULE 4 (TASK 8)
Finite State Machine for Sequence Detection

 Finite state machine for detecting sequence of 11010.

MODULE 5 (TASK 9)
ADC-DAC Interface with FPGA/SoC

 Realize ADC-DAC interface with FPGA.

MODULE 6 (TASK 10-11)

Digital Filter Structure Realization with FPGA/SoC

 Realize a 2nd order moving average filter using structural modelling.

 Realize 2nd order FIR filter on FPGA.

67
 Task-1
Realization of AND, OR & NOT gates
Aim: Realize the AND, OR & NOT gates by using behavioural modelling using VHDL.

Software Used: vivado 2018.3, ALDEC pro 2020.04

THEORY:
AND gate is a digital logic gate with two or more inputs and one output that performs logical
conjunction. The output of an AND gate is true only when all of the inputs are true.

VHDL Code for AND gate :

library IEEE;
use IEEE.std_logic_1164.all; entity and_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end and_gate;
architecture rtl of and_gate is begin
process(a,b) is
begin
q<=a and b;
end process;
end rtl
--Test Bench:
library IEEE;
use IEEE.std_logic_1164.all; entity testbench is
-- empty
end testbench;
architecture tb of testbench is
-- DUT component component and_gate is port(
a: in std_logic; b: in std_logic; q: out std_logic);
end component;
signal a_in, b_in, q_out: std_logic; begin
-- Connect DUT
DUT: and_gate port map(a_in, b_in, q_out); process
begin

68
a_in <= '0';
b_in <= '0'; wait for 20 ns;
assert(q_out='0') report "Fail 0/0" severity error;

a_in <= '0';

b_in <= '1'; wait for 20 ns;
assert(q_out='0') report "Fail 0/1" severity error; a_in <= '1';
b_in <= '0'; wait for 20 ns;
assert(q_out='0') report "Fail 1/0" severity error; a_in <= '1';
b_in <= '1'; wait for 20 ns;
assert(q_out='1') report "Fail 1/1" severity error;
-- Clear inputs a_in <= '0';

b_in <= '0';

assert false report "Test done." severity note; wait;
end process; end tb;

Result:

69
OR GATE :

Theory:
OR gate is a digital logic gate with two or more inputs and one output that performs logical
OR. The output of an OR gate is true when either or all of the inputs are true.
pin diagram:

Truth table:

-- VHDL Code for OR gate

-- Header file declaration library IEEE;

use IEEE.std_logic_1164.all;
entity or_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end or_gate;

architecture rtl of or_gate is

begin

process(a, b) is
begin
q <= a or b;
end process;
end rtl;
Test bench:
library IEEE;
use IEEE.std_logic_1164.all; entity testbench is
-- empty
end testbench;
architecture tb of testbench is
-- DUT component component or_gate is port(
a: in std_logic; b: in std_logic; q: out std_logic);
end component;
signal a_in, b_in, q_out: std_logic; begin

70
-- Connect DUT
DUT: or_gate port map(a_in, b_in, q_out); process
begin
a_in <= '0';
b_in <= '0'; wait for 1 ns;
assert(q_out='0') report "Fail 0/0" severity error; a_in <= '0';
b_in <= '1'; wait for 1 ns;
assert(q_out='1') report "Fail 0/1" severity error; a_in <= '1';
b_in <= '0'; wait for 1 ns;
assert(q_out='1') report "Fail 1/0" severity error; a_in <= '1';
b_in <= '1'; wait for 1 ns;
assert(q_out='1') report "Fail 1/1" severity error;
-- Clear inputs a_in <= '0';
b_in <= '0';
assert false report "Test done." severity note; wait;
end process;
end tb;
RESULT:

NOT Gate:
Theory:

If the input variable is A, the inverted output is known as NOT A.

71
 Pin Diagram:

VHDL code for NOT gate:

-- Simple not gate design: library IEEE;

use IEEE.std_logic_1164.all; entity not_gate is
port(

a: in std_logic;
q: out std_logic);
end not_gate;
architecture rtl of not_gate is
begin
process(a ) is
begin
q<=not a;
end process;
end rtl;
Test bench:
library IEEE;
use IEEE.std_logic_1164.all; entity testbench is
-- empty
end testbench;
architecture tb of testbench is
-- DUT component
component not_gate is
( a: in std_logic; q: out std_logic);
end component;
signal a_in, q_out: std_logic;
begin
-- Connect DUT
DUT:
not_gate port map(a_in, q_out);
process
begin
a_in <= '0'; wait for 20 ns;
assert(q_out='1') report "Fail 0/1" severity error;
a_in <= '1';
wait for 20 ns;
assert(q_out='0') report "Fail 1/0" severity error;
-- Clear inputs a_in <= '0';
assert false report "Test done." severity note; wait;
end process;
end tb;
Result:

72
 Task-2
Realization of following circuits using Verilog and VHDL
1. 4:1 MUX by using 2:1 MUX
2. JK Flip-flop
Aim of the experiment:
Realization of the above circuits using Verilog and VHDL.

Software used:
Xilinx Vivado 2020.2
Theory:
JK flip flop:
When clock pulse is not given the output of the JK flip-flop remains as the previous
output value. When clock pulse is given the JK flip-flop behaves as in the truth table.

JK flip flop logic circuit.

JK flip flop truth table

2:1 multiplexer:
A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one
output Y. Depending on the select signal, the output is connected to either of the
inputs. If the select line is 0, then the output will be D0 input, whereas if select line is
1, then the output will be D1 input.

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 (2:1 mux block diagram)

(2:1 MUX truth table.)

The output Y for 2:1 mux can be written as Y=D0S+D1S

4:1 multiplexer:

A 4-to-1 multiplexer consists four input lines D0 to D3, two select lines as S0 and S1 and
a output line Y. The select lines S1 and S2 select one of the four input lines to connect the
output line.

4:1 MUX block diagram.

74
 4:1 MUX truth table.
The output Y for 2:1 mux can be written as

4:1 MUX using 2:1 MUX:

To design a 4:1 mux using 2:1 mux we need 3 2:1 mux’s. The outputs of two multiplexers
are given as inputs to the third multiplexer. The same select line is used for first two multiplexers.
The final output is taken from the third multiplexer.

Block diagram for 4:1 mux using 2:1 mux

Code (in Verilog):
JK flip flop:
Top module:
module JK_FF(
input J,
input K,
input CLK,
output Q,
output Qb
);
reg temp;
always @(negedge CLK)
begin
if(J==1'b0 & K==1'b0) //J=0 and K=0
temp<=temp;
else if(J==1'b0 & K==1'b1) //J=0 and K=1

75
temp<=1'b0;
else if(J==1'b1 & K==1'b1) //J=1 and K=0
temp<=1'b1;
else //J=1 and K=1
temp<=~Q;
end
assign Q=temp; //Storing Q(n+1) values
assign Qb=~temp;
endmodule
Test bench code:
module JK_ff_tb;
-------------------------------Inputs
reg J;
reg K;
reg CLK;
---------------------------------Outputs
wire Q;
wire Qb;
--------------------------------- Instantiate the Unit Under Test (UUT)
JK_FF uut (
.J(J),
.K(K),
.CLK(CLK),
.Q(Q),
.Qb(Qb)
);
initial begin
-----------------------------------Initialize Inputs
J = 0;
K = 1'b1;
CLK = 0;
#100;
J=1'b1;
K=1'b0;
#100;
J=1'b0;
#100;
J=1'b1;
K=1'b1;
end
always #25 CLK=~CLK;
endmodule
In VHDL:

Top module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JKFF is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
CLOCK : in STD_LOGIC;
Q : inout STD_LOGIC;
Qb : inout STD_LOGIC);
end JKFF;
architecture Behavioral of JKFF is
begin
process (CLOCK) //Check rising edge
begin
76
if(J='0' and K='0') then //J=0 and K=0
Q<=Q;
Qb<=Qb;
elsif (J='0' and K='1') then //J=0 and K=1
Q<='0';
Qb<='1';
elsif (J='1' and K='0') then //J=1 and K=0
Q<='1'
Qb<='0';
else //J=1 and K=1
Q<=not Q;
Qb<=not Qb;
end if;
end process;
end Behavioral;
Test bench code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY JKFF_vhdl_TB IS
END JKFF_vhdl_TB;
ARCHITECTURE behavior OF JKFF_vhdl_TB IS
-------------------------------Component Declaration for the Unit Under Test (UUT)
COMPONENT JKFF
PORT(
J : IN std_logic;
K : IN std_logic;
CLOCK : IN std_logic;
Q : INOUT std_logic;
Qb : INOUT std_logic
);
END COMPONENT;
--------------------------------------------Inputs
signal J : std_logic := '0';
signal K : std_logic := '1';
signal CLOCK : std_logic := '0';
---------------------------------------------BiDirs
signal Q : std_logic;
signal Qb : std_logic;
-------------------------------------------- Clock period definitions
constant CLOCK_period : time := 50 ns;
BEGIN
---------------------------------------------- Instantiate the Unit Under Test (UUT)
uut: JKFF PORT MAP (
J => J,
K => K,
CLOCK => CLOCK,
Q => Q,
Qb => Qb
);
-- -------------------------------------------Clock process definitions
CLOCK_process :process
begin
CLOCK <= '0';
wait for CLOCK_period/2;
CLOCK <= '1';
wait for CLOCK_period/2;
end process;
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------------------------------------------Stimulus process
stim_proc: process
begin
-----------------------------------------hold reset state for 100 ns.
wait for 100 ns;
J<='1';
K<='0';
wait for 100 ns;
J<='0';
wait for 100 ns;
J<='1';
K<='1';
wait;
end process;END;

Output:

Verilog output of JK flip flop.

VHDL output of JK flip flop.

RTL diagram:

RTL diagram for JK flipflop for Verilog code.

78
 RTL diagram for JK flipflop in VHDL language.

4:1 Multiplexer:
In Verilog:
Top module 2:1 mux:
module Mux2x1(
input [3:0] a,
input [3:0] b,
input s,
output [3:0] y
);
assign y=s?b:a; //Ternary Operator to select channel
endmodule
4:1 Mux:
module Mux4x1(
input [3:0] IN1, //Input
input [3:0] IN2, //Channels
input [3:0] IN3,
input [3:0] IN4,
input S0, //Select line 1
input S1, //Select line 2
output [3:0] OUT //Output selected channels
);
wire [3:0] t1,t2; //Creating temporary variable
Mux2x1 mux1(IN1,IN2,S0,t1); //Creating Mux1
Mux2x1 mux2(IN3,IN4,S0,t2); //Creating Mux2
Mux2x1 mux3(t1,t2,S1,OUT); //Creating Mux3
Endmodule
Test bench:
module Mux4x1_tb;
-------------------------------------- Inputs
reg [3:0] IN1;
reg [3:0] IN2;
reg [3:0] IN3;
reg [3:0] IN4;
reg S0;
reg S1;
------------------------------------- Outputs
wire [3:0] OUT;
------------------------------------- Instantiate the Unit Under Test (UUT)
Mux4x1 uut (
.IN1(IN1),
.IN2(IN2),
.IN3(IN3),
.IN4(IN4),
79
.S0(S0),
.S1(S1),
.OUT(OUT)
);

initial begin
-----------------------------------------Initialize Inputs
IN1 = 4'b1100;
IN2 = 4'b1101;
IN3 = 4'b1110;
IN4 = 4'b1111;
S0 = 1'b0;
S1 = 1'b0;
#100;
S0 = 1'b0;
S1 = 1'b0;
#100;
S0 = 1'b0;
S1 = 1'b1;
#100;
S0 = 1'b1;
S1 = 1'b0;
#100;
S0 = 1'b1;
S1 = 1'b1;
end
endmodule
In VHDL:

Top Module 2:1 mux:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2x1 is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : in STD_LOGIC_vector(3 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_vector(3 downto 0));
end mux2x1;
architecture Behavioral of mux2x1 is
begin
process (a,b,s)
begin
if (s='0') then
z<=a; //Select input 1 if s=0
else
z<=b; //Select input 2 if s=1
end if;
end process;
end Behavioral;
4:1 Mux:
use IEEE.STD_LOGIC_1164.ALL;
entity mux4x1 is
Port ( IN1 : in STD_LOGIC_vector(3 downto 0);
IN2 : in STD_LOGIC_vector(3 downto 0);
IN3 : in STD_LOGIC_vector(3 downto 0);
IN4 : in STD_LOGIC_vector(3 downto 0);
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
OUTPUT : out STD_LOGIC_vector(3 downto 0));
80
end mux4x1;
architecture Behavioral of mux4x1 is
component mux2x1
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : in STD_LOGIC_vector(3 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_vector(3 downto 0));
end component;
signal t1,t2 : std_logic_vector(3 downto 0);--Variable to get output from first two 2x1
mux
begin
m1:mux2x1 port map(IN1,IN2,s0,t1); --Sending first two inputs to MUX 2x1
m2:mux2x1 port map(IN3,IN4,s0,t2); --Sending first two inputs to MUX 2x1
m3:mux2x1 port map(t1,t2,s1,OUTPUT);--Sending the obtained linesto MUX 2x1
end Behavioral;

Output:

4:1 mux output using Verilog.

4:1 mux output using VHDL.

81
RTL diagram:

RTL diagram for 4:1 MUX Verilog language.

RTL diagram for 4:1 MUX VHDL language.

Conclusion:
The results observed in simulator are same as that of the truth table for JK flip-flop
and 4:1 mux. And for the multiplier the product of two numbers obtained are verified.

82
 Task-3
Objective: To realize synchronous and asynchronous FIFO

Equipment required and Software used:

Vivado 2020.1 Desin Suite.

Theory:

FIFO:
A FIFO is a special type of buffer. The name FIFO stands for first in first out and means
that the data written into the buffer first comes out of it first. There are other kinds of buffers like the
LIFO (last in first out), often called a stack memory, and the shared memory. The choice of a buffer
architecture depends on the application to be solved. FIFOs can be implemented with software or
hardware. The choice between a software and a hardware solution depends on the application and
the features desired. When requirements change, a software FIFO easily can be adapted to them
by modifying its program, while a hardware FIFO may demand a new board layout. Software is
more flexible than hardware. The advantage of the hardware FIFOs shows in their speed.
In concurrent read/write FIFOs, there is no dependence between the writing and reading of data.
Simultaneous writing and reading are possible in overlapping fashion or successively. Concurrent
read/write FIFOs, depending on the control signals for writing and reading, fall into two groups:
➢ Synchronous FIFO
➢ Asynchronous FIFO.

Synchronous FIFO:
The purpose of a FIFO is to pass the first given input as the first output, second input as
the second output, etc... What makes the circuit synchronous is the use of a clock signal. The clk
signal for our circuit has a period of 20 nano-seconds (ns), and is positive edge triggered. This
means the clock will only recognize the data during the rising edge of the clock. If the data were to
change within the 20ns period, the clk will not recognize the data until the next positive edge
trigger – this assumes the data hasn’t changed to a new value before the next positive edge of the
clock. One limitation of the Synchronous FIFO circuit is the speed at which the circuit can be
operable.
A Synchronous FIFO circuit must be clocked depending on the slowest block that processes the
information. Data can be fully processed through each ‘Reg’ block during the same clock period –
keeping the process synchronized. During the positive edge of the clock, an 8-bit binary number is
passed into the first Register block (Reg1). In the next clock cycle, the data within Reg1 is
transferred to Reg2, while at the same time a new 8-bit binary number is passed into Reg1. This
process is repeated until the data that was first entered into Reg1 is outputted out of Reg4.
Fig 3.1 represents the basic block diagram of Synchronous FIFO.

Asynchronous FIFO:
A FIFO is a digital circuit that is used for safe transmission of data, usually from one clock
domain to another asynchronous clock domain. That is, a block of data is sent to the FIFO memory
from one clock domain and that stored data is read back from the same FIFO by a different clock
83
domain, with the two clock domains being asynchronous with each other. This is usually achieved
by placing the data block into the FIFO memory with the help of control signals in one clock
domain and control signals from the other clock. domain are used to retrieve the stored data from
the FIFO memory from the output port of the FIFO.
The FIFO is full, when both the pointers are equal, in the case where the write pointer has
wrapped around and caught up with the read pointer. This gives rise to a problem as we are
unable to distinguish between the cases where the FIFO is full or empty. One way to overcome this
ambiguity is to add an extra bit to the read and write pointers. Using this, whenever the write
pointer moves past the last FIFO address, it will toggle that extra bit and will reset the rest of its bits
back to zero. The read pointer follows the same technique. If the MSBs of the two pointers are the
same then that would mean that the pointers have wrapped the same number of times and the
FIFO is empty and if the MSBs of the two pointers are different, that means that the write pointer
has wrapped one more time than the read pointer and hence the FIFO is full

Represents The Basic Block Diagram Of Asynchronous FIFO

Procedure of Experiment:
 Vivado Design suite was opened and a new project is created and name of project was set
and coding language was selected as VHDL.
 The code is written and simulated with test bench and appropriate inputs were given with
respective delays.
 Test bench is run to get the output.

Code for Synchronous FIFO:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--Creating the Top Level Architecture of one register containing 8 DFF's

--7 downto 0 represents 8 bits in each Register block

entity FIFO_4reg_8bits is Port

( clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0));
end FIFO_4reg_8bits;

---Will use 4 registers, each contains 8 DFF's

architecture Behavioral of FIFO_4reg_8bits is
--Instanciating a DFF

component DFF
port (
84
D : in STD_LOGIC_VECTOR (7 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC );
end component;
--'Signal' represents wires interconnecting each Register block within the top level module
signal W1,W2,W3 : std_logic_vector(7 downto 0);
begin
--Format
--Block name: DFF (input, output, clock);
Reg1: DFF port map(input,W1,clk);
Reg2: DFF port map(W1,W2,clk);
Reg3: DFF port map(W2,W3,clk);
Reg4: DFF port map(W3,output,clk);
end Behavioral;
--FIFO Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FIFO_4reg_8bits_TB is
END FIFO_4reg_8bits_TB;
ARCHITECTURE behavior of FIFO_4reg_8bits_TB is
-- Declare the component for the Unit Under Test (UUT)
COMPONENT FIFO_4reg_8bits PORT(
clk : in std_logic;
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Defining Inputs Outputs
signal clk : std_logic := '0';
signal input : std_logic_vector(7 downto 0) := (others => '0');
signal output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
--Assigning equivalent ports from Design to TB
uut: FIFO_4reg_8bits PORT MAP (
clk => clk,
input => input,
output => output );
-- Clock process definitions
--Clock starts at 0, and toggles every clk_period/2 (10ns)
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold state for 200 ns.
input <= "11111111"; --FF
wait for 200 ns;
input <= "11101110"; --EE
wait for 200 ns;

85
input <= "11011101"; --DD
wait for 200 ns;
input <= "11001100"; --CC
wait for 200 ns;
input <= "10111011"; --BB
wait for 200 ns;
wait for clk_period*4;
wait;
end process;
END;
--code for DFF component Used
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Define I/O's of DFF
entity DFF is
Port
( clk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (7 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0));
end DFF;
--Process to set the clock characteristics.
--DFF becomes Synchronous with the introduction of a clock architecture Behavioral of DFF is
--Defines the behavior of the DFF.
architecture Behavioral of DFF is
begin
process(clk)
begin
if ( rising_edge(clk) ) then
Q <= D;
end if;
end process;
end Behavioral;
2. Code for Asynchronous FIFO:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Define top level ports of Async FIFO block
--Design contains 8 Async FIFO reg's
entity Async is Port
( R_in_Top : in STD_LOGIC;
A_in_Top : out STD_LOGIC;
A_out_Top : in STD_LOGIC;
R_out_Top : out STD_LOGIC;
D_in_Top : in STD_LOGIC_VECTOR (7 downto 0);
D_out_Top : out STD_LOGIC_VECTOR (7 downto 0));
end Async;

2. Code for Asynchronous FIFO:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Define top level ports of Async FIFO block
--Design contains 8 Async FIFO reg's
entity Async is Port
( R_in_Top : in STD_LOGIC;
A_in_Top : out STD_LOGIC;
A_out_Top : in STD_LOGIC;
R_out_Top : out STD_LOGIC;
D_in_Top : in STD_LOGIC_VECTOR (7 downto 0);
86
D_out_Top : out STD_LOGIC_VECTOR (7 downto 0));
end Async;
--Describe architecture of sub-blocks
architecture Behavioral of Async_Top is
--Instanciate Async register
component Async_FIFO_reg port
( R_in : in STD_LOGIC;
A_in : out STD_LOGIC;
A_out : in STD_LOGIC;
R_out : out STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
D_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--Wires connecting the sub-blocks
signal Data_1,Data_2,Data_3 : STD_LOGIC_VECTOR(7 downto 0);
signal R_1, R_2, R_3 : STD_LOGIC;
signal A_1, A_2, A_3 : STD_LOGIC;
begin
Reg1: Async_FIFO_reg port map(R_in_Top, A_in_Top, A_1, R_1, D_in_Top, Data_1);
Reg2: Async_FIFO_reg port map(R_1, A_1, A_2, R_2, Data_1, Data_2);
Reg3: Async_FIFO_reg port map(R_2, A_2, A_3, R_3, Data_2, Data_3);
Reg4: Async_FIFO_reg port map(R_3, A_3, A_out_Top, R_out_Top, Data_3,D_out_Top);
end Behavioural;
-- Asynchronous FIFO Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Async_Top_TB IS
END Async_Top_TB;
ARCHITECTURE behaviour OF Async_Top_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Async_Top PORT
( R_in_Top : IN std_logic;
A_in_Top : OUT std_logic;
A_out_Top : IN std_logic;
R_out_Top : OUT std_logic;
D_in_Top : IN std_logic_vector(7 downto 0);
D_out_Top : OUT std_logic_vector(7 downto 0) );
END COMPONENT;
--Outputs
signal A_in_Top : std_logic;
signal R_out_Top : std_logic;
signal D_out_Top : std_logic_vector(7 downto 0);
--Inputs
signal A_out_Top : std_logic := '0';
signal R_in_Top : std_logic := '0';
signal D_in_Top : std_logic_vector(7 downto 0) := (others => '0');
-- No clocks in used port list.
-- constant <clock>_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test UUT (Unit Under Test)
uut: Async_Top PORT MAP
( R_in_Top => R_in_Top,
A_in_Top => A_in_Top,
A_out_Top => A_out_Top,
R_out_Top => R_out_Top,
D_in_Top => D_in_Top,
D_out_Top => D_out_Top );
-- Stimulus process
stim_proc: process
87
begin
-- hold reset state for 50 ns.
wait for 50 ns;
-- Total time before data inputted is 150ns
-- Toggle R_in_Top & insert FEh for data input
R_in_Top <= not(R_in_Top); --Makes Rin high
D_in_Top <= "11111110"; --FE entered while Rin is high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- 1 clock cycle
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- 2nd clock cycle
-- Change data input to CB while clock is high
D_in_Top <= "11001011"; --CB
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- 1 clock cycle
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- 1 clock cycle
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- Change data input to CB while clock is high
D_in_Top <= "10000100"; --84
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- 1 clock cycle
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- 2 clock cycle
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- Change data input to AE while clock is high
D_in_Top <= "10111110"; --AE
88
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- After one clock cycle, change data input to 45
D_in_Top <= "00100101"; --45
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- After one clock cycle, change data input to 94
D_in_Top <= "10010100"; --94
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- After one clock cycle, change data input to 3D
D_in_Top <= "00111101"; --3D
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- After one clock cycle, change data input to EA
D_in_Top <= "11101010"; --EA
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
--Now, we will demonstrate when the clock stays high and low for different amounts of time.
-- After two clock cycles, change data input to 09
D_in_Top <= "00001001"; --09
89
wait for 20 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 30 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- After two clock cycles, change data input to 06
D_in_Top <= "00000110"; --06
wait for 10 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 20 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- After two clock cycles, change data input to 19 D_in_Top <= "00011001"; --19
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 20 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 25 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- After two clock cycles, change data input to 88 D_in_Top <= "10001000"; --88
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 40 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 30 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 20 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 20 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 25 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 25 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 15 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 25 ns;
R_in_Top <= not(R_in_Top); -- Rin toggles high
wait for 10 ns;
R_in_Top <= not(R_in_Top); -- Rin is now low
wait for 10 ns;
90
R_in_Top <= not(R_in_Top); -- Rin toggles high
--Ran several clock cycles to ensure the last D_in bit
--Can be processed through to the output
wait;
end process;
end;
--Code for Reg used in async fifo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Define ports of Async Reg
entity Async_FIFO_reg is
Port
( R_in : in STD_LOGIC;
A_out : in STD_LOGIC;
A_in : out STD_LOGIC;
R_out : out STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
D_out : out STD_LOGIC_VECTOR (7 downto 0));
end Async_FIFO_reg;
--Define behavior of one Async Reg
architecture Behavioral of Async_FIFO_reg is
begin
process(R_in, A_out)
--Statement for the process
begin
if ( R_in = '1' ) then
--This clocks the process
D_out <= D_in;
A_in <= '1';
R_out <= '1';
else if ( A_out = '1' ) then
R_out <= '0'; A_in <= '0';
end if;
end if;
end process;
end Behavioral;

91
Results:

shows the simulation results of Synchronous FIFO.

shows the simulation results of Asynchronous FIFO.

Conclusions:
Designed and obtained results for synchronous and asynchronous FIFO using VIVADO Design
Suite and simulation results are also obtained.

92
 TASK-4
Objective: To design Finite state machine for detecting sequence of 11010.

Equipment required and Software used:

Vivado 2020.1 Desin Suite.

Theory:

FSM:
The definition of a finite state machine is, the term finite state machine (FSM) is also known
as finite state automation. FSM is a calculation model that can be executed with the help of
hardware otherwise software. This is used for creating sequential logic as well as a few computer
programs. FSMs are significant for understanding the decision making logic as well as control the
digital systems. In the FSM, the outputs, as well as the next state, are a present state and the input
function. This means that the selection of the next state mainly depends on the input value. There
are two types of FSMs.

➢ Mealy State Machine

➢ Moore State Machine

Mealy State Machine: A Finite State Machine is said to be Mealy state machine, if outputs depend
on both present inputs & present states. The block diagram of Mealy state machine is shown in the
following figure.

Mealy State Machine: A Finite State Machine is said to be Mealy state machine, if outputs
depend on both present inputs & present states. The block diagram of Mealy state machine is
shown in the following figure.

Moore State Machine: A Finite State Machine is said to be Moore state machine, if outputs depend
only on present states. The block diagram of Moore state machine is shown in the following figure.

93
Procedure of Experiment:
 Vivado Design suite was opened and a new project is created and name of project was set
and coding language was selected as VHDL.
 The code is written and simulated with test bench and appropriate inputs were given with
respective delays.
 Test bench is run to get the output.

CODES:

Code for FSM to detect sequence 11010.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM is
Port
( clk, X, rst : in std_logic;
Y : out std_logic);
end FSM;
architecture Behavioral of FSM is
type mystate is (S0,S1,S2,S3,S4);
signal ps,ns: mystate;
begin
process(clk)
begin
if rising_edge(clk) then
if (rst<='1') then
ps<=S0;
else
ps<=ns;
end if;
end if;
end process;
state_moments:process(ps,X)
begin
Y<='0';
case (ps) is
--CASE OF S0
when S0=>
if (X='1') then
ns<=S1;
Y<='0';
else if (X='0') then
ns<=S0;

94
Y<='0';
end if;
end if;
--CASE OF S1
when S1=>
if (X='1') then
ns<=S2;
Y<='0';
else if (X='0') then
ns<=S0;
Y<='0';
end if;
end if;
--CASE OF S2
when S2=>
if (X='0') then
ns<=S3;
Y<='0';

else if (X='1') then

ns<=S2;
Y<='0';
end if;
end if;
--CASE OF S3
when S3=>
if (X='1') then
ns<=S4;
Y<='0';
else if (X='0') then
ns<=S0;
Y<='0';
end if;
end if;
--CASE OF S4
when S4=>
if (X='0') then
ns<=S4;
Y<='1';
else if (X='1') then
ns<=S1;
Y<='0';
end if;
end if;
end case;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM_tb is
-- Port ( );
end FSM_tb;
architecture Behavioral of FSM_tb is
component FSM
Port ( clk ,X, rst: in std_logic;
Y : out std_logic);
end component;
signal rst:std_logic:='0';
signal clk:std_logic:='0';
signal X:std_logic:='0';

95
signal Y:std_logic;
constant clk_period : time := 100 ns;
begin
uut: FSM port map(clk=>clk,rst=>rst,X=>X,Y=>Y);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
instances:process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
X<='0';
wait for 100ns;
X<='1';
wait for 100ns;
X<='1';
wait for 100ns;
X<='0';
wait for 100ns;
X<='1';
wait for 100ns;
X<='0';
wait for 100ns;
X<='0';
wait for 100ns;
X<='1';
end process;
end Behavioral;

Results:

(shows the simulation of FSM detecting sequence 11010.)

Conclusion: Designed and obtained simulation results for FSM detecting sequence 11010.

96
 Aim: To realize the 8-bit fixed point adder and 8-bit fixed point multiplier using Verilog

Software Required: Vivado Design Suit 2017.4

Code:
Bit fixed point Adder

Top module
module qadd #(
//Parameterized values
parameter Q = 4,
parameter N = 8
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
reg [N-1:0] res;
assign c = res;
always @(a,b) begin
if(a[N-1] == b[N-1]) begin
res[N-2:0] = a[N-2:0] + b[N-2:0];
res[N-1] = a[N-1];
end
else if(a[N-1] == 0 && b[N-1] == 1) begin
if( a[N-2:0] > b[N-2:0] ) begin
res[N-2:0] = a[N-2:0] - b[N-2:0];
res[N-1] = 0;
end
else begin
res[N-2:0] = b[N-2:0] - a[N-2:0];
if (res[N-2:0] == 0)
res[N-1] = 0;
else
res[N-1] = 1;
end
end
else begin
if( a[N-2:0] > b[N-2:0] ) begin
res[N-2:0] = a[N-2:0] - b[N-2:0];
if (res[N-2:0] == 0)
res[N-1] = 0;
else
res[N-1] = 1;
end
else begin
res[N-2:0] = b[N-2:0] - a[N-2:0];
res[N-1] = 0;
end
end
end
endmodule
Testbench Code
`timescale 1ns / 1ps
module Test_add;

97
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire [7:0] c;
// Instantiate the Unit Under Test (UUT)
qadd #(8,8) uut (
.a(a),
.b(b),
.c(c)
);
//These are to monitor the values...
wire [6:0] c_out;
wire [6:0] a_in;
wire [6:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[6:0];
assign b_in = b[6:0];
assign c_out = c[6:0];
assign a_sign = a[7];
assign b_sign = b[7];
assign c_sign = c[7];
initial begin
// Initialize Inputs
a[6:0] = 0;
a[7] = 0;
b[7] = 1;
b[6:0] = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+5179347;
a[7] = 0;
b[7] = 1;
if (a[6:0] > 2.1E9)
begin
a = 0;
b[7] = 1;
b[6:0] = b[6:0] + 3779351;
end
end
end
endmodule
8-Bit fixed point multiplier
`timescale 1ns / 1ps
module qmult #(
//Parameterized values
parameter Q = 4,
parameter N = 8
)
(
input [N-1:0]i_multiplicand,

98
input [N-1:0]i_multiplier,
output[N-1:0]o_result,
output reg ovr
);
reg [2*N-1:0] r_result;
reg [N-1:0]r_RetVal;
assign o_result = r_RetVal;
always @(i_multiplicand, i_multiplier)
begin
r_result <= i_multiplicand[N-2:0] * i_multiplier[N-2:0];
ovr <= 1'b0;
end
always @(r_result) begin
r_RetVal[N-1] <= i_multiplicand[N-1] ^ i_multiplier[N-1];
r_RetVal[N-2:0] <= r_result[N-2+Q:Q];
if (r_result[2*N-2:N-1+Q] > 0)
ovr <= 1'b1;
end
endmodule
Testbench Code:
module Test_mult;
// Inputs
reg [7:0] i_multiplicand;
reg [7:0] i_multiplier;
// Outputs
wire [7:0] o_result;
wire ovr;
// Instantiate the Unit Under Test (UUT)
qmult #(8,8) uut (
.i_multiplicand(i_multiplicand
.i_multiplier(i_multiplier),
.o_result(o_result),
.ovr(ovr)
);
initial begin
$monitor ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result, ovr);
// Initialize Inputs
i_multiplicand = 8'b00110010; //pi = 3.141592
i_multiplicand[7] = 0;
i_multiplier[7] = 0;
i_multiplier[6:0] = 0;
#100;
#100
i_multiplier[0] = 1;
end
always begin
#10
i_multiplier[6:0] = (i_multiplier[6:0] << 1) + 1;
end
endmodule

99
Result:

Conclusion:
Fixed point number is the binary representation of fixed position decimal. This use for
precision in DSP.

100
 TASK-9
Realize ADC-DAC interface with FPGA.

AIM: To simulate ADC-DAC interface using VHDL code

Software used: Quartus II and Vivado 2018.3

Theory:
12 bit ADC and 14 bit DAC are interfaced with FPGA. FPGA uses 16 I/O pins to interface
ADC/DAC to have parallel and fast read/write access.
ADC converts analog signal to digital data format. The ADC VHDL code for receiver part is
mentioned below in which 12 bits are converted to 16 bits with four leading zeroes for FPGA to
read the digital data from ADC.
Pin Diagram:

ADC-DAC serial data interface with FPGA:

101
VHDL Code for rtl modelling:
library ieee;
use ieee.std_logic_1164.all;
entity adc_parallel_interface_ddr is
port (
i_clk : in std_logic;
i_rise_fall_b : in std_logic;
i_data : in std_logic_vector(3 downto 0);
o_data : out std_logic_vector(3 downto 0));
end adc_parallel_interface_ddr;
architecture rtl of adc_parallel_interface_ddr is
signal r_data_rise : std_logic_vector(3 downto 0);
signal r_data_fall : std_logic_vector(3 downto 0);
begin
p_sample_rise : process(i_clk) -- sample ADC data on rising edge
begin
if(rising_edge(i_clk)) then
r_data_rise <= i_data;
end if;
end process p_sample_rise;
p_sample_fall : process(i_clk) -- sample ADC data on falling edge
begin
if(falling_edge(i_clk)) then
r_data_fall <= i_data;
end if;
end process p_sample_fall;
p_output : process(i_clk) -- select EDGE sampling
begin
if(rising_edge(i_clk)) then
if(i_rise_fall_b='1') then
o_data <= r_data_rise;
else
o_data <= r_data_fall;
end if;
end if;
end process p_output;
end rtl;

RTL model:

102
 TASK-8

Realize a 2nd order moving average filter using structural modelling.

AIM: To realize 2nd order moving average filter using structural modelling.

Software Used: vivado 2018.3, ALDEC pro 2020.04

Theory:
The moving average filter operates by averaging a number of points from the input signal to
produce each point in the output signal , shows the theory of moving average filter.

VHDL code for Modelling:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AvgFilter is
generic (
G_DATA_W :integer := 16;
G_FIL_L :integer := 4
);
port (
clk :in std_logic;
rst :in std_logic;
en :in std_logic;
iv_data :in std_logic_vector(G_DATA_W-1 downto 0);
ov_avg :out std_logic_vector(G_DATA_W-1 downto 0)
);
end entity;
architecture AvgFilter_rtl of AvgFilter is
-- calculate number of bits needed to extend sum vector
function sumlog2(m :positive) return natural is
begin
for index in 1 to 30 loop
if (m <= 2**index) then
return(index);
end if;
end loop;
return(31);
end function;
signal en_reg :std_logic;
-- array for storing samples
type t_arr_FilL_x_data is array (G_FIL_L-1 downto 0) of unsigned(G_DATA_W-1 downto 0);
signal a_samples :t_arr_FilL_x_data;
begin
reg: process(clk)
-- to add G_FIL_L values is needed sumlog2(G_FIL_L) more bits for result
variable v_sum :unsigned(G_DATA_W+sumlog2(G_FIL_L)-1 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
en_reg <= '0';
a_samples <= (others => (others => '0'));
v_sum := (others => '0');

103
ov_avg <= (others => '0'
else
en_reg <= en;
a_samples(0) <= unsigned(iv_data);
for i in 1 to G_FIL_L-1 loop
a_samples(i) <= a_samples(i-1);
end loop;
v_sum := (others => '0');
if en_reg = '1' then
for i in 0 to G_FIL_L-1 loop
v_sum := v_sum + resize(a_samples(i), v_sum'length);
end loop;
end if;
ov_avg <= std_logic_vector(v_sum(G_DATA_W+sumlog2(G_FIL_L)-1 downto
sumlog2(G_FIL_L))); -- divide by sumlog2(G_FIL_L)
end if;
end if;
end process;
end architecture;
TEST BENCH:
library ieee;
use ieee.std_logic_1164.all;
entity tb_AvgFilter is
generic (
G_DATA_W :integer := 16;
G_FIL_L :integer := 4
);
end entity;
architecture tb_AvgFilter_rtl of tb_AvgFilter is
component AvgFilter is
generic (
G_DATA_W :integer := 16;
G_FIL_L :integer := 4
);
port (
clk :in std_logic;
rst :in std_logic;
en :in std_logic;
iv_data :in std_logic_vector(G_DATA_W-1 downto 0);
ov_avg :out std_logic_vector(G_DATA_W-1 downto 0)
);
end component;
signal clk :std_logic := '0';
signal rst :std_logic := '0';
signal en :std_logic := '0';
signal iv_data :std_logic_vector(G_DATA_W-1 downto 0);
signal ov_avg :std_logic_vector(G_DATA_W-1 downto 0);
constant ClkGenConst :time := 10 ns;
begin
UUT: AvgFilter
generic map (
G_DATA_W => G_DATA_W,
G_FIL_L => G_FIL_L
)
port map (
clk => clk,
rst => rst,

104
en => en,
iv_data => iv_data,
ov_avg => ov_avg
);
ClockGenerator: process
begin
clk <= '0' after ClkGenConst, '1' after 2*ClkGenConst;
wait for 2*ClkGenConst;
end process;
run_proc: process
begin
rst <= '1';
iv_data <= (others => '0');
en <= '0';
wait for 100 ns;
rst <= '0';
wait for 40 ns;
iv_data <= x"000A";
en <= '1';
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
iv_data <= x"000A";
wait for 20 ns;
en <= '0';
wait;
end process;
end architecture;

Simulation:

105
 TASK-10

Realize 2nd order FIR filter on FPGA.

AIM: To simulate 2nd order FIR filter

Software Used: vivado 2018.3, ALDEC pro 2020.04

Theory:

A finite impulse response (FIR) filter is a filter whose impulse response (or response to any
finite length input) is of finite duration, because it settles to zero in finite time. An FIR filter is
designed by finding the coefficients and filter order that meet certain specifications, which can be
in the time domain (e.g. a matched filter) and/or the frequency .
Filters play an important role for removal of unwanted signal or noise from original input signal by
removing the selected frequencies from incoming signal. They became much popular due to the
increase of the digital signal processing
The first order filters can be easily converted into second order filters simply by using an additional
RC network within the input or feedback path. Then we can define second order filters as simply
being two 1st-order filters cascaded together with amplification circuit.
VHDL code for the FIR filter(low pass):
Library IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.Std_logic_signed.all;
entity FIR_RI is generic (
input_width : integer :=8; -- set input width
output_width : integer: =16; -- set output width
coef_width : integer : =8 -- set coefficient
tap : integer :=11 ; -- set filter order
guard : integer :=0);
port(Din : in std_logic_vector(input_width-1 downto 0);-- input data
Clk : in std_logic;-- input clk
reset: in std_logic;-- input reset
Dout : out std_logic_vector(output_width-1 downto 0));-- output data
end FIR_RI;
architecture behaivioral of FIR_RI is
component N_bit_Reg
generic (input_width: integer:=8);
port(
Q : out std_logic_vector(input_width-1 downto 0);
Clk :in std_logic;
reset :in std_logic;
D :in std_logic_vector(input_width-1 downto 0)
);
end component;
type Coeficient_type is array (1 to tap) of std_logic_vector(coef_width-1 downto 0);
constant coeficient: coeficient_type := ( X"F1", X"F3", X"07", X"26", X"42", X"4E", X"42", X"26",
X"07", X"F3", X"F1" );
type shift_reg_type is array (0 to tap-1) of std_logic_vector(input_width-1 downto 0);
signal shift_reg : shift_reg_type;
type mult_type is array (0 to tap-1) of std_logic_vector(input_width+coef_width-1 downto 0);
signal mult : mult_type;
type ADD_type is array (0 to tap-1) of std_logic_vector(input_width+coef_width-1 downto 0);
signal ADD: ADD_type;
begin
shift_reg(0) <= Din;

106
mult(0)<= Din*coeficient(1);
ADD(0)<= Din*coeficient(1);
GEN_FIR:
for i in 0 to tap-2 generate
begin
N_bit_Reg_unit : N_bit_Reg generic map (input_width => 8)
port map ( Clk => Clk,
reset => reset,
D => shift_reg(i),
Q => shift_reg(i+1)
);
-- filter multiplication
mult(i+1)<= shift_reg(i+1)*coeficient(i+2);
-- filter conbinational addition
ADD(i+1)<=ADD(i)+mult(i+1);
end generate GEN_FIR;
Dout <= ADD(tap-1);
end Architecture;
Library IEEE;
USE IEEE.Std_logic_1164.all;
entity N_bit_Reg is
generic (input_width : integer :=8);
port(
Q : out std_logic_vector(input_width-1 downto 0);
Clk :in std_logic;
reset :in std_logic;
D :in std_logic_vector(input_width-1 downto 0)
);
end N_bit_Reg;
begin
process(Clk,reset)
begin
if (reset = '1') then
Q <= (others => '0');
elsif ( rising_edge(Clk) ) then
Q <= D;
end if;
end process;
end Behavioral;
Testbench VHDL code for the FIR filter:
Library IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.numeric_std.all;
Use STD.TEXTIO.all;
entity TB_FIR is
end TB_FIR;
architecture behaivioral of TB_FIR is
Component FIR_RI is
generic (input_width: integer :=8; -- set input width
output_width: integer:=16; -- set output width coef_width: integer:=8; -- set coefficient width
tap: integer:=11; -- set filter order
guard : integer:=4); -- log2(tap)+1
port(Din : in std_logic_vector(input_width-1 downto 0;
-- input data
Clk: in std_logic; -- input clk
reset : in std_logic; -- input reset
Dout : out std_logic_vector(output_width-1 downto 0));
end Component;
107
signal Din : std_logic_vector(7 downto 0);
signal Clk: std_logic:='0';
signal reset : std_logic:='1’;
signal output_ready : std_logic:='0';
signal Dout : std_logic_vector(15 downto 0);
signal input: std_logic_vector(7 downto 0);
file my_input : TEXT open READ_MODE is "input101.txt";
file my_output : TEXT open WRITE_MODE is "output101_functional_sim.txt";
begin
FIR_int : FIR_RI
generic map(input_width => 8,
output_width => 16,
coef_width => 8,
tap=>11,
guard => 0);
port map (Din => Din,
Clk => Clk,
reset => reset,
Dout => Dout );
process(clk)
begin
Clk <= not Clk after 10 ns;
end process;
reset <= '1', '1' after 100 ns, '0' after 503 ns;
process(clk)
variable my_input_line : LINE;
variable input1: integer;
begin
if reset ='1' then
Din <= (others=> '0');
input <= (others=> '0');
output_ready <= '0';
elsif rising_edge(clk) then
readline(my_input, my_input_line);
read(my_input_line,input1);
Din <= std_logic_vector(to_signed(input1, 8));
--Din<=input(7 downto 0);
output_ready <= '1';
end if;
end process;
process(clk)
variable my_output_line : LINE;
variable input1: integer;
begin
if falling_edge(clk) then
if output_ready ='1' then
write(my_output_line, to_integer(signed(Dout)));
writeline(my_output,my_output_line);
end if;
end if;
end process;
end Architecture;
VERILOG code:
module fir_4tap(
input Clk,
input signed [7:0] Xin,
output reg signed [15:0] Yout);

108
//Internal variables.
wire signed [7:0] H0,H1,H2,H3;
wire signed [15:0] MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3;
wire signed [15:0] Q1,Q2,Q3;
//filter coefficient initializations.
//H = [-2 -1 3 4].
assign H0 = -2;
assign H1 = -1;
assign H2 = 3;
assign H3 = 4;
//Multiple constant multiplications.
assign MCM3 = H3*Xin;
assign MCM2 = H2*Xin;
assign MCM1 = H1*Xin;
assign MCM0 = H0*Xin;
//adders
assign add_out1 = Q1 + MCM2;
assign add_out2 = Q2 + MCM1;
assign add_out3 = Q3 + MCM0;
//flipflop instantiations (for introducing a delay).
DFF dff1 (.Clk(Clk),.D(MCM3),.Q(Q1));
DFF dff2 (.Clk(Clk),.D(add_out1),.Q(Q2));
DFF dff3 (.Clk(Clk),.D(add_out2),.Q(Q3));
//Assign the last adder output to final output.
always@ (posedge Clk)
Yout <= add_out3;
Endmodule
DFF:
module DFF
(input Clk,
input [15:0] D,
output reg [15:0] Q
);
always@ (posedge Clk)
Q = D;
endmodule
Testbench for the FIR filter:
module tb;
// Inputs
reg Clk;
reg signed [7:0] Xin;
// Outputs
wire signed [15:0] Yout;
// Instantiate the Unit Under Test (UUT)
fir_4tap uut (
.Clk(Clk),
.Xin(Xin),
.Yout(Yout)
);
//Generate a clock with 10 ns clock period.
initial Clk = 0; always #5 Clk =~Clk;
//Initialize and apply the inputs.
initial begin
Xin = 0; #40;
Xin = -3; #10;
Xin = 1; #10;
Xin = 0; #10;
Xin = -2; #10;
109
Xin = -1; #10;
Xin = 4; #10;
Xin = -5; #10;
Xin = 6; #10;
Xin = 0; #10;
END

Simulation waveform:

110
XA Zynq UltraScale+ MPSoC Data Sheet: Overview
General Description
The XA Zynq® UltraScale+™ MPSoC family is based on the Xilinx® UltraScale™ MPSoC architecture. This family of products
integrates a feature-rich 64-bit quad-core Arm® Cortex™-A53 and dual-core Arm Cortex-R5 based processing system (PS)
and Xilinx programmable logic (PL) UltraScale architecture in a single device. Also included are on-chip memory, multiport
external memory interfaces, and a rich set of peripheral connectivity interfaces.

Processing System (PS)

Arm Cortex-A53 Based Application Processing Unit (APU)
 Quad-core
 CPU frequency: Up to 1.2GHz
 Extendable cache coherency
 Armv8-A Architecture
o 64-bit or 32-bit operating modes
o TrustZone security
o A64 instruction set in 64-bit mode, A32/T32 instruction set in 32-bit mode
 NEON Advanced SIMD media-processing engine
 Single/double precision Floating Point Unit (FPU)
 CoreSight™ and Embedded Trace Macrocell (ETM)
 Accelerator Coherency Port (ACP)
 AXI Coherency Extension (ACE)
 Power island gating for each processor core
 Timer and Interrupts
o Arm Generic timers support
o Two system level triple-timer counters
o One watchdog timer
o One global system timer
 Caches
o 32KB Level 1, 2-way set-associative instruction cache with parity (independent for each CPU)
o 32KB Level 1, 4-way set-associative data cache with ECC (independent for each CPU)
o 1MB 16-way set-associative Level 2 cache with ECC (shared between the CPUs)

Dual-core Arm Cortex-R5 Based Real-Time Processing Unit (RPU)

 CPU frequency: Up to 500MHz
 Armv7-R Architecture
o A32/T32 instruction set
 Single/double precision Floating Point Unit (FPU)
 CoreSight and Embedded Trace Macrocell (ETM)
 Lock-step or independent operation
 Timer and Interrupts:
o One watchdog timer
o Two triple-timer counters
 Caches and Tightly Coupled Memories (TCMs)
o 32KB Level 1, 4-way set-associative instruction and data cache with ECC (independent for each
CPU)
o 128KB TCM with ECC (independent for each CPU) that can be combined to become 256KB in lock-step
mode
On-Chip Memory
 256KB on-chip RAM (OCM) in PS with ECC
 Up to 27Mb on-chip RAM (UltraRAM) with ECC in PL
 Up to 21.1Mb on-chip RAM (block RAM) with ECC in PL
 Up to 9.1Mb on-chip RAM (distributed RAM) in PL

111
Arm Mali-400 Based GPU
 Supports OpenGL ES 1.1 and 2.0
 Supports OpenVG 1.1
 GPU frequency: Up to 600MHz
 Single Geometry Processor, Two Pixel Processors
 Vertex processing: 66 M Triangles/s
 Pixel processing: 1.2 G Pixels/s
 64KB L2 Cache
 Power island gating
External Memory Interfaces
 Multi-protocol dynamic memory controller
 32-bit or 64-bit interfaces to DDR4, DDR3, DDR3L, or LPDDR3 memories, and 32-bit interface to
LPDDR4 memory
 ECC support in 64-bit and 32-bit modes
 Up to 32GB of address space using single or dual rank of 8-, 16-, or 32-bit-wide memories
 Static memory interfaces
o eMMC4.51 Managed NAND flash support
o ONFI3.1 NAND flash with 24-bit ECC
o 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or two Quad-SPI (8-bit) serial NOR flash
8-Channel DMA Controller
 Two DMA controllers of 8-channels each
 Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction
support
Serial Transceivers
 Four dedicated PS-GTR receivers and transmitters supports up to 6.0Gb/s data rates
o Supports SGMII tri-speed Ethernet, PCI Express® Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort
Dedicated I/O Peripherals and Interfaces
 PCI Express — Compliant with PCIe® 2.1 base specification
o Root complex and End Point configurations
o x1, x2, and x4 at Gen1 or Gen2 rates
 SATA Host
o 1.5, 3.0, and 6.0Gb/s data rates as defined by SATA Specification, revision 3.1
o Supports up to two channels
 DisplayPort Controller
o Up to 5.4Gb/s rate
 Four 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0
support
o Scatter-gather DMA capability
o Recognition of IEEE Std 1588 rev.2 PTP frames
o GMII, RGMII, and SGMII interfaces
o Jumbo frames
 Two USB 3.0/2.0 Device, Host, or OTG peripherals, each supporting up to 12 endpoints
o USB 3.0/2.0 compliant device IP core
o Super-speed, high- speed, full-speed, and low-speed modes
o Intel XHCI- compliant USB host
 Two full CAN 2.0B-compliant CAN bus interfaces
o CAN 2.0-A and CAN 2.0-B and ISO 118981-1
standard compliant
 Two SD/SDIO 2.0/eMMC4.51 compliant controllers
 Two full-duplex SPI ports with three peripheral chip selects
 Two high-speed UARTs (up to 1Mb/s)
 Two master and slave I2C interfaces
 Up to 78 flexible multiplexed I/O (MIO) (up to three banks of 26 I/Os) for peripheral pin assignment
 Up to 96 EMIOs (up to three banks of 32 I/Os) connected to the PL
112
 Interconnect
 High-bandwidth connectivity within PS and between PS and PL
 Arm AMBA® AXI4-based
 QoS support for latency and bandwidth control
 Cache Coherent Interconnect (CCI)
System Memory Management
 System Memory Management Unit (SMMU)
 Xilinx Memory Protection Unit (XMPU)
Platform Management Unit
 Power gates PS peripherals, power islands, and power domains
 Clock gates PS peripheral user firmware option
Configuration and Security Unit
 Boots PS and configures PL
 Supports secure and non-secure boot modes
System Monitor in PS
 On-chip voltage and temperature sensing

Programmable Logic (PL)

Configurable Logic Blocks (CLB)
 Look-up tables (LUT)
 Flip-flops
 Cascadable adders
36Kb Block RAM
 True dual-port
 Up to 72 bits wide
 Configurable as dual 18Kb
UltraRAM
 288Kb dual-port
 72 bits wide
 Error checking and correction
DSP Blocks
 27 x 18 signed multiply
 48-bit adder/accumulator
 27-bit pre-adder
Programmable I/O Blocks
 Supports LVCMOS, LVDS, and SSTL
 1.0V to 3.3V I/O
 Programmable I/O delay and SerDes
JTAG Boundary-Scan
 IEEE Std 1149.1 Compatible Test Interface
PCI Express
 Supports Root complex and End Point configurations
 Supports up to Gen3 speeds
 Up to two integrated blocks in select devices
Video Encoder/Decoder (VCU)
 Available in EV devices
 Accessible from either PS or PL
113
  Simultaneous encode and decode
 H.264 and H.265 support
System Monitor in PL
 On-chip voltage and temperature sensing
 10-bit 200KSPS ADC with up to 17 external inputs

Zynq UltraScale+ MPSoCs

A comprehensive device family, Zynq UltraScale+ MPSoCs offer single-chip, all programmable,
heterogeneous multiprocessors that provide designers with software, hardware, interconnect, power, security, and I/O
programmability. The range of devices in the Zynq UltraScale+ MPSoC family allows designers to target cost-sensitive
as well as high-performance applications from a single platform using industry-standard tools. While each Zynq
UltraScale+ MPSoC contains the same PS, the PL, Video hard blocks, and I/O resources vary between the
devices.XA Zynq UltraScale+ MPSoCs are able to serve a wide range of Automotive applications including multi-camera
multi-feature driver assistance systems, high resolution and video graphic infotainment systems, and driver information.

The UltraScale MPSoC architecture provides processor scalability from 32 to 64 bits with support for
virtualization, the combination of soft and hard engines for real-time control, graphics/video processing, waveform and
packet processing, next-generation interconnect and memory, advanced power management, and technology
enhancements that deliver multi-level security, safety, and reliability. Xilinx offers a large number of soft IP for the XA Zynq
UltraScale+ MPSoC family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL.
Xilinx’s Vivado® Design Suite, SDK™, and PetaLinux development environments enable rapid product development for
software, hardware, and systems engineers. The Arm-based PS also brings a broad range of third-party tools and IP
providers in combination with Xilinx's existing PL ecosystem.

The XA Zynq UltraScale+ MPSoC family delivers unprecedented processing, I/O, and memory bandwidth
in the form of an optimized mix of heterogeneous processing engines embedded in a next-generation, high-
performance, on-chip interconnect with appropriate on-chip memory subsystems. The heterogeneous processing
and programmable engines, which are optimized for different application tasks, enable the XA Zynq UltraScale+ MPSoC
to deliver the extensive performance and efficiency required to address next-generation smarter systems while retaining
backwards compatibility with the original XA Zynq-7000 All Programmable SoC family. The UltraScale MPSoC architecture
also incorporates multiple levels of security, increased safety, and advanced power management, which are critical
requirements of next-generation smarter systems. Xilinx’s embedded UltraFast™ design methodology fully exploits the ASIC-
class capabilities afforded by the UltraScale MPSoC architecture while supporting rapid system development.The inclusion
of an application processor enables high-level operating system support (e.g., AutoSAR and Linux). Other standard
operating systems used with the Cortex-A53 processor are also available for the XA Zynq UltraScale+ MPSoC family.
The PS and the PL are on separate power domains, enabling users to power down the PL for power management if
required. The processors in the PS always boot first, allowing a software centric approach for PL configuration. PL
configuration is managed by software running on the CPU, so it boots similar to an ASSP.

Processing System
Application Processing Unit (APU)
The key features of the APU include:
 64-bit quad-core Arm Cortex-A53 MPCores. Features associated with each core include:
o Arm v8-A Architecture
o Operating target frequency: up to 1.2GHz
o Single and double precision floating
point: 4 SP/2 DP FLOPS/MHz
o NEON Advanced SIMD support with single and double precision floating point instructions
o A64 instruction set in 64-bit operating mode, A32/T32 instruction set in 32-bit operating mode
o Level 1 cache (separate instruction and data, 32KB each for each Cortex-A53 CPU)
– 2-way set-associative Instruction Cache with parity support
– 4-way set-associative Data Cache with ECC support
o Integrated memory management unit (MMU) per processor core
o TrustZone for secure mode operation

114
 o Virtualization support
 Ability to operate in single processor, symmetric quad processor, and asymmetric quad-processor modes
 Integrated 16-way set-associative 1MB Unified Level 2 cache with ECC support
 Interrupts and Timers
o Generic interrupt controller (GIC-400)
o Arm generic timers (4 timers per CPU)
o One watchdog timer (WDT)
o One global timer
o Two triple timers/counters (TTC)
 CoreSight debug and trace support
o Embedded Trace Macrocell (ETM) for instruction trace
o Cross trigger interface (CTI) enabling hardware breakpoints and triggers
 ACP interface to PL for I/O coherency and Level 2 cache allocation
 ACE interface to PL for full coherency
 Power island gating on each processor core
 Optional eFUSE disable per core
Real-Time Processing Unit (RPU)
 Dual-core Arm Cortex-R5 MPCores. Features associated with each core include:
o Arm v7-R Architecture (32-bit)
o Operating target frequency: Up to 500MHz
o A32/T32 instruction set support
o 4-way set-associative Level 1 caches (separate instruction and data, 32KB each) with ECC support
o Integrated Memory Protection Unit (MPU) per processor
o 128KB Tightly Coupled Memory (TCM) with ECC support
o TCMs can be combined to become 256KB in lockstep mode
 Ability to operate in single-processor or dual-processor modes (split and lock-step)
 Dedicated SWDT and two Triple Timer Counters (TTC)
 CoreSight debug and trace support
o Embedded Trace Macrocell (ETM) for instruction and trace
o Cross trigger interface (CTI) enabling hardware breakpoints and triggers
 Optional eFUSE disable
Full-Power Domain DMA (FPD-DMA) and Low-Power Domain DMA (LPD-DMA)
 Two general-purpose DMA controllers one in the full-power domain (FPD-DMA) and one in the low-power
domain (LPD-DMA)
 Eight independent channels per DMA
 Multiple transfer types:
o Memory-to-memory
o Memory-to-peripheral
o Peripheral-to-memory and
o Scatter-gather
 8 peripheral interfaces per DMA
 TrustZone per DMA for optional secure operation

115
 Xilinx Artix Nexys4 DDR™ FPGA Board Reference Manual:

overview
The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the
latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx®. With its large, high-capacity FPGA (Xilinx
part number XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other
ports, the Nexys4 DDR can host designs ranging from introductory combinational circuits to powerful embedded
processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital
microphone, a speaker amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range of
designs without needing any other components

The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher
performance, and more resources than earlier designs. Artix-7 100T features include:
15,850 logic slices, each with four 6-input LUTs and 8 flip-flops
4,860 Kbits of fast block RAM
Six clock management tiles, each with phase-locked loop (PLL)
240 DSP slices
Internal clock speeds exceeding 450 MHz
On-chip analog-to-digital converter (XADC)
The Nexys4 DDR also offers an improved collection of ports and peripherals, including:

 16 user switches  16 user LEDs  Two 4-digit 7-segment displays

 USB-UART Bridge  Two tri-color LEDs  Micro SD card connector
 12-bit VGA output  PWM audio output  PDM microphone
 3-axis accelerometer  Temperature sensor  10/100 Ethernet PHY
 128MiB DDR2  Serial Flash  Four Pmod ports
 Pmod for XADC signals  USB-JTAG port for FPGA  USB HID Host for mice,
programming and keyboards and memory sticks
communication

116
Callout Component Description Callou Component Description
t
1 Power select jumper and battery header 13 FPGA configuration reset button
2 Shared UART/ JTAG USB port 14 CPU reset button (for soft cores)
3 External configuration jumper (SD / USB) 15 Analog signal Pmod connector (XADC)
4 Pmod connector(s) 16 Programming mode jumper
5 Microphone 17 Audio connector
6 Power supply test point(s) 18 VGA connector
7 LEDs (16) 19 FPGA programming done LED
8 Slide switches 20 Ethernet connector
9 Eight digit 7-seg display 21 USB host connector
10 JTAG port for (optional) external cable 22 PIC24 programming port (factory use)
11 Five pushbuttons 23 Power switch
12 Temperature sensor 24 Power jack

117
Power Supplies
The Nexys4 DDR board can receive power from the Digilent USB-JTAG port (J6) or from an
external power supply. Jumper JP3 (near the power jack) determines which source is used.

All Nexys4 DDR power supplies can be turned on and off by a single logic-level power switch
(SW16). A power-good LED (LD22), driven by the “power good” output of the ADP2118 supply, indicates
that the supplies are turned on and operating normally. An overview of the Nexys4 DDR power circuit is
shown in Figure 2.

The USB port can deliver enough power for the vast majority of designs. Our out-of-box demo draws
~400mA of current from the 5V input rail. A few demanding applications, including any that drive
multiple peripheral boards, might require more power than the USB port can provide. Also, some
applications may need to run without being connected to a PC’s USB port. In these instances, an
external power supply or battery pack can be used.

118
 TM4C123G Launchpad Evaluation Kit
The Tiva C Series TM4C123G LaunchPad Evaluation Kit (EK-TM4C123GXL) is a low-cost evaluation platform for
ARM® Cortex™-M4F based microcontrollersThe Tiva C Series LaunchPad design highlights the TM4C123GH6
microcontroller’s USB 2.0 Device interface, Hibernation module, Motion Control PWMs and overall cost effectiveness. The Tiva C
Series LaunchPad also features programmable user buttons and an RGB LEDfor custom applications. The stackable head- ers
of the Tiva C Series TM4C123G Launch- Pad BoosterPack XL interface demonstrate how easy it is to expand the functionality
of the C Series LaunchPad when interfacing to other peripherals with MSP430™ and other TI MCU BoosterPacks

Features
• Tiva C Series TM4C123GH6 microcontroller
• USB Micro-AB connector
• Device mode default configuration
• Host/OTG modes supportable
• RGB user LED
• Two user switches (application/wake)
• Available I/O brought out to headers on a 0.1" grid
• On-board In-Circuit Debug Interface (ICDI)
• Switch-selectable power sources
• ICDI USB Device
• Reset switch.
• Preloaded RG. quickstart application.
• Supported by TivaWare™ for C Series software including the USB library and the peripheral driver library.
• Tiva C Series TM4C123G LaunchPad BoosterPack XL interface which features stackable headers to expand the
capabilities of the 40-pin Tiva C Series LaunchPad evaluation platform.

119