mc166 Kompend Bin e
mc166 Kompend Bin e
mc166 Kompend Bin e
07.11.01
B0009 PMU MOP DOWN Binector for "Lower mot. potentiometer" via PMU
B0047 SLB2 Timeout This binector is set when a timeout on the additional
non-active SIMOLINK ring (SLB2). When
communication is re-established, the binector is reset
again.
B0048 SLB2 start This binector is set when no connection is made on
the additional non-active SIMOLINK ring (SLB2). This
generally means that the line is interrupted or one of
the nodes is without supply voltage.
B0050 SCB TlgOFF SCB telegram failure
not Compact PLUS
B0055 SCom2 TlgOFF SCom2 telegram failure
not Compact PLUS
B0060 SBP CtrlTrack SBP control track
B0070 MeasV valid If this binector is 1, the position measured values are
applicable. During initialization or during any encoder
faults, the angles and the position values are not
applicable. Only when this binector is set, can the
angle or the position be evaluated. In the case of
resolvers, encoders and multiturn encoders, the
analog tracks are evaluated for monitoring.
B0071 MValValidMachEn If this binector is 1, the position measured values of
the machine encoder are valid. During initialization or
during any encoder faults in the encoder, the angle
and the position values are not applicable. Only when
this binector is set, can the angle or the position be
evaluated. In the case of resolvers, encoders and
multiturn encoders, the analog tracks are evaluated
for monitoring.
B0072 Zero pt acquird The zero point deviation shown on connector K0089 is
valid.
B0073 Z pt mach aqurd The zero point deviation of the external encoder
output on KK0088 is valid.
B0089 Status DTComp The binector indicates whether the dead time
compensation is enabled.
B0101 Not Rdy for ON "NOT ready for switching on" binector
B0147 No Tmp Flt Drv "NO converter overtemperature fault active" binector
B0203 Limitr FWD act. Speed limitation positive rotation direction reached
B0204 Limitr REV act. Speed limitation negative rotation direction reached
B0212 PosMem Valid The binector indicates that a valid value has been
registered by the measured-value memory.
B0215 MaEnAcknRef Fixed binector 0
In function diagram 15.2, 15.4
B0216 AckPosCorMEncod Fixed binector 0
In function diagram 15.2, 15.4
B0217 AckMVal MEncod Fixed binector 0
In function diagram 15.2, 15.4
B0220 PosReg release Status bit of position control released
B0241 LZ receive OK Binary output signal for validity of the ready signal of
the receive block
1: OK
0: Not OK
B0255 Excitation End The excitation time of the motor has expired.
B0307 Rel Ref P Control signal to the position actual-value detection for
enabling referencing
B0308 Rel MValMem P Control signal to the position actual-value detection for
enabling the measured value memory
B0311 QuickOutp1 P Quick output of positioning. The significance is
determined with MD47 and MD48 (U501.47 and 48)
B0312 QuickOutp2 P Quick output of positioning. The significance is
determined with MD47 and MD48 (U501.47 and 48)
B0313 QuickOutp3 P Quick output of positioning. The significance is
determined with MD47 and MD48 (U501.47 and 48)
B0314 QuickOutp4 P Quick output of positioning. The significance is
determined with MD47 and MD48 (U501.47 and 48)
B0315 FastOutp5.P Fixed binector 0
In function diagram 15.2, 15.4
B0316 FastOutp6.P Fixed binector 0
In function diagram 15.2, 15.4
B0330 Simulation Binector simulation
B0430 ... B0445 K->B CONV2 16 binectors of the 2nd connector -> binector converter
B0450 ... B0465 K->B CONV3 16 binectors of the 3rd connector -> binector converter
B0490 ... B0491 COUNTER 1.36 B 16-bit counter: positive overflow and negative overflow
B0571 SampTimeChB0.67 Binary output signal of the 2nd sampling time changer
B0572 SampTimeChB0.68 Binary output signal of the 3rd sampling time changer
B0573 SampTimeChB0.69 Binary output signal of the 4th sampling time changer
B0574 SampTimeChB0.70 Binary output signal of the 5th sampling time changer
B0575 SampTimeChB0.71 Binary output signal of the 6th sampling time changer
B0576 PulsGen1 B 0.65 Binary output signal of the 1st pulse generator
B0577 I32 OG B 1.53 Flag for output value at upper limit of the 1st integrator
B0578 I32 UG B 1.53 Flag for output value at lower limit of the 1st integrator
B0579 I32 OG B 1.85 Flag for output value at upper limit of the 2nd integrator
B0580 I32 UG B 1.85 Flag for output value at lower limit of the 2nd integrator
B0803 Start/Stop During the time span of the start/stop length (U611)
B0828 Trig. MastV Cor Trigger master-value correction is used with the
master-value correction function during homing to
compensate for the actual-value jump. To this end,
this connector can be connected to "Trigger master-
value correction" B828, and "Absolute value master-
value correction" KK308 can be connected to
"Correction displacement" U453.
B0850 EHIEncoder1 POV Binector output of the 1st single ramp generator (32
bit) for displaying the upper limit active.
[FP786a]
B0851 EHIEncoder1 NOV Binector output of the 1st single ramp generator (32
bit) for displaying the lower limit active.
[FP786a]
B0852 EHIEncoder2 POV Binector output of the 2nd single ramp generator (32
bit) for displaying the upper limit active.
[FP786b]
B0853 EHIEncoder1 NOV Binector output of the 2nd single ramp generator (32
bit) for displaying the lower limit active.
[FP786b]
B0856 Emerg/lowering Fixed binector 0
In function diagram 15.2, 15.4
B0858 Uzk>max lower Fixed binector 0
In function diagram 15.2, 15.4
B0859 Uzk< min lower Fixed binector 0
In function diagram 15.2, 15.4
B0860 EPos POS OK POS_OK (in window)
B5106 1stEB1 DI2 inv. Digital input 2 inverted on the first inserted EB1
B5108 1stEB1 DI3 inv. Digital input 3 inverted on the first inserted EB1
B5110 1stEB1 DI4 inv. Digital input 4 inverted on the first inserted EB1
B5112 1stEB1 DI5 inv. Digital input 5 inverted on the first inserted EB1
B5114 1stEB1 DI6 inv. Digital input 6 inverted on the first inserted EB1
B5116 1stEB1 DI7 inv. Digital input 7 inverted on the first inserted EB1
B5121 WireBreak1stEB2 Signal for wire break on the first inserted EB2
B5122 BI1 inv.1stEB2 Digital input 1 inverted on the first inserted EB2
B5123 BI1 1st EB2 Digital input 1 on the first inserted EB2
B5124 BI2 inv. 1stEB2 Digital input 2 inverted on the first inserted EB2
B5201 2EB1WireAnaIn1 Signal for wire break at analog input 1 on the second
inserted EB1
B5202 2EB1 U>8VAnaIn2 Signal for high at input (U_in > 8V) at analog input 2
on the second EB1
B5203 2EB1 U>8VAnaIn3 Signal for high at input (U_in > 8V) at analog input 3
on the second inserted EB1
B5204 2ndEB1 DI1 inv. Digital input 1 inverted on the second inserted EB1
B5206 2ndEB1 DI2 inv. Digital input 2 inverted on the second inserted EB1
B5208 2ndEB1 DI3 inv. Digital input 3 inverted on the second EB1
B5210 2ndEB1 DI4 inv. Digital input 4 inverted on the second inserted EB1
B5212 2ndEB1 DI5 inv. Digital input 5 inverted on the second inserted EB1
B5214 2ndEB1 DI6 inv Digital input 6 inverted on the second inserted EB1
B5216 2ndEB1 DI7 inv. Digital input 7 inverted on the second inserted EB1
B5221 WireBreak2ndEB2 Signal for wire break on the second inserted EB2
B5222 BI1 inv. 2ndEB2 Digital input 1 inverted on the second inserted EB2
B5224 BI2 inv. 2ndEB2 Binary input 2 inverted on the second inserted EB2