ATJ2135

Actions ATJ2135 Product
Datasheet
Latest Version: 1.1
DEC 2006
ATJ2135 PRODUCT DATASHEET
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Ver 1.1 Page 3 2007-1-29
Contents
Declaration......................................................................................................................2
Contents ..........................................................................................................................4
List of Figures .................................................................................................................8
List of Tables ................................................................................................................ 11
Revision History ........................................................................................................... 13
1 Introduction........................................................................................................... 14
2 Pin Description ..................................................................................................... 15
2.1 Pin Assignment ..............................................................................................................15
2.2 Pin Definition.................................................................................................................. 16
3 Function Description ............................................................................................ 23

3.1 Functional Block Diagram ............................................................................................23
3.2 Memory Map .................................................................................................................. 24
3.3 CMU.................................................................................................................................. 26
3.3.1 CMU/HOSC Description ............................................................................................26
3.3.2 RTC/LOSC/Watch Dog/Timers Block.....................................................................30
3.4 Interrupt Controller ........................................................................................................ 31

3.4.1 Interrupt Controller Logic .........................................................................................32
3.4.2 Interrupt Source .........................................................................................................32
3.4.3 External Interrupt Sources........................................................................................34
3.5 PMU/DC-DC Converter ..................................................................................................34

3.5.1 Description..................................................................................................................34
3.5.2 DC/DC Converter and Regulator .............................................................................35
3.5.3 Battery Monitor and Temperature Monitor............................................................38
3.5.4 Remote Control ADC .................................................................................................38
3.5.5 Charger Circuits .........................................................................................................38
3.5.6 PWM Back-light IC Control .......................................................................................38
3.5.7 Signal Description .....................................................................................................40

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3.6 32-BIT RISC Core............................................................................................................40

3.6.1 Coprocessor 0 ............................................................................................................40
3.6.2 Exceptions...................................................................................................................40
3.6.3 Performance Counters.............................................................................................. 41
3.6.4 Other Reference......................................................................................................... 41
3.7 SDRAM Interface ...........................................................................................................42

3.7.1 SDRAM Signals ..........................................................................................................42
3.8 SRAM on Chip.................................................................................................................43
3.9 BROM............................................................................................................................... 43
3.10 DMA/Bus Arbiter............................................................................................................43

3.10.1 DMA Architecture ......................................................................................................44
3.10.2 DMA Bus Timing ........................................................................................................45
3.11 24-BIT DSP Core.............................................................................................................46

3.11.1 Features ......................................................................................................................46
3.11.2 Block Diagram ........................................................................................................... 47
3.12 Media Hardware Accelerator (MHA) ...........................................................................48

3.12.1 Description..................................................................................................................48
3.12.2 Features ......................................................................................................................49
3.12.3 Block Diagram .........................................................................................................50
3.13 Motion Compensation Accelerator (MCA).................................................................. 50

3.13.1 Description..................................................................................................................50
3.13.2 Features ...................................................................................................................... 51
3.13.3 Block Diagram ...........................................................................................................51
3.14 NAND FLASH Interface .................................................................................................52
3.15 SD/MMC Interface.........................................................................................................53
3.16 YUV2RGB Interface........................................................................................................53
3.17 USB2.0 SIE...................................................................................................................... 54

3.17.1 General Description...................................................................................................54
3.17.2 Features ......................................................................................................................54
3.18 I2C (2) Interface .............................................................................................................55
3.19 IR Interface ..................................................................................................................... 55
3.20 Key Scan.......................................................................................................................... 58
3.21 DAC and Headphone Driver.......................................................................................... 61

3.21.1 Framework.................................................................................................................. 61

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3.21.2 Block Diagram ...........................................................................................................63
3.22 ADC .................................................................................................................................. 63
4 Electrical Characteristics..................................................................................... 65
4.1 Absolute Maximum Ratings.........................................................................................65
4.2 Capacitance....................................................................................................................65
4.3 DC Characteristics .........................................................................................................66
4.4 PMU.................................................................................................................................. 66
4.5 AC Characteristics..........................................................................................................70
4.5.1 AC Test Input Waveform ........................................................................................... 71
4.5.2 AC Test Output Measuring Points............................................................................ 71
4.6 Reset Parameter............................................................................................................ 71
4.7 Initialization Parameter ................................................................................................ 71
4.8 GPIO Interface Parameter............................................................................................72
4.9 Ordinary ROM Parameter .............................................................................................73
4.10 External System Bus Parameter.................................................................................. 74
4.11 Bus Operation.................................................................................................................75
4.12 I2C Interface Parameter...............................................................................................78
4.13 A/D Converter Characteristics .....................................................................................79
4.14 DAC Characteristics .......................................................................................................83
4.15 Headphone Driver Characteristics ..............................................................................84
4.16 LCM Driver Parameter................................................................................................... 87
4.17 NAND Flash IF ................................................................................................................89
4.18 SD Card............................................................................................................................ 92
4.19 SDRAM IF ........................................................................................................................ 94

4.19.1 104
5 Ordering Information ......................................................................................... 105

5.1 Recommended Soldering Conditions.......................................................................105
5.2 Precaution against ESD for Semiconductors ..........................................................105
5.3 Handling of Unused Input Pins for CMOS ................................................................106
5.4 Status before Initialization of MOS Devices ............................................................106

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6 ATJ2135 Package Drawing ............................................................................... 107

7 Appendix.............................................................................................................. 108
7.1 Acronym and Abbreviations .......................................................................................108

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List of Figures
Figure 1: Pin Assignment......................................................................................................15

Figure 2: ATJ2135 Functional Block Diagram .....................................................................23
Figure 3: ATJ2135 Clock Diagram........................................................................................27
Figure 4: CMU Framework.....................................................................................................28
Figure 5: SPECIAL CLK Framework ......................................................................................29
Figure 6: Watch Dog/RTC/Timers Block Diagram..............................................................31
Figure 7: Interrupt Controller Logic.......................................................................................32
Figure 8: External Interrupt 0 Logic......................................................................................34
Figure 9: DC/DC Converters & Regulator--Block Map ........................................................37
Figure 10 PWM Back-light IC Application diagram ............................................................39
Figure 11 PWM Block diagram ............................................................................................39
Figure 12: Performance Counters Block Diagram..............................................................41
Figure 13: Bus Topology........................................................................................................44
Figure 14: DMA Architecture ................................................................................................45
Figure 15: DMA Basic Bus Timing ........................................................................................45
Figure 16: DMA Bus Timing with Wait States .....................................................................46
Figure 17: DMA Bus Burst Timing.........................................................................................46
Figure 18: 24-Bit DSP Core Block Diagram.........................................................................47
Figure 19: How to Use MHA in a System .............................................................................48
Figure 20: MHA Block Diagram............................................................................................50
Figure 21: Application Example of MCA ..............................................................................51
Figure 22: MCA Block Diagram ............................................................................................52
Figure 23: YUV to RGB Decoder Module Block Diagram....................................................54
Figure 24: Packet for MIR Mode...........................................................................................57
Figure 25: Packet for FIR Mode............................................................................................57
Figure 26: Max Key Scan Matrix in Parallel Mode ..............................................................58
Figure 27: 8*8 Key Scan Matrix in Serial Mode ..................................................................59
Figure 28: One Line Scan Timing .........................................................................................60
Figure 29: The Whole Key Scan Timing ...............................................................................60
Figure 30: DAC Block Diagram .............................................................................................61
Figure 31: DAC Framework ...................................................................................................62
Figure 32: ADDA Analog Diagram........................................................................................63
Figure 33: Efficiency Curve for Backlight Step Up Circuit...................................................67

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Figure 34: DC/DC Efficiency Curve 1 ...................................................................................68

Figure 35: DC/DC Efficiency Curve 2 ...................................................................................69
Figure 36: Charging Curve—Voltage Characteristics Curve ................................................69
Figure 37: Charging Curve—Current Characteristics Curve.................................................70
Figure 38: AC Test Input Waveform......................................................................................71
Figure 39: AC Test Output Measuring Points.......................................................................71
Figure 40: Reset Timing ........................................................................................................71
Figure 41: Initialization Timing .............................................................................................72
Figure 42: GPIO Interface -- Output time .............................................................................72
Figure 43: Ordinary ROM Parameter ...................................................................................73
Figure 44: External System Bus Timing ...............................................................................74
Figure 45: Instruction Fetch Timing .....................................................................................76
Figure 46 Memory Read Timing...........................................................................................76
Figure 47: Memory Write Timing ..........................................................................................77
Figure 48: IO Read Timing ....................................................................................................77
Figure 49: IO Write Timing....................................................................................................78
Figure 50: I2C Interface Timing............................................................................................79
Figure 51: A/D Converter -- Frequency Response Characteristics.....................................80
Figure 52: A/D Converter -- THD+N vs AMP.........................................................................81
Figure 53: A/D Converter --Small Signal Power Spectrum.................................................82
Figure 54: A/D Converter -- Linearity ...................................................................................83
Figure 55: DAC --Small Signal Power Spectrum..................................................................84
Figure 56: Headphone Driver–Frequency Response ..........................................................85
Figure 57: Headphone Driver--THD + N Amplitude Diagram of Headphone Driver..........86
Figure 58: Headphone Driver--Small Signal Power Spectrum ...........................................86
Figure 59: Headphone Driver—Linearity ..............................................................................87
Figure 60: LCM Timing ..........................................................................................................88
Figure 61: Conventional Serial Access Mode ......................................................................89
Figure 62: EDO Type Serial Access Mode ............................................................................89
Figure 63: Another Serial Access Mode...............................................................................90
Figure 64: Command Latch Cycle ........................................................................................90
Figure 65: Address Latch Cycle ............................................................................................90
Figure 66: WR/RD Signal Rising & Falling Driver Request................................................91
Figure 67: Timing Diagram Data Input/Output Referenced to Clock................................92
Figure 68: Standard SDRAM Power Up................................................................................94
Figure 69: Mobile SDRAM Power Up....................................................................................94
Figure 70: SDRAM IF-- Power Down .....................................................................................95
Figure 71: SDRAM IF-- Clock Suspend .................................................................................96
Figure 72: SDRAM IF-- Auto Refresh ....................................................................................97
Figure 73: SDRAM IF -- Self Refresh ....................................................................................98

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Figure 74: SDRAM IF-- Read..................................................................................................99

Figure 75: SDRAM IF -- Read DQM Operation ...................................................................100
Figure 76: SDRAM IF-- Write ...............................................................................................101
Figure 77: SDRAM IF-- Write-DQM Operation ....................................................................102
Figure 78: ATJ2135 Package Drawing...............................................................................107

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List of Tables
Table 1: ATJ2135 Pin Definition ...........................................................................................16

Table 2: ATJ2135 Physical Memory Map .............................................................................24
Table 3 Interrupt Controller Connects to CPU......................................................................32
Table 4: Interrupt Sources.....................................................................................................33
Table 5: DC/DC Converters & Regulators--Power Mode Set ..............................................35
Table 6: ATJ2135 PMU Slave—Power Mode.........................................................................36
Table 7: DC/DC Converters & Regulators—Loading Capacity ............................................36
Table 8: Relationship between Battery Type & ADC Input Range .....................................38
Table 9: CPU Interrupt Sources.............................................................................................40
Table 10: SDRAM Signals .....................................................................................................42
Table 11: Functions and Application of MHA ......................................................................48
Table 12: IR Interface Modes................................................................................................57
Table 13: Absolute Maximum Ratings.................................................................................65
Table 14: Capacitance...........................................................................................................65
Table 15: DC Characteristics.................................................................................................66
Table 16: System Standby Dissipation ................................................................................66
Table 17: Vccout Load Capability..........................................................................................67
Table 18: LRADC Precision ...................................................................................................67
Table 19: LDO Load Capacity................................................................................................70
Table 20: Reset Parameter ...................................................................................................71
Table 21: Initialization Parameter ........................................................................................71
Table 22: GPIO Interface Parameter....................................................................................72
Table 23: GPIO Drive..............................................................................................................72
Table 24: Ordinary ROM Parameter .....................................................................................73
Table 25: External System Bus Parameter ..........................................................................74
Table 26: I2C Interface Parameter.......................................................................................78
Table 27: A/D Converter Characteristics..............................................................................79
Table 28: DAC Characteristics ..............................................................................................83
Table 29: Headphone Driver Characteristics .......................................................................84
Table 30: LCM Driver Parameter ..........................................................................................88
Table 31: Nand Flash Timing Request .................................................................................91
Table 32: Card Interface Timings .........................................................................................92
Table 33: Bus Signal Line Load ............................................................................................93
Table 34: SD Spec. ver1.0 Timing ........................................................................................93

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Table 35: SDRAM IF -- Parameter.......................................................................................103

Table 36: Soldering Conditions for Surface-mount Devices.............................................105

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Revision History
Date Revision Description Author

Dec 2006 1.0 Initial release; Fionawx
Updated based on SD Spec
Jan 2007 1.1 Fionawx
0.40M (061124)

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1 Introduction
Overview
The Actions ATJ2135 is a highly integrated 32bit RISC-based SoC for digital media
solution. The RISC architecture and high speed bus controller are capable of achieving high
performance with low power consumption. With a built-in JPEG co-processor, this media
platform is capable of processing both JPEG and MJPEG format with higher efficiency. The
integrated high-speed USB 2.0 SIE enables the platform to act as a mass storage device at
the speed up to 480Mbps. The audio codec in the SoC is based on sigma-delta modulation,
providing high performance with low power consumption as well as allowing the flexible
adjustment of sample rates from 8k to 96k. The built-in audio codec is able to switch inputs
within headphones, microphones, FM radios and direct drive for low impedance earphones.
The ATJ2135 also provides integrated SDRAM and Flash interfaces; IIC, IR and UART etc.
interfaces for changeable control and transfer modes. The ATJ2135 therefore provides a true
“ALL-IN-ONE” solution that is ideally suited for highly optimized digital media devices.
Features
Audio playing support: MP3, WMA, OGG, APE, WAV
Audio recording support: ADPCM, MP3
Video playing support: AMVB, XVID, MJPEG QVGA 25fp
Image view support: JPEG, BMP, GIF
USB 2.0 Device
High Speed NAND I/F
Supports SLC & MLC device
Multi-bit Error Correction
Supports SD/MMC FLASH Card
OLED, TFT, STN support
Integrated stereo DAC & ADC
Li-Ion battery charger
11-16V backlight driver for LED
6bit battery monitoring ADC

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2 Pin Description
2.1 Pin Assignment
Figure 1: Pin Assignment

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2.2 Pin Definition
Table 1: ATJ2135 Pin Definition

Driver Reset
Pin No. Pin Name I/O Type Short Description
Capacity Default
1 RTCVDD PWRI / RTC Power VDD

2 LOSCI AI / Low Oscillator Input
3 LOSCO AO / Low Oscillator Output
NF_CEB2 NAND FLASH Interface CE2
O
4 /RGB_CE 4mA RGB Interface CE
GPIOA17 BI GPIOA Port 17
NF_CEB1 NAND FLASH Interface CE1

5 O 4mA
/RGB_CE RGB Interface CE
SIRQ1 I External IRQ 1

6 2mA
GPIOB31 BI GPIOB Port 31
NF_WR NAND FLASH Interface WR

7 O 8mA
/RGB_WRB RGB Interface WR
NF_RD NAND FLASH Interface RD
8 O 16mA
/RGB_RDB RGB Interface RD
9 VDD PWRI / VDD
10 VCC PWRI / VCC
11 GND PWR / GND
12 SDRAM_BA0 O 8mA SDRAM Interface Bank Address0
13 SDRAM_DQ0 BI 8mA SDRAM Interface Data 0
14 SDRAM_A0 O 8mA SDRAM Interface Address 0
17 SDRAM_A2 O 8mA SDRAM Interface Address2

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24 SDRAM_VP PWRI / SDRAM Interface Power
25 SDRAM_GND PWR / SDRAM Interface GND
SDRAM_A7 O SDRAM Interface Address 7

27 8mA

28 8mA
GPIOA22 BI GPIOA Port A 22

30 8mA
SDRAM_A10 O SDRAM Address 10

31 8mA

SDRAM_A11 O SDRAM Interface Address11
33 8mA
34 SDRAM_DQ7 BI 8mA SDRAM Interface Data7
SDRAM_WEB O SDRAM Interface Write Enable
35 8mA
SDRAM_A12 O SDRAM Interface Address12
37 8mA

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SDRAM_RASB O SDRAM Interface RAS

42 8mA
SDRAM_CASB O SDRAM Interface CAS
43 8mA
45 SDRAM_CSB O 8mA SDRAM Interface CS
46 SDRAM_GND PWR / SDRAM Interface GND
47 SDRAM_VP PWRI / SDRAM Interface Power
48 SDRAM_CK O 16mA SDRAM Interface Clock
49 SDRAM_CKE O 16mA SDRAM Interface Clock Enable
SDRAM Interface LDQM (for 16bits
50 SDRAM_LDQM O 8mA
SDRAM)
51 SDRAM_DQ14 BI 8mA SDRAM Data14
SDRAM Interface DQM
SDRAM_DQM/UD (for 8bits SDRAM)
52 O 8mA
QM SDRAM Interface UDQM
(for 16bits SDRAM)
54 VBUS I / VBUS
55 UVCC PWR / UVCC
56 DP BI / Data Plus
57 DM BI / Minus
58 UGND PWR / UGND
59 RREF AO / Reference Resistance
60 AGNDP PWR / AGND
61 AVDDP PWR / AVDD
62 UGNDS PWR / UGND
63 UVCCS PWR / UVCC
64 MICINL AI / Microphone In Left Channel
65 VMIC AI / Microphone Power Supply

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66 FMINR AI / FM In Right Channel

67 FMINL AI / FM in Left Channel
68 AGND PWR / Audio Analog GND
69 AVCC PWRO / Audio Analog VCC
70 VRDA AO / Audio DAC Voltage Reference
71 VREFI AI / Voltage Reference Input
72 PAGND PWR / Audio PA GND
73 AOUTR AO / Audio output Right Channel
74 PAVCC PWRO / Audio PA VCC
75 AOUTL AO / Audio output Left Channel
76 AVDD PWRO / Audio VDD
77 HOSCO AO / High Oscillator Output
78 HOSCI AI / High Oscillator Input
79 VCC PWRI / VCC
KSIN[2] BI Key Scan Input2
80 2mA
KS_OUT[2] BI Key Scan output 2
81 2mA
KS_IN[1] BI Key Scan Input 1
82 2mA
KS_OUT[1] BI Key Scan Output 1
83 2mA
KS_IN[0] BI KEY Scan in 0
84 2mA
KS_OUT[0] BI Key Scan Output 0
85 2mA
GPIOA12 BI GPIOA Port12
86 NF_CEB3 O 4mA NAND FLASH Interface CE3
87 RESETB I / System RESET
TEST TEST
88 I /
/CLKOUT FM Module Clock out

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I2C1_SDA I2C1 Interface SDA

BI 2mA
89 /UART2IR_RX UART2 or IrDA Interface RX
I2C1_SCL I2C1 Interface SCL
BI 2mA
90 /UART2IR_TX UART2 or IrDA Interface TX
91 BL_NDR AO / Back Light NDR
92 REM_CON AI / Remote Control ADC input
93 BL_FB O / Back Light Feed Back
94 IO_VDD PWR / POW Pin IOVDD
95 LXVDD PWR / POW Pin LXVDD
96 PGND PWR / POWER MOS GND
97 PGND PWR / POWER MOS GND
98 LXVCC PWR / POW Pin LXVCC
99 IO_VCC PWR / POW Pin IOVCC
100 BAT PWRI / Battery input
101 DC5V PWRI / DC5V input
102 VCC PWRIO / VCC
103 VDD PWRIO / VDD
104 VCCOUT PWRO / Programmed VCC output
105 GND PWR / GND
SD_CLK SD CARD Interface CLOCK
O 16mA
106 /CE6 LCD Interface CE6
NF_ALE NAND FLASH ALE
O
107 /RGB_WD[0] 4mA RGB Interface Data0
NF_RB NAND FLASH Interface Ready/Busy
O
108 /RGB_WD[9] 4mA RGB Interface Data 9

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NF_CLE NAND FLASH Interface CLE

/RGB_RS O RGB Interface RS
109 4mA
/SD_CMD SD card Interface CMD
NF_D[8] NAND FLASH Data 8
110 /RGB_WD[1] BI 4mA RGB Interface Data 1
/SD_DAT[0] SD Card Interface Data 0
NF_D[9] NAND FLASH Interface Data 9
/SD_DAT[5] SD card Interface Data 5
NF_CEB0 O NAND FLASH Interface CE0
118 4mA

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119 VDD PWRI / VDD

120 BI 4mA
/RGB_WD[10] RGB Interface Data 10
121 BI 4mA
122 BI 4mA
NF_D[3] NAND FLASH Interface 3
123 BI 4mA
124 BI 4mA
125 BI 4mA
/RGB_WD[15] RGB Interface WD 15
126 BI 4mA
127 BI 4mA
128 GND PWR / GND
NOTE:
1 PWR----Power Supply
2 AI-----Analog Input
3 AO----Analog Output
4 O----Output
5 I----Input
6 BI----Bi-direction
7 USCU, USCL----Schmitt Type
8 OD----Open Drain
9 ABI----Analog Bi-direction

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3 Function Description
3.1 Functional Block Diagram
Figure 2: ATJ2135 Functional Block Diagram

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3.2 Memory Map
Altogether 4G memory map; user mode 512M: 00000000～1FFFFFFF.

Table 2: ATJ2135 Physical Memory Map
ATJ2135 Physical Memory Map
Start End Size（M） Function

0x00000000 0x0FFFFFFF 256 SDRAM Space
0x10000000 0x11FFFFFF 32 IO Device
0x12000000 0x13FFFFFF 32 Reserved
0x14000000 0x17FFFFFF 64 IO Device/MEM
0x18000000 0x1FFFFFFF 128 MEM (boot)
IO Map
Start End Size（K） Function
0x10000000 0x1000FFFF 64 PMU/LRADC
0x10010000 0x10017FFF 32 CMU/HOSC
0x10018000 0x1001FFFF 32 RTC/LOSC/WD
0x10020000 0x1002FFFF 64 Interrupt Controller
0x10030000 0x10037FFF 32 Reserved
0x10038000 0x1003FFFF 32 Reserved
0x10040000 0x1004FFFF 64 32Bit Risc Core Performance CNT
0x10050000 0x1005FFFF 64 DSP Control
0x10060000 0x1006FFFF 64 DMA Controller
0x10070000 0x1007FFFF 64 SDRAM Controller
0x10080000 0x1008FFFF 64 MCA
0x100A0000 0x100AFFFF 64 FLASH I/F
0x100B0000 0x100BFFFF 64 SD IF
0x100C0000 0x100CFFFF 64 MHA
0x100D0000 0x100DFFFF 64 Reserved
0x100E0000 0x100EFFFF 64 USB
0x100F0000 0x100FFFFF 64 YVU2RGB

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0x10100000 0x1010FFFF 64 DAC＋PA

0x10110000 0x1011FFFF 64 ADC
0x10160000 IR
0x10180000 0x1018FFFF 64 IIC
0x101A0000 0x101AFFFF 64 Key Scan
0x101B0000 0x101BFFFF 64 Reserved
0x101C0000 0x101CFFFF 64 GPIO
0x101D0000 0x101DFFFF 64 Reserved
0x101E0000 0x101EFFFF 64 Reserved
0x101F0000 0x101FFFFF 64 Reserved
2048 SUM
0x10200000 0x11FFFFFF Reserved
IO/MEM Map
Start End Size（K） Function

0x14000000 0x1403FFFF 256k Reserved
DSP mode 24bit Wide (128k)
0x14040000 0x1405FFFF 128k/96k
MIPS mode 32bit Wide (96k)
0x140600000 0x17FFFFFF Reserved
MEM (LCD and LAN) Map
Start End Size（M） Function

0x18000000 0x18FFFFFF 16M Reserved
0x19000000 0x19FFFFFF 16M Reserved
0x1A000000 0x1AFFFFFF 16M Reserved
0x1B000000 0x1BFFFFFF 16M Reserved
0x1C000000 0x1CFFFFFF 16M CE3 (LCD)
0x1D000000 0x1DFFFFFF 16M CE2 (LAN)

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0x1E000000 0x1EFFFFFF 16M Reserved

0x1F000000 0x1FFFFFFF 16M CE0 (BROM)
3.3 CMU
ATJ2135 supports two oscillator inputs: 24M and 32.768K.

Clock Management Unit (CMU) can be driven by a 24M high oscillator and a 32.768k
low oscillator.
It provides:
¾ Four main clocks: MIPS core clock, DSP clock, AHB bus clock, APB bus clock;
¾ A low oscillator and a real time clock (RTC) module with alarm function.
ATJ2135 has a built-in Watch-Dog circuit.
Two 24bit timers are integrated in this IC. User may select either low or high oscillator
as the source.
3.3.1 CMU/HOSC Description
ATJ2135 system is driven mainly by four clocks.

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SDRA M
I/F
3 2 b it
R IS C
FLASH
I/F
DSP
C_CLK
U S B 2 .0
JPEG
S_CLK
COPROCESSOR
SD/MMC
D_CLK
I/F
D _C LK
CM U C _C LK DM A
S P E C IA L C L K S_CLK
P_CLK Interrupt
Control
Key scan
PM U
LR ADC
P_CLK
IIC (2 ) I/F
ADC
IrD a I/F
DA C+PA
G P IO
Figure 3: ATJ2135 Clock Diagram
The four main clocks and a special clock for module are managed by CMU. The CMU
framework is as follows. Core_Clk is used only in CMU module.

Ver 1.1 Page 27 2007-1-29
24M DSP_Pll D_CLK
32k
C_CLK Div
CORE_CLK (/1,/2,
Core /3,/4)
Pll
C_CLK
Special CLK
Generator
S_CLK Div
(/1,/2,
/3,/4)
U_CLK(480M)
SPECIAL CLK
DAC_CLK(24.576M)
S_CLK
...
P_CLK Div
DMA SCH4 CLK (/2.../16)
DMA SCH5 CLK
DMA
DMA SCH6 CLK
Special
Channle CLK
DMA SCH7 CLK P_CLK

SPECIAL
Channel
Clock
Generator
CMU Framework
Figure 4: CMU Framework
The DMA special channel clock configuration is in DMA blocks. The SPECIAL CLK
framework is as follows:

Ver 1.1 Page 28 2007-1-29
480M USB_C
HOSC_C
USB Pll LK
LK
HOSC_CL AUDIO_CL
AUDIO_PLL /1,/2,/3,
K Audio Pll /4,/6,/8,/12
K
24.576M
/22.5792M
SDRAM_C
S_CLK /DIV[1:0] LK
CORE_CL FLASH_CL
K /DIV[3:0] K
CORE_CL SD_CL
K /DIV[3:0] K
1/128
MHA_C
CORE_CLK /DIV[3:0] LK
MCA_C
CORE_CLK /DIV[3:0] LK
LOSC RTC_C
_CLK LK
Key_CL
K
The divider can be reused
Figure 5: SPECIAL CLK Framework

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3.3.2 RTC/LOSC/Watch Dog/Timers Block
ATJ2135 has a low frequency oscillator, which can choose a built-in source or an
external one. Meanwhile the chip also has RTC (Real Time Clock) with an alarm IRQ. The
alarm IRQ can wake up the system. For the purpose of protection, a watch dog circuit is also
available in the chip.
The block diagram is as follows. There are two Timers, namely, Timer0 and Timer1,
which can only count down. The clock of the Timer is APB.

Ver 1.1 Page 30 2007-1-29
Watch_Dog_RST
Watch_Dog
Timer
Watch_Dog_Clk_Sel
Watch Dog
32k
LOSC_Buildin
2HZ IRQ
÷16384
32.768k
LOSC_Ext
Date&Time
Count
Date&Time RTC
Reg
RTC Alarm IRQ

Date&Time
Date&Time Comparer
Alarm Reg
Timer0 IRQ
Timer0
Timer_Load
Timer
Timer1 IRQ
Timer1
Timer1_Load
Figure 6: Watch Dog/RTC/Timers Block Diagram
3.4 Interrupt Controller
Interrupt controller supports 32 interrupt sources. It can generate five outputs as

interrupt requests 0, 1, 2, 3 and 4. Each of these outputs is connected to CPU core; the
following table shows the interrupt controller’s connections to CPU.

Ver 1.1 Page 31 2007-1-29
Table 3 Interrupt Controller Connects to CPU

Interrupt Controller Requests CPU Interface CPU Interrupt Request
Request 0 SI_INT[0] IP2
3.4.1 Interrupt Controller Logic
The following shows the interrupt controller logic. Where applicable, the names in the
diagram correspond to bit n in the relative control register.
IC_PD[n]
Request 0
IC_MASK[n] Request 1
IC_CFG0[n] Request 2
IC_CFG1[n] Decoder
IC_CFG1[n]
Request 3
Request 4
Figure 7: Interrupt Controller Logic
3.4.2 Interrupt Source
Table 4 shows all the interrupt sources. Please refer to the respective peripheral
sections for the details on the interrupt sources.

Ver 1.1 Page 32 2007-1-29
Table 4: Interrupt Sources

Interrupt Number Sources Type
0 MCA High Level
1 Reserved High Level
2 SD/MMC High Level
3 MHA High Level
4 USB High Level
5 DSP High Level
7 PC (Performance Counter) High Level
8 2Hz/WatchDog High Level
9 TIMER1 High Level
10 TIMER0 High Level
11 RTC High Level
12 DMA High Level
13 Key High Level
14 External High Level
17 IIC2 High Level
18 IIC1 High Level
21 ADC High Level
22 DAC High Level
24 NAND High Level
26 YUV2RGB High Level

Ver 1.1 Page 33 2007-1-29
3.4.3 External Interrupt Sources
Interrupt controller has two external interrupt sources, which are input from SIRQ0/1
and can be configured as level or edge-triggered interrupt. When using external interrupt
source, the corresponding multi-function pad must be set as input mode. Figure 7 shows the
external interrupt 0 logic. External interrupt 1 has the similar logic.
EXT0_MASK
IC_PD
EXT0_TYPE[1] Decoder
EXT0_TYPE[0]
EXT0_PD
EXT0_IRQ
Figure 8: External Interrupt 0 Logic
3.5 PMU/DC-DC Converter
3.5.1 Description
ATJ2135 PMU includes:

z Two DC/DC Converters, both can work in buck & boost mode. The output voltages
are 3.1V and 1.6V, and programmable.
z Two regulators, whose output voltages are 3.1V and 1.6V, and programmable.
z A bias current generator.
z An Oscillator, outputs a 600KHz for DC-DC converters and a 32KHz for RTC.
z 6 bits low speed ADC, whose input range is from 0.7V to 1.5V, monitors batteries
voltage and battery.
z 4 bits low speed ADC, whose input range is form 0V to 3.1V, monitors remote
control signal.
z Battery charger, support Li+ battery.

Ver 1.1 Page 34 2007-1-29
z VCC voltage detector, VDD voltage detector, Power OK signal (PWROK) generator.
z A PFM - Modulated high voltage DC/DC converters for LED.
PIN in PMU
z DC-DC1 PIN: LX_VCC, IO_VCC.
z DC-DC2 PIN: LX_VDD, IO_VDD.
z High voltage regulator input and output PIN: DC5V, VCC
z Low voltage regulator output PIN: VDD
z Battery input/output PIN: BAT
z DC-DC NMOS ground: PGND
z ECL PFM DC/DC PIN: BL_LX, BL_FB
z External power PIN: VCCOUT
PMU Working Mode

z Li+ Battery, 2 Inductors
z Li+ Battery, 1 Inductor for VCC
z Li+ Battery, 1 Inductor for VDD
z Li+ Battery, No Inductor
z External power
3.5.2 DC/DC Converter and Regulator
There are two DC-DC converters and two Regulators in ATJ2135. Each DC-DC
converter can work in buck and boost mode for different input voltage. It also can work
in PFM or PWM modulation for different load current. An ECL PFM converter is built-in.
Table 5: DC/DC Converters & Regulators--Power Mode Set

DC5V>4.3V DC-DC1 DC-DC2 Regulator1 Regulator2 Description
N (No) Buck Buck N N Li+, 2 Inductors
Li+, 1 Inductor
N Buck N N From BAT
for VCC
Li+, 1 Inductor
N N Buck From BAT N
VDD
N N N From BAT From BAT Li+, No Inductor
From
Y(Yes) N N From VCC External power
DC5V

Ver 1.1 Page 35 2007-1-29
Table 6: ATJ2135 PMU Slave—Power Mode

DC5V>4 DC-DC DC-DC
Regulator1 Regulator2 BAT Description
3V 1 2
VCC/ External VCC
N N N N N
VDD External VDD
VCC/ External VCC
N N N N From VCC
VDD Internal VDD
Form Internal VCC
N N N N VDD
VDD External VDD
External VCC
N N N N N VCC
External VDD
External VCC
N N N N From VCC VCC
Internal VDD
From External VCC
N N N N VCC
VCC Internal VDD
From Internal VCC
N N N N VDD
VDD External VDD
External VCC
N N N N N VCC
External VDD
From External VCC
N N N N VCC
VCC Internal VDD
External VCC
N N N N From VCC VCC
Internal VDD
Internal VCC
Y N N From DC5V From VCC *
Internal VDD
Table 7: DC/DC Converters & Regulators—Loading Capacity

Block name Loading
3.3V, 200mA @ BAT=1.2/1.5/2.4/3.0V, boost mode
DC-DC1
3.3V, 200mA @ BAT=4.2V, buck mode
1.8V, 200mA @ BAT=1.2/1.5V, boost mode
DC-DC2
1.8V, 250mA @ BAT=2.4/3.0V, buck mode
ECL PFM 11---16V, 20---30mA
Regulator1 3.3V, 200mA @ BAT=4.2V
Regulator2 1.8V, 200mA @ BAT=4.2V

Ver 1.1 Page 36 2007-1-29
VBUS
OTG pump
USB PWR
DC5V
VR2
-
Charger 3.1V
VCCOK VCC
Vref
EN3
BAT
L_VCC
VIO1
LX1 Mode MD_DC_VCC

MAX(VCC,BAT)
DC_VCC
En EN_DC_VCC
Gate
driver
BAT VCC
DIV Low frequency

CK800K OSC Vref Vref
VIO2 L_VDD
EN2
EN1
Mode MD_DC_VDD VDD
LX2
DC_VDD
En EN_DC_VDD
Gate
driver
ECL_FB Bypass mode @ PREOK=”0"
VCC LDO AVCC
DC_ECL
ECL_NDR En EN_DC_ECL
Gate
driver
AVCC LDO AVDD
Temp
6 bits
ADC
VBAT
VCC > 2.1V

VCCOK
PWRM
rtc_pwr Debouce
Vddgood PWROK
vccgood & delay
Linein
4 bits
ADC
PWRM[1:0]=1*
/ L_VCC EN3
PWRM[1:0]=01/1* PWRM[1:0]=00 /UVLO
/ L_VDD EN1 EN2
/ UVLO / L_VDD
UVLO UVLO
Charge_en
/ VDDOK BE6
L_VCC EN_DC_VCC PWRM[1:0]=1* MD_DC_VCC “1” LIION

“1”=boost PWRM[1:0]=1* Kind “0” NIMH/Alkaline
L_VDD EN_DC_VDD
PWRM[1:0]=00 MD_DC_VDD “1” Two battery
PWRM[1:0]=01 Count
“1”=boost “0” One battery
Figure 9: DC/DC Converters & Regulator--Block Map

Ver 1.1 Page 37 2007-1-29
3.5.3 Battery Monitor and Temperature Monitor
There is a low speed 6 bits ADC in ATJ2135 for Battery Monitor and Temperature
Monitor. Temperature sensor is a built-in Li+ battery with one end connected to the
battery’s negative end.
Table 8: Relationship between Battery Type & ADC Input Range

Battery type Internal Voltage divider for battery Input range
1 Li+ 1/3 1.0-1.4
3.5.4 Remote Control ADC
There is a low speed 4 bits ADC in ATJ2135 for remote control. The input rage is from 0
to AVCC.
3.5.5 Charger Circuits
Constant current charge

Default is 200mA; software can set control bit to change it.
Constant voltage charge for Li+ battery.
Battery voltage
Li-ION’s voltage range is from 2.9V to 4.2V
Charge Style
Linear charger for Li+ battery;
UVLO changes from low go high at 4.3V, high go low at 3.75V.
3.5.6 PWM Back-light IC Control
In ATJ2135 PMU, a programmable PWM signal generator is integrated for PWM Back-light IC.
Application diagram is as follow:

Ver 1.1 Page 38 2007-1-29
PWM Signal
EN
LCD Backlight Driver

VDD
LED1
LED2
LED3
LED4
Figure 10 PWM Back-light IC Application diagram

The built-in block diagram is as follow. There are 8 clock source of the PWM can be
configured.
The pwm signal can be programmed up to 32-level duty. All together, 8 frequencies PWM
signal can be output. They are 1k, 500, 250, 125, 94k, 47k, 23k, 12k.These frequencies
can meet most PWM back light IC application.
32K PWM Duty（ 0/32---31/32）
16K PWM Duty（ 0/32---31/32）
32K 0 8K
Bit（0-4）
4K
3M
1.5M
DIV /8 1
24M 3M 750K
375K PWM Duty （ 0/32---31/32）
Figure 11 PWM Block diagram

Ver 1.1 Page 39 2007-1-29
3.5.7 Signal Description
z Power mode configuration PIN: PWRM [1:0].

z DC-DC1 PIN: LX_VCC, IO_VCC.
z DC-DC2 PIN: LX_VDD, IO_VDD.
z High voltage regulator input and output PIN: DC5V, VCC
z Low voltage regulator input and output PIN: VDD
z Battery input/output PIN: BAT
z Temperature monitor input PIN: TEMP
z DC-DC NMOS ground: PGND
z BL PFM DC/DC PIN: BL_NDR, BL_FB
3.6 32-BIT RISC Core
The core follows MIPS 4KEc SPEC. This chapter describes the features of RISC Core
which are not implemented or different from MIPS 4KEc SPEC.
3.6.1 Coprocessor 0
In MIPS architecture, CP0 is responsible for the virtual-to-physical address translation

and cache protocols, the exception control system, the processor’s diagnostics capability,
the operating modes (kernel, user and debug) and whether interrupts are enabled or
disabled.
3.6.2 Exceptions
The chip implements MIPS 4KEc compliant exception scheme. The scheme consists of
the exception vector entry points in both KSEG0 and KSEG1, and the exception code
(ExcCode) encodings the nature of the exception. The exception causes include interrupts,
debug, execution error conditions, control conditions, and MMU conditions.
The chip implements a MIPS 4KEc compliant interrupt mechanism in which eight
interrupt sources are presented to the core. Each interrupt source individually is able to
either enable or disable the core from detecting the interrupt. Interrupts are generated by
software, integrated interrupt controller, and timer, as noted in Table 9.
Table 9: CPU Interrupt Sources

Interrupt Sources Interrupt request Interrupt Mask

Ver 1.1 Page 40 2007-1-29
Software Interrupt 0 IP0 IM0

Software Interrupt 1 IP1 IM1
Interrupt Controller IP2~IP6 IM2~IM6
Timer IP7 IM7
3.6.3 Performance Counters
Performance counters are typically configurable to allow the counting of a variety of

processor events. The counters can be read and configured by software. Monitoring software
can periodically read the registers or can be configured to signal an interrupt when the
counter overflows. A system designer can use performance counters to profile software and
hardware performance.
On this chip two performance counters are configurable to count one or two MIPS 4KEc
core events, which are fetched from Performance Monitoring (PM) interface or EC bus
interface. Therefore the relative frequency of different events can be compared to a large
sample set, for example, the ratio of D-cache hits to misses, or the ratio of micro TLB misses
to instructions completed. Figure 9 shows the performance counters block diagram.
SI_EXL
SI_ERL PC_IRQ
MIPS Performance Interrupt
4KEc EJ_DebugM Counters Controller
PM interface
Peripheral Bus
Figure 12: Performance Counters Block Diagram
3.6.4 Other Reference
Please refer to MIPS32. 4KEc. Processor Core Datasheet: MD00111-2B-4KEC-DTS-02.00.pdf

Ver 1.1 Page 41 2007-1-29
3.7 SDRAM Interface
SDRAM interface can support both SDRAM (Synchronous DRAM) and Mobile SDRAM. It
has the following features:
¾ Supports SDRAM and Mobile SDRAM
¾ Separate I/O power supply supporting 1.8V, 2.5V and 3.3V
¾ Supports 3.3V SDRAM of clock frequency up to PC100
¾ Supports 3.3V SDRAM of capacity up to 512Mbits
¾ Supports 3.3V/2.5V/1.8V Mobile SDRAM of Clock frequency up to PC100
¾ Supports 3.3V/2.5V/1.8V Mobile SDRAM of capacity up to 512Mbits
¾ Fourteen address signals including two bank addresses
¾ Access to SDRAM in Byte, Half a Word are supported
¾ Supports up to 22 address bits, 12 for row address, and 10 for column address
¾ Three clock sources to be chosen for different application
¾ Priority of transferring through special channel or AHB bus is programmable
¾ Supports random read or write operation
3.7.1 SDRAM Signals
Table 10: SDRAM Signals

Symbol Type Function
Clock output: CK is clock output.
CK, CK# O
All outputs are sampled on the positive edge of CLK.
CKE O Clock enable output
CS# O Chip select output
RAS#,CAS#,WE# O Command outputs
DM (UDQM)
O Output data mask
(LDQM)
BA0~BA1 O Bank address outputs
A0~A12 O Address outputs
DQ I/O Data input/ output: bi-directional data bus.
NC No connect: No internal electrical connection is present.
DQ power supply:
VDDQ PWR For SDRAM, voltage: 3.3V +/- 0.3V
For Mobile SDRAM, voltage: 3.3V or 2.5V or 1.8v
VSSQ PWR DQ ground
VDD PWR Power supply:

Ver 1.1 Page 42 2007-1-29
For SDRAM, voltage: 3.3V +/- 0.3V

For mobile SDRAM, voltage: 3.3V or 2.5V or 1.8v
VSS PWR Ground
Note:
1: I for Input
2: O for Output
3: PWR for Power Supply Signal
4: Typical logic high voltage of all input or output depends on the value of SV bits in
SDRAMPARA register. If SV bits are set to be 1, select 3.3v, and 10 for 2.5v, 01 for 1.8v.
3.8 SRAM on Chip
ATJ2135 has 96k-byte SRAM which can map 24k*32bit (for MIPS) or 32k*24bit (for
DSP). It can be operated in byte and possesses BIST test function.
3.9 BROM
Built-in boot ROM in ATJ2135. MIPS can be selected to boot up from Boot ROM.
3.10 DMA/Bus Arbiter
ATJ2135 DMA controller contains 8 tasks, which are divided into two types, bus DMA
and special channel DMA. System bus adopts the subset of AMBA bus protocol. The bus
topology is as follows:

Ver 1.1 Page 43 2007-1-29
DMA Bus Req priority

Arbiter
HAD HAD
DR DR Drqx
HWDA HWDA
Slave #1 Dackx
MIPS TA TA double port
HRDAT HRDAT
A A （below）
Addr Mux
ch1 HWdata
ch1 HRdata
DMA Bus Req priority
HAD HAD
DR Hwdata Mux DR Drqx
Drq0 HWDA HWDA Slave Dackx
Dack0 DMA TA TA #2
Drq1 HRDAT HRDAT
Dack1 A A double port
...
ch2 HWdata
ch2 HRdata
...
...
Hrdata Mux
ch1 HWdata
ch2 HWdata
ch1 HRdata
ch2 HRdata
...
HAD
Standard ahb with DR
Slave
HWDA
double port slaves TA
HRDAT
#3
A single port
Figure 13: Bus Topology
There are six slaves with double ports, the system bus and DMA special port. They are:
SDRAM, DSPMEM, NAND, SD, USB and YUV.
Other slaves are only with system bus, or APB bus. They are: DAC, ADC.
3.10.1 DMA Architecture
DMA controller in ATJ2135 is a special master with four independent special channels
to high-speed AHB slaves. Since these six special slaves have two access ports, the slave has
to decide which port enjoys higher priority. A register in the slave to set which port enjoys

Ver 1.1 Page 44 2007-1-29
higher priority.
Each DMA task can be set as priority.
DMA0~DMA3 can be transferred through bus only, DMA4~DMA7 can be transferred
only through the special channel.
Figure 14: DMA Architecture

The slave perhaps has two DRQ and DACK.
Some slave devices have address bus, such as SDRAMIF, SRAMOC while others do not
have one, such as FLASH port. However, the control register can be accessed through AHB
bus, no matter through the special channel access or not.
3.10.2 DMA Bus Timing
Figure 15: DMA Basic Bus Timing

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Figure 16: DMA Bus Timing with Wait States
Figure 17: DMA Bus Burst Timing
3.11 24-BIT DSP Core
3.11.1 Features
DSP Core has the following features:

¾ Read ADC data directly
¾ Write some DAC/ADC control register
¾ With Byte selection function
¾ 24bit instruction and data bus
¾ 1 instruction per machine cycle
¾ Maximum 96 (=12x8) Million Instructions Per Second (MIPS) and extra mass
production margin
¾ One 56bit MAC result register including extension byte
¾ Parallel 24 x 24 bits multiply-accumulate in 1 instruction cycle
¾ Fractional and integer arithmetic with rounding mode
¾ Hardware nested DO loops up to 4 layers
¾ 16K x 24 bits of Access Program Memory space (IPM)
¾ 16K x 24 bits of Access Data Memory space (IDM)
¾ 8bit Parallel Host Interface Port
¾ Independent Arithmetic/Logic (ALU), Multiplier/Accumulator (MAC) and Barrel
Shifter (BASH) Computational Units

Ver 1.1 Page 46 2007-1-29
¾ Two Independent Data Address Generators (DAGS)

¾ Automatic Booting of Internal Program Memory through Host Interface Port (HIP)
¾ Stand-alone ROM Execution (Optional)
¾ Built-in Debug Support Unit (DSU)
¾ Full static design for operating frequencies up to 96MIPS or down to 0 Hz
¾ On-chip Harvard architecture permitting simultaneous accessed to PM and DM
3.11.2 Block Diagram
Data Data
Address Address Program
Generator Generator Sequencer
#2 #2
14 PMA BUS
14 DMA BUS
24 PMD BUS
24 DMD BUS
Input Regs Input Regs Input Regs
ALU MAC Shifter
Output Regs Output Regs Output Regs
R BUS 24
Figure 18: 24-Bit DSP Core Block Diagram

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3.12 Media Hardware Accelerator (MHA)
3.12.1 Description
MHA (Media Hardware Accelerator) is a coprocessor for image or video processing. It

supports the following processing: DCT (Discrete Cosine Transform), IDCT (Inverse DCT), Q
(Quantization), IQ (Inverse Q), IDRO (Input Data Reorder), ODRO (Output Data Reorder), LS
(Level Shift) and ILS (Inverse Level Shift). Table 11 shows all the processing and their
applications.
Table 11: Functions and Application of MHA

Applications JPEG/ JPEG/
MPEG4
Move Move MPEG4 H.263
/H2.63
Processing JPEG JPEG Decoder Decoder
Encoder
Encoder Decoder
DCT Y - Y - -
IDCT - Y - Y Y
JPEG Q S - - - -
JPEG IQ - S - - -
H.263 IQ - - - S S
MPEG4 IQ - - - S -
IDRO - S - - -
ODRO S - - - -
LS S - - - -
ILS - S - - -
Note: Y is necessary processing; S is optional processing; - is unused processing.
MHA_INT Memo
MCU MHA
ry
......
Bus
Figure 19: How to Use MHA in a System

Ver 1.1 Page 48 2007-1-29
3.12.2 Features
¾ When MHA is busy, RISC can access to the other blocks.

¾ MHA has dual multipliers.
¾ MHA data buffer can be accessed with DMA, without the special channel.
¾ MHA can be controlled by MCU with IO registers, and its status can read by MCU at
any time.
¾ MHA will send interrupt signal to MCU when one or more blocks accomplish the
processing. The block number can be set as a maximum of 8.
¾ MHA supports 8bit per sample mode and 9bit per sample mode processing. For
8bit mode, the valid width of DCT input data is 8bit and output data is 11bit, the
valid width of IDCT input data is 11bit and output data is 8bit. For 9bit mode, the
valid width of DCT input data is 9bit and output data is 12bit, the valid width of IDCT
input data is 12bit and output is 9bit.
¾ MHA has two modes for input data and output data: normal order mode and “Z”
scanning mode.
¾ MHA can enable or disable level shift or inverse level shift processing.
¾ MHA supports optional Q and IQ processing: JPEG Q and IQ, H.263 IQ, MPEG4 IQ. In
every Q or IQ processing, it can be chosen from one of 4 Q tables, which is stored in
normal order mode.
¾ Division is replaced by multiplication to reduce the hardware area; since its result
equals the dividend multiply the divisor’s reciprocal.
¾ There are two 512x16bits buffer blocks within the MHA. They are used in turn by IO
registers. When one block is used for data processing, the other one can be used
for data transfers.
¾ The MHA can accomplish one block processing within 3us, which can satisfy the
MJPEG (4:2:0) encoding or decoding with 640x480 30fps or 720x576 25fp.
¾ MHA data bus is 32bit width, which contains two data of 16bit.

Ver 1.1 Page 49 2007-1-29
B1/B2 RAM
Data Input/Output SP RAM

Scanning/Inverse Scanning
LS/ILS Z Scan
Saturation Sequence
Bus
Q Table 0 DCT/IDCT
Multiplier 2
Q Table 1 Rows/ Multiplier 1

Q/IQ
Q Table 2 Columns
Q Table 3 Transform ALU
Controller
Figure 20: MHA Block Diagram
3.13 Motion Compensation Accelerator (MCA)
3.13.1 Description
MCA (Motion Compensation Accelerator) is applied to the interpolation process of the

motion compensation in inter block decoding process of WMV, which is required by
progressive P frame and B frame decoding. It accepts various types of pixel blocks from the
reference frame in progressive mode to produce 8x8 or 16x16 interpolated block based on
WMV interpolation technology. The following figure indicates how to use MCA in a system.

Ver 1.1 Page 50 2007-1-29
MCA_IP
MCU MCA Memory
.....
AHB
Figure 21: Application Example of MCA
3.13.2 Features
¾ Supports Interpolations of blocks in both P frame and B frame in progressive mode

¾ Supports 8x8 and 16x16 interpolated block output
¾ Support Bilinear and bicubic filter
¾ Support Half-pel and quarter-pel precisions
¾ Two buffer blocks with 38x20x8 bits respectively, and the size of read and write is
word.
¾ SPRAM with 16x19x14 bits for temporary data in two-dimension interpolation
¾ In P frame and B frame with backward and forward prediction mode, about one
clock is needed for generating one subpixel with one-dimension bilinear and bicubic
interpolation.
¾ In B frame with direct and interpolated prediction mode, about two clocks is
needed for generating one subpixel with one-dimension bilinear and bicubic
interpolation.
¾ In P frame and B frame with backward and forward prediction mode, less than 228
clocks is needed for two-dimension bicubic interpolation of 8x8 block, and less than
700 clocks is needed for two-dimension bicubic interpolation of 16x16 block.
¾ In B frame with direct and interpolated prediction mode, the number of clock is
about twice more than the number in P frame for two-dimension bicubic
interpolation of 8x8 block and 16x16 respectively.
MCA consists of controller, interpolation processor, rounding & saturation, SPRAM and
B1/B2 RAM, as in Figure 19.

Ver 1.1 Page 51 2007-1-29
MCA
Rounding &
Saturateion
SP RAM
Controller
MCA_IP Interpolation
Process
B1/B2 RAM
A H B
Figure 22: MCA Block Diagram
3.14 NAND FLASH Interface
The general purpose of NAND FLASH Interface controller is a State Machine

configurable interface to external NAND FLASH/SMC. The highly configurable and flexible
interface can be used in most readily available NAND FLASH devices. The FLASH data bus
can be configured to be 8bit or 16bit access.
FLASH State Machine provides automatic timing control for data read and write through
signal line. The interface automatically maintains proper CLE, ALE and CE setup and
properly holds up read/write DMA. The Controller will transfer the data between Int-RAM
memory and ext-FLASH memory by either MCU or DMA.
Controller Module can monitor the interval transitions of the NAND FLASH device’s
Ready/Busy signal. It includes an interrupt that can monitor the rising edge of busy signal
and can be set to generate a timeout interrupt if the NAND FLASH device is hung up.
The controller can support SLC/MLC NAND FLASH as well as Hamming ECC and
Reed-Solomon ECC.

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3.15 SD/MMC Interface
SD/MMC Interface is based on MMC card SPEC 4.1 and is compatible with SD memory
card physical layer SPEC version 1.01. Multimedia Card/SD is a serial input/output interface
to send command and receive data. Its features are as follows:
1. Supports SD memory card, MMC memory card.
2. Supports 1bit, 4bit, 8bit, bus mode.
3. Clock max rate up to 52MHz.
4. Data transfer FIFO and DMA control.
5. Read /Write CRC Status Hardware checked automatically.
3.16 YUV2RGB Interface
The module performs the image data transfer from frame buffer to LCD panel. It
accelerates the frame data displayed by hardware operation. It is optional and mainly used
in movie decoding. The processes include:
1. Up-sampling from YUV 422 to YUV 444
2. Change from YUV / YCbCr to RGB (8,8,8) format
YCbCr to RGB:
R = Y + 1.402 *(Cr-128)
G = Y - 0.34414*(Cb-128) - 0.71414*(Cr-128)
B = Y + 1.772 *(Cb-128)
YUV to RGB:
R = Y + 1.14V
G = Y - 0.39U - 0.58V
B = Y + 2.03U
3. Cut down RGB (8, 8, 8) to the RGB format required in LCD Panel.
The following figure shows the YUV2RGB block diagram.

Ver 1.1 Page 53 2007-1-29
YUV to RGB Decoder Module
YUV DRQ IRQ
YCbCr AHB Bus

16 级 RGB(5,6,5)
422 YUV RGB
DMA FIFO RGB(6,6,6)
LCD Panel
Buffer 4,4,4 8,8,8
RGB(8,8,8)
LCD Interface PIN

AHB Bus
RGB DMA
Buffer
SRAM
Interface
DMA
Figure 23: YUV to RGB Decoder Module Block Diagram
3.17 USB2.0 SIE
3.17.1 General Description
AS 2135 USB2.0 device controller is fully compliant with the Universal Serial Bus 2.0
specification. This high performance USB2.0 device controller integrates USB transceiver,
SIE, and provides multifarious interfaces for generic MCU, RAM, ROM and DMA controller. So
it is suitable for a variety of peripherals, such as: scanners, printers, mass storage devices,
and digital cameras. It is designed to be a cost-effective USB total solution.
3.17.2 Features
Fully compliant with USB Specification 2.0.

UTMI+ level2 Transceiver Macrocell Interface.
Supports Session Request Protocol (SRP).
Supports full-speed or high-speed in peripheral mode.
Supports 4 IN endpoint and 4 OUT endpoint except endpoint0.
Supports high-speed high-bandwidth Isochronous and Interrupt transfer.
Partially configurable endpoint buffer size, endpoint type and single, double triple
or quad buffering.

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Integrated synchronous RAM as endpoint FIFO.

Supports suspend, resume and power managements function.
Supports remote wakeup.
32bit AHB bus interface to up.
32bit AHB external DMA master access.
3.18 I2C (2) Interface
ATJ2135 has two I2C Interfaces, which can be configured as either master or slave
device. In master mode, it generates the clock (I2C_SCL) and initiates the transactions on
the data line (I2C_SDA). The data on the I2C bus is byte-oriented. Multi-Master mode cannot
support 10bit address and hi-speed mode. See the I2C_Bus_Specification_1995 for the
details.
Pull-up resistors are necessary on both of the I2C lines as all of the I2C drivers are open
drain. External 2k-Ohm resisters are typically used to pull the signals up to VCC.
3.19 UART Interface
ATJ2135 contains UART interface and it has the following features:

¾ 5-8 Data Bits and LSB first in transmitting and receiving.
¾ 1-2 stop bits
¾ Even, Odd, or No Parity
¾ 8-byte transmit and receive FIFO
¾ Interrupts for receiving FIFO half full and not empty
¾ Interrupts for transmit FIFO empty and half empty
¾ Capable of speeding up to 1.5Mbs to enable the connections with Bluetooth and

other peripherals.
¾ Has Infrared Data Association (IrDA) inputs and outputs (Optional)
Description of RTS/CTS hardware auto-control flow:

When the receiver FIFO level reaches the trigger level of 6 bytes, RTS- will be pulled up
to invalid state. The sending UART may send an additional byte after the trigger level is
reached (in case the sending UART has another byte to send) because it may not recognize
the invalid state of RTS- until it has begun sending the additional byte. RTS- is automatically

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reasserted once the receiver FIFO is empty by reading the receiver buffer register. The
reassertion signals the sending UART to continue transmitting data.
The transmitter checks CTS- before sending the next data byte. When CTS- is active, the
transmitter sends the next byte. To stop the transmitter from sending the following byte,
CTS- must be released before the middle of the last stop the bit that is currently being sent.
Figure 24: RTS/CTS Autoflow Control Timing
3.20 IR Interface
IrDA is a standard defined by IrDA consortium (Infrared Data Association). It specifies

the way to transfer data via infrared radiation wireless. The IrDA specifications include
standards for both the physical devices and the protocols used to communicate with each
other. IrDA devices conform to standards IrDA 1.0 and 1.1.
Speed for IrDA v1.0 ranges from 2400bps to 115200bps. Pulse modulation with 3/16
of the length of the original duration of a bit is used. Data format is the same as a serial port
asynchronously transmitted word, with a start bit at the beginning.
IrDA v1.1 defines the speed 0.576 and 1.152 Mbps for MIR mode and 4Mbps for FIR
mode with 1/4 mark-to-space ratio.
For MIR mode, the basic unit (packet) is transmitted synchronously, with a starting
sequence at the beginning. A packet consists of two start words followed by a target address
(IrDA devices are assigned numbers by the means of IrDA protocol, so they are able to
unambiguously identify themselves), data, CRC-16 and a stop word.

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Figure 25: Packet for MIR Mode
For FIR mode, two bits are encoded in a pulse within one of the four possible positions
in time. Therefore the information is carried by the pulse position, instead of pulse existence
as in previous modulations. With the bit speed of 4Mbps, the transmitter flashes at 2MHZ
rate. However, unlike 0.576 and 1.152 Mbps, 4Mbps packets use CRC-32 correction code.
Figure 26: Packet for FIR Mode
ATJ2135 supports SIR, MIR and FIR mode and has 16bit and 32bit hardware CRC
generation and detection.
The simultaneous application of UART2 and IR is not allowed since they have some
common register.
UART/IR BaudRate (baud rate) must be selected by setting the UART2_CLK_CTL
Register of the CMU.
Supports IrDA mode.
Table 12: IR Interface Modes

Mode Speed CLK setting Compliance
SIR 2.4 to 115.2kbps BaudRate*16=CORE_CLK IrDA 1.0
MIR 0.576 and 1.152 Mbps BaudRate*8=CORE_CLK IrDA 1.1 with error detection
FIR 4 Mbps 24M=CORE_CLK IrDA 1.1 with error detection

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3.21 Key Scan
The Key Scan supports parallel mode and serial mode. The max scan matrix is 16x8.
The key scan data FIFO is 4 levels (4*32).
In parallel mode, the max scan matrix is 3x3 and is showed as follows:
KEYI KEYI KEYI

0 1 2
KEYO b00 b01 b02

0
KEYO b10 b11 b12

1
KEYO b20 b21 b22

2
Figure 27: Max Key Scan Matrix in Parallel Mode
In the serial mode, one or more external shift register chips should be used. The
following is an 8x8 scan matrix.

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KEYO0 KEYO1 KEYO2 KEYO3 KEYO4 KEYO5 KEYO6 KEYO7
KEYSO D Q D Q D Q D Q D Q D Q D Q D Q
KEYSCLK CLK CLK CLK CLK CLK CLK CLK CLK
KEYI0 KEYI1 KEYI2 KEYI3 KEYI4 KEYI5 KEYI6 KEYI7
b00 b01 b02 b03 b04 b05 b06 b07

KEYO0
b10 b11 b12 b13 b14 b15 b16 b17

KEYO1
b20 b21 b22 b23 b24 b25 b26 b27

KEYO2
b30 b31 b32 b33 b34 b35 b36 b37

KEYO3
b00 b01 b02 b03 b04 b05 b06 b07

KEYO4
b10 b11 b12 b13 b14 b15 b16 b17

KEYO5
b20 b21 b22 b23 b24 b25 b26 b27

KEYO6
b30 b31 b32 b33 b34 b35 b36 b37

KEYO7
Figure 28: 8*8 Key Scan Matrix in Serial Mode
Note: KEYSO is PIN KEYO1, KEYSCLK is PIN KEYO0.

One line Scan timing: the line 7

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Figure 29: One Line Scan Timing
The whole timing is as follows:
Figure 30: The Whole Key Scan Timing
In serial mode, two external 8bit shift registers can be used at last, that is to say, the
maximum scan matrix is 8x16.

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3.22 DAC and Headphone Driver
ATJ2135’s internal DAC is an on-chip Sigma-Delta Modulator of which a high

performance DAC is composed. DAC interface supports 8-level playback FIFO (16 X 24bit
PCM data for L/R channel and variable sample rates, such as
48K/44.1K/32K/24K/22.05K/16K/12K/11.025K/8KHz).
Vol Control
AudioOutR
Modulator Three order AudioOutL

FIFO low-pass filter
Figure 31: DAC Block Diagram
3.22.1 Framework
DSP ports include data port, RW control, IRQ.

ADC module sends the FIFO DRQ to DSP as DSP_IRQ.
DAC module sends the FIFO DRQ to DSP as DSP_IRQ.

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DAC_Fifo_In_Sel
ADC_In DAC_Out_Sel
DAC_Fifo_APB_E
n
FIFO
PCM_In 24*16 DAC_ DAC_
APB DAC_Fifo_DSP_E
D A
n
ADC_In
ADC_Fifo_In_Sel
ADC_Fifo_APB_E
n
ADC_ ADC_ FIFO ADC_Fifo_DSP_E
A D 24*16 n
PCM_In
PCM_In FIFO APB

16*8
ADC_In
PCM_Fifo_In_Sel
FIFO
APB PCM_Out
16*8
Figure 32: DAC Framework

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ADDA Analog diagram

MIC_En
ADC_Mux_Sel ADC_E
EN n
MIC_Gai
MICI n ADC_Gai EN
N n Sigmal
MU
X delta
modulator
FM_E
n
ENFM_Gai
FMINL/ n
R
MIC_Mix_E
FM_Mix_E
n
n
DAC_E
n
DAC_Mute
EN
sigmal
AoutL/R + delta
EN DAC
DAC_Volue
DAC_Analog_En
Figure 33: ADDA Analog Diagram
3.23 ADC
Internal microphone amplifier has gain for recording. VMIC pin is the power supply
(2.57V) for microphone.
Audio ADC is a 21bit Sigma-delta Analog-to-digital Converter. Its input source can be
selected from MIC amplifier or external FM, and it has two FIFO.

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Fs supports 48K/44.1K/32K/24K/22.05K/16K/12K/11.025K/8KHz.

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4 Electrical Characteristics
4.1 Absolute Maximum Ratings
Table 13: Absolute Maximum Ratings
Parameter Symbol Min Max Unit

VDD -0.3 VDD+0.3 V
Supply voltage
VCC -0.3 VCC+0.3 V
VIH 0.9VCC VCC+0.3 V

Input voltage
VIL -0.3 0.1VCC V
Junction Temperature Tj 150 ℃
Lead Temperature (Soldering, 10 sec) 260 ℃
Storage temperature Tstg -65 150 ℃

Note:
1. TO = 25℃（Operating Temperature）
2. Do not short-circuit two or more output pins simultaneously.
3. Even if one of the above parameters exceeds the absolute maximum ratings momentarily,
the quality of the product may be degraded. The absolute maximum ratings, therefore,
specify the value exceeding, which the product may be physically damaged. Use the product
well within these ratings.
4. The specifications and conditions shown in the DC and AC characteristics are the ranges
for normal operation and the quality assurance of the product.
4.2 Capacitance
Table 14: Capacitance
Parameter Symbol Condition MIN. MAX. Unit
Input capacitance CI fC = 1 MHz 20 pF

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I/O capacitance CIO Unmeasured pins returned to 0 V 20 pF
Note: TO = 25℃, VCC = 0 V.
4.3 DC Characteristics
Table 15: DC Characteristics
Parameter Symbol Condition MIN. TYP. MAX. Unit

High-level output voltage VOH IOH = -2 mA 2.4 V
Low-level output voltage VOL IOL = 2 mA 0.4 V
High-level input voltage VIH 0.9VCC VCC+0.3 V
Low-level input voltage VIL -0.3 0.1VCC V
Input leakage current ILI VCC = 3.6 V, VI = VCC, 0 V +10 uA
Output leakage current ILO VCC = 3.6 V, VI = VCC, 0 V +5 uA
Notes:
1. TA = 0 to +70℃, VDD = 1.8 V, VCC = 3.1 V
2. IVDD is a total power supply current for the 2.5 V power supply. IVDD is applied to the
LOGIC and PLL and OSC block.
3. IVCC is a total power supply current for the 3.0 V power supply. IVCC is applied to the USB,
IO, TP, and AD block.
4.4 PMU
DC/DC Operating Voltages: When Li-ion mode: DC/DC operates with battery as low as
2.8V.
Table 16: System Standby Dissipation

Parameter MIN (uA) Typical (uA) MAX (uA)
IVCC+IAVCC 100 110
IVDD 40 55
IAVDD 3.5 4.5
1.01
RTCVDD
0.32

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IUVCC 150 175

Note1: When ex osc is enabled.
Note2: When ex osc is disabled.
Table 17: Vccout Load Capability

Parameter MIN (mA) Typical (mA) MAX (mA)
IVCCOUT 22 25
Note: the parameter is tested when VCC is 3.1V and VCCOUT is 95%VCC.
Table 18: LRADC Precision

ERROR MIN TYPICAL MAX Unit
Parameter
TEMP_ADC - - 50 mV
REMO_ADC - - 20 mV
1AAA - - 20 mV
BAT_ADC 2AAA - - 40 mV
Li-ION - - 50 mV
Figure 34: Efficiency Curve for Backlight Step Up Circuit
77
76
75
74
73
72
Series 1
71
70
69
68
67
66
10 20 30 40 60

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It is the ordinary TDK47uH inductor that has been applied in backlight circuit, and the diode
is RB491D Schottky.
Figure 35: DC/DC Efficiency Curve 1

(Please refer to the corresponding schematic diagram of reference circuit for DC/DC circuit
components)
Li-ION mode: VBAT=3.6V
Relation between VDD Load Current and the Efficiency
90
85
80
Efficiency（%）
75
70
65
60
55
50
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270
Ivdd（mA）

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Figure 36: DC/DC Efficiency Curve 2
Relation between VCC Load Current and the Efficiency
100
95
90
85
Efficiency（%）
80
75
70
65
60
55
50
0 10 20 30 40 50 60 70 80 90 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VCC Current（mA）
Figure 37: Charging Curve—Voltage Characteristics Curve

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Figure 38: Charging Curve—Current Characteristics Curve
Note: the above results is measured when charging 270mAh Li-ion battery at the charging
current of 200mA.
Table 19: LDO Load Capacity

IVCC IVDD
LDO Input
MIN (mA) Typical (mA) MAX (mA) MIN (mA) Typical (mA) MAX (mA)
2.5V 220 240
3.1V 350 400
3.6V 320 350 350 400
4.5V 350 380
5.0V 420 480
Note: the parameter is tested when VOUT is 95%VIN.
4.5 AC Characteristics
(To = 0 to +70℃, VDD = 2 to 3 V, VCC = 2.7 to 3.6 V)

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4.5.1 AC Test Input Waveform
Figure 39: AC Test Input Waveform
4.5.2 AC Test Output Measuring Points
Figure 40: AC Test Output Measuring Points
4.6 Reset Parameter
Table 20: Reset Parameter

Reset input low-level width tWRSL RESET# pin 230 us
Figure 41: Reset Timing
4.7 Initialization Parameter
Table 21: Initialization Parameter

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Data sampling time

tSS 120 us
(from RESET# )
Output delay time (from RESET# ) tOD 120 us
Figure 42: Initialization Timing
4.8 GPIO Interface Parameter
Table 22: GPIO Interface Parameter
Parameter Symbol Condition MIN. TYPE MAX. Unit
GPIO output rise time tGPRISE 3 40 ns

GPIO output fall time tGPFALL 3 40 ns
Figure 43: GPIO Interface -- Output time
Table 23: GPIO Drive

GPIO_X IoH IoL GPIO_X IoH IoL
A26 10.7mA 11.5mA B31 2.3mA
A25 10.7mA 11.5mA B29 20.1mA 18.7mA
A24 10.7mA 11.5mA B22 2.3mA 2.4mA
A23 10.7mA 11.5mA
A22 10.7mA 11.5mA

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A21 10.7mA 11.5mA

A20 10.7mA 11.5mA
A19 10.7mA 11.5mA
A18 10.7mA 11.5mA
A17 11.6mA 11.3mA
A16 11.6mA 11.3mA
A13 2.3mA 2.4mA
A12 2.3mA 2.4mA
A10 2.3mA 2.4mA
A9 2.3mA 2.4mA
A8 2.3mA 2.4mA
A7 2.3mA 2.4mA
A6 2.3mA 2.4mA
A2 11.6mA 11.3mA
A1 11.6mA 11.3mA
A0 11.6mA 11.3mA
4.9 Ordinary ROM Parameter
Table 24: Ordinary ROM Parameter
Data access time (from address)Note tACC HOSC=24MHz 102 ns
Data access time (from CEx# )Note tCE HOSC=24MHz 82 ns
Data input setup time tDS HOSC=24MHz 0 ns
Data input hold time tDH HOSC=24MHz 0 ns
Figure 44: Ordinary ROM Parameter

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4.10 External System Bus Parameter
Figure 45: External System Bus Timing
Table 25: External System Bus Parameter
tXAS Memory Read 25 ns

Address setup time (to command signal)Note 1, 2
tXAS Memory Write 10 ns

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Address hold time (from command signal)Note 1, 2 tXAH 5 ns
Data output setup time (to command signal)Note 1 tWXDS 20 ns
Data output hold time(from command signal)Note 1 tWXDH 10 ns
Data input setup time (to command signal)Note 1 tRXDS 20 ns
Data input hold time (from command signal)Note 1 tRXDH 10 ns
Notes: 1. MRD#, MWR# are called the command signals for the External System Bus Interface.
2. T (ns) = 1/ fMCUCLK
4.11 Serial Interface Parameter UART
Table 26: Serial Interface Parameter UART
Pre-scale Value 13 1.625 1
Baud Rate Divisor %Error Divisor %Error Divisor %Error
600 192 0.16% - - - -
1200 96 0.16% - - - -
1800 64 0.16% - - - -
2000 58 0.16% - - - -
2400 48 0.16% - - - -
3600 32 0.16% 256 0.16% - -
4800 24 0.16% 192 0.16% - -
7200 16 0.16% 128 0.16% 208 0.16%
9600 12 0.16% 96 0.16% 156 0.16%
14400 8 0.16% 64 0.16% 104 0.16%
19200 6 0.16% 48 0.16% 78 0.16%
28800 4 0.16% 32 0.16% 52 0.16%
38400 3 0.16% 24 0.16% 39 0.16%

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57600 2 0.16% 16 0.16% 26 0.16%
115200 1 0.16% 8 0.16% 13 0.16%
230400 - - 4 0.16% - -
460800 - - 2 0.16% - -
750000 - - - - 2 0.00%
921600 - - 1 0.16% - -
1500000 - - - - 1 0.00%
Note: Data transfer rate per bit, which is determined by the divisor of the baud-rate
generator that is set with UART2 Baud Rate Registers and clock pre scale that is set with
UART2 Control Registers
4.12 Bus Operation
Figure 46: Instruction Fetch Timing
Figure 47 Memory Read Timing

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Figure 48: Memory Write Timing
Figure 49: IO Read Timing

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Figure 50: IO Write Timing
4.13 I2C Interface Parameter
Table 27: I2C Interface Parameter

Parameter Symbol Typical Unit
SCL period fSCL 100 400 kHz
Clock low time TLOW 5.0 1.26 us
Clock high time THIGH 4.96 1.22 us
Clock rise time tr 90 90 ns
Clock fall time tf 7.5 8 ns
Data setup time tSU:DAT 3.7 0.68 us
Data hold time tHD:DAT 1.24 740 us
Start hold time tHD:STA 9.2 2.45 us
Start setup time tSU:STA 5.3 1.3 us
Stop setup time tSU:STO 5.3 1.3 us

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Figure 51: I2C Interface Timing
I2C Interface Timing

tLO tHIGH 1/fSCL
tSU:STA W
SC
L
tr tf
tBU
F
SDA
tHD:ST tHD:DA tSU:ST
A tSU:DA T O
T
4.14 A/D Converter Characteristics
Table 28: A/D Converter Characteristics

(TA = -10 - +70℃, VDD = 1.8 V, VCC = 3.1V, Sample Rate=48KHz)
Characteristics Min. Typ. Max. Unit
Dynamic Range –40 dBFS Input 91.2 dB
Total Harmonic Distortion+Noise -81 dB
Frequency Response 20-18KHz 0.5 dB
Input Common Mode Voltage 1.510 Vrms
Full Scale Input Voltage 2.58 Vpp

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Figure 52: A/D Converter -- Frequency Response Characteristics

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Figure 53: A/D Converter -- THD+N vs AMP

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Figure 54: A/D Converter --Small Signal Power Spectrum

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Figure 55: A/D Converter -- Linearity
4.15 DAC Characteristics
Table 29: DAC Characteristics
Characteristics MIN. Typ. MAX. UNIT
Dynamic Range –48 dBFS Input 91.5 dB
Total Harmonic Distortion+Noise -85.5 dB
Full Scale Output Voltage 0.48 0.58 0.72 Vrms
Interchannel Isolation (1k) -99/-81 dB

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Figure 56: DAC --Small Signal Power Spectrum
4.16 Headphone Driver Characteristics
(TA =-10 - +70℃, VDD = 2.0 V, VCC = 3.0 V, Sample Rate=48KHz, , Volume Level=0x1F)
Table 30: Headphone Driver Characteristics
Characteristics MIN. Typ. MAX. UNIT
Dynamic Range 94 dB
Total Harmonic Distortion+Noise -90 dB
Output Common Mode Voltage 1.516 Vrms
Full Scale Output Voltage@-70dB thd+n 1.77 Vpp
Output Power @16ohm 24 mW

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Figure 57: Headphone Driver–Frequency Response

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Figure 58: Headphone Driver--THD + N Amplitude Diagram of Headphone Driver
Figure 59: Headphone Driver--Small Signal Power Spectrum

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Figure 60: Headphone Driver—Linearity
4.17 LCM Driver Parameter

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Figure 61: LCM Timing
Table 31: LCM Driver Parameter

Item Symbol Unit Min. Typ. Max. Test Condition
Write tCYCW ns 34 200 - AHB clk.=60MHz
Bus cycle time
Read tCYCR ns 34 134 - AHB clk.=60MHz
Write low-level pulse width PWLW ns 17 100 - AHB clk.=60MHz
Read low-level pulse width PWLR ns 17 67 - AHB clk.=60MHz
Write high-level pulse width PWHW ns 17 100 - AHB clk.=60MHz
Read high-level pulse width PWHR ns 17 67 - AHB clk.=60MHz
tWRr ,
Write / Read rise / fall time ns - 11 - AHB clk.=60MHz
tWRf
Write data set up time tDSW ns 27 110 - AHB clk.=60MHz
Write data hold time tH ns 23 28 - AHB clk.=60MHz
Read data delay time tDDR ns - 45 - AHB clk.=60MHz
Read data hold time tDHR ns - 105 - AHB clk.=60MHz

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4.18 NAND Flash IF
Data Fetch at RD# Rising Edge

Figure 62: Conventional Serial Access Mode
Data Fetch at RD# Falling Edge

Figure 63: EDO Type Serial Access Mode

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Data Fetch at RD# Falling Edge
Figure 64: Another Serial Access Mode
IO[15:8] must be set to zero

Figure 65: Command Latch Cycle
IO[15:8] must be set to zero

Figure 66: Address Latch Cycle

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Figure 67: WR/RD Signal Rising & Falling Driver Request
Table 32: Nand Flash Timing Request

Conventional
Item EDO Type Serial Access Remark
Serial Access
tCEA 23nS (min) 23nS (min)
tREA 30nS (max) 18nS (max)
tREH 15nS (min) 12.5nS (min)

tRP 25nS (min) 12.5nS (min)
Conventional: duty≠50%
tRC 30nS (min) 25nS (min)
EDO type: duty=50%
Data Fetch At RD# Rising Edge At next RD# Falling Edge
tFALLING 5nS 5nS
tRISINFG 5nS 5nS
tCLS 25nS (min) 12nS (min)
tCLH 10nS (min) 5nS (min)

tCS 35nS (min) 20nS (min)
tCH 10nS (min) 5nS (min)
tALS 25nS (min) 12nS (min)
tALH 10nS (min) 5nS (min)
tDS 20nS (min) 12nS (min)
tDH 10nS (min) 5nS (min)

tWC 30nS (min) 25nS (min)
DMA clk 30MHz 40MHz

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4.19 SD Card
Figure 68: Timing Diagram Data Input/Output Referenced to Clock
Table 33: Card Interface Timings

Parameter Symbol Min. Max. Unit Remark
Clock CLK
Clock frequency data Transfer Mode fpp 0 26/52 MHz CL<=30pF(tolerance
(Push Pull) +100KHz)
Clock frequency identification fOD 0 400 KHz Tolerance:+20KHz
Mode(Open Drain)
Clock low time tWL 6.5 ns CL<=30pF
Clock rise time tTLH 3 ns CL<=30pF
Clock fall time 3 ns CL<=30pF
Inputs CMD DAT (reference to CLK)
Input setup time tISU 3 ns CL<=30pF
Input hold time tIH 3 ns CL<=30pF
Output CMD DAT(reference to CLK)

Ver 1.1 Page 92 2007-1-29
Output setup time tOSU 5 ns CL<=30pF

Output hold time tOH 5 ns CL<=30pF
Signal rise time trise 3 ns CL<=30pF
Signal fall time tfall 3 ns CL<=30pF
Table 34: Bus Signal Line Load

Parameter Symbol Min Recommend Max Unit Remark
Pull up resistance for To prevent bus
Rcmd 4.7 10 100 KOhm
CMD floating
Pull up resistance for To prevent bus
Rdat 50 50 100 KOhm
dat0-7 floating
Bus signal line
CL 30 pF Single card
capacitance
Signal card capacitance Ccard 7 pF
Maximum signal line
16 nH Fpp<=52MHz
inductance
CL=CHost+Cbus+Ccard
Table 35: SD Spec. ver1.0 Timing

Parameter Symbol Min Max Unit Remark
Clock Frequency Data transfer mode fpp 0 25 MHz CL<=100Pf
Clock Frequency identification mode fOD 0~100 400 KHz CL<=250pF
Clock Low Time tWL 10 Ns CL<=100pF
Clock High Time TWH 10 Ns CL<=100pF
Clock Rise Time tTLH 10 Ns CL<=100pF
Clock Fall Time tTHL 10 Ns CL<=100pF
Clock Low Time tWL 50 Ns CL<=100pF
Clock High Time TWH 50 Ns CL<=100pF
Clock Rise Time tTLH 50 Ns CL<=100pF
Clock Fall Time tTHL 50 Ns CL<=100pF
Input Set-up Time tISU 5 Ns CL<=25pF
Input Hold Time tIH 5 Ns CL<=25pF
Output Delay Time under Data Transfer
tODLY 14 Ns CL<=25pF
Mode
Output Delay time under identification
tODLY 50 Ns CL<=25pF
transfer mode

Ver 1.1 Page 93 2007-1-29
4.20 SDRAM IF
Figure 69: Standard SDRAM Power Up
Figure 70: Mobile SDRAM Power Up

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NOTE:
1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock high time, all commands applied are NOP.
3. Outputs are guaranteed High-Z after command is issued.
4. A12 should be a LOW at tP + 1.
Figure 71: SDRAM IF-- Power Down
NOTE:
1. Violating refresh requirements during power-down may result in a loss of data.
2. CAS latency indicated in parentheses

Ver 1.1 Page 95 2007-1-29
Figure 72: SDRAM IF-- Clock Suspend
NOTE:
1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is
disabled.

Ver 1.1 Page 96 2007-1-29
Figure 73: SDRAM IF-- Auto Refresh
NOTE:

Ver 1.1 Page 97 2007-1-29
Figure 74: SDRAM IF -- Self Refresh
NOTE:
1. No maximum time limit for Self Refresh. tRAS(MIN) applies to non-Self Refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency or timing.

Ver 1.1 Page 98 2007-1-29
Figure 75: SDRAM IF-- Read
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed
by a “manual” PRECHARGE.

Ver 1.1 Page 99 2007-1-29
Figure 76: SDRAM IF -- Read DQM Operation
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. CAS latency indicated in parentheses.

Ver 1.1 Page 100 2007-1-29
Figure 77: SDRAM IF-- Write
NOTE:
1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual”
PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of
frequency.

Ver 1.1 Page 101 2007-1-29
Figure 78: SDRAM IF-- Write-DQM Operation
NOTE:
1. For this example, the burst length = 4.

Ver 1.1 Page 102 2007-1-29
Table 36: SDRAM IF -- Parameter

AC Characteristics PC-100
Symbol
Parameter Min Max Units
CL =
tAC (3) 7 ns
Access time from CLK 3
(positive edge) CL =
tAC (2) 8 ns
2
Address hold time tAH 1 ns
Address setup time tAS 2.5 ns
CLK high-level width tCH 3 ns
CLK low-level width tCL 3 ns
CL =
tCK (3) 10 ns
3
Clock cycle time
CL =
tCK (2) 12 ns
2
CKE hold time tCKH 1 ns
CKE setup time tCKS 2.5 ns
CS#, RAS#, CAS#, WE#, DQM
tCMH 1 ns
hold time
CS#, RAS#, CAS#, WE#, DQM
tCMS 2.5 ns
setup time
Data-in hold time tDH 1 ns
Data-in setup time tDS 2.5 ns
CL =
tHZ (3) 7 ns
3
Data-out High-Z time
CL =
tHZ (2) 8 ns
2
Data-out Low-Z time tLZ 1 ns
Data-out hold time (load) tOH 2.5 ns
Data-out hold time (no load) tOHN 1.8 ns
ACTIVE-to-PRECHARGE command tRAS 50 120,000 ns
ACTIVE-to-ACTIVE command
tRC 100 ns
period
ACTIVE-to-READ or WRITE delay tRCD 20 ns
Refresh period tREF 64 ms
AUTO REFRESH command period tRFC 100 ns
PRECHARGE command period tRP 20 ns
ACTIVE bank a to ACTIVE bank b tRRD 2 tCK

Ver 1.1 Page 103 2007-1-29
command
Transition time tT 0.5 1.2 ns
WRITE recovery time Auto tWR
1 CLK +5ns –
precharge mode (a) (a)
tWR
Manual precharge mode (m) 15 ns
(m)
Exit SELF REFRESH to ACTIVE
tXSR 100 ns
command
4.20.1

Ver 1.1 Page 104 2007-1-29
5 Ordering Information
5.1 Recommended Soldering Conditions
Table 37: Soldering Conditions for Surface-mount Devices
Soldering
Soldering Conditions
Process
Peak package’s surface temperature: 235℃ (Lead) or 260℃ (Lead Free)
Reflow time: 30 seconds or less (210℃or more)----(Lead) or 60 seconds or less
(217℃or more)---- (Lead Free)

Infrared Ray Reflow
Maximum allowable number of reflow processes: 2
Exposure limit: 1 days at Rh=60%, Tem=30℃ (12 hours of pre-baking is
required at 125℃ afterward).
Partial heating Terminal temperature: 300℃ or less
method Heat time: 3 seconds or less (for one side of a device)
Note:
The maximum number of days during which the product can be stored at a temperature
of 25℃ and a relative humidity of 65% or less after dry-pack package is opened.
Caution:
Do not apply two or more different soldering methods to one chip (except for partial
heating method for terminal sections).
5.2 Precaution against ESD for Semiconductors
When the strong electric field is exposed to a MOS device, the destruction of the gate
oxide may occur and then it can ultimately degrade the device operation. Measures must be

Ver 1.1 Page 105 2007-1-29
taken to stop the generation of static electricity as many as possible, and it is a must to
quickly dissipate the static electricity when it occurs. Environmental control must be
adequate enough. Humidifier should be used when it is dry. Recommend to avoid using
insulators, which may easily build static electricity. Semiconductor devices must be stored
and transported in an anti-static container or a static shielding bag or objects made from
conductive material. All test and measurement tools including work bench and floor should
be grounded. The operator shall be grounded by using wrist strap. Semiconductor devices
shall not be touched with bare hands. Similar precautions shall be taken for PW boards with
semiconductor devices on it.
5.3 Handling of Unused Input Pins for CMOS
The cause for no connection to CMOS device inputs can be the malfunction. If no
connection is provided for the input pins, the possible cause is that an internal input level
may be generated due to noise, etc., which results in malfunction. CMOS devices behave
differently from Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or
low by using a pull-up or pull-down circuitry. Each unused pin shall be connected to VDD or
GND with a resistor, if it is considered to have the possibility of being an output pin. All
handling related to the unused pins must be judged device by device and follows the related
specifications governing the devices.
5.4 Status before Initialization of MOS Devices
Power-on does not necessarily define the initial status of MOS device. Production
process of MOS does not define the initial operation status of the device. Immediately after
the power source is turned on, the devices with reset function have not yet been initialized.
Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers.
Device is not initialized until the reset signal is received. Reset operation must be executed
immediately after the power-on.

Ver 1.1 Page 106 2007-1-29
6 ATJ2135 Package Drawing
Figure 79: ATJ2135 Package Drawing

Ver 1.1 Page 107 2007-1-29
7 Appendix
7.1 Acronym and Abbreviations
ADC: Analog-to-Digital Converter
AHB: Advance High-Performance Bus
ALE: Address-Locked Enable
APB: Advance Peripheral Bus
ATA: Advance Technology Attachment
BIST: Build-in Self-Test
CLE: Command-Locked Enable
CMU: Clock Management Unit
CP0: System Control Coprocessor
CRC: Cyclic redundancy Check
CVBS: Composite Video Broadcasting Signal
DAC: Digital-to-Analog Converter
dB: Decibel
DC: Direct Current
DSP: Digital Signal Processing
DVB: Digital Video Broadcasting
EAV: End of Active Video
ECC: Error Correct Code
FIR: Fast Infrared
GPIO: General-Purpose Input/Output

Ver 1.1 Page 108 2007-1-29
I2C: Inter-Integrated Circuit
I2S: Inter-IC Sound
IR: Infrared
IrDA: Infrared Data Association
IRQ: Interrupt Request
JPEG: Joint Photographic Experts Group
Li-Ion: Lithium Ion (battery type)
LRADC: Low Resolution ADC
MAC: Multiplier Accumulator Control
MCA: Motion Compensation Accelerator
MHA: Media Hardware Accelerator
MIPS: Million Instructions Per Second
MIR: Mid Infrared
MJPEG: Motion JPEG
MMC: Multimedia Card
MMU: Memory Management Unit
MLC: Multi-Level Cell
MPEG: Motion Picture Expert Group
NTSC: National Television Standards Committee
OLED: Polymer Light-Emitting Diode
OTG: On the Go
PA: Power Amplifier
PAL: Phase Alteration Line
PCM: Pulse Code Modulation
PFM: Pulse Frequency Modulation
PLL: Phase-Locked Loop
PMU: Power Management Unit

Ver 1.1 Page 109 2007-1-29
PWM: Pulse Width Modulation
RISC: Reduced Instruction Set Computing
RTC: Real-Time Clock
SAV: Start of Active Video
SD: Secure Digital memory card
SIR: Slow Infrared
SMC: State Machine Controller
SLC: Single-Level Cell
SOC: System on Chip
SPEC: Specification
SPDIF: SONY-Philips Digital Interface Format
SPI: Serial Peripheral Interface
SPRAM: Scratch Pad RAM
SW: Software
THD: Total Harmonic Distortion
TLB: Translation Look-aside Buffer
TS: Transport Stream
UART: Universal Asynchronous Receiver Transmitter
WMA: Windows Media Audio
WMV: Windows Media Video

Ver 1.1 Page 110 2007-1-29
Actions Semiconductor Co., Ltd.
Address: Bldg.15-1, NO.1, HIT Rd., Tangjia, Zhuhai, Guangdong, China

Tel: +86-756-3392353
Fax: +86-756-3392251
Post Code: 519085
http://www.actions-semi.com
Business Email: mp-sales@actions-semi.com
Technical Service Email: mp-cs@actions-semi.com

Ver 1.1 Page 111 2007-1-29

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Circuit diagrams and other information relating to products of Actions Semiconductor

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

2.2 Pin Definition.................................................................................................................. 16

3 Function Description ............................................................................................ 23

3.2 Memory Map .................................................................................................................. 24

3.4 Interrupt Controller ........................................................................................................ 31

3.5 PMU/DC-DC Converter ..................................................................................................34

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

3.6 32-BIT RISC Core............................................................................................................40

3.7 SDRAM Interface ...........................................................................................................42

3.8 SRAM on Chip.................................................................................................................43

3.10 DMA/Bus Arbiter............................................................................................................43

3.11 24-BIT DSP Core.............................................................................................................46

3.12 Media Hardware Accelerator (MHA) ...........................................................................48

3.13 Motion Compensation Accelerator (MCA).................................................................. 50

3.14 NAND FLASH Interface .................................................................................................52

3.15 SD/MMC Interface.........................................................................................................53

3.16 YUV2RGB Interface........................................................................................................53

3.17 USB2.0 SIE...................................................................................................................... 54

3.18 I2C (2) Interface .............................................................................................................55

3.19 IR Interface ..................................................................................................................... 55

3.20 Key Scan.......................................................................................................................... 58

3.21 DAC and Headphone Driver.......................................................................................... 61

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

3.21.2 Block Diagram ...........................................................................................................63

3.22 ADC .................................................................................................................................. 63

4.3 DC Characteristics .........................................................................................................66

4.6 Reset Parameter............................................................................................................ 71

4.7 Initialization Parameter ................................................................................................ 71

4.8 GPIO Interface Parameter............................................................................................72

4.9 Ordinary ROM Parameter .............................................................................................73

4.10 External System Bus Parameter.................................................................................. 74

4.11 Bus Operation.................................................................................................................75

4.12 I2C Interface Parameter...............................................................................................78

4.13 A/D Converter Characteristics .....................................................................................79

4.14 DAC Characteristics .......................................................................................................83

4.15 Headphone Driver Characteristics ..............................................................................84

4.16 LCM Driver Parameter................................................................................................... 87

4.17 NAND Flash IF ................................................................................................................89

4.19 SDRAM IF ........................................................................................................................ 94

5 Ordering Information ......................................................................................... 105

5.2 Precaution against ESD for Semiconductors ..........................................................105

5.3 Handling of Unused Input Pins for CMOS ................................................................106

5.4 Status before Initialization of MOS Devices ............................................................106

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

6 ATJ2135 Package Drawing ............................................................................... 107

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

Figure 1: Pin Assignment......................................................................................................15

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

Figure 34: DC/DC Efficiency Curve 1 ...................................................................................68

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

Figure 74: SDRAM IF-- Read..................................................................................................99

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

Table 1: ATJ2135 Pin Definition ...........................................................................................16

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.

Table 35: SDRAM IF -- Parameter.......................................................................................103

Copyright © Actions Semiconductor Co., Ltd. 2006. All rights reserved.