www.DataSheet4U.

com

a
®
SALEM Three-Phase
Electronic Energy Meter
ADSST-EM-3035
FEATURES FUNCTIONAL BLOCK DIAGRAM
IEC 687, Class 0.5 and Class 0.2 Accuracy
ANSI C12.1 SMPS LCD DISPLAY
IEC 1268, Requirements for Reactive Power
Configurable as Import/Export or Import Only
Simultaneous Measurement of:
DSP
Active Power and Energy—Import and Export RESISTOR
BLOCK SPI BUS
Reactive Power and Energy
C

Apparent Power
ADC
Power Factor for Individual Phases and Total Frequency
RMS Voltage for All Phases BUTTONS

RMS Current for All Phases

CT
Harmonic Analysis for Voltage and Current
ADSST-EM-3035 FLASH OPTO
All Odd Harmonics up to 21st Order CT
CHIPSET
Interface with a General Purpose Microcontroller
CT RTC RS-232
User-Friendly Calibration of Gain Offset and Phase and
Nonlinearity Compensation on CTs (Patent Pending)
Two Programmable Output E-Pulses
Programmable E-Pulse Constant from 1,000 Pulses/kWh
to 20,000 Pulses/kWh
15 kHz Sampling Frequency
Tamper-Proof Metering DataShee
Single 5 V Supply
DataSheet4U.com
GENERAL DESCRIPTION
The ADSST-EM-3035 Chipset consists of a fast and accurate
6 channel, 16-bit sigma-delta analog-to-digital converter
ADSST-73360AR (ADC), an efficient digital signal processor
ADSST-2185KST-133 (DSP), and Metering Software. The
ADC and DSP are interfaced together to simultaneously acquire
voltage and current samples on all the three phases and perform
mathematically intensive computations to accurately calculate
the Powers, Energies, Instantaneous Quantities, and Harmonics.
The chipset could be interfaced to any general-purpose micropro-
cessor to develop state of the art polyphase or Tri-vector energy
metering solution in accordance with IEC 1036, IEC 687, or
ANSI C12.1.
All calibrations are done in digital domain and no trimming
potentiometers are required.

SALEM is a registered trademark of Analog Devices, Inc.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
DataSheet4U.com
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002

DataSheet 4 U .com
 www.DataSheet4U.com

ADSST-EM-3035
ADSST-2185KST-133 (DSP) SPECIFICATION GENERAL DESCRIPTION
FEATURES The ADSST-2185KST-133 is a single-chip microcomputer
30 ns Instruction Cycle 33 MIPS Sustained Performance optimized for digital signal processing (DSP) and other high
Single-Cycle Instruction Execution speed numeric processing applications.
Single-Cycle Context Switch The ADSST-2185KST-133 combines the ADSP-2100 family
Three-Bus Architecture Allows Dual Operand Fetches base architecture (three computational units, data address
in Every Instruction Cycle generators, and a program sequencer) with two serial ports, a
Multifunction Instructions 16-bit internal DMA port, a byte DMA port, a programmable
Power-Down Mode Featuring Low CMOS Standby Power timer, Flag I/O, extensive interrupt capabilities, and on-chip
Dissipation with 100 Cycle Recovery from Power-Down program and data memory.
Condition The ADSST-2185KST-133 integrates 40 kBytes of on-chip
Low Power Dissipation in Idle Mode memory configured as 8 Kwords (24-bit) of program RAM and
ADSP-2100 Family Code Compatible, with Instruction 8 Kwords (16-bit) of data RAM. Power-down circuitry is also
Set Extensions provided to meet the low power needs of battery operated portable
40 kBytes of On-Chip RAM, Configured as equipment. The ADSST-2185KST-133 is available in a 100-lead
8 KWords On-Chip Program Memory RAM and TQFP package.
8 KWords On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction In addition, the ADSST-2185KST-133 supports instructions
and Data Storage that include bit manipulations, bit set, bit clear, bit toggle, bit
Independent ALU, Multiplier/Accumulator, and Barrel test new ALU constants, new multiplication instruction (x squared),
Shifter Computational Units biased rounding, result free ALU operations, I/O memory trans-
Two Independent Data Address Generators fers, and global interrupt masking for increased flexibility.
Powerful Program Sequencer Provides Zero Overhead Fabricated in a high speed, double metal, low power, CMOS
Looping Conditional Instruction Execution process, the ADSST-2185KST-133 operates with a 25 ns
Programmable 16-Bit Interval Timer with Prescaler instruction cycle time. Every instruction can execute in a single
100-Lead TQFP processor cycle.
16-Bit Internal DMA Port for High Speed Access to On-
et4U.com The ADSST-2185KST-133’s flexible architecture and com- DataShee
Chip Memory (Mode Selectable)
prehensive instruction set allow the processor to perform
4 MBytes Byte Memory Interface for Storage of Data
multiple operations in parallel. In one processor cycle, the
DataSheet4U.com
Tables and Program Overlays
ADSST-2185KST-133 can:
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable) • Generate the next program address
I/O Memory Interface with 2048 Locations Supports • Fetch the next instruction
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
• Perform one or two data moves
Memory Space Permits Glueless System Design • Update one or two data address pointers
(Mode Selectable) • Perform a computational operation
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding • This takes place while the processor continues to:
Hardware and Automatic Data Buffering Receive and transmit data through the two serial ports
Automatic Booting of On-Chip Program Memory from Receive and/or transmit data through the internal DMA port
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port Receive and/or transmit data through the byte DMA port
Six External Interrupts Decrement timer
13 Programmable Flag Pins Provide Flexible System Signaling
UART Emulation through Software SPORT Reconfiguration POWER-DOWN
CONTROL
FULL MEMORY
ICE-Port Emulator Interface Supports Debugging in Final Systems MODE
MEMORY PROGRAMMABLE
DATA ADDRESS
GENERATORS PROGRAM 16K  24 16K  16 I/O EXTERNAL
SEQUENCER PROGRAM DATA AND ADDRESS
DAG 1 DAG 2 MEMORY MEMORY FLAGS BUS

EXTERNAL
PROGRAM MEMORY ADDRESS
DATA
BUS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS SERIAL PORTS TIMER
INTERNAL
ALU MAC SHIFTER SPORT0 SPORT 1 DMA
PORT
ADSP-2100 BASE HOST MODE
ARCHITECTURE

DataSheet4U.com Figure 1. Functional Block Diagram

–2– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
ARCHITECTURE OVERVIEW An interface to low cost byte-wide memory is provided by the
The ADSST-2185KST-133 instruction set provides flexible Byte DMA port (BDMA port). The BDMA port is bidirectional
data moves and multifunction (one or two data moves with a and can directly address up to four megabytes of external RAM
computation) instructions. Every instruction can be executed in or ROM for off-chip storage of program overlays or data tables.
a single processor cycle. The ADSST-2185KST-133 assembly The byte memory and I/O memory space interface supports slow
language uses an algebraic syntax for ease of coding and read- memories and I/O memory-mapped peripherals with programmable
ability. A comprehensive set of development tools supports wait state generation. External devices can gain control of external
program development. buses with bus request/grant signals (BR, BGH, and BG). One
Figure 1 is an overall block diagram of the ADSST-2185KST-133. execution mode (Go Mode) allows the ADSST-2185KST-133
The processor contains three independent computational units: to continue running from on-chip memory. Normal execution
the ALU, the multiplier/accumulator (MAC), and the shifter. mode requires the processor to halt while buses are granted.
The computational units process 16-bit data directly and have The ADSST-2185KST-133 can respond to 11 interrupts.
provisions to support multiprecision computations. The ALU There are up to six external interrupts (one edge-sensitive, two
performs a standard set of arithmetic and logic operations; division level-sensitive, and three configurable) and seven internal inter-
primitives are also supported. The MAC performs single-cycle rupts generated by the timer, the serial ports (SPORTs), the
multiply, multiply/add and multiply/subtract operations with 40 Byte DMA port, and the power-down circuitry. There is also a
bits of accumulation. The shifter performs logical and arithmetic master RESET signal. The two serial ports provide a complete
shifts, normalization, denormalization and derive exponent synchronous serial interface with optional companding in hard-
operations. ware and a wide variety of framed or frameless data transmit
The shifter can be used to efficiently implement numeric format and receive modes of operation.
control including multiword and block floating-point representations. Each port can generate an internal programmable serial clock or
The internal result (R) bus connects the computational units accept an external serial clock.
so the output of any unit may be the input of any unit on the The ADSST-2185KST-133 provides up to 13 general purpose
next cycle. flag pins. The data input and output pins on SPORT1 can be
A powerful program sequencer and two dedicated data address alternatively configured as an input flag and an output flag. In
generators ensure efficient delivery of operands to these com- addition, eight flags are programmable as inputs or outputs, and
et4U.com DataShee
putational units. The sequencer supports conditional jumps, three flags are always outputs.
subroutine calls, and returns in a single cycle. With internal loop A programmable interval timer generates periodic interrupts. A
counters and loop stacks, the ADSST-2185KST-133 executesDataSheet4U.com
16-bit count register (TCOUNT) decrements every n processor
looped code with zero overhead. No explicit jump instructions cycle, where n is a scaling value stored in an 8-bit register (TSCALE).
are required to maintain loops. When the value of the count register reaches zero, an interrupt is
Two data address generators (DAGs) provide addresses for simul- generated and the count register is reloaded from a 16-bit period
taneous dual operand fetches from data memory and program memory. register (TPERIOD).
Each DAG maintains and updates four address pointers. Whenever Serial Ports
the pointer is used to access data (indirect addressing), it is post- The ADSST-2185KST-133 incorporates two complete synchronous
modified by the value of one of four possible modify registers. A serial ports (SPORT0 and SPORT1) for serial communications
length value may be associated with each pointer to implement and multiprocessor communication.
automatic modulo addressing for circular buffers.
Here is a brief list of the capabilities of the ADSST-2185KST-133
Efficient data transfer is achieved with the use of five internal buses: SPORTs. For additional information on Serial Ports, refer to
• Program Memory Address (PMA) Bus the ADSP-2100 Family User’s Manual, Third Edition.
• Program Memory Data (PMD) Bus • SPORTs are bidirectional and have a separate, double-buffered
• Data Memory Address (DMA) Bus transmit and receive section.
• Data Memory Data (DMD) Bus • SPORTs can use an external serial clock or generate their own
• Result (R) Bus serial clock internally.
The two address buses (PMA and DMA) share a single external • SPORTs have independent framing for the receive and transmit
address bus, allowing memory to be expanded off-chip, and the two sections. Sections run in a frameless mode or with frame synchro-
data buses (PMD and DMD) share a single external data bus. Byte nization signals internally or externally generated. Frame
memory space and I/O memory space also share the external buses. sync signals are active high or inverted, with either of two
pulsewidths and timings.
Program memory can store both instructions and data, permitting
the ADSST-2185KST-133 to fetch two operands in a single cycle, • SPORTs support serial data word lengths from 3 to 16 bits and
one from program memory and one from data memory. The provide optional A-law and M-law companding according to
ADSST-2185KST-133 can fetch an operand from program CCITT recommendation G.711.
memory and the next instruction in the same cycle. • SPORT receive and transmit sections can generate unique
When configured in host mode, the ADSST-2185KST-133 has interrupts on completing a data-word transfer.
a 16-bit Internal DMA port (IDMA port) for connection to • SPORTs can receive and transmit an entire circular buffer of
DataSheet4U.com
external systems. The IDMA port is made up of 16 data/address data with only one overhead cycle per data-word. An interrupt
pins and five control pins. The IDMA port provides transparent, is generated after a data buffer transfer.
direct access to the DSP’s on-chip program and data RAM.
REV. 0 –3–
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
• SPORT0 has a multichannel interface to selectively receive and Pin Descriptions
transmit a 24- or 32-word, time-division multiplexed, serial The ADSST-2185KST-133 is available in a 100-lead TQFP
bitstream. package. To maintain maximum functionality and reduce pack-
• SPORT1 can be configured to have two external interrupts age size and pin count, some serial ports, programmable flags,
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The interrupt and external bus pins have dual, multiplexed function-
internally generated serial clock may still be used in this ality. The external bus pins are configured during RESET only,
configuration. while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concur-
rently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics.

Table I. Common-Mode Pins

Pin Number Input/ Pin Number Input/

Name(s) of Pins Output Function Name(s) of Pins Output Function
RESET 1 I Processor Reset Input PF0 (Mode A) 1 I Mode Select Input-Checked
BR 1 I Bus Request Input only During RESET
BG 1 O Bus Grant Output CLKIN, 2 I Clock or Quartz Crystal Input
BGH 1 O Bus Grant Hung Output XTAL
DMS 1 O Data Memory Select Output CLKOUT 1 O Processor Clock Output
PMS 1 O Program Memory Select Output SPORT0 5 I/O Serial Port I/O Pins
IOMS 1 O Memory Select Output SPORT1 5 I/O Serial Port I/O Pins
BMS 1 O Byte Memory Select Output IRQ1:0 Edge- or Level-Sensitive
CMS 1 O Combined Memory Interrupts
Select Output F1, F0 Flag In, Flag Out2
et4U.comRD 1 O Memory Read Enable Output PWD 1 I Power-Down Control Input DataShee
WR 1 O Memory Read Enable Output PWDACK 1 O Power-Down Control Output
IRQ2+PF7 1 I Edge- or Level-Sensitive DataSheet4U.com
FL0, FL1, 3 O Output Flags
Interrupt Request1 FL2
IRQL0+PF5 1 I Level-Sensitive VDD 16 I VDD and GND
Interrupt Requests1 AND
IRQL1+PF6 1 I Level-Sensitive GND
Interrupt Requests1 EX-Port 9 I/O For Emulation Use
IRQE+PF4 1 I Edge-Sensitive NOTES
Interrupt Requests1 1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable
PF3 1 I/O Programmable I/O Pin the corresponding interrupts, the DSP will vector to the appropriate interrupt
PF2 (Mode C) 1 I Programmable I/O Pin Mode vector address when the pin is asserted, either by external devices or set as a
programmable flag.
Select Input-Checked only 2
SPORT configuration determined by the DSP System Control Register. Software
During RESET configurable.
PF1 (Mode B) 1 I Mode Select Input-Checked
only During RESET

DataSheet4U.com

–4– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
100-Lead TQFP Package Pinout

93 PF1 [MODE B]

89 PF2 [MODE C]
94 PF0 [MODE A]
96 PWDACK
100 A3/IAD2
99 A2/IAD1
98 A1/IAD0

91 PWD
92 GND

80 GND
95 BGH

90 VDD

88 PF3

84 D23
83 D22

79 D19
78 D18
77 D17
76 D16
81 D20
82 D21
86 FL1
85 FL2
87 FL0
97 A0
A4/IAD3 1 75 D15
A5/IAD4 2 PIN 1 74 D14
IDENTIFIER
GND 3 73 D13
A6/IAD5 4 72 D12
A7/IAD6 5 71 GND
A8/IAD7 6 70 D11
A9/IAD8 7 69 D10
A10/IAD9 8 68 D9
A11/IAD10 9 67 VDD
A12/IAD11 10 66 GND
A13/IAD12 11 65 D8
GND 12 64 D7/IWR
CLKIN 13
ADSST-2185KST-133 63 D6/IRD
XTAL 14 TOP VIEW 62 D5/IAL
(Not to Scale)
VDD 15 61 D4/IS
CLKOUT 16 60 GND
GND 17 59 VDD
VDD 18 58 D3/IACK
WR 19 57 D2/IAD15
RD 20 56 D1/IAD14
BMS 21 55 D0/IAD13
DMS 22 54 BG
et4U.com PMS 23 53 EBG DataShee
IOMS 24 52 BR
CMS 25 DataSheet4U.com 51 EBR
IRQL0+PF5 27
GND 28
IRQL1+PF6 29
IRQ2+PF7 30
DT0 31
TFS0 32
RFS0 33
DR0 34
SCLK0 35
VDD 36
DT1/FO 37
TFS1/IRQ1 38
RFS1/IRQ0 39
DR1/FI 40
GND 41
SCLK1 42
ERESET 43
RESET 44
EMS 45
EE 46
ECLK 47
ELOUT 48
ELIN 49
EINT 50
IRQE+PF4 26

DataSheet4U.com

REV. 0 –5–
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
System Interface Clock Signals
Figure 2 shows typical basic system configurations with the Either a crystal or a TTL-compatible clock signal can clock the
ADSST-2185KST-133, two serial devices, a byte-wide EPROM ADSST-2185KST-133.
and optional external program and data overlay memories (mode The CLKIN input cannot be halted, changed during operation,
selectable). Programmable wait state generation allows the proces- or operated below the specified frequency during normal
sor to connect easily to slow peripheral devices. The ADSST- operation. The only exception is while the processor is in the
2185KST-133 also provides four external interrupts and two serial power-down state. For additional information, refer to Chapter 9,
ports, or six external interrupts and one serial port. Host Memory ADSP-2100 Family User’s Manual, Third Edition, for detailed
Mode allows access to the full external data bus, but limits address- information on this power-down feature.
ing to a single address bit (A0). Additional system peripherals can
If an external clock is used, it should be a TTL-compatible signal
be added in this mode through the use of external hardware to
running at half the instruction rate. The signal is connected to the
generate and latch address signals.
processor's CLKIN input. When an external clock is used, the
FULL MEMORY MODE
XTAL input must be left unconnected.
ADSST-2185 The ADSST-2185KST-133 uses an input clock with a frequency
KST-133 A13–0 equal to half the instruction rate; a 20.00 MHz input clock
1/2x CLOCK CLKIN 14
OR ADDR13–0
CRYSTAL XTAL D23–16 A0–A21 yields a 25 ns processor cycle (which is equivalent to 40 MHz).
FL0–2
24 D15–8 BYTE Normally, instructions are executed in a single processor cycle.
PF3 MEMORY
IRQ2/PF7
DATA23–0 DATA All device timing is relative to the internal instruction clock rate,
IRQE/PF4 BMS CS which is indicated by the CLKOUT signal when enabled.
IRQL0/ PF5
A10–0
IRQL1/ PF6
ADDR Because the ADSST-2185KST-133 includes an on-chip oscillator
MODE C/PF2 D23–8
MODE B/PF1
I/O SPACE
DATA (PERIPHERALS) circuit, an external crystal may be used. The crystal should be
MODE A/PF0
IOMS CS 2048 LOCATIONS connected across the CLKIN and XTAL pins, with two capacitors
A13–0 connected as shown in Figure 3. Capacitor values are dependent
SPORT1
SCLK1 D23–0
ADDR OVERLAY on crystal type and should be specified by the crystal manufacturer.
RFS1 OR IRQ0 MEMORY
SERIAL
DEVICE
TFS1 OR IRQ1
DATA
TWO 8K
A parallel-resonant, fundamental frequency, microprocessor-
DT1 OR FO PMS
DR1 OR FI DMS
PM SEGMENTS grade crystal should be used.
CMS
et4U.com SPORT0
TWO 8K
DM SEGMENTS
DataShee
SCLK0 BR
SERIAL RFS0 BG
DEVICE TFS0 BGH CLKIN XTAL CLKOUT
DT0
DR0 PWD DataSheet4U.com
PWDACK DSP

HOST MEMORY MODE Figure 3. External Crystal Connections

ADSST-2185 A clock output (CLKOUT) signal is generated by the processor
KST-133
1/2x CLOCK CLKIN 1
at the processor’s cycle rate. This can be enabled and disabled by
OR
CRYSTAL XTAL
ADDR0
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
FL0–2
PF3 16 Reset
IRQ2/PF7
DATA23–8
The RESET signal initiates a master reset of the ADSST-
IRQE/PF4
IRQL0/ PF5
BMS
2185KST-133. The RESET signal must be asserted during the
IRQL1/ PF6
power-up sequence to assure proper initialization. RESET dur-
MODE C/PF2
MODE B/PF1 ing initial power-up must be held long enough to allow the
MODE A/PF0
IOMS
internal clock to stabilize. If RESET is activated any time after
SPORT1
SCLK1 power-up, the clock continues to run and does not require stabi-
SERIAL RFS1 OR IRQ0
DEVICE TFS1 OR IRQ1
DT1 OR FO
lization time.
DR1 OR FI
PMS
The power-up sequence is defined as the total time required for
SPORT0
SCLK0 DMS the crystal oscillator circuit to stabilize after a valid VDD is
RFS0 CMS
SERIAL
DEVICE
TFS0 applied to the processor, and for the internal phase-locked loop
DT0 BR
DR0 BG (PLL) to lock onto the specific crystal frequency. A minimum of
BGH
IDMA PORT PWD
2000 CLKIN cycles ensures that the PLL has locked, but does
IRD/D6
SYSTEM IWR/D7
PWDACK not include the crystal oscillator start-up time. During this power-
INTERFACE
OR
IS/D4
IAL/D5 up sequence, the RESET signal should be held low. On any

CONTROLLER IACK/D3
IAD15–0 subsequent resets, the RESET signal must meet the minimum
16
pulsewidth specification, tRSP.
Figure 2. Basic System Interface The RESET input contains some hysteresis; however, if you use
Recommended Operating Conditions an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended. The master reset sets
A Grade B Grade all internal stack pointers to the empty stack condition, masks
Parameters Min Max Min Max Unit all interrupts and clears the MSTAT register. When RESET is
released, if there is no pending bus request and the chip is con-
VDD Supply Voltage
DataSheet4U.com 4.5 5.5 4.5 5.5 V
figured for booting, the boot-loading sequence is performed.
TAMB Ambient 0 +70 –40 +85 °C
The first instruction is fetched from on-chip program memory
Operating Temperature
location 0x0000 once boot loading completes.
–6– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
ELECTRICAL CHARACTERISTICS
K/B Grade
Parameters Test Conditions Min Typ Max Unit
1, 2
VIH High-Level Input Voltage @ VDD = max 2.0 V
VIH High-Level CLKIN Voltage @ VDD = max 2.2 V
VIL Low-Level Input Voltage1, 3 @ VDD = min 0.8 V
VOH High-Level Output Voltage1, 4, 5 @ VDD = min
IOH = –0.5 max 2.4 V
@ VDD = min
IOH = –100 µA6 VDD – 0.3 V
VOL Low-Level Output Voltage1, 4, 5 @ VDD = min 0.4 V
IOL = 2 mA
IIH High-Level Input Current3 @ VDD = max
VIN = VDD max 10 µA
IIL Low-Level Input Current3 @ VDD = max
VIN = 0 V 10 µA
IOZH Three-State Leakage Current7 @ VDD = max
VIN = VDD max 10 µA
IOZL Three-State Leakage Current7 @ VDD = max
VIN = 0 V8 10 µA
IDD Supply Current (Idle)9 @ VDD = 5.0 12.4 mA
IDD Supply Current @ VDDINT = 5.0
(Dynamic)10, 11 TAMB = 25°C
tCK = 30 ns11 55 mA
tCK = 25 ns11 [65] mA
CI Input Pin @ VIN = 2.5 V,
et4U.com DataShee
Capacitance3, 6, 12 fIN = 1.0 MHz,
TAMB = 25°C 8 pF
CO Output Pin DataSheet4U.com
@ VIN = 2.5 V,
Capacitance6, 7, 12, 13 fIN = 1.0 MHz,
TAMB = 25°C 8 pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input only pins: RESET, BR, DR0, DR1, PWD.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.
5
Although specified for TTL outputs, all ADSST-2185KST-133 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0, D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0, PF7.
8
0 V on BR, CLKIN inactive.
9
Idle refers to ADSST-2185KST-133 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12
Applies to TQFP package type
13
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* ENVIRONMENTAL CONDITIONS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V Ambient Temperature Rating:
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V TAMB = TCASE – (PD ⫻ ␪CA)
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V TCASE = Case Temperature in °C
Operating Temperature Range (Ambient) . . . –40°C to +85°C PD = Power Dissipation in W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C ␪JA = Thermal Resistance (Junction-to-Ambient)
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . 280°C ␪JC = Thermal Resistance (Junction-to-Case)
*Stresses above those listed under Absolute Maximum Ratings may cause perma- ␪CA = Thermal Resistance (Case-to-Ambient)
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
Package ␪JA ␪JC ␪CA
section of this specification is not implied. Exposure to absolute maximum rating TQFP 50°C/W 2°C/W 48°C/W
conditions for extended periods may affect device reliability.
DataSheet4U.com

REV. 0 –7–
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
ADSST-73360AR (ADC) GENERAL DESCRIPTION
FEATURES The ADSST-73360AR is a six-input channel analog front-end
Six 16-Bit A/D Converters processor for power metering. It features six 16-bit A/D conver-
Programmable Input Sample Rate sion provide 76 dB signal-to-noise ratio over a dc to 4 kHz
Simultaneous Sampling signal bandwidth. Each channel also features a programmable
76 dB SNR input gain amplifier (PGA) with gain settings in eight stages
64 kS/s Maximum Sample Rate from 0 dB to 38 dB.
–83 dB Crosstalk The ADSST-73360AR is particularly suitable for industrial
Low Group Delay (125
s Typ per ADC Channel) power metering as each channel samples synchronously, ensur-
Programmable Input Gain ing that there is no (phase) delay between the conversions. The
Flexible Serial Port which Allows Multiple Devices to ADSST-73360AR also features low group delay conversions on
be Connected in Cascade all channels.
Single (2.7 V to 5.5 V) Supply Operation An on-chip reference voltage is included with a nominal value
80 mW Max Power Consumption at 2.7 V of 1.2 V.
On-Chip Reference
28-Lead SOIC The sampling rate of the device is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The ADSST-73360AR is available in 28-lead SOIC.

VINP1 ANALOG
et4U.com SIGNAL
CONDITIONING
0/38dB - DECIMATOR SDI DataShee
PGA CONDITIONING
VINN1
SDIFS
DataSheet4U.com
VINP2 ANALOG SCLK
SIGNAL 0/38dB - DECIMATOR
CONDITIONING PGA CONDITIONING
VINN2

VINP3 ANALOG
SIGNAL 0/38dB - DECIMATOR
CONDITIONING PGA CONDITIONING
VINN3
RESET
REFCAP REFERENCE SERIAL
ADSST-73360AR I/O MCLK
REFOUT PORT
SE
VINP4 ANALOG
SIGNAL 0/38dB - DECIMATOR
CONDITIONING PGA
VINN4 CONDITIONING

VINP5 ANALOG
SIGNAL 0/38dB - DECIMATOR
CONDITIONING PGA
VINN5 CONDITIONING SDO

SDOFS
VINP6 ANALOG
SIGNAL 0/38dB - DECIMATOR
CONDITIONING PGA
VINN6 CONDITIONING

Figure 4. Functional Block Diagram

DataSheet4U.com

–8– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
SPECIFICATIONS
ADSST-73360AR
(AVDD = 5 V  10%; DVDD = 5 V  10%; DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted1.)

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE
REFCAP
Absolute Voltage, VREFCAP 1.25 V 5 VEN = 0
2.5 V 5 VEN = 1
REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from, REFCAP to AGND2
REFOUT
Typical Output Impedance 130 Ω
Absolute Voltage, VREFOUT 1.25 V 5 VEN = 0, Unloaded
2.5 V 5 VEN = 1, Unloaded
Minimum Load Resistance 2 kΩ 5 VEN = 1
Maximum Load Capacitance 100 pF
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3 3.156 V p-p 5 VEN = 1, Measured Differentially
3.17 dBm
Nominal Reference Level at VIN 2.1908 V p-p 5 VEN = 1, Measured Differentially
(0 dBm0) 0 dBm
Absolute Gain
PGA = 0 dB +0.1 dB 1.0 kHz
PGA = 38 dB –0.5 dB 1.0 kHz
et4U.com Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0 DataShee
Signal to (Noise + Distortion)
PGA = 0 dB 76 dB 0 Hz to fS/2; fS = 8 kHz
DataSheet4U.com
PGA = 38 dB 70 dB 0 Hz to 4 kHz; fS = 64 kHz
Total Harmonic Distortion
PGA = 0 dB –86 dB
PGA = 38 dB –80 dB
Intermodulation Distortion –79 dB PGA = 0 dB
Idle Channel Noise –76 dB PGA = 0 dB
Crosstalk ADC-to-ADC –85 dB ADC1 Input Signal Level: 1 kHz, 0 dBm0
ADC2 Input at Idle
DC Offset 20 mV PGA = 0 dB
Power Supply Rejection –55 dB Input Signal Level at AVDD and DVDD
Pins 1.0 kHz, 100 mV p-p Sine
Wave Group Delay4, 5 25 µs 64 kHz Output Sample Rate
50 µs 32 kHz Output Sample Rate
95 µs 16 kHz Output Sample Rate
190 µs 8 kHz Output Sample Rate
Input Resistance at VIN 2, 4 25 kΩ6 DMCLK = 16.384 MHz
FREQUENCY RESPONSE
(ADC)7 Typical Output
Frequency (Normalized to f S)
0 0 dB
0.03125 –0.1 dB
0.0625 –0.25 dB
0.125 –0.6 dB
0.1875 –1.4 dB
0.25 –2.8 dB
0.3125 –4.5 dB
0.375 –7.0 dB
0.4375 –9.5 dB
> 0.5 < –12.5 dB

DataSheet4U.com

REV. 0 –9–
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
VINH, Input High Voltage VDD – 0.8 VDD V
VINL, Input Low Voltage 0 0.8 V
IIH, Input Current –0.5 µA
CIN, Input Capacitance 10 pF
LOGIC OUTPUT
VOH, Output High Voltage VDD – 0.4 VDD V |IOUT| < 100 A
VOL, Output Low Voltage 0 0.4 V |IOUT| < 100 A
Three-State Leakage Current –0.3 A
POWER SUPPLIES
AVDD1, AVDD2 4.5 5.5 V
DVDD 4.5 5.5 V
IDD8 See Table II
NOTES
1
Operating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.
2
Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADCs input impedance is inversely proportional to DMCLK and is approximated by: (4 ∞10”)/DMCLK.
7
Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.

et4U.com Table II. Current Summary (AVDD = DVDD = 3.3 V) DataShee

Analog Digital DataSheet4U.com

Total MCLKON
Conditions Current Current Current (Max) SE ON Comments
ADCs Only On 16 16 32 1 YES REFOUT Disabled
REFCAP Only On 0.8 0 0.8 0 NO REFOUT Disabled
REFCAP and REFOUT Only On 3.5 0 3.5 0 NO
All Sections Off 0.1 1.9 2.0 0 YES MCLK Active Levels
Equal to 0 V and DVDD
All Sections Off 0 0.05 0.06 0 NO Digital Inputs Static and
Equal to 0 V and DVDD

ABSOLUTE MAXIMUM RATINGS* Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

(TA = 25°C unless otherwise noted.) SOIC, JA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W
AVDD, DVDD to GND . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Lead Temperature, Soldering
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Digital I/O Voltage to DGND . . . . . . –0.3 V to DVDD + 0.3 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
Operating Temperature Range Industrial (A Version) nent damage to the device. This is a stress rating only; functional operation of the
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C device at these or any other conditions above those listed in the operational
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the ADSST-EM-3035 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

DataSheet4U.com

–10– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
PIN CONFIGURATION
VINP2 1 28 VINN3
VINN2 2 27 VINP3
VINP1 3 26 VINN4
VINN1 4 25 VINP4
REFOUT 5 24 VINN5
ADSST-
REFCAP 6 73360AR 23 VINP5
AVDD2 7 TOP VIEW 22 VINN6
(Not to Scale)
AGND2 8 21 VINP6

DGND 9 20 AVDD1
DVDD 10 19 AGND1
RESET 11 18 SE
SCLK 12 17 SDI
MCLK 13 16 SDIFS
SDO 14 15 SDOFS

PIN FUNCTION DESCRIPTIONS

Mnemonic Function Mnemonic Function

VINP1 Analog Input to the Positive Terminal of Input RESET Active Low Reset Signal. This input resets the entire chip,
Channel 1 resetting the control registers and clearing the digital
circuitry.
VINN1 Analog Input to the Negative Terminal of Input
Channel 1 SCLK Output Serial Clock whose rate determines the serial trans-
fer rate to/from the ADSST73360AR. It is used to clock
VINP2 Analog Input to the Positive Terminal of Input data or control information to and from the serial port
Channel 2 (SPORT). The frequency of SCLK is equal to the frequency
VINN2 Analog Input to the Negative Terminal of Input of the master clock (MCLK) divided by an integer number
et4U.com This integer number being the product of the external
DataShee
Channel 2
master clock rate divider and the serial clock rate divider.
VINP3 Analog Input to the Positive Terminal of Input
DataSheet4U.com
Channel 3 MCLK Master Clock Input. MCLK is driven from an external
clock signal.
VINN3 Analog Input to the Negative Terminal of Input
Channel 3 SDO Serial Data Output of the ADSST-73360AR. Both data
and control information may be output on this pin and are
VINP4 Analog Input to the Positive Terminal of Input clocked on the positive edge of SCLK. SDO is in three-
Channel 4 state when no information is being transmitted and when
SE is low.
VINN4 Analog Input to the Negative Terminal of Input
Channel 4 SDOFS Framing Signal Output for SDO Serial Transfers. The
frame sync is one bit wide and it is active one SCLK period
VINP5 Analog Input to the Positive Terminal of Input
before the first bit (MSB) of each output word. SDOFS
Channel 5
is referenced to the positive edge of SCLK. SDOFS is
VINN5 Analog Input to the Negative Terminal of Input in three-state when SE is low.
Channel 5
SDIFS Framing Signal Input for SDI Serial Transfers. The frame
VINP6 Analog Input to the Positive Terminal of Input sync is one bit wide and it is valid one SCLK period
Channel 6 before the first bit (MSB) of each input word. SDIFS is
sampled on the negative edge of SCLK and is ignored
VINN6 Analog Input to the Negative Terminal of Input when SE is low.
Channel 6
SDI Serial Data Input of the ADSST-73360AR. Both data
REFOUT Buffered Reference Output, which has a nominal value and control information may be input on this pin and are
of 1.2 V or 2.4 V, the value being dependent on the clocked on the negative edge of SCLK. SDI is ignored
status of Bit 5 VEN (CRC:7). This pin can be overdriven when SE is low.
by an external reference if required.
SE SPORT Enable. Asynchronous input enable pin for the
REFCAP A Bypass Capacitor to AGND2 of 0.1 µF is required SPORT. When SE is set low by the DSP, the output pins
for the on-chip reference. The capacitor should be of the SPORT are three-stated and the input pins are
fixed to this pin. ignored. SCLK is also disabled internally in order to decrease
AVDD2 Analog Power Supply Connection power dissipation. When SE is brought high, the control
and data registers of the SPORT are at their original values
AGND2 Analog Ground/Substrate Connection (before SE was brought low. However, the timing counters
and other internal registers are at their reset values.
DGND Digital Ground/Substrate Connection
AGND1 Analog Ground Connection
DVDD Digital Power Supply Connection
DataSheet4U.com AVDD1 Analog Power Supply Connection

REV. 0 –11–
DataSheet 4 U .com
 www.DataSheet4U.com

ADSST-EM-3035
Grounding and Layout and DGND respectively, with 0.1 µF ceramic capacitors in
parallel with 10 µF tantalum capacitors. To achieve the best
ANALOG GROUND from these decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against it. In systems
where a common supply voltage drives both the AVDD and
DVDD of the ADSST-73360AR, it is recommended that the
system’s AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the ADSST-73360AR and AGND and the recommended
digital supply decoupling capacitors between the DVDD pin
and DGND.
DIGITAL GROUND NOTE: FOR MORE DETAILS ON ADSST-73360AR, PLEASE
REFER TO DATA SHEET OF AD73360
Figure 5. Grounding and Layout
Interfaces between ADSST-EM-3035 and Microcontroller
Since the analog inputs to the ADSST-73360AR are differential, Overview
most of the voltages in the analog modulator are common-mode The following paragraphs describe the interface between the
voltages. The excellent common-mode rejection of the part will ADSST-EM-3035 chipset and the microcontroller. The sequence
remove common-mode noise on these inputs. The analog and of operations is a critical issue for proper functioning of the two
digital supplies of the ADSST-73360AR are independent and processors on the board. The DSP processor is primarily used to
separately pinned out to minimize coupling between analog and compute various parameters, provide the impulse outputs on the
digital sections of the device. The digital filters on the encoder external LEDs and provide automatic gain switching inside the
section will provide rejection of broadband noise on the power ADC. The microcontroller can collect the data from the chipset
supplies, except at integer multiples of the modulator sampling for data management for further processing. There are two basic
frequency. The digital filters also remove noise from the analog functions that the microcontroller performs in a handshaking
inputs provided the noise source does not saturate the analog mode with the DSP processor:
modulator. However, because the resolution of the ADSST-
• Boot loading the DSP with metering software on power up
et4U.com73360LAR ADC is high, and the noise levels from the (for non-ROM coded version only) DataShee
ADSST-73360AR are so low, care must be taken with regard to
grounding and layout. • Communication with the DSP on SPI to:
DataSheet4U.com
The printed circuit board that houses the ADSST-73360AR Send Initialization data on power up after boot loading the
should be designed so the analog and digital sections are sepa- DSP with metering software
rated and confined to certain sections of the board. The Receive data from DSP during normal operation
ADSST-73360AR pin configuration offers a major advantage in
Receive and send data during calibration
that its analog and digital interfaces are connected on opposite
sides of the package. This facilitates the use of ground planes This section describes the Boot loading and SPI operations.
that can be easily separated, as shown in Figure 5. A minimum
etch technique is generally best for ground planes as it gives the BOOT LOADING THE DSP PROCESSOR FROM THE
best shielding. Digital and analog ground planes should be MICROCONTROLLER
joined in only one place. If this connection is close to the device, The DSP processor has an internal program memory RAM that
it is recommended to use a ferrite bead inductor as shown in supports boot loading. With boot loading, the processor reads
Figure 5. instructions from a byte-wide data bus connected to the microcon-
troller and stores the instructions in the 24-bit wide internal
Avoid running digital lines under the device for they will couple
program memory. The host microcontroller, is the source of
noise onto the die. The analog ground plane should be allowed
bytes to be loaded into on-chip memory. The choice of which
to run under the ADSST-73360AR to avoid noise coupling.
technique to use depends upon the I/O structure of the host
The power supply lines to the ADSST-73360AR should use as
microcontroller, availability of I/O port lines, and the amount
large a trace as possible to provide low impedance paths and
of address decoding logic already available in the system. The
reduce the effects of glitches on the power supply lines. Fast
description here is one of the many ways that this could be
switching signals such as clocks should be shielded with digital
configured. However, the software on the microcontroller has
ground to avoid radiating noise to other sections of the board,
been written in way to make optimum use of the configuration.
and clock signals should never be run near the analog inputs.
Traces on opposite sides of the board should run at right angles Figure 6 illustrates the system implementation to allow a
to each other. This will reduce the effects of feedthrough microcontroller to boot the DSP processor. The only hardware
through the board. A micro-strip technique is by far the best but required is a D-type flip-flop and a 5 kΩ resistor. The resistor
is not always possible with a double-sided board. In this tech- is used to pull the DSP processor’s BMS pin (Boot Memory
nique, the component side of the board is dedicated to ground Select) high.
planes while signals are placed on the other side. The DSP processor boots using the BDMA option. The BDMA
Good decoupling is important when using high speed devices. option can be used when pins Mode A, Mode B, and Mode C on
All analog and digital supplies should be decoupled to AGND the DSP are tied low. With these pins tied low the DSP auto-
DataSheet4U.com matically enters its boot sequence after the processor is reset.

–12– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
In the sequence of booting the DSP, it has to be loaded with an program code, it will overwrite the first 113 words (i.e., 339
object code into the internal program memory. The byte wide bytes). After reading 20136 bytes, it will start execution auto-
memory boot code file has the following structure: matically.
a) 32 words or 96 bytes of the initial header, The process of loading the code to the DSP is as follows:
b)81 words or 243 bytes for initializing BDMA and associated • After the microcontroller is reset, hold DSP in reset by bringing
registers, reset pin low.
c) 6712 words or 20136 bytes of program code. • Make PX high and clock PY (low to high transition). This will
make BR low. In effect, the DSP will not read because it has
VDD granted its buses since BR is asserted.

C DSP
5k • Put the first byte of the program code on the DSP bus D8 to
BMS
D15 and deassert BR, which is done by taking PX low and
clocking a transition on PY (low to high). Since the DSP buses
PX D PR
have been released, it will read the byte and assert BMS. The
74L574 assertion of BMS will cause the flip-flop to preset (PR on 74LS74)
itself and therefore BR is again asserted.
O
PY CLK BR
• Continue this process byte by byte for 96 bytes and give a
PZ RESET small delay.
• After the delay continue the byte loading process for the next
D0–D7 D0–D7 D8–D15 243 bytes and give a small delay again.
•
FLASH
Continue the byte loading process for 20136 bytes.
D0–D7
CLOCK • Soon after the last program byte is loaded, the DSP starts
Figure 6. System Architecture for Boot Loading DSP execution of the code.
Processor From Microcontroller At the start of execution, the DSP waits for uploading of 154
bytes of data consisting of calibration constants (gain & dc offsets),
When the DSP is reset with the pins Mode A, Mode B, and
et4U.com E-pulse constants and filter coefficients. This data has to be sentDataShee
Mode C tied low, it enters into the byte wide memory data
to the DSP processor on the SPI port. Until the DSP receives
access mode. The boot loading process will consist of the DSP
the 154 bytes, the actual process of executing the metering code
DataSheet4U.com
reading the first 32 words, a small delay, say one millisecond for
on the DSP does not start. Soon after receiving all the constants
it execute these 32 words of program. The DSP will then read
(i.e. 154 bytes) the metering process starts. Four dummy bytes
the next 81 words. After which a small delay, of say one milli-
have to be sent after the start of execution for the DSP to send
second, will be required for it to execute these 81 words. The
back the check sum of its internal code. The microcontroller can
DSP will now (with BDMA registers initialized) read the code
use this to verify that the complete metering code has been
length also initialized in the previous process. It should be noted
loaded on the DSP processor properly. The DSP is now ready
that when the DSP reads the 20136 bytes from its port of the
to provide the computed data on the SPI port.

1ST BYTE OF DATA

DATA
D0–D7

T1 MINIMUM 6 DSP
PIN BOOT 1 CLOCK CYCLES

PIN BOOT 2

BR

BMS

Figure 7. Timing Diagram for Boot Loading the DSP Processor

DataSheet4U.com

REV. 0 –13–
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
SERIAL PERIPHERAL INTERFACE (SPI) AND CONTROL data train. The data received from the DSP will be in the
The DSP and the microcontroller are interfaced through Serial same sequence as described in Table IV. If the micro-
Peripheral Interface (SPI). The microcontroller is always config- controller does not require all the parameters then it may
ured as a master and the DSP as a slave. stop sending dummy bytes at any time.
FRAMING SIGNAL
The diagram below shows the sequence of operation.

RFS
DSP
CONTROL
TF FRAMING SIGNAL

SPI
DR TRANSMIT CLOCK

SPI
DT
RECEIVE

DATA
SCLK CLK

Figure 9. SPI Sequence of Operation

FL2 INTERRUPT
Quadrant and Other Conventions
DSP MICROCONTROLLER The data sent by the DSP is based on the following convention:
Figure 8. Serial Peripheral Interface and Control • Figure 10 gives the quadrant convention used by the chipset.
• Import means delivered from the utility to the user.
SPI OPERATION • Export means delivered by the user to the utility.
There are two modes of communication between DSP and
microcontroller. • Total means total of all three phases.
et4U.com DataShee
• Microcontroller to DSP (while uploading the initial data of – REACTIVE
154 bytes, including four bytes to read checksum of code
DataSheet4U.com ACTIVE EXPORT ACTIVE IMPORT
from DSP, and sending a command)
Bring the DSP_control pin low, i.e., give a high to low
transition. This informs the DSP that the data after this
CAPACITIVE
transition is a valid data.
Send the data byte on the microcontroller’s SPI port. Since
the microcontroller is configured as a master, the clock Q2 Q1
signal will be generated by the microcontroller and the
DSP being a slave will read the data byte in sync with the
Q3 Q4
clock signal. Bring DSP_control signal back to high state.
• DSP to Microcontroller (while transmitting computed data
to the microcontroller) INDUCTIVE

The DSP during its metering code execution, is ready to

give the computed parameters to the microcontroller after
every 32 cycles of power line.
To request data from the DSP, the microcontroller sends a + REACTIVE

request code 45h on the SPI bus. Figure 10.

The DSP then sends a high to low transition on Pin FL2 Power Up Initialization
soon after it completes the next 32 cycles of computation as To reduce the component count, cost and to give designer a
an indication to the microcontroller that it is ready to greater flexibility in designing, ADSST-EM-3035 has not been
transmit most recent data. provided with any Nonvolatile Memory to store the calibration
Since the microcontroller is a master, it has to now send constants and initialization data. On power up, after the boot
clock signal to the DSP on the SPI to receive data. For the loading of the DSP software, the microcontroller provides the
clock signal to be generated, the microcontroller has to DSP with all the initialization data. After receiving the initializa-
send a dummy byte. The dummy byte (say, 0xFF) should tion data the DSP starts the metering. The table below list outs
be one that is not recognized by the DSP as a command. the data that has to be transferred to the DSP on power up.
The microcontroller may send as many dummy bytes as it
requires up to a maximum of 522 bytes for the complete
DataSheet4U.com

–14– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
Table III. Data Transfer to DSP on Power-Up Data from DSP to Microcontroller
To facilitate easy of operation, the data transfer form DSP to
Initialization Gain Constants microcontroller has been segregated into multiple blocks.
and DC Offsets Value Defaults Table IV lists the various data blocks:
R Phase Voltage Gain 2 4000h
Y Phase Voltage Gain 2 4000h Table IV. Data Transfer Sequence from DSP to Microcontroller
B Phase Voltage Gain 2 4000h
DATA from DSP on SPI BUS Byte(s)
R Phase Current Low Gain 2 4000h
Y Phase Current Low Gain 2 4000h REQUEST CODE 45h 1
B Phase Current Low Gain 2 4000h R Phase Voltage 2
R Phase Current High Gain 2 4000h R Phase Current 2
Y Phase Current High Gain 2 4000h R Phase Active Power 4
B Phase Current High Gain 2 4000h R Phase Apparent Power 4
R Phase Voltage DC Offset 2 0 R Phase Inductive Power 4
Y Phase Voltage DC Offset 2 0 R Phase Capacitive Power 4
B Phase Voltage DC Offset 2 0 R Phase Power Factor 2
R Phase Current Low Gain DC Offset 2 0 R Phase Active Energy Import 4
Y Phase Current Low Gain DC Offset 2 0 R Phase Apparent Energy 4
B Phase Current Low Gain DC Offset 2 0 R Phase Inductive Energy 4
R Phase Current High Gain DC Offset 2 0 R Phase Active Energy Export 4
Y Phase Current High Gain DC Offset 2 0 R Phase Capacitive Energy 4
B Phase Current High Gain DC Offset 2 0 Y Phase Voltage 2
E-pulse (Type)* Y Phase Current 2
Energy Pulse eφ = active Y Phase Active Power 4
e1 = Apparent 1 1 Y Phase Apparent Power 4
Pulse E-pulse Constant Y Phase Inductive Power 4
Range from 1,000–20,000 Impulse Constant 1 2 2000 Y Phase Capacitive Power 4
et4U.com (pulses/kWh) Y Phase Power Factor 2 DataShee
Pulse E-pulse Constant Range from 1,000–20,000 2 2000 Y Phase Active Energy Import 4
DataSheet4U.com
Y Phase Apparent Energy 4
PHASE COMPENSATION VARIABLES
Y Phase Inductive Energy 4
R Phase Coeff for High Current Range 12 0000, Y Phase Active Energy Export 4
0000, Y Phase Capacitive Energy 4
7FFF, B Phase Voltage 2
0000, B Phase Current 2
0000, B Phase Active Power 4
0000 B Phase Apparent Power 4
R Phase Coeff for Middle Current Range 12 -Do- B Phase Inductive Power 4
R Phase Coeff for Low Current Range 12 -Do- B Phase Capacitive Power 4
Y Phase Coeff for High Current Range 12 -Do- B Phase Power Factor 2
Y Phase Coeff for Middle Current Range 12 -Do- B Phase Active Energy Import 4
Y Phase Coeff for Low Current Range 12 -Do- B Phase Apparent Energy 4
B Phase Coeff for High Current Range 12 -Do- B Phase Inductive Energy 4
B Phase Coeff for Middle Current Range 12 -Do- B Phase Active Energy Export 4
B Phase Coeff for Low Current Range 12 -Do- B Phase Capacitive Energy 4
*The first byte to be sent for initialization is 45h followed by all the above tabled
Total Active Power 4
parameters in the same sequence. Total Apparent Power 4
Total Inductive Power 4
Phase Compensation Coefficients
Total Capacitive Power 4
Three sets of filter coefficients have been provided which will be
Average Power Factor 2
automatically selected by the DSP during execution based on
Total Active Energy Import 4
the maximum current (Imax). In the ADSST-EM-3035, the
Total Apparent Energy 4
Imax is fixed at 20 Amps. Therefore the current ranges have
Total Inductive Energy 4
been grouped as:
Total Active Energy Export 4
• High current range: From 20 Amps to 7 Amps Total Capacitive Energy 4
• Middle current range: 7 Amps to 1.5 Amps Frequency 2
R Phase Channel_Present 1
• Low current range: 1.5 Amps to 0 Amps Y Phase Channel_Present 1

DataSheet4U.com

REV. 0 –15–
DataSheet 4 U .com
 www.DataSheet4U.com

ADSST-EM-3035
DATA from DSP on SPI BUS Byte(s) Table V. Interpretation of the Voltage Data

B Phase Channel_Present 1 Phase Voltage Data

R Phase Current Division FlagUnits_flag_R 1 from DSP
Y Phase Current Division FlagUnits_flag_Y 1 Hex (2 byte) Decimal Voltage
B Phase Current Division FlagUnits_flag_B 1
R Phase Negative Power Flag 1 5A10h 23056 230.56 V
Y Phase Negative Power Flag 1
B Phase Negative Power Flag 1 Table VI. Interpretation of the Current Data
R Phase (INDUC/CAP POWER Flag) 1
Y Phase (INDUC/CAP POWER Flag) 1 Line Current Data Unit
B Phase (INDUC/CAP POWER Flag) 1 from DSP flag_X
Hex (2 Byte) Decimal (X = R/Y/B) Current
GAIN CONTRASTS AND DC OFFSETS
278Bh 10123 1 1.0123 A
R Phase Voltage Gain 2
278Bh 10123 0 10.123 A
Y Phase Voltage Gain 2
B Phase Voltage Gain 2 Frequency Data from DSP
R Phase Current Low Gain 2 The frequency data is with two decimal places. This means that
Y Phase Current Low Gain 2 the value has to be divided by 100 to get the frequency. For
B Phase Current Low Gain 2 example, if DSP data = 139Fh (decimal value = 5023), then the
R Phase Current High Gain 2 frequency is 50.23 Hz
Y Phase Current High Gain 2 Interpretation of the Power Data
B Phase Current High Gain 2 As in the case of current and voltages, described above, all the
R Phase Voltage DC Offset 2 power data supplied by DSP has to be interpreted, as shown in
Y Phase Voltage DC Offset 2 Table VII.
B Phase Voltage DC Offset 2
R Phase Current Low Gain DC Offset 2 The data received from the DSP is in a 4-byte format. The least
Y Phase Current Low Gain DC Offset 2 significant word comes first and the most significant word
et4U.com comes last, e.g., 000D1C4A will come as 1C4A000D and this DataShee
B Phase Current Low Gain DC Offset 2
R Phase Current High Gain DC Offset 2 word reversal has to be performed by the controller.
Y Phase Current High Gain DC Offset 2 DataSheet4U.com
B Phase Current High Gain DC Offset 2 Table VII. Interpretation of the Power Data
DC_Offset Calibration Done (EFh) 1
Power Data from DSP
Total Negative Power Flag 1
Total Inductive Capacitive Flag 1 Hex (4-Byte) Decimal Power
HARMONIC ANALYSIS DATA 000D1C4A 859210 859.210 W
(All odd harmonics sequenced from fundamental Interpretation of the Power Factor Data
to 21st order, total 11 harmonics of 2 bytes each) The DSP data for power factor has a resolution up to four deci-
R Phase Voltage Components Magnitude 2 ⫻ 11 = 22 mal places. To get the value of Power Factor the DSP data has
R Phase Current Components Magnitude 22 to be divided by 10,000.
R Phase Voltage Components Phase 22
R Phase Current Components Phase 22 Table VIII. Interpretation of the Power Factor Data
Y Phase Voltage Components Magnitude 22
Y Phase Current Components Magnitude 22 Power Factor Data
Y Phase Voltage Components Phase 22 from DSP
Y Phase Current Components Phase 22 Hex (2-Byte) Decimal Power Factor
B Phase Voltage Components Magnitude 22
B Phase Current Components Magnitude 22 1388h 5000 0.5
B Phase Voltage Components Phase 22 Interpretation of the Energy Data
B Phase Current Components Phase 22 The DSP data for energy has a resolution up to four decimal
places. To get the value of Energy the DSP data has to be
divided by 10,000.

Table IX. Interpretation of the Energy Data

Energy Data
from DSP
Hex (4-Byte) Decimal Energy

DataSheet4U.com 000D1C4Ah 859210 85.9210 kWh

–16– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
Interpretation of Harmonics Data The reference design has a CT with turn ratio of 1:2500 and
Each harmonic data from DSP is two byte wide. The voltage burden resistance of 82 Ω. This generates 0.656 V rms or 0.928 V
and phase angle values have a resolution of up to second deci- (0–pk) at 20 amps current. This leaves enough margins for cur-
mal place and the current has up to third decimal place. rent pulses or low crest factor loads, such as electronic loads
such as SMPS.
INPUT SECTION The maximum current can be up to 32.767 amps.
PHASE VOLTAGE
CALIBRATION
1M
ADSST-EM-3035 Chipset has a highly advance calibration
100 TO ADC
routines embedded into the software. Easy of calibration is the
philosophy in ADSST-EM-3035 Chipset. ADSST-EM-3035
0.001
F chipset enables dc offset and gain computation on the voltage
3.3k
NEUTRAL and current channels and also performs phase and nonlinearity
GND PDSP
compensation on the current transformer. Calibrations for
power is done internally and no extra procedure is required for
LINE CURRENT 100 TO ADC
it. This section describes the calibration procedure required.
82 0.01
F
Voltage Gain Calibration
To calibrate voltage channel:
*VALUE MAY CHANGE ACCORDING
GND VCC • Inject a known voltage (VI ) to the meter based on ADSST-
EM-3035
Figure 11. Input Section
• Note the voltage read by meter say VM
ADSST-73360AR has an input range of VREF + (VREF
0.6525)
to VREF – (VREF
0.6525) V p-p (0.856 V to 4.14 V for 2.5 V
• Voltage gain coefficient = (VI/VM)
0x4000.
VREF). This limit defines the resistance network on the potential • The calculated coefficients are to be communicated to the
circuits and the burden resistance on the secondary side of the microcontroller for storage.
et4U.com
CT. ADSST-73360AR being a unipolar ADC the ac, poten- • Repeat the same procedure for all the three channels DataShee
tial, and current have to be offset by a desired dc level. The
reference design has a dc offset of 2.5 V. This limits the p-p • Note: Where 0x4000 is default coefficient in hex
signal range of potential and current to ± 1.64 V peak or DataSheet4U.com
Current Gain Calibration
1.16 V rms. The Current Gain calibration is performed at two current set-
For details please refer to the data sheet of AD73360. tings to compute two current gain coefficients, namely current
high gain and current low gain coefficients. In all six current
Potential Section gain coefficients are calculated for all the three phase currents.
The selection of potential divider circuit should be such that it can: The gains are calculated at:
• Handle high surge voltages • I1 = 20 A
• Should have minimum VA burden • I2 = 5 A
• Give approximately 0.656 V rms output at nominal voltage Inject the meter with current value I1
such that it sufficiently takes care of over voltage.
Note the value of the current sent by meter (IM)
• The reference design has 1 MΩ and 3.3 kΩ resistance
network. Current low gain coefficient = (I1/IM)
0x4000
Current Section Inject the meter with I2 current
The selection of CT ratio and burden resistance should be such Note the value of the current sent by meter (IM)
that it can Current high gain coefficient = (I2/IM)
0x4000
• Handle the complete dynamic range for the current signal input. The calculated coefficients are to be communicated to the
• Give around 1 V(0–pk) output at maximum current such that microcontroller for storage
it sufficiently takes of loads with low crest factors and Repeat the procedure for other Phases
current surges.
DC Offset Calibration for Voltage and Current
Writing EFh to DSP on SPI initiates the dc offset calibration in
the DSP. After 32 cycles the DSP returns back the offset values
and sends FEh as a mark of completion on the SPI. The
microcontroller has to store the dc offset constants for uploading
during power up.

DataSheet4U.com

REV. 0 –17–
DataSheet 4 U .com
 www.DataSheet4U.com

ADSST-EM-3035
Table X. DC Offset Calibration Data • Calculate the normalized lag value (LA, LB, LC) for each phase
as under :
Command from Setup Input
DC-Offset Microcontrolled Voltage and
Calibration in Hex Current 60° – PA
LA = +2 (1)
1.20
Offset 0xEF V = Nominal
Calibration Voltage 60° – PB
(All Three Phases) I=0 LB = +2 (2)
1.20
The microcontroller now issues 0x45H command on SPI to the
DSP. The DSP sends back Table IV. This table will contain
new dc-offset coefficients. The microcontroller should store 60° – PC
LC = +2 (3)
these coefficients. 1.20
Procedure • Run ADSSTCOMP.EXE on PC
• Power up the meter with nominal voltage • Feed the normalized lag value during the execution of
ADSSTCOMP.EXE.
• Give command for calculation of the coefficient (EFh) to
DSP on SPI. • The ADSSTCOMP.EXE will provide six coefficients for each
phase and the size of each coefficient is 2 bytes.
• Receive the coefficient by sending Ox45 on SPI after waiting
at least 1s. • The phase compensation should be performed for the three
currents on each phase. These coefficients must be stored in a
• Store the coefficient
suitable location such that DSP can get these coefficients on
Phase Compensation power up in the same sequence as shown in Table III.
The ADSST-EM-3035 employs a patent pending algorithm for
Configuration of Output E-pulses
phase compensation and non-linearity. This also reduces the
The ADSST-EM-3035 Chipset provides two pulse outputs
cost of the end product by reducing the cost of the sensing ele-
ments i.e., CT. To compensate for the phase non-linearity in • Configurable for Active energy or Apparent energy
et4U.comCTs, the compensation is performed at three current ranges. • Reactive energy DataShee
The three current ranges for calibration are:
• Table III gives the default conditions and configuration for
• 20 A > I1 > 7 A DataSheet4U.com
first E-pulse.
• 7 A > I2 > 1.5 A • The E-pulse constant is variable from 1,000 pulses/kWh to
• 1.5 A > I3 > 0 A 20,000 pulses/kWh.
Procedure • Example: To set 1,500 pulses/kWh, the new E-pulse con-
• The ADSSTCOMP.EXE supplied with the chipset is an stant will be 1,500
executable file for calculation of the phase compensation Inaccuracy of the E-pulse
coefficients. Higher E-pulse constant is always desirable as it reduces the
• Set the voltage equal to 230 V which is the nominal voltage at testing time. However, increase in pulses/kWh may increases the
all phases. error at higher power. The error can be calculated by the
given formula.
• Inject I1 current at 0.5 inductive (60° lagging) in all phases.
General Note About Calibration
• The chipset performs the harmonic analysis by providing
information about the magnitude and phase angle for all odd
• It should be noted that ADSST-EM-3035 does not have any
permanent memory and hence all the calibration data are to
harmonics sequenced from fundamental to 21st order. The
be stored by the microcontroller and provided to the DSP at
DSP sends the phase angle information along with other data
the time of power up.
as described in Table IV after sending the command 0x45.
• The value of the phase angle for line current A, B, and C is • Before starting the calibration the meter should be supplied with
the default calibration constants as specified in the Table III.
available at the locations 283, 371, and 459 respectively (say
PA, PB, PC) in the data stream sent by the DSP.

DataSheet4U.com

–18– REV. 0
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
• The whole calibration can be done in very few steps as shown MEASUREMENT ACCURACY
in the example below. Overall Accuracy, Power and Energy Measurement
Start meter with nominal voltage and calculate dc offset The accuracy figures are measured in nominal conditions
unless otherwise indicated. The measurement are taken on the
Set current at 20 A and calculate voltage gain and reference design with the given below nominal values.
low current gain for all channels
Reference Design with
Metal CT (0.5 Class)
Set current at 5 A and calculate low current gain for
all channels Table XI. Nominal Value: Reference Design Parameters
Set current at 20 A < I < 7 A and perform phase compensation
for all channels Parameters Nominal Value

Set current at 1.5 A < I < 7 A and perform phase compensation Nominal Voltage (Neutral to Line) VN VN = 230 V ± 1%
for all channels Max Voltage (Neutral to Line) 300 V
Max Current IMAX IMAX = 20 A
Set current at 1.5 A < I < 0 A and perform phase compensa- Base Current In = 5 A
tion for all channels Frequency FN = 50 Hz/60 Hz ± 10%
Power Factor 1
THD of Voltage < 2%
Temperature 23 ± 2°C

Table XII. Maximum Error (Power and Energies)

Current Voltage PF Min Typ Max Unit

0.01 In < I < 0.05 In VN 1.0 ± 0.1 ± 0.2 %
0.05 In < I < IMAX VN 1.0 ± 0.1 ± 0.2 %
0.02 In < I < 0.1 In VN 0.5 Lagging ± 0.15 ± 0.35 %
et4U.com DataShee
0.8 Leading ± 0.15 ± 0.35 %
0.1 In < I < IMAX VN 0.5 Lagging ± 0.1 ± 0.2 %
DataSheet4U.com
0.8 Leading ± 0.1 ± 0.2 %

Table XIII. Unbalanced Load Error

Current Voltage PF Min Typ Max Unit

0.05 In < I < IMAX VN 1.0 ± 0.15 ± 0.2 %
0.1 In < I < IMAX VN 0.5 Lagging ± 0.15 ± 0.2 %

Table XIV. Voltage Variation Error

Voltage Current PF Min Typ Max Unit

VN ± 10% 0.05 In < I < IMAX 1.0 ± 0.05 ± 0.1 %
VN ± 10% 0.1 In < I < IMAX 0.5 Lagging ± 0.05 ± 0.1 %

Table XV. Frequency Variation Errors

Frequency Current PF Min Typ Max Unit

VN ± 10% 0.05 In < I < IMAX 1.0 ± 0.05 ± 0.1 %
VN ± 10% 0.1 In < I < IMAX 0.5 Lagging ± 0.05 ± 0.1 %

DataSheet4U.com

REV. 0 –19–
DataSheet 4 U .com
www.DataSheet4U.com

ADSST-EM-3035
Table XVI. Harmonic Distortion Error Table XVIII. Voltage Unbalance Error

Current Current Min Typ Max Unit Current Voltage Min Typ Max Unit
10% of Third 0.05 In < I < IMAX ± 0.05 ± 0.1 % In VN ± 15 ± 0.1 ± 0.2 %
Harmonic
Table XIX. Starting Current
Table XVII. Reverse Phase Sequence Error

C02740–0–11/02(0)
Voltage Min Typ Max Unit
Current Voltage Min Typ Max Unit
VN 0.0007 0.001 In
0.1 In VN ± 0.05 %
RECOMMENDED OPERATING CONDITIONS

A Grade B Grade
ELECTRICAL CHARACTERISTICS OF ADSST-EM-3035 Parameters Min Max Min Max Unit
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V VDD 7 0 7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Temperature 0 +70 –40 +85 °C
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Ordering Codes
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C A Grade: ADSST-EM-3035-BST
B Grade: ADSST-EM-3035-KST

ORDERING GUIDE

Temperature
Model Range Model Included Package Option
ADSST-EM-3035K 0 to +70ºC ADSST-2185KST-133 SU-100
et4U.com
ADSST-73360AR RW-28
DataSheet4U.com

OUTLINE DIMENSIONS

100-Lead Thin Plastic Quad Flat Package [TQFP] 28-Lead Standard Small Outline Package [SOIC]
(SU-100) Wide Body
Dimensions shown in millimeters (RW-28)
Dimensions shown in millimeters and (inches)
0.75 1.20 16.00 SQ
MAX 18.10 (0.7126)
0.60 14.00 SQ
0.45 17.70 (0.6969)
100 76
1 75
SEATING 28 15
PLANE 7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
1 14
10.00 (0.3937)
TOP VIEW
(PINS DOWN)

PRINTED IN U.S.A.
2.65 (0.1043) 0.75 (0.0295)
2.35 (0.0925) ⴛ 45ⴗ
0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
25 50 8ⴗ
26 49 1.27 (0.0500) 0.51 (0.0201) SEATING 0ⴗ 1.27 (0.0500)
COPLANARITY 0.32 (0.0126)
1.05 0.10
BSC 0.33 (0.0130) PLANE 0.40 (0.0157)
0.23 (0.0091)
1.00
7ⴗ 0.95 COMPLIANT TO JEDEC STANDARDS MS-013AE
0ⴗ CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
0.27 0.15 REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.50 BSC
0.22 0.05
0.17

COMPLIANT TO JEDEC STANDARDS MS-026AED-HD

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

DataSheet4U.com

–20– REV. 0
DataSheet 4 U .com