FALL SEMESTER 2021-2022

ECE5017 – Digital Design with FPGA

J COMPONENT

GROUP NO: 12

TITLE: DESIGN OF SIMPLE PROCESSOR

UNDER GUIDANCE OF:

PROF. NITISH KUMAR V

M. Tech VLSI Design

School of Electronics Engineering

Vellore Institute of Technology

Slot: B2

Submitted by:
Name Registration Number
Linu Phil Mathew 21MVD0077
Krishna Sri AK 21MVD0090
Munagala Tejaswini 21MVD0100
Shreya Roy 21MVD0106
Naomi Mallik 21MVD0115
Amit Verma 21MVD0142
 Date: 13/01/2022

J COMPONENT
Design of Simple Processor
AIM:
To design, write a Verilog code and verify the design by writing testbench of Simple
Processor as the Figure shown below shows a digital system that contains a number
of 9-bit registers, a multiplexer, an adder/subtractor unit, and a control unit (finite
state machine).

Each instruction can be encoded and stored in the IR register using the 9-bit format
IIIXXXYYY, where III represents the instruction, XXX gives the Rx register, and
YYY gives the Ry register. Although only two bits are needed to encode our four
instructions, we are using three bits because other instructions will be added to the
processor in later parts of this exercise. Instructions are loaded from an external
source, hence IR has to be connected to the nine bits of the DIN input, as indicated
in Figure 1. For the mvi instruction the YYY field has no meaning, and the immediate
data #D has to be supplied on the 9-bit DIN input after the mvi instruction word is
stored into IR. Some instructions, such as an addition or subtraction, take more than
one clock cycle to complete, because multiple transfers have to be performed across
the bus. The processor starts executing the instruction on the DIN input when the
Run signal is asserted and the processor asserts the ‘Done’ output when the
instruction is finished. Table 2 indicates the control signals that can be asserted in
each time

And to synthesize it using Intel Quartus Prime.

BLOCK DIAGRAM:

Fig: Multiplexer Submodule

 Fig: Control Unit Submodule

VERILOG CODES TO IMPLEMENT SUB MODULES:

MULTIPLEXER MODULE:
module mux_add(R0in, R1in,R2in,R3in,R4in,R5in,R6in,R7in, DIn,sel, clk, R0,R1, R2, R3,
R4, R5,R6, R7, LdA, LdG, Add_sub);
input R0in, R1in,R2in,R3in,R4in,R5in,R6in,R7in, LdA, LdG, Add_sub;
input [8:0] DIn;
output [8:0] R0,R1, R2, R3, R4, R5,R6, R7;
input [9:0] sel;
input clk;
wire [8:0] bus,G;
Reg_store ha2(R0in, R1in,R2in,R3in,R4in,R5in,R6in,R7in,bus,R0,R1, R2, R3, R4, R5,R6,
R7,clk);
multiplex10_to_1 ha1 (R0,R1, R2, R3, R4, R5,R6, R7,DIn,G,sel,bus);
adder_subtractor g01 (LdA, LdG, Add_sub,bus, clk, G);
endmodule

module Reg_store(R0in, R1in,R2in,R3in,R4in,R5in,R6in,R7in,bus,R0,R1, R2, R3, R4,

R5,R6, R7,clk);
input R0in, R1in,R2in,R3in,R4in,R5in,R6in,R7in;
input [8:0] bus;
input clk;
output reg [8:0] R0= 9'd0,R1= 9'd0, R2= 9'd0, R3= 9'd0, R4= 9'd0, R5= 9'd0,R6= 9'd0, R7 =
9'd0;

always @ (posedge clk)

begin
if (R0in || R1in || R2in || R3in || R4in || R5in || R6in || R7in)
begin
if(R0in == 1)
R0 <= bus;
if (R1in == 1)
R1 <= bus;
if (R2in == 1)
R2 <= bus;
if (R3in == 1)
R3 <= bus;
if (R4in == 1)
R4 <= bus;
if (R5in == 1)
R5 <= bus;
if (R6in == 1)
R6 <= bus;
if (R7in == 1)
R7 <= bus;
end
else
begin
R0 <= R0;
R1 <= R1;
R2 <= R2;
R3 <= R3;
R4 <= R4;
R5 <= R5;
R6 <= R6;
R7 <= R7;
end
end
endmodule

module multiplex10_to_1
(Reg0in,Reg1in,Reg2in,Reg3in,Reg4in,Reg5in,Reg6in,Reg7in,DIn,G,sel,bus);
input [8:0] Reg0in,Reg1in,Reg2in,Reg3in,Reg4in,Reg5in,Reg6in,Reg7in,DIn,G;
input [9:0] sel;
//input Reg0out, Reg1out, Reg2out, Reg3out, Reg4out, Reg5out, Reg6out,
Reg7out,Din_out,G_out;
output reg [8:0] bus;
always @ (sel or DIn or G)
begin
if (sel == 10'b0000000001)
bus <= DIn;
else if (sel == 10'b0000000010)
bus <= G;
else if (sel == 10'b0000000100)
bus <= Reg7in;
else if (sel == 10'b0000001000)
bus <= Reg6in;
else if (sel == 10'b0000010000)
bus <= Reg5in;
 else if (sel == 10'b0000100000)
bus <= Reg4in;
else if (sel == 10'b0001000000)
bus <= Reg3in;
else if (sel == 10'b0010000000)
bus <= Reg2in;
else if (sel == 10'b0100000000)
bus <= Reg1in;
else if (sel == 10'b1000000000)
bus <= Reg0in;
else
bus <= bus;
end
endmodule

ADDER/SUBTRACTOR MODULE:
module adder_subtractor (LdA, LdG, Add_sub,data_in, clk,Z1);
input LdA, LdG, Add_sub,clk;
// Add_sub=1 add else subtract
// data_in is the output of the mux
input [8:0] data_in;
output reg [8:0] Z1;
reg [8:0] X1 ;
wire [8:0] X, Y, Z, Bus;
assign Bus = data_in;

always @ (posedge clk)

begin
X1 <= X;
Z1 <= Z;
end

// X is output of the Register A

PIPO1 A (X,Bus, LdA, clk);
//PIPO1 (dout, din, ld, clk);

// Y is output of the adder

// Adder block
add_sub h01 (Y, Bus,X, Add_sub);
//add_sub (out, in1, in2);

// Z is output of the Register G

PIPO1 B (Z,Y, LdG, clk);
//PIPO1 (dout, din, ld, clk);

endmodule
module PIPO1 (dout, din, ld, clk);
input [8:0] din;
input ld, clk;
output reg [8:0] dout;

always @(posedge clk)

if (ld) dout <= din;
endmodule

module add_sub (out, in1, in2,Add_sub);

input [8:0] in1, in2;
output reg [8:0] out;
input Add_sub;
always @(*)
begin
if(Add_sub)
out = in1 + in2;
else
out = in1-in2;
end
endmodule

MAIN MODULE/ CONTROL UNIT:

module proc (DIN, Resetn, Clock, Run, Done, BusWires,

Sel,LdR0,LdR1,LdR2,LdR3,LdR4,LdR5,LdR6,LdR7,LdA,LdG,Add_sub,Xreg, Yreg);
input [8:0] DIN;
input Resetn, Clock, Run;
output reg Done;
output [8:0] BusWires;
output reg [9:0] Sel;
output reg LdR0,LdR1,LdR2,LdR3,LdR4,LdR5,LdR6,LdR7,LdA,LdG,Add_sub;
output [9:0] Xreg, Yreg;
parameter T0 = 2'b00, T1 = 2'b01, T2 = 2'b10, T3 = 2'b11;
parameter mv = 3'b000, add = 3'b001, sub = 3'b010, mvi = 3'b011;

/*
mv R1,R2
000 001 010
add R1,R2
001 001 010
sub R1,R2
010 001 010
*/

reg Z=9'b111111111;
reg [1:0] PS,NS;
// Registers
reg [8:0] IRin;
//=9'001001010;
reg [8:0] R0,R1,R2,R3,R4,R5,R6,R7; // 8 Internal Registers
reg [8:0] A,G; // Two registers

// T0 is for loading state

// If mv instruction then go T1 and RYout and LdRx enabled Control signals go high
// [8:0] IR
// [8,7,6] IR ------> Opcode
// [5,4,3] IR ------> RX
// [2,1,0] IR ------> RY
reg [2:0] opcode;
wire [8:0] Data_reg;
assign Data_reg = DIN;

// State is in T0
//opcode = Data_reg [8:6];

reg En=1;

dec3to8 Z1 (IRin[5:3], En, Xreg);

// RX register
dec3to8 Z2 (IRin[2:0], En, Yreg);
// RY register

initial
begin
// Predefined Values for Register Initial values of the Register are stored here
R0 = 9'b000000001;
R1 = 9'b000000010;
R2 = 9'b000000100;
R3 = 9'b000001000;
R4 = 9'b000010000;
R5 = 9'b000100000;
R6 = 9'b001000000;
R7 = 9'b010000000;
G = 9'b111111111;
end

multiplex10_to_1 YZ1 (R0,R1,R2,R3,R4,R5,R6,R7,DIN,G,Sel,BusWires);

//mux_add G12 (LdR0,LdR1,LdR2,LdR3,LdR4,LdR5,LdR6,LdR7, DIN,Sel, Clock,LdA, LdG,
Add_sub);

always @(posedge Clock)

begin
if(Resetn)
PS <= NS;
else
PS <= T0;
end

always @(PS,Run,Done)
begin
case(PS)
T0: begin
if(!Run)
NS <= T0;
else
begin
IRin = DIN;
opcode <= IRin[8:6];
NS <= T1;
end
end
T1: begin
if (opcode == mv)
begin
// Ryout corresponding Reg should be high
// Rx in corresponding Reg should be high
// Done 1
// mv R1,R2 R1<----- R2
Sel <= Yreg;
case(Xreg)
10'b1000000000: begin LdR0 <= 1; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R0 <= BusWires;end
10'b0100000000: begin LdR0 <= 0; LdR1 <= 1; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R1 <= BusWires;end
10'b0010000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 1; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0;R2 <= BusWires;end
10'b0001000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 1; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 0; R3 <= BusWires;end
10'b0000100000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 1;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 0; R4 <= BusWires;end
10'b0000010000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 1; LdR6 <= 0; LdR7 <= 0; R5 <= BusWires;end
10'b0000001000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 1; LdR7 <= 0;R6 <= BusWires;end
10'b0000000100: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 1; R7 <= BusWires;end
endcase
Done <= 1;
NS<=T1;
end
else if(opcode == add)
begin
 // Ryout corresponding Reg should be high
// Rx in corresponding Reg should be high
// Done 1
// add R1,R2 R1<----R1+R2
Sel <= Xreg;
LdA <= 1;
LdG <= 0;
A <= BusWires;
Add_sub <= 1; // 1 for add
NS<=T2;
end

else if(opcode == sub)

begin
Sel <= Xreg;
LdA <= 1;
LdG <= 0;
A <= BusWires;
Add_sub <= 0; // 1 for sub
NS<=T2;
end

else if(opcode == mvi)

begin
Sel <= 10'b0000000001; // Sel = Din out
case(Xreg)
10'b1000000000: begin LdR0 <= 1; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R0 <= BusWires;end
10'b0100000000: begin LdR0 <= 0; LdR1 <= 1; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R1 <= BusWires;end
10'b0010000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 1; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R2 <= BusWires;end
10'b0001000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 1; LdR4 <= 0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R3 <= BusWires;end
10'b0000100000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 1;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 0; R4 <= BusWires;end
10'b0000010000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 1; LdR6 <= 0; LdR7 <= 0; R5 <= BusWires;end
10'b0000001000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 1; LdR7 <= 0; R6 <= BusWires;end
10'b0000000100: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 1; R7 <= BusWires;end
endcase
Done <= 1;
NS <= T1;
end
end
T2:begin
 if(opcode == add)
begin
Sel <= Yreg;
LdA <= 0;
LdG <= 1;
G <= Z; // Z is result of addition from the adder block;
NS<=T3;
end

else if(opcode == sub)

begin
Sel <= Yreg;
LdA <= 0;
LdG <= 1;
G <= Z;
NS<=T3;
end

end

T3: begin
if(opcode == add)
begin
Done <= 1;
Sel<=10'b0000000010;
case(Xreg)
10'b1000000000: begin LdR0 <= 1; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R0 <= BusWires;end
10'b0100000000: begin LdR0 <= 0; LdR1 <= 1; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R1 <= BusWires;end
10'b0010000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 1; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R2 <= BusWires;end
10'b0001000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 1; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 0; R3 <= BusWires;end
10'b0000100000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 1;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 0; R4 <= BusWires;end
10'b0000010000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 1; LdR6 <= 0; LdR7 <= 0; R5 <= BusWires;end
10'b0000001000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 1; LdR7 <= 0; R6 <= BusWires;end
10'b0000000100: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 1; R7 <= BusWires; end
endcase
end

else if(opcode == sub)

begin
Done <= 1;
 Sel<=10'b0000000010;
case(Xreg)
10'b1000000000: begin LdR0 <= 1; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R0 <= BusWires;end
10'b0100000000: begin LdR0 <= 0; LdR1 <= 1; LdR2 <= 0; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R1 <= BusWires;end
10'b0010000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 1; LdR3 <= 0; LdR4 <=0; LdR5
<= 0; LdR6 <= 0; LdR7 <= 0; R2 <= BusWires;end
10'b0001000000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 1; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 0; R3 <= BusWires;end
10'b0000100000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 1;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 0; R4 <= BusWires;end
10'b0000010000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 1; LdR6 <= 0; LdR7 <= 0; R5 <= BusWires;end
10'b0000001000: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3<= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 1; LdR7 <= 0; R6 <= BusWires;end
10'b0000000100: begin LdR0 <= 0; LdR1 <= 0; LdR2 <= 0; LdR3 <= 0; LdR4 <= 0;
LdR5 <= 0; LdR6 <= 0; LdR7 <= 1; R7 <= BusWires;end
endcase
end
end
default : NS<=T0;
endcase
end

endmodule

module dec3to8(W, En, Y);

input [2:0] W;
input En;
output reg [9:0] Y;

always @(W or En)

begin
if (En == 1)
case (W)
3'b000: Y = 10'b1000000000;
3'b001: Y = 10'b0100000000;
3'b010: Y = 10'b0010000000;
3'b011: Y = 10'b0001000000;
3'b100: Y = 10'b0000100000;
3'b101: Y = 10'b0000010000;
3'b110: Y = 10'b0000001000;
3'b111: Y = 10'b0000000100;
//3'b1000: Y = 10'b0000000010;
endcase
else
Y = 10'b1000000000;
end
endmodule

module multiplex10_to_1
(Reg0in,Reg1in,Reg2in,Reg3in,Reg4in,Reg5in,Reg6in,Reg7in,DIn,G,sel,bus);
input [8:0] Reg0in,Reg1in,Reg2in,Reg3in,Reg4in,Reg5in,Reg6in,Reg7in,DIn,G;
input [9:0] sel;
//input Reg0out, Reg1out, Reg2out, Reg3out, Reg4out, Reg5out, Reg6out,
Reg7out,Din_out,G_out;
output reg [8:0] bus;
always @ (sel or DIn or G)
begin
if (sel == 10'b0000000001)
bus <= DIn;
else if (sel == 10'b0000000010)
bus <= G;
else if (sel == 10'b0000000100)
bus <= Reg7in;
else if (sel == 10'b0000001000)
bus <= Reg6in;
else if (sel == 10'b0000010000)
bus <= Reg5in;
else if (sel == 10'b0000100000)
bus <= Reg4in;
else if (sel == 10'b0001000000)
bus <= Reg3in;
else if (sel == 10'b0010000000)
bus <= Reg2in;
else if (sel == 10'b0100000000)
bus <= Reg1in;
else if (sel == 10'b1000000000)
bus <= Reg0in;
else
bus <= bus;
end
endmodule

Testbench Code:
module testbench_proc();
reg [8:0] DIN;
reg Resetn, Clock, Run;
wire Done;
wire[8:0] BusWires;
wire [9:0] Sel,Xreg, Yreg;
wire LdR0,LdR1,LdR2,LdR3,LdR4,LdR5,LdR6,LdR7,LdA,LdG,Add_sub;
proc X1 (DIN, Resetn, Clock, Run, Done, BusWires,
Sel,LdR0,LdR1,LdR2,LdR3,LdR4,LdR5,LdR6,LdR7,LdA,LdG,Add_sub,Xreg, Yreg);

initial
begin
Clock = 1'b0;
Resetn = 1'b1;
Run = 0;
#1 Run = 1;
#100 $finish;
end

always #5 Clock = ~ Clock;

initial
begin
$monitor($time,"Clock=%b, Resetn=%b, Run=%b, DIN=%b,IRin=%b,Done=%b,

BusWires=%b,
LdR0=%b,LdR1=%b,LdR2=%b,LdR3=%b,LdR4=%b,LdR5=%b,LdR6=%b,LdR7=%b,LdA=%
b,LdG=%b,Add_sub=%b,PS=%b,NS=%b,opcode=%b",Clock,Resetn,Run,DIN,testbench_pr
oc.X1.IRin,Done,BusWires,LdR0,LdR1,LdR2,LdR3,LdR4,LdR5,LdR6,LdR7,LdA,LdG,Add_s
ub, testbench_proc.X1.PS,testbench_proc.X1.NS,testbench_proc.X1.opcode);
end

initial
begin
#1 DIN = 9'b001001010;
//000 001 010 for move R1 Din read in next clock cycle
// 001 001 010 for add R1 R2
// 010 001 010 for sub R1 R2
end
endmodule

OUTPUT SCREENSHOTS:
The output screenshots from MODELSIM ALTERA is pasted as follows for the four
given operations:
MOVE OPERATION (mv):
T0 CYCLE:

T1 CYCLE:
MOVE IMMEDIATE OPERATION (mvi):
LOAD STATE:

T0 CYCLE:
T1 CYCLE:

ADDER OPERATION:
LOADING OPERATION:
T0 CYCLE:

T1 CYCLE:
T2 CYCLE:

T3 CYCLE:
SUBTRACTER OPERATION:
LOADING OPERATION:

T0 CYCLE:
T1 CYCLE:

T2 CYCLE:
T3 CYCLE:

CONCLUSION:
The processor is implemented and simulated in the MODELSIM software and the
outputs are obtained accordingly.