APJ ABDUL KALAM

TECHNOLOGICAL UNIVERSITY

ALLAPUZHA-PATHANAMTHITTA CLUSTER

Master of Technology
Curriculum, Syllabus and Course Plan

Cluster : 03

Branch : Electronics and Communication Engineering

Stream : VLSI and Embedded Systems

Year : 2015

No. of Credits : 68
 VLSI and Embedded Systems-Scheme

SEMESTER 1

Semester
Examination Slot

Internal Marks

Exam
End
Course No

Credits
L- T - P
Marks Duration (hrs)
Name

A 03EC 6001 VLSI Technology and Emerging 4-0-0 40 60 3 4

Device Architecture

B 03EC 6011 Digital VLSI System Design 4-0-0 40 60 3 4

C 03EC 6021 Design with Advanced 4-0-0 40 60 3 4

Microcontrollers

D 03EC6031 Embedded System Concepts and 3-0-0 40 60 3 3

Design

E Elective 1 3-0-0 40 60 3 3

S 03RM6001 Research methodology 1-1-0 100 2

T 03EC 6901 Seminar I 0-0-2 100 2

U 03EC 6801 Embedded System Lab 0-0-2 100 1

Elective 1

03EC 6041 ASIC Design

03EC6051 Digital Design Principles and Applications
03EC6061 Robotics and Machine Vision

TOTAL CONTACT HOURS : 24

TOTAL CREDITS :23

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

2
 SEMESTER 2

End Semester
Examination Slot

Course Number

Examination

Internal Marks
Name L-T-P

Duration

Credits
(hours)
Marks
A 03EC 6002 Real Time Operating Systems 4-0-0 40 60 3 4

B 03EC 6012 High Speed Digital Design 3-0-0 40 60 3 3

C 03EC 6022 Analog VLSI Design 3-0-0 40 60 3 3

D Elective-2 3-0-0 40 60 3 3

E Elective-3 3-0-0 40 60 3 3

V 03EC 6902 Mini Project 0-0-4 100 2

U 03EC 6802 Physical Design Lab 0-0-2 100 1

Elective II Elective III

03EC 6032 Embedded Networking 03EC6062 VLSI Design Automation

03EC 6042 Advanced VLSI-DSP Concepts and 03EC 6072 Testing of VLSI Circuits
Architecture
03EC 6052 Low Power VLSI Design 03EC 6082 MEMS

TOTAL CONTACT HOURS : 22

TOTAL CREDITS :19

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

3
 SEMESTER 3

End Semester
Examination Slot

Course Number

Examination

Internal Marks
Name L-T-P

Duration

Credits
(hours)
Marks
40 60
A Elective IV 3-0-0 3 3
40 60
B Elective V 3-0-0 3 3

03EC7903 Seminar II 0-0-2 100 2

03EC7913 Project (Phase 1) 0-0-8 50 6

Elective IV Elective V

03EC 7003 Electromagnetic Compatibility 03EC7033 Semiconductor Memories

03EC 7013 Embedded Linux Systems 03EC 7043 System on Chip Design
03EC 7023 Electronic Packaging 03EC 7053 VLSI Interconnects

TOTAL CONTACT HOURS : 16

TOTAL CREDITS :14

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

4
 SEMESTER 4

End Semester
Examination

Course Internal
Examination Slot Name L-T-P Credit

Duration
Number Marks

(hours)
Marks
Project
03EC7914 0-0-21 70 30 12
(Phase 2)

TOTAL CONTACT HOURS : 21

TOTAL CREDITS :12

TOTAL NUMBER OF CREDITS : 68

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

5
 Year of
Course No. Course Name L-T-P Credits
Introduction
VLSI Technology and Emerging Device
03EC6001 4-0-0 4 2015
Architecture

Course Objectives

 To impart knowledge on various technologies used for fabricating VLSI devices.

 To familiarize the bottle neck issues in the current technology
 To introduce new trends in the device fabrication and its advantages

Syllabus
Review of Microelectronics and Introduction to MOS Technologies, Basic IC Processing Steps: Crystal
growth, Ion implantation, Rapid thermal annealing, Oxidation, Lithography, Metallization, Need for
emerging technologies: Second order effects in DSM technologies, Sub threshold leakage current,
Random dopant fluctuations, Drain induced barrier lowering, Hot electron effect, Velocity saturation,
Threshold voltage roll off, GIDL, Introduction of SOI technology, FinFET, VLSI interconnects and related
emerging technologies, Introduction to graphene transistor, Single electron transistor, Junction-less nano-
wire transistors, Tunnel FET

Expected Outcome
1. Conceptual understanding of the above Technologies and ability to apply them in practical
situations.

References

1. S.M Sze, VLSI Technology, McGraw Hill 1983, 2nd Edition.

2. SK Gandhi, VLSI Fabrication Principles, Wiley 2nd Edition, 1994.
3. James D. Plummer, Michael D.Deal and Peter B. Griffin, Silicon VLSI Technology:
Fundamentals, Practice and Modeling, Pearson, 3rd Edition, 2009.
4. Ali Javey and Jing Kong, Carbon Nanotubes Electronics, Springer 2009.
5. International Technology Roadmap for Semiconductors ITRS (2013), http://public.itrs.net
6. M. S. Dresselhaus, G.Dresselhaus and P.Avouris, Carbon Nanotubes: Synthesis,
Structure, Properties and Applications, Springer-Verlag 2000.
7. Colinge J.P. FinFETs and Other Multi-Gate Transistors, Springer, 2008.
8. Dae Mann Kim, Yoon-Ha Jeon, Nanowire Field Effect Transistors: Principles and
Applications, Springer, 2014.
9 Mathias Born, Vertical Gate Controlled Tunnel Transistors in Si and SiGe, Curvillier
Verlag Gottingen, 2007.
10. John D Cressler, Silicon-Germanium Hetero Junction Bipolar Transistors, Artech House Inc,
2003.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

6
 03EC6001 VLSI Technology and Emerging Device Architecture-COURSE PLAN

% of Marks in
End-Semester
Examination
Allotted
Module

Hours
Contents

Review of Microelectronics and Introduction to MOS Technologies:

Technology trends, Brief overview of recent ITRS road map,
6
Fabrication steps of NMOS, PMOS CMOS (n- Well, p-Well and twin
tub) technologies and Berkeley n-Well fabrication steps.
I Basic IC Processing Steps: Crystal growth: Preparation of Electronic 25
Grade silicon using CVD reactor and its basic block diagram,
Czochralski Crystal grower and FZ method, Silicon shaping and its
6
process consideration. Ion implantation: Range theory, Range
distribution, Channeling, Working of basic ion implantation
equipment, Rapid thermal annealing.
FIRST INTERNAL EXAM
Oxidation: Working of Conceptual Silicon oxidation system, Growth
mechanism and kinetics of oxidation with Deal Grove’s model, Effect
of impurities and damage on oxidation rate, Thin oxides, Oxidation 3
induced defects, Limits and future trends in oxidation.
Lithography: Introduction to Electron lithography, Optical
25
II lithography, Ion lithography and X-ray lithography (basic level only),
Pattern generation and mask making, Optical lithography, Limits and 6
future trends in lithography.
Metallization: Metallization Applications, Physical vapor deposition,
patterning and etching in metallization, Limits and future trends in 3
metallization.
Need for emerging technologies: Second order effects in DSM
technologies due to scaling (with a Case study for 22nm technology),
III 25
Sub threshold leakage current, Random dopant fluctuations, Drain 10
induced barrier lowering, Hot electron effect, Velocity saturation,
Threshold voltage roll off, GIDL(gate induced drain leakage).
SECOND INTERNAL EXAM
Introduction to VLSI interconnects: Problems of copper
interconnects, Introduction to emerging technology in VLSI
5
interconnects- Optical interconnects, CNT interconnects and Optical
IV waveguide interconnects. 25
Introduction to graphene transistor, Single electron transistor,
Junction-less nano-wire transistors, Tunnel FET (Explanation and
5
working of all transistors listed in this group with a schematic
diagram).
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

7
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 6011 Digital VLSI System Design 4-0-0 4 2015

Course objectives

 To learn basic working of NMOS and CMOS Devices and compare its performance at gate level

 Introduction to different circuit design styles for designing combinational and sequential circuits

 To learn various parasitic effects and its related timing issues in digital IC design

Syllabus

MOS Transistor Theory, The MOS Inverter, Static CMOS Circuits, Arithmetic circuits in CMOS VLSI,
Pass transistor logic ,Dynamic CMOS Circuits, CMOS Memory Design, High Performance Digital
Circuits, Circuit design Process, Timing issues in Digital system design.

Expected Outcome
Upon successful completion of this course:

1. Students will be able to use mathematical methods and circuit analysis of CMOS
digital electronics circuits.
2. Students will have an understanding of the different design steps required to carry
out a complete digital VLSI design in silicon.
3. Be able to complete a VLSI Design project having a set of objectives and
design constraints.

References
1. Jan M Rabaey, Digital Integrated Circuits - A Design Perspective, Pearson Education,
Second Edition, 2003.
2. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System Perspective,” 2nd edition,
Pearson Education (Asia) Pte. Ltd., 2000.
3. Sung-Mo Kang & Yusuf Leblebici, “CMOS Digital Integrated Circuits - Analysis &Design”, Tata
MGH, 3rd edition.2003.
4. R L Geiger, P E Allen and N R Strader,” VLSI Design Techniques for Analog& Digital
Circuits”, McGraw Hill, 1990.
5. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI, Third Edition,2005
6. Wayne, Wolf, “Modern VLSI design: System on Silicon”, Pearson Education, Second,2008
7. David A.Hodges, Horace G.Jackson, “Analysis and Design of Digital Integrated circuits”, McGraw
Hill Book Company 2nd Edition.1998
8. Ken Martin, “Digital Integrated Circuit Design”, Oxford University Press, 2000.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

8
 03EC 6011 Digital VLSI System Design - COURSE PLAN

Allotted

Semeste
Contents
Module

Examin
in End-
Marks
Hours

% of

r
MOS Transistor Theory: Properties of digital circuits, Basic working of 6
depletion/ enhancement MOSFET, Threshold voltage equation, Body
effect, MOS Current equation, Transconductance and drain conductance
Sub threshold region, Channel length modulation. Mobility variation,
Tunneling, Punch through, Hot electron effect, Scaling of MOS circuits,
I. Modeling of MOS transistors using SPICE (level 1, 2, and 3). 25

The MOS Inverter: Principle, Depletion and enhancement load 6

inverters, Transfer characteristics, Logic threshold, Noise margins, and
Dynamic behavior, Propagation Delay. Study the performance
variation of MOS Depletion and enhancement load inverters using
SPICE -preferably with basic MOS models (level 1,2, and 3).

FIRST INTERNAL EXAM

Static CMOS Circuits(4hrs): CMOS Inverter-The basic CMOS inverter, 4

Transfer characteristics, logic threshold, Noise margins, and Dynamic
behavior, Propagation Delay, Power Dissipation. Latch-up in CMOS
circuits. 25
II Arithmetic circuits in CMOS VLSI (2hrs): Basic Combinational circuits, 4
Adders- multipliers- shifters.
Pass transistor logic : Pass transistor, Transmission gate, 4
Implementation of mux and X-OR gate using pass transistor logic.
Pseudo NMOS, Static latches, Flip flops.
Dynamic CMOS Circuits(4hrs): Dynamic Latches & Registers, CMOS 4
Schmitt trigger, Mono stable sequential Circuits, Astable Circuits.
25
CMOS Memory Design: ROM & RAM (1T RAM and 3T Ram) design, 4
III. Comparison between SRAM and DRAM circuits
High Performance Digital Circuits: C2MOS, Domino and NORA logic. 4
Analysis of charge charging and noise problems in Dynamic logic
circuits, True Single Phase Clock (TSPC) CMOS Logic .
SECOND INTERNAL EXAM

IV Circuit design Process : Circuit elements- Resistor , Capacitor, 15

Interconnects, Sheet resistance , Standard unit capacitance and unit
delay concepts , Inverter delays , Driving capacitive loads, Propagation 25
delays, MOS layers, Stick diagrams and mask layout encoding, Design
rules and layout, Lambda Based Design rules, Micron based design
rules.
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

9
 Course No. Course Name L-T-P Credits Year of Introduction

03EC 6021 Design with Advanced Microcontrollers 4-0-0 4 2015

Course objectives

 To learn the architecture, programming and interfacing of microcontrollers with

peripherals.
 To design microcontroller based embedded systems.

Syllabus
PIC18 architecture, programming and Interfacing, Using Flash and EEPROM Memories for data
storage, ARM architecture, organization programming and implementation.

Expected Outcome

1.To learn the architecture, programming, interfacing of PIC and ARM microcontrollers
2. To design and develop microcontroller based embedded systems

References

1. Muhammad Ali Mazidi, Rolin D. Mckinlay, Danny Causey, “PIC Microcontroller and
Embedded systems”, Pearson Education,2007
2. S. Furber, “ARM System-on-Chip Architecture”, Pearson Education,2nd 2013.
3. Andrew N. Sloss, Dominic Symes, Chris Wright, “ARM System Developer’s guide”,
Morgan Kaufman,2004.
4. David Seal, “ARM Architecture Reference Manual”, second edition Addison
Wesley,2nd edition 2001

5. Joseph Yiu, “The Definitive Guide to the ARM Cortex- M3”, Newness.2nd edition 2010

6. PIC18FXX8 data sheets.

7. Lyla B. Das, “Embedded systems, an integrated approach”,Pearson Education 2013

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

10
 03EC 6021 Design with Advanced microcontrollers- COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

PIC18 architecture , Assembly language programming, I/O Port

programming, addressing modes, Instruction set, programming in
I C, Timer programming in assembly and C, serial port and Interrupt 12 25
programming in assembly and C, LCD and Keyboard Interfacing,
ADC, DAC, and sensor interfacing.
FIRST INTERNAL EXAM

Using Flash and EEPROM Memories for data storage, CCP and
ECCP Programming, SPI Protocol and DS1302 RTC Interfacing,
III Motor control: Relay, PWM, DC, and stepper motors 12 25

ARM architecture, ARM organization and Implementation, Memory

Hierarchy, ARM Instruction Set and Thumb Instruction set,
Assembly Language Programming, 15 25
III

SECOND INTERNAL EXAM

High- Level Language Programming, System Development using
ARM. Digital Signal Processing on ARM. Peripheral Programming
IV and system design for a specific ARM processor (ARM7/9). 12 25

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

11
Course No. Course Name L-T-P Credits Year of Introduction
03EC 6031 Embedded System Concepts
3-0-0 3 2015
and Design

Course objectives
•Understand current applications, trends and new directions in embedded systems
•To do hardware/software co-design for embedded systems and to develop skills in analysis, approach,
optimization, and implementation of embedded systems

Syllabus

Introduction To Embedded Systems, Hardware Software Co-Design and Program Modeling,

Real-Time Operating System (RTOS) based Embedded System Design, The Embedded System
Development Environment:

Expected Outcome

Upon successful completion of this course, students will be able to:

1. Understand embedded system development environment.
2. Understand different hardware and software required for developing
embedded system

References
1. Shibu K.V.,” Introduction to Embedded Systems, Tata McGraw Hill Education Private
Limited, 2010.
2. Lyla B Das,”Embedded Systems-An Integrated Approach”, Pearson, 2013

3. Rajkamal, “Embedded systems: Architecture, Programming and Design”, TMH, 2012.

4. Greg Osborn, “Embedded Microcontrollers and Processor Design”, Pearson, 2012.
5. Keith, E. Curtis, “Embedded Multitasking with small microcontrollers”, Newness, 2007.
6. Tammy Noergaard, “Embedded Systems architecture: A comprehensive guide for
engineers and programmers”,Newnes, 2011.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

12
 03EC 6031 Embedded System Concepts and Design-Course plan

Contents

Examination
% of Marks

Semester
Allotted
Module

in End-
Hours
I Introduction To Embedded Systems :Core of the Embedded System, 10
Memory, Sensors and Actuators, Communication Interface, Embedded
25
Firmware, Other System Components, Characteristics and Quality
attributes of embedded systems, Embedded system examples

FIRST INTERNAL EXAM

II. Embedded Hardware aspects: IO types, Serial communication 10 25
devices, serial data communication-UART-SPI-I2C-CAN-LIN-I2S-
IrDA-USB- Bluetooth, Parallel communication-ISA-PCI.
Hardware Software Co-Design and Program Modeling:
Fundamental Issues in Hardware Software Co-Design, Computational
Models in Embedded Design, Introduction to Unified Modeling
Language, Hardware Software Trade-offs.

III. Real-Time Operating System (RTOS) based Embedded System 12 25

Design: Operating System Basics, Types of OS, Tasks, Process and
Threads, Multiprocessing and Multitasking, Task Scheduling, Threads,
Processes and Scheduling: Putting them altogether, Task
Communication, Task Synchronization, Device Drivers, How to Choose
an RTOS

SECOND INTERNAL EXAM

IV The Embedded System Development Environment: The Integrated 15 25
Development Environment (IDE), Types of Files Generated on Cross
compilation, Disassembler/Decompiler, Simulators, Emulators and
Debugging, Target Hardware Debugging, Boundary Scan. The
Embedded product development life cycle: What is EDLC, Why EDLC,
Objectives of EDLC, Different phases of EDLC, EDLC Approaches

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

13
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 6041 ASIC Design 3-0-0 3 2015

Course Objectives

 To learn the fundamentals of ASIC and its design methods

 To gain knowledge on programmable architectures for ASIC
 To understand the physical design of ASIC
Syllabus

Introduction to ASICs- Types of ASIC, ASIC Library Design, Programmable ASICS, Programmable
ASIC Logic cells Synchronous Design Using Programmable Devices: ASIC Construction Floor
Planning and Placement.

Expected Outcome
1. Students will have an understanding of the ASIC Design flow and the various types
of ASICs and their implementations.
2. Be able to understand the physical design algorithms having a set of objectives and
design constraints.

References
1. M.J.S. Smith, “Application – specific integrated circuits” Addison – Wesley
Longman Inc. 1997.
2. John M Yarbrough ,”Digital Logic applications and Design”, Thomson Learning, 2001
3. Samir Palnitkar, Verilog HDL, Pearson Education, 1996.
4. Data sheet:” Spartan-3 FPGA Family Advanced Configuration Architecture “– Xilinx
XAPP452 (v1.1) June 25, 2008
5. Cyclone III Device Hand book, Volume 1,2012
6. Andrew Brown, - “VLSI circuits and systems in silicon”, McGraw Hill, 1991.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

14
 03EC 6041 ASIC Design-Course Plan

% Marks in End
Hours Allotted

Examination
of Semester
Module

Contents

Introduction to ASICs : Types of ASICs – full custom ASIC –

semi custom ASIC –standard cell based ASIC – gate array
I based ASIC – programmable ASIC, PLD ,FPGA, Economics of
10 25
ASIC.
ASIC Library Design: Transistors as resistors, Transistor
Parasitic capacitance, Logical Effort.
FIRST INTERNAL EXAM
Programmable ASICS, Programmable ASIC Logic cells : Anti
fuse, Static RAM ,EPROM and EEPROM technology, PREP
benchmarks, Actel ACT, Xilinx LCA, AlteraFLEX, Altera MAX,
II
Architecture of FPGAs Case study using Xilinx Spartan-3 and 12 25
Altera Cyclone-3.

Synchronous Design Using Programmable Devices: EPROM

to Realize a Sequential Circuit , Programmable Logic Devices ,
III Designing a Synchronous Sequential Circuit using a GAL ,
12 25
EPROM , Realization State machine using PLD ,FPGA ,Xilinx
FPGA ,Xilinx 2000 , Xilinx 3000.

SECOND INTERNAL EXAM

ASIC Construction: Physical Design, System partitioning,

FPGA partitioning, Partitioning methods- Constructive
partitioning, Iterative Partitioning, Group migration algorithm
case study using KL algorithm.
IV Floor Planning and Placement: Goal and objectives of floor
10 25
planning, Measurement of delay, I/O and power planning,
Clock planning, Goals and objectives of placement, Placement
algorithm case study using min-cut placement and eigen value
placement algorithm.
Special Routing: Clock routing and power routing.
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

15
 Course No. Course Name L-T-P Credits Year of Introduction
Digital Design Principles and
03EC 6051 3-0-0 3 2015
Applications
Course Objectives
• To learn how to design synchronous and asynchronous digital systems.
• To learn about the techniques and tools for programmable logic design.
• To develop a digital system using HDL.

Syllabus
Synchronous Sequential Circuit Design, Asynchronous Sequential Circuit Design, Programmable
Logic Devices, Digital System Design Using HDL, VHDL implementation of Combinational and
sequential circuits.

Expected Outcome
1. Ability to design synchronous and asynchronous sequential circuits and a thorough
understanding of VHDL

References
1.Donald G. Givone, “ Digital principles and Design”, Tata McGraw Hill 2002.
2.Charles H. Roth Jr., “Fundamentals of Logic design”, Thomson Learning, 2004
3.Milos D Ercegovac, Tomas Lang,” Digital systems and hardware / firmware algorithm”,
John Wiley, 1985
4.Milos Ercegovac, Tomas Lang, Jaime H. Moreno ,”Introduction to digital systems”, John
Wiley,1998
5.John M Yarbrough, “Digital Logic Applications and Design”, Thomson learning,2006
6.John F Wakerly, “Digital Design Principles and Practices”, Pearson ,2005
7.J Bhasker, “A VHDL Primer”, PHI,2009
8.Stephen Brown, Zvonko Vranesic, “Fundamentals of Digital Logic with VHDL Design”,
McGraw-Hill, 2004.
9.G.K.Kharate “Digital Electronics”,Oxford Higher Education

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

16
 03EC 6051- Digital Design Principles and Applications - COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Synchronous Sequential Circuit Design: Clocked Synchronous State

Machine Analysis, Mealy and Moore machines.

Finite State Machine design procedure- state diagrams, state tables,

I. 25
state reduction methods, state assignments. 10

Modeling of clocked synchronous circuits as mealy and Moore

machines: serial binary adder, Sequence detector, design examples.

FIRST INTERNAL EXAM

Asynchronous Sequential Circuit Design: Analysis of Asynchronous
Sequential state machine, Primitive Flow Table- Flow tables, State
Assignment.
II. Races and Cycles, Shared single row state assignment, Shared multi row 25
10
state assignment, One hot state assignment.
Design of Asynchronous system with examples, Static and dynamic
hazards, Essential hazards, Methods for avoiding races and hazards.
Programmable Logic Devices: Programmable Array Logic PALs,
Programmable Logic Arrays PLAs, PLA minimization and PLA
III. folding, GAL, Design of combinational and sequential circuits using 25
10
PLD’s, XILINX FPGAs – Block diagram elements, XILINX CPLDs,
ASIC- Semi Custom, Full Custom.
SECOND INTERNAL EXAM
Digital System Design Using HDL: Introduction to VHDL, Design
IV elements, Data types, Operators, user defined primitives, Types of 25
12
modeling, VHDL implementation of Combinational and sequential
circuits.
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

17
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 6061 Robotics and Machine Vision 3-0-0 3 2015

Course Objectives

 Identifying, classifying and describing the functionality of the different elements that
compose a robotic vision system.
 Learn machine vision system design and applications

Syllabus

Fundamental of Robotics Basic, Classification of robot and robotic systems, Kinematics of Robot,
Machine Vision: Principles of Machine Vision Basic Machine Vision Processing Operators, Robot
Sensing and Vision Systems, Industrial Applications of Robots

Expected Outcome

1. Conceptual understanding of the robotics and machine vision .

1. R K Mithal, I.J.Nagrath,”Robotics and control”, Tata McGraw-Hill,2003.

2. Louis J. Galbiati, Jr.,” Machine Vision and Digital Image Processing”, Prentice Hall,
Englewood Cliffs, New Jersy.1990
3. Boguslaw Cyganek,”Object Detection and Recognition in Digital Images: Theory and Practice”
Wiley,2013
4. YoramKoren, “Robotics for Engineers”, McGraw Hill.1985
5. Janakiraman P. A,”Robotics and Image Processing – an Introduction”, Tata McGraw
Hill, New Delhi,2007
6. Robert J.Schalkoff, “Digital Image Processing and Computer Vision”, John Wiley &
Sons Inc.1989
7. Mikell P, Groover, Mitchell Wein, Roger N. Nagel and Nicholas G. Odlrey,” Industrial Robotics –
Technology, Programming and Applications”, McGraw Hill,1986
8. Richard Szeliski, “Computer Vision: Algorithms and Applications” . Springer, ISBN-10:
1848829345, ISBN-13: 978-1848829343, Publishing, 2010.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

18
 03EC 6061- Robotics and Machine Vision - COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Fundamental of Robotics Basic: Concepts of Robotics, Robot anatomy,

Robot parts and their functions, Classification of robot and robotic
systems.
I Kinematics of Robot: Introduction, Definition, Open and closed 25
10
kinematic mechanisms, Matrix representation, Homogeneous
transformation, forward and inverse kinematics, Direct Vs. inverse
kinematic task.

FIRST INTERNAL EXAM

Machine Vision: Principles of Machine Vision, Human Vision Vs.

Machine Vision, Machine Vision – System Overview, Image acquisition,
II Illumination, Image formation and Focusing, Image Detection, Types of 25
10
Cameras, Image Processing and presentation, Object detection, tracking
and recognition.

Basic Machine Vision Processing Operators: Binary Threshold operator,

Inverted Binary Threshold Operator, Gray Scale Threshold and Inverted
III Gray Scale Threshold Operators; Two Point Transformations –Image 25
10
Addition, Image Subtracting, Image Multiplication; Convolution and
Spatial Transformations.

SECOND INTERNAL EXAM

Robot Sensing and Vision Systems: Sensors-Force and torque sensors,

Types of end effectors, Types of grippers, Low level vision, High level
vision, Robot Programming languages, Introduction to Intelligent
IV Robot,-Robots in manufacturing automation. 25
10
Industrial Applications of Robots- Quality control, Mapping and robot
guidance, Motion estimation, Passive navigation and structure from
motion.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

19
Course No. Course Name L-T-P Credits Year of Introduction
03RM 6001 Research methodology 1-1-0 2 2015

Course Objectives
This course is designed to familiarize the student with the research process, problem identification
strategies and formulation of a research plan by doing case studies.

Syllabus

Introduction to Research Methodologies - Objectives -motivation in research- Significance of

research - interaction between industries and research units –research and innovation.

Research Formulation- - literature review.

Ethics in research: – copy right – plagiarism – citation –acknowledgement.

Research Design and Report writing

Case Studies : Department / stream specific case study and preparation of a research plan or
a review paper
Expected Outcome
Upon successful completion of this course
 Students will be able to write a review paper after critically evaluating the state of
the art development in a topic of interest
 Students will acquire capability to write a research proposal in the form of a
technical paper which could lead the student towards his / her final thesis topic
 No formal end semester examination is intended – Evaluation is based on internal
oral presentations and a Technical Report or a Research Plan or a Review Paper

References

1. R. Paneersalvam, “Research Methodology”, Prentice Hall of India Pvt. Ltd.,2011

2. Mike Martin, Roland Schinzinger, “Ethics in Engineering”, McGraw Hill Education,
Fourth Edition,.2014
3. Vinod V Sople,” Managing Intellectual Property-The Strategic Imperative, EDA”, Prentice
of Hall Pvt. Ltd., 2014
4. Kothari C R &Gaurav Garg – “Research Methodology- Methods and Techniques”, New
Age International(P) Ltd Publications, 2006
5. Day A Robert, ”How to write and publish a scientific paper”, Cambridge University,
UK,2012
6. Leedy P D, ”Practical Research-Planning and Design”, Prentice Hall of India Pvt. Ltd.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

20
 03RM 6001 Research methodology– COURSE PLAN

Examination
% of Marks

Semester
Allotted
Module

in End-
Hours
Contents

Introduction –Need for research- objectives and

motivations in research
Significance of research - -need for interaction between academic
I institutions, industrial and research establishments – research and
4 25
innovation.
Research Formulation- Identifying a research problem- literature
review– confirming to a research problem based on literature review.

FIRST ASSESSMENT
Research Ethics – Environmental impacts – Ethical issues -
II Intellectual Property Rights – Patents – legal formalities in filing
3
patent in India – Copy right– plagiarism – citation and
acknowledgement.
25
Research design –Prepare research plan.
III Report writing – types of report – research report, research proposal,
3
funding agencies for research concerned to the specialization,
significance of peer reviewed articles and technical paper- - simple
exercises - oral presentation
SECOND ASSESSMENT
Case Studies: The student is expected to prepare a research plan
relating to a topic of current interest in the concerned specialization,
which has appeared in a recent journal. A minimum of 20 related
IV referred articles should be critically studied. On the basis of this, the 50
6
student is expected to prepare a review report/paper of publishable
quality. This paper has to be presented for open defence before the
departmental committee. (This would carry 50% marks)

END SEMESTER ASSESSMENT

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

21
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 6901 Seminar I 0-0-2 1 2015

Course Objectives
To make students,
 Identify a domain of interest
 Identify sufficient number of latest good quality research papers on a particular problem or
allied problems
 Do extensive study and analysis of the problem and solution(s)
 Prepare a comprehensive report
 Make a presentation (20-25 minutes) based on the report

Syllabus
.
No specific Syllabus

Expected Outcome

At the end of the course student

 gets good exposure to a domain of interest and the research problems in the domain
 gets practice in the art doing literature survey
 improves his/her writing and presentation skills
 (in rare cases) gets a good domain and problem to pursue his/her thesis work.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

22
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 6801 Embedded System Lab 0-0-2 1 2015
Course Objectives

 Understand the programming and interfacing concepts for microcontroller based systems
 To familiarize System design using HDL

Syllabus
Experiments are based on o the topics covered in 03EC 6021,03EC6051

03EC 6801 – EXPERIMENTS

Experiment

Allotted
Hours
No

Description

Interfacing experiments with any two of PIC/ARM/AVR series microcontroller.

Use Assembly language or C for the following experiments(any five)

1. Keypad (4*3) / (4*4) and LCD interface.

2. Write data into and read data from the microcontroller’s EEPROM.
3. Interface RTC / EEPROM using I2C / SPI and establish communication
to a desktop computer using serial interface.
4. Use of parallel slave port and exchange data between two microcontrollers.
I
10
5. Interface DC motor and control its speed.

6. Write a program to generate square, triangular and sine wave using DAC

7. Write a program to interface relay card.

8. Program to generate a 50% duty cycle, 1 KHz wave and to use it for exciting
a buzzer

Design and implement various combinational sequential circuits and Finite

II State Machines using HDL (any five) 10
1. Simulation and Verification of Logic Gates.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

23
 2. Design and Simulation of Half adder, Serial Binary Adder, Multi Precision
Adder, Carry Look Ahead Adder and Full Adder.
3. Simulation and Verification of Decoder, MUXs, Encoder using all Modeling
Styles.
4. Modeling of Flip-Flops with Synchronous and Asynchronous reset. .
5. Design and Simulation of Counters- Ring Counter, Johnson Counter,
Up- Down Counter, Ripple Counter.
6. Design of a N- bit Register of Serial-in Serial-out, Serial in Parallel out,
Parallel in Serial out and Parallel in Parallel Out.
7. Design of Sequence Detector (Finite State Machine- Mealy and Moore
Machines).
8. Design Unsigned and Signed Multiplier/Divider
9. Design and implementation of a simple Microprocessor
10. Vending Machine Controller using FSM approach

Implement the above designs on Xilinx/Altera/Cypress/equivalent based

FPGA/CPLD
Note:
End semester evaluation through a mini project using any one of the above mentioned
microcontrollers to develop prototype as solutions to real life problem.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

24
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 6002
Real Time Operating Systems 3-1-0 4 2015

Course Objectives
• Understand the basics of RTOS
• Familiarize various Real time operating systems available and their use in embedded systems

Syllabus

Introduction to Embedded System and Real Time Operating system ,Survey of software
Architectures, Basic Design using an RTOS, Modern real time kernels and operating systems.

Expected Outcome
Upon successful completion of this course, students will be :
1. Able to summarize the basic properties of a real-time operating system
2. Able to apply RTOS concepts for solving multi tasking embedded applications

References
1.Qing Li, Caroline Yao ,”Real-Time Concepts for Embedded Systems”,CMP Books.2003
2. Dr.K V K K Prasad ,”Embedded / Real time systems: Concepts, Design and Programming”,
Dream Tech press, New Delhi, 2003.
3.Raj Kamal, “Introduction to Embedded Systems”, TMS, Tata McGraw Hill Publications, 2002.
4.Gary Nutt, Nabendu Chakki and Sarmistha Neogy, “Operating systems”, Third edition,
Pearson Education, 2009
5. Charles Crowley, “Operating System” – A design oriented approach, McGraw Hill, 1997. 66.
6. LaPlante, Philip A., “Real Time System Design And Analysis”, 3rd edition, Wiley, 2004
7. Rajkamal, “Microcontrollers: Architecture, programming, interfacing, and system design”,
2nd Edition, Pearson Education, 2012
8. Shehrzad Qureshi, “Embeded Image Processing on the TMS320C6000 DSP”, Springer, 2005.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

25
 03EC 6002 Real Time Operating Systems –COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Introduction to Embedded System and Real Time Operating system:

Basics of developing for embedded systems, Embedded System
I Initialization, Features of Operating Systems, Introduction to real time 25
12
operating systems.

FIRST INTERNAL EXAM

Survey of software Architectures: Round Robin, Round Robin with
interrupts, Function Queue scheduling Architecture, RTOS
Architecture, Architecture selection, Introduction to RTOS, Task and
II task states, Task and data, Semaphore and shared data, More operating 25
12
system services, Message Queues, Mail boxes and pipes, Timer
functions , Events, Memory Management, Interrupt routine in an RTOS
environment.

Basic Design using an RTOS: Principle, Encapsulating Semaphores and

Queues, Process, Multitasking and Process Management- Process
III implementation - Process scheduling algorithms 12 25

SECOND INTERNAL EXAM

Modern real time kernels and operating systems: POSIX,POSIX mutexes
and condition variables, POSIX semaphores, POSIX messages, Real time
POSIX signals, Clocks and timers, Asynchronous I/O,POSIX memory
tasking,RTX51,RTX51 functions, Preemptive scheduling in RTX51,C
functions in RTX51,Use of Signal functions of RTX51 in design, Use of
IV RTX51 in the design of traffic light control system and vending 25
15
machine, Real Time Software components, TI DSP/BIOS and SYS/BIOS
as scalable real time kernels, Use of DSP/BIOS in the design of an edge
detection system.

Course No. Course NameEND SEMESTER

L-T-PEXAMCredits Year of Introduction
03EC 6012 High Speed Digital Design 3-0-0 3 2015

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

26
 Course Objectives

 To develop the skills for analyzing high-speed circuits with signal behavior modeling.
 To demonstrate power distribution and noise concepts

Syllabus

Introduction to High Speed Digital Design, Power Distribution and Noise, Signalling convention
and Circuits, Timing Convention and Synchronization

Expected Outcome
1. Deeper understanding of behaviour of high-speed digital circuits.
2. To be able to analyze signaling and timing conventions.

References
1. Henry W. Ott, Electromagnetic Compatibility Engineering, John Wiley & Sons, Inc.
Publication.2009
2. William S. Dally & John W. Paulton, “Digital System Engineering”, Cambridge
University Press, 1998.
3. Jan M.Rabaey “Digital Integrated Circuits: A design Perspective”, 2nd Edition 2003
4. Masakazu Shoji., “High Speed Digital Circuits”, Addison Wesley Publishing
Company, 1996
5. Howard Johnson “High-Speed Digital Design”, A Handbook of Black Magic
Prentice Hall.1993

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

27
 03EC 6012-High Speed Digital Design- COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Introduction to High Speed Digital Design: Frequency, Time, Distance

Capacitance and Inductance Effects¬, High speed properties of logical
gates, Speed and power- modeling of wires ,Geometry and Electrical
I properties of wires, Electrical model of wires, transmission lines, 25
12
lossless LC transmission lines, lossy RLC transmission lines , Special
transmission lines

FIRST INTERNAL EXAM

Power Distribution and Noise :Power supply network, Local power
regulation, IR drops, Area bonding, On Chip bypass capacitors,
II Symbiotic bypass capacitors, Power supply isolation- Noise sources in 25
12
digital system, Power supply Noise - Cross talk, EMI, inter symbol
interference.
Signalling convention and Circuits: Signalling modes for
transmission lines , Signalling over lumped transmission media,
III Signalling over RC interconnects, Driving lossy LC lines, Skin effect, 25
12
Proximity effect, Dielectric loss, Effects of source and load impedance,
Reflections of transmission line, Terminators, Transmitter and receiver
circuits
SECOND INTERNAL EXAM
Timing Convention and Synchronization: Timing fundamentals, Timing
properties of clocked storage elements, signals and events, open loop
IV timing, level sensitive clocking-,Pipeline Timing ,Closed loop Timing 25
12
,Clock Distribution, Synchronization failure and meta stability, PLL and
DLL based lock aligners.
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

28
 Course No. Course Name L-T-P Credits Year of Introduction
03EC6022 Analog VLSI Design 3-0-0 3 2015

Course Objectives
 To understand CMOS analog circuits design
 To simulate Analog circuits using SPICE.
 To learn about various data converter circuits

Syllabus
Analog MOS transistor models: Various CMOS device models-MOSFET Current source and current
steering circuits, Single stage amplifiers: Frequency response of single stage amplifiers, Cascode stage,
Folded cascade, Choice of device models. MOS Differential Amplifiers: Operational Amplifiers: Basic
CMOS Op-Amp design and Characterization, High speed/ high frequency op-amps and micro power-
opamps, Low noise opamps and low voltage opamps, Filter implementations. Bandgap References,
Dynamic Analog Circuits: Switched capacitor circuits, Switched capacitor integrator. Data Converter
Architectures

Expected Outcome
1. To understand various analogue designs and develop an ability to design analogue circuits.
2. Extend the knowledge acquired to design and develop mixed signal circuits

References
1. Adel S Sedra and Kenneth C Smith, Microelectronic Circuits, Oxford University Press. VthEdition.2004
2. Behzad Razavi, Design of Analog CMOS Integrated Circuit, Tata McGraw HILL, 2002.
3. Philip Allen & Douglas Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002.
4. R Jacob Baker, Harry W Li and David E Boyce, CMOS Circuit design, Layout and simulation.
PHI,1998
5. Paul B Gray and Robert G Meyer, Analysis and Design of Analog Integrated Circuits.
6. BehzadRazavi, Principles of data conversion system design, 2000. John Wiley
7. R Gregorian and G C Temes, Analog MOS Integrated Circuits for Signal Processing,
John Wiley,1986.
8. R L Geiger, P E Allen and N R Strader, VLSI Design Techniques for Analog & Digital Circuits,
McGraw Hill, 1990.
9. Gray, Wooley, Brodersen, Analog MOS Integrated circuits, IEEE press, 1989.
10. Kenneth R. Laker, Willy M.C. Sensen, Design of Analog Integrated circuits and systems, McGraw
Hill, 1994.
11. Mohammed Ismail &Feiz, Analog VLSI – Signal Information and Processing, John Wiley and Sons.3rd
edition, 1993.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

29
 03EC6022 Analog VLSI Design -COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

EC 5018-Contents

Analog MOS transistor models: CMOS device models-MOS large

signal model, Small signal models, Computer simulation models, 5
I Subthreshold MOS models, SPICE simulation. 25
MOSFET Current source and current steering circuits, Current mirrors-
Cascode MOS Mirrors, Wilson Current mirror and Wildar Current 5
source- Bipolar mirror with base current compensation.

FIRST INTERNAL EXAM

Single stage amplifiers: Basics of single stage CMOS amplifiers,
Common Source, Common gate and source follower stages, Frequency
response of single stage amplifiers, Cascode stage, Folded cascade,
5
Choice of device models.
25
II Differential Amplifiers: MOS Differential pair- Operation with
common mode input voltage ,Operation with differential input voltage,
Large signal operation, Small signal operation of MOS differential pair,
5
Differential gain, Common mode gain and common mode rejection
ratio, One stage and two stage differential amplifier.

Operational Amplifiers: Basic CMOS Op-Amp design: Characterizing

the Op-Amp, Compensation without Buffer, Cascode input Op-Amp 5
III 25
High Performance Opamps: High speed/ high frequency op-amps,
micro power opamps, Low noise opamps and low voltage opamps, 5
Filter implementations.
SECOND INTERNAL EXAM
Bandgap References: Temperature Independent reference, Negative TC
voltage, Positive TC voltage, Band gap reference
5
Dynamic Analog Circuits: MOSFET Switch, Switched capacitor circuits,
Switched capacitor integrator.
IV Data Converter Architectures: DAC and ADC specifications, DAC 25
Architectures – Current Steering, Charge scaling DAC, Cyclic and
pipeline DAC. ADC Architectures- Pipeline ADC, Integrating ADC, 5
Successive approximation ADC and Oversampling ADC.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

30
Course No. Course Name L-T-P Credits Year of Introduction
03EC 6032 Embedded Networking 3-0-0 3 2015

Course Objectives
• Learning of different embedded networking protocols.
• Familiarize various bus standards and embedded networks.

Syllabus

Embedded Networking Requirements, Controller Area Network ,SPI , I2C , USB bus, Wireless
embedded networking

Expected Outcome
Able to identify and implement suitable embedded protocols and buses in
Embedded System Design

References

1. Lyla B Das, “Embedded Systems-An Integrated Approach”, Pearson, 2012.

2. Olaf P Feiffer, Andrew Ayre & Christian Keyold, “Embedded Networking with CAN and CAN
Open”, Embedded System Academy 2005.
3. Marco Di Natale, Haibo Zeng, Paolo Giusto & Arakadeb Ghosal, “Understanding and Using the
Controller Area Network” ,Springer, 2012.
4. John Catsoulis,” Designing Embedded Hardware”, O'Reilly Media, Inc., 2002
5. NXP Semiconductors, I2C-bus Specification and User Manual , Rev. 5, October 2012. (Available
at http://www.nxp.com/documents/user_manual/UM10204.pdf)
6.Motorola Inc., “S12SPIV3/D:SPI Block Guide V03.06”, Feb 2003, (Available at
http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf)
7. Bhaskar Krishnamachari,” Networking wireless sensors”, Cambridge press 2005

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

31
 03EC 6032 - Embedded Networking– COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Embedded Networking Requirements: Introduction to Network for

Embedded Systems, Introduction to buses and protocols for embedded
I networking: CAN Bus, I2C, SPI, USB, Ethernet protocol, TCP/IP 10 25
Protocol, Internet connectivity over an Ethernet connection, Wireless -
Bluetooth, Zig Bee standard.
FIRST INTERNAL EXAM
Controller Area Network : CAN Overview, Introduction, CAN 2.0b
Standard (covering Physical Layer, Message Frame Formats, Bus
Arbitration, Message Reception and Filtering, Error Management),
II Selecting a CAN Controller, CAN Development Tools, Evaluating 10 25
system requirements choosing devices and tools, Configuring single
devices, Overall network configuration, Network simulation, Network
Commissioning, Advanced features and testing
SPI : Introduction, Features, Modes of Operation , External Signal
Description, Functional Description(Covering Master Mode, Slave
Mode, Transmission Formats, Baud Rate Generation, Error Conditions,
Low Power Mode Options)
I2C : I2C-bus features, Modes of Operation - Standard-mode, Fast-
mode ,Fast-mode plus, Ultra fast mode(covering the following topics -
III Signals and Logic levels, Start/Stop conditions, byte format, 12 25
Acknowledge and Not-Acknowledge, Clock Synchronization,
Arbitration, Clock Stretching, Addressing, Call Addresses, Reset, Device
ID),Applications of I2C bus protocol
USB bus: Introduction, Speed Identification on the bus, USB States, USB
bus communication: Packets, Data flow types, Enumeration,
Descriptors, PIC 18Microcontroller USB Interface.
SECOND INTERNAL EXAM
Wireless embedded networking : Wireless sensor networks
,Introduction , Applications ,Network Topology ,Localization ,Time
IV 10 25
Synchronization , Energy efficient MAC protocols ,SMAC , Energy
efficient and robust routing, Data Centric routing.
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

32
 Course No. Course Name L-T-P Credits Year of Introduction
Advanced VLSI- DSP Concepts
03EC 6042 3-0-0 3 2015
and Architecture

Course Objectives

 To integrates VLSI architecture theory and algorithms, addresses various architectures at the
implementation level.
 Help to design high-speed, low-area, and low-power VLSI systems for a broad range of DSP
applications.

Syllabus

Multirate system fundamentals, Pipe lining and parallel processing, Strength reduction algorithms,
Synchronous wave and asynchronous pipelines

Expected Outcome
1. Students gain in-depth theoretical on advanced DSP architecture.

References

1. Keshab K Parhi,VLSI DSP Systems- Design and Implementation – John Wiley, 2004.
2. P P Vaidyanathan, Multirate Systems and filter banks,, Prentice Hall, PTR.1993
3. Bernard Widrow & Samuel D. Streams Adaptive Signal Processing, Prentice Hall,1985.
4. N J Fliege, Multirate Digital Signal Processing, John Wiley 1994.
5. John G Proakis and Dimitris G Manolokis, Digital Signal Processing Principles –
Algorithms and applications, Prentice Hall, Third Edition,1999

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

33
 03EC 6042- Advanced VLSI- DSP Concepts and Architecture COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Multirate system fundamentals: Basic Multirate operation – up

I sampling and down sampling, Time domain and frequency domain 25
10
analysis, identities for multirate operations, Interpolator and decimator
design, Rate conversion, Polyphase representation.
FIRST INTERNAL EXAM
Pipe lining and parallel processing: Pipe lining of FIR filters, Parallel
processing, Pipe lining and parallel processing for low power, Retiming-
Definitions and properties, Solving system of inequalities, Retiming
II techniques, Unfolding-Algorithm for unfolding, Properties of unfolding,
15 25
Critical path, Unfolding and retiming, Applications folding- Folding
transformation, Register minimization techniques, Register
minimization in folded architectures.

Strength reduction algorithms:. Fast convolution – Cook Toom

III Algorithm, Modified Cook Toom Algorithm, Winograd Algorithm, 25
15
Modified Winograd Algorithm ,Cyclic convolution.
SECOND INTERNAL EXAM
Synchronous wave and asynchronous pipelines: Synchronous
IV pipelining and clocking styles, Clock skew and clock distribution in
12 25
bit level pipelined VLSI designs, Wave pipelining, Asynchronous
pipelining
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

34
Course No. Course Name L-T-P Credits Year of Introduction
EC 6052 LOW POWER VLSI DESIGN 3-0-0 3 2015

Course Objectives
 To introduce the need of Low power CMOS designs in the current scenario.
 To introduce various levels of power consumption and its relative impact at various technological
nodes
 To introduce various power simulation methods used from high level to low level design
 To introduce various power reduction methods that can be used in different levels of design

Syllabus
Need for low power VLSI chips, Physics of power dissipation in CMOS devices. Emerging Low
power approaches. Device & Technology Impact on Low Power. Simulation Power analysis: Gate
level logic simulation, Architecture level analysis, Data correlation analysis in DSP systems,
Probabilistic power analysis. Low Power Design- Circuit level, Logic level power analysis.
Low power Architecture & Systems, Low power arithmetic components, Low power memory
design, Low power Clock Distribution, Algorithm & architectural level methodologies:

Expected Outcome
1. To understand the need of low power designs
2. To extend the acquired knowledge to design power effective systems and circuits.

References
1. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002
2. Rabaey, Pedram, “Low power design methodologies” Kluwer Academic, 1997
3. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley, 2000

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

35
 EC 6052-- LOW POWER VLSI DESIGN -COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Need for low power VLSI chips, Sources of power dissipation on Digital
Integrated circuits, Emerging Low power approaches. 3
I 25
Physics of power dissipation in CMOS devices. Device & Technology
Impact on Low Power, Dynamic dissipation in CMOS, Transistor sizing 7
& gate oxide thickness, Power estimation, SPICE circuit simulators.

FIRST INTERNAL EXAM

Simulation Power analysis: Gate level logic simulation, Capacitive
power estimation, Static state power, Gate level capacitance estimation,
Architecture level analysis, Data correlation analysis in DSP systems,
5 25
II Monte Carlo simulation.

Probabilistic power analysis: Random logic signals, Probability &

frequency, Probabilistic power analysis techniques, Signal entropy. 5

Low Power Design- Circuit level: Power consumption in circuits, Flip

Flops & Latches design, High capacitance nodes, Low power digital
cells library. 5
Logic level: Gate reorganization, Signal gating, Logic encoding, State
III 25
machine encoding, precomputation logic.
Low power Architecture & Systems: Power & performance
management, Switching activity reduction, Parallel architecture with
5
voltage reduction, Flow graph transformation.

SECOND INTERNAL EXAM

Low power arithmetic components, Low power memory design.
Low power Clock Distribution: Power dissipation in clock distribution,
Single driver Vs. distributed buffers, Zero skew Vs tolerable skew, chip 5
& package co design of clock Network.
IV 25
Algorithm & architectural level methodologies: Introduction, Design
flow, Algorithmic level analysis & optimization, Architectural level
5
estimation & synthesis.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

36
 Course No. Course Name L-T-P Credits Year of Introduction
VLSI Design Automation
03 EC6062 3-0-0 3 2015

Course Objectives
 To impart knowledge of various graph algorithms in VLSI
 To impart knowledge on automation methods for VLSI physical design
 To impart knowledge of various levels of automation in VLSI CAD.

Syllabus
Graph Algorithms: Data structures for Representation of Graphs and introduction to various graph
algorithms. N-P complete Problem: Polynomial time non-deterministic algorithm, N-P
completeness and reducibility, Proof and problems. Logic synthesis &verification in VLSI
automation, Compaction: One-dimensional compaction, Two dimension based compaction,
Hierarchical compaction. VLSI Algorithms for Partitioning, Placement, floor planning & pin
assignment. Routing in VLSI, Global Routing, Detailed routing algorithms . constraints and method
of optimization.

Expected Outcome
1. Extend the acquired knowledge to develop VLSI CAD for different automation levels.

References
1. Sabih H. Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons, 1999
2. Naveed Shervani, Algorithms for VLSI physical design Automation, Kluwer Academic
Publisher, Second edition. 1999
3. ChristophnMeinel& Thorsten Theobold, Algorithm and Data Structures for VLSI Design, KAP,
2002.
4. Rolf Drechsheler ,Evolutionary Algorithm for VLSI, Second edition 1998
5. Trimburger, Introduction to CAD for VLSI, Kluwer Academic publisher, 2002
6.T .H. Cormen, C. E. Leiserson, R. L. Rivest ,Introduction to Algorithms, PHI.2009

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

37
 03EC6062-VLSI DESIGN AUTOMATION -COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Graph Algorithms: Data structures for Representation of Graphs,

Breadth First Search, Depth First Search, Topological Sort, Spanning
Tree Algorithm - Kruskal’s and Prim’s, Shortest path Algorithm -
Dijkstra’s and Bellman Fort Algorithm for single pair Shortest paths,
7
Floyd-Warshall algorithm for All pair Shortest path, Matrix
I multiplication modeling of All pairs shortest path problem, Min cut and 25
Max cut Algorithms.

N-P complete Problem: Polynomial time non-deterministic algorithm,

N-P completeness and reducibility, Proof and problems. 3

FIRST INTERNAL EXAM

Logic synthesis &verification: Introduction to combinational logic
synthesis, Binary Decision Diagram, Hardware models for High-level
synthesis, Allocation , Assignment and scheduling. 5 25
II
Compaction: Problem formulation, One-dimensional compaction, Two
dimension based compaction, Hierarchical compaction. 5

VLSI automation Algorithms: Partitioning-Problem formulation,

Classification of partitioning algorithms, Group migration algorithms, 5
Simulated annealing & evolution, Other partitioning algorithms.
III Placement, floor planning & pin assignment: Problem formulation, 25
Placement algorithms, Floor planning concepts, Constraint based floor
planning, Floor planning algorithms for mixed block & cell design, 5
General & channel pin assignment.

SECOND INTERNAL EXAM

Global Routing: Problem formulation, Classification of global routing
algorithms, Maze routing algorithm, Line probe algorithm, Steiner Tree
5
based algorithms, ILP based approaches.

IV Detailed routing: Problem formulation, Single layer routing algorithms, 25%

Two layer channel routing algorithms, Three layer channel routing
algorithms and switchbox routing algorithms. Over the cell routing &
5
via minimization: Two layers over the cell routers, Constrained &
unconstrained via minimization.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

38
 Course No. Course Name L-T-P Credits Year of Introduction

03EC 6072 TESTING OF VLSI 3-0-0 3 2015

CIRCUITS

Course Objectives
 To introduce the scope and need of digital testing in VLSI design.
 To teach various testing methods for digital circuits.
 To introduce various methods of memory testing

Syllabus
Introduction to test and design for Testability Fundamentals: Modeling digital circuits, Levels of
Modeling, Logic Simulation Types Logic Fault models, Fault detection and redundancy.
Testing for single Stuck Faults (SSF), Compaction and Compression, Selecting ATPG Tools.
Design for Testability: Testability trade offs and techniques, Compression Techniques – Syndrome
test band signature analysis, Ad-hoc design.Digital DFT and Scan design, Built-in Self test- random
logic: BIST and memory logic BIST, Boundary Scan standard, Memory Test-Analog and Mixed
signal, Introduction to automatic in circuit testing.

Expected Outcome
 Extend the acquired knowledge to develop efficient testing and fault detection
methods for chip design

Reference

1. Viswani D Agarwal and Michael L Bushnell, Essentials of Electronic Testing of Digital

Memory and Mixed Signal VLSI Circuits, Springer, 2000.
2. MironAbramovici, Melvin A. Breur, Arthur D. Friedman ,Digital systems Testing and testable
Design,,Jaico Publishing House, 2001.
3. Englehood cliffs, Robert J. Feugate, Jr., Steven M. Mentyn, Introduction to VLSI Testing,
Prentice Hall,1998
4. Alfred L Cronch, Design for Test for Digital IC’s and Embedded Core system,
Prentice Hall, 1999.
5. NirajJha and Sanjeep K Gupta, Testing of Digital Systems, Cambridge University
Press, 2003.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

39
 03EC 6072- TESTING OF VLSI CIRCUITS -COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Introduction to test and design for Testability Fundamentals:

Modeling- Modeling digital circuits at logic, Register and structural 5
models, Levels of Modeling, Logic Simulation Types of simulation,
I 25
Delay models, Element evaluation, Hazard detection , Gate level event
driven simulation, Logic Fault models, Fault detection and redundancy,
5
Fault equivalence and fault location.

FIRST INTERNAL EXAM

Testing for single Stuck Faults (SSF): Automated test pattern
generation (ATPG/ATG) for SSFs in combinational and sequential
circuits. 5 25
II
Functional Testing with specific fault models, Vector Simulation ATPG
Vectors, Formats, Compaction and Compression, Selecting ATPG Tools. 5

Design for Testability: Testability trade offs and techniques Scan

Architectures and testing Controllability and observability, Generic
Boundary scan, Full integrated scan, Storage cells for scan design, Board
III 25
level and system level DFT approaches, Boundary scan standards, 10
Compression Techniques – Syndrome test band signature analysis, Ad-
hoc design, Generic scan based design, Classical scan based design.

SECOND INTERNAL EXAM

Digital DFT and Scan design, Built-in Self test- random logic: BIST
and memory logic BIST, Boundary Scan standard, Memory Test-Analog
and Mixed signal Test-delay test-IDDQ Test. DFT Fundamentals-ATPQ
IV Fundamental-Scan Architecture and Technique. System Test-Embedded 25
10
core testing-Introduction to automatic in circuit testing JTAG testing
features.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

40
Course No. Course Name L-T-P Credits Year of Introduction

03EC 6082 3-0-0 3 2015

MEMS

Course Objectives
 To introduce basics of MEMS
 To introduce various MEMS sensors and actuators
 To teach real time application studies using MEMS devices

Syllabus
History of Micro Electro Mechanical Systems (MEMS), MEMS Materials, Mechanical properties of
materials, Cantilevers and bridges, Point load & uniform loading, Torsional, Dynamic system;
Piezoelectric & piezo resistive materials. MEMS Fabrication processes, MEMS Devices &
Packaging. Application case studies of MEMS as Scanners, Grating, Light Valve (GLV), Digital
Micromirror Devices (DMD), Optical switching, Capacitive Micro-machined Ultrasonic
Transducers (CMUT), Air bag system, Micro-motors, Scanning Probe Microscopy.

Expected Outcome
 Extend the acquired knowledge to real life practical level to provide alternate
solutions to existing sensing technology.
 Utilize the knowledge acquired to design and develop MEMS instead of heavy
sensors.

Reference

1. Chang Liu, Foundation of MEMS, Second Edition 2011 –Pearson.

2. Gregory T A, Kovacs, Micromachined Transducers Sourcebook, WCB McGraw-
Hill,1998.
3. Stephen D. Senturia, Microsystem Design, Publishers: Kluwer Academic /Springer, 2nd
Edition (2005), ISBN: 0792372468
4. Marc Madou, Fundamentals of Microfabrication, CRC Press, New York, 2002.
5. Nadim Maluf, An introduction to Microelectro mechanical system design, Artech
House, 2000
6. Mohamed Gad-el-Hak, , The MEMS Handbook, CRC Press, Baco Raton,2002.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

41
 03EC 6082-MEMS-COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

History of Micro Electro Mechanical Systems (MEMS): Market for

MEMS, MEMS Materials: Silicon and other materials , Mechanical 5
I properties of materials- Elasticity, Stress and strain. 25
Beams & Structures –Cantilevers and bridges, Point load & uniform
loading, Torsional, Dynamic system; Piezoelectric & piezo resistive 5
materials.

FIRST INTERNAL EXAM

MEMS Fabrication processes: Review of IC fabrication process,
Micromachining: Bulk micromachining (dry and wet etching), Surface
micromachining (deposition, evaporation, sputtering, epitaxial growth), 6
25
II Deep RIE.
Advanced Lithography, LIGA process; Multi User MEMS Process.
4

MEMS Devices & Packaging: MEMS Sensors and Actuators

(Electrostatic, Electromagnetic, Thermal and Piezo), Bio-MEMS, Optical
III 25
MEMS, Micro-fluidics MEMS; MEMS packaging issues, die-level 10
packaging, micro assembled caps & sealing.

SECOND INTERNAL EXAM

Application case studies: MEMS Scanners and Retinal Scanning
Displays (RSD), Grating
IV Light Valve (GLV), Digital Micromirror Devices (DMD), Optical 25
10
switching, Capacitive Micromachined Ultrasonic Transducers (CMUT),
Air bag system, Micromotors, Scanning Probe Microscopy.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

42
Course No. Course Name L-T-P Credits Year of Introduction

03EC 6902 Mini Project 0-0-4 2 2015

Course Objectives

• For doing mini project students can take up any Industry oriented application /real life
problems/emerging technology in VLSI and embedded systems. The work will be supervised
and evaluated by a faculty member

• It is essential to submit a clear and concise report that reflects the literature survey, problem
identification, project aims and objectives, the engineering design work carried out, tests
performed, analysis and discussion of results.

Syllabus

No specific syllabus

Expected Outcome

The student gains in-depth knowledge in the concept/problem he/she has undertaken and allied
topics.

References

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

43
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 6802 Physical Design Laboratory 0-0-2 1 2015

Syllabus
Experiments are based on topics covered in subjects EC 6001, EC 6022

03EC 6802 – Physical Design Laboratory- EXPERIMENTS

Experiment No

Hours Allotted
Description

I Part A (Analog VLSI Design)

Parameter Extraction(Compulsory):

Using a SPICE simulator design a circuits (either pMOSFET or nMOSFET, use any
technology node from the available library) which should help in doing the
following jobs

 Extract threshold voltage, drain induced barrier lowering, body effect,

channel length modulation for different length ( L= 0.8Lmin, , Lmin, 2 Lmin, 3
Lmin…….5 Lmin)
I.A  Use the extracted values to plot ID Vs Vgs(Using MATLAB or any scientific 4
graph plotting tool)
 Report maximum and minimum error percentage (in linear and saturation
regions)
 List the reasons for error
 Analyze the fashion in which results vary with length
 Comment on the transition frequency for L=0.8 Lmin to 5 Lmin)
 Prepare a report with the information required and the extraction method.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

44
 Simulation and Characterization of minimum any three Analog Circuits given
below
- Use both Schematic and Layout design tools.

I.
B. Current Mirrors circuit
C. Inverting Amplifiers 4
(B-E)
D. Differential Pairs
E. Operational Transconductance Amplifiers
F. Operational Amplifier

II Part B (Digital VLSI Design)

Objective of part B experiments are:
A. Simulation and Characterization of the CMOS Logic Circuits Basic Gates
II.A (using CMOS, Domino CMOS logics) (both at Schematic and Layout level ) 4
(Compulsory)

B. Design a Minimum length inverter which meets the following

specification(Maximum acceptable error is 10%)(Compulsory)
 NML= NMH= (1/4)Vdd
 Switching Threshold - Vdd/2
 TPHL=TPLH
 Power dissipation
 Layout of the above inverter and compare pre and post layout simulation
II.B results
C. Design a five stage ring oscillator r using above inverter as an instance. 4
Compare the frequency with that of a ring oscillator designed with
transistors having twice the length to meet the same conditions of noise
margin, propagation delay and switching threshold) (Compulsory)

Simulation and Characterization of minimum any three Digital Circuits given

below
- Use both Schematic and Layout design tools.
II
C. Two input CMOS NAND/ NOR gate 4
(C-G)
D. Realize any thee variable sum of product function
E. Parallel shifter
F. XOR gate using pass gate

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

45
 G. D-Flipflop

III MOSFET Device Characterization(optional)

MOSFET Device Characterization for Small Signal Device Parameters and

extraction of various parasitic effects
a) Realize any one architecture of advanced device (such as FinFET, CNTFET,
Graphene Transistor, Herto-junction device, Nanowire devices using any
available TCAD
4
or
b) Study about any one of the device such as FinFET, CNTFET, Graphene
Transistor, Herto-junction device, Nanowire devices using analytical
models using MATLAB or by using compact SPICE models

Note :
End semester evaluation through mini project based knowledge acquired from the lab sessions

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

46
Course No. Course Name L-T-P Credits Year of Introduction
03EC7003 Electromagnetic Compatibility 3-0-0 3 2015

Course Objectives

 To learn the Electromagnetic Compatibility issues in Electronic System Design.

Syllabus

Need of Electromagnetic compatibility, Noise and Interference, Noise sources, Non-ideal behavior
of electronic components, Cabling-Capacitive and Inductive coupling, Balanced loads, Effect of
power supply decoupling on noise coupling, Grounding, Power Supplies, DC-DC Converters,
Power-Line Filters
Expected Outcome
Understand the EMC issues in design process

References
1. Henry W. Ott, “Electromagnetic Compatibility Engineering”, John Wiley & Sons,
Inc. Publication.2009
2. Clayton R. Paul, “Introduction to Electromagnetic Compatibility”, Second
Edition, John Wiley & Sons, Inc. Publication.2006

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

47
 03EC 7003 Electromagnetic Compatibility– COURSE PLAN

Examination
% of Marks

Semester
Allotted
Module

in End-
Hours
Contents

Need of Electromagnetic compatibility, Noise and Interference, Noise

sources, Non-ideal behavior of electronic components, Typical Noise
I Path, Methods of Noise Coupling, Near fields and Far fields, Radiated
10 25
Emission, Conducted Emission, Radiated Susceptibility, Conducted
Susceptibility, Need of EMC Regulations, FCC Regulations, CISPR/IEC
Regulations, Military Standards, Advantages of EMC design
FIRST INTERNAL EXAM
Cabling-Capacitive and Inductive coupling, Effect of shield on
Capacitive and Inductive coupling, Magnetic coupling between shield
and inner conductor, Shielding Effectiveness, Shielding to Prevent
Magnetic Radiation, Shielding a receptor against magnetic fields, Shield
Transfer Impedance, Shielding properties of various cable
configurations, Coaxial cable and Shielded Twisted Pair, Braided
II shields, Ribbon cables, Shield terminations, Pigtails, Grounding of Cable
12 25
Shields, Low frequency, High frequency and Hybrid, Signal Balancing-
CMRR, Cable balance, System balance, Balanced loads- Differential and
Instrumentation amplifiers, Transformer coupled inputs, Input cable
shield termination. Signal filtering- Common Mode filters, Parasitic
effects in filters, Effect of power supply decoupling on noise coupling-
Analog circuit decoupling, Amplifier Decoupling, driving capacitive
loads, System bandwidth.
Grounding- Safety grounds, Signal grounds, Single point, multipoint
and hybrid ground systems, Chassis grounds, System grounding,
Isolated systems, Safety and Signal grounding of clustered systems,
Inter-Unit Cabling, Ground loops , Breaking of ground loop using
Transformers, Common-mode chokes and Optical couplers, Low and
High frequency analysis of Common-mode choke. PCB Layout-
Partitioning, Keep out zones, Critical Signals, System clocks, PCB-to-
III. Chassis ground connection, Return path discontinuities-Slots in 25
12
Ground/Power planes, Split Ground/Power planes, Changing
reference planes, Connectors, Ground fill, PCB stack up- One and two
layer boards, Multilayer boards- Basic multilayer PCB Structures,
General PCB design procedure, Mixed signal PCB Layout- Split ground
planes, Analog and Digital ground pins, Mixed Signal ICs, High
resolution A/D and D/A Converters- Stripline, Asymmetric Stripline,
Isolated Analog and Digital Ground planes, Vertical isolation, Mixed

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

48
 03EC 7003 Electromagnetic Compatibility– COURSE PLAN

Examination
% of Marks

Semester
Allotted
Module

in End-
Hours
Contents

Signal Power distribution, Industrial Process Control problem in PCB

Layout.

SECOND INTERNAL EXAM

Power Supplies – Linear and Switched Mode Power Supplies,
Conducted Emissions, Line Impedance Stabilization Network, Common
Mode and Differential Mode Emissions of SMPS, DC-DC Converters,
Rectifier Diode Noise, Power-Line Filters- Common Mode and
Differential Mode Filtering, Filter Mounting, Digital Circuit Power
Distribution- Power supply decoupling, Transient Power supply
currents, Decoupling Capacitors, Effective decoupling strategies, Effect
IV of decoupling on Radiated Emissions, Decoupling Capacitor Type and 25
10
Value, Decoupling Capacitor Placement and Mounting, Bulk
decoupling Capacitors, Power Entry Filters, Electrostatic Discharge
(ESD) ,Static generation, Human body model, Static discharge, ESD
protection in equipment design, Preventing ESD entry- Metallic
Enclosures, Input/output Cable treatment, Insulated enclosures,
Keyboards and Control panels, Hardening sensitive circuits, ESD
grounding, Non-grounded products, Field induced upset.
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

49
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 7013 Embedded Linux Systems 3-0-0 3 2015

Course Objectives

To introduce the students to Linux Embedded OS

To understand Embedded drivers and application porting

Syllabus

Introduction to Embedded Linux, Real Time Linux, Types of Embedded Linux systems,
Cross platform Development tool chain, Kernel and Root File System, Storage Device
Manipulation, Embedded Bootloaders , File system Types for Embedded Devices, Device
Drivers

Expected Outcome

Conceptual understanding of RTOS Embedded drivers

References
1. Karim Yaghmour, JonJason Brittain and Ian F. Darwin Masters, Gilad Ben-Yossef, and
Philippe Gerum ,”Building Embedded Linux Systems”, O’Reilly,2008
2. Alessandro Rubini, Jonathan Corbet, “Linux Device Drivers “, O’Reilly,2001
3. Christopher Hallinan, “Embedded Linux Primer A Practical Real – World Approach”,
Prentice Hall,2006
4.P Raghavan, Amol Lad, Sriram Neelakandan, “Embedded Linux System Design and
DevelopmentAuerbach “,Publications ,2005
5. Alan Cox, Sreekrishnan, Venkateswaran,” Essential Linux Device Drivers” , Prentice
Hall ,2008
6.Craig Hollabaugh, “Embedded Linux Hardware, Software and Interfacing” Pearson
Education ,2002

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

50
 03EC 7013 Embedded Linux Systems - COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Introduction: Embedded Linux, Real Time Linux, Types of Embedded

Linux systems, Advantages of Linux OS, Using distributions, Examples
of Embedded Linux systems- system architecture, Types of host/target
architectures for the development of Embedded Linux Systems, Debug
I setups, Boot Configurations, Processor architectures supported by
10 25
Linux
Cross platform Development tool chain: GNU tool chain basics, Kernel
Headers Setup, Binutils setup, Bootstrap Compiler Setup, Library Setup,
Full Compiler Setup, Using the tool chain, C library alternatives, JAVA,
Perl, Python, Ada, IDEs , Terminal Emulators
FIRST INTERNAL EXAM
Kernel and Root File System :Kernel Considerations- selection,
configuration , Compiling and Installing the kernel Root File System
Structure, Libraries, Kernel Modules, Kernel Images, Device Files, Main
II System Applications, Custom Applications, System Initialization
10 25
Storage Device Manipulation: MTD-Supported Devices, Disk Devices,
Swapping
Setting Up the Bootloader :Embedded Bootloaders, Server Setup for
Network Boot, Using the U-Boot Bootloader
Root File system Setup: File system Types for Embedded Devices,
Writing a File system Image to Flash using an NFS-Mounted Root File
system, Placing a Disk File system on a RAM Disk, Rootfs and Initramfs,
III 25
Choosing a File system’s Type and Layout, Handling Software 10
Upgrades

SECOND INTERNAL EXAM

Device Drivers: Introduction, Building and running modules, Char
IV Drivers, Allocating memory, USB Drivers, Device Model, Memory 25
10
mapping and DMA, Block Drivers
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

51
 Course No. Course Name L-T-P Credits Year of Introduction
03EC 7023 ELECTRONIC PACKAGING 3-0-0 3 2015

Course Objectives

 To learn the various aspects of Microsystems packaging.

Syllabus

Functions of an Electronic Package, Packaging Hierarchy, Role of Packaging in Microsystems-

Electrical Package Design ,Design for Reliability ,IC Assembly ,Sealing and Encapsulation- Printed
Wiring Board ,Board Assembly ,Role of Materials in Microsystems Packaging- Packaging Materials
and Properties, Electrical Testing , Life Cycle assessment.

Expected Outcome
1. Understand basic concepts in Electronic packing

References
1. Rao R. Tummala,Fundamentals of Microsystems Packaging, McGraw Hill.2007
2. Richard K. Ulrich &William D. Brown Advanced Electronic Packaging - 2nd Edition : IEEE
Press ,2006

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

52
 03EC 7023 Electronic Packaging– COURSE PLAN

% of Marks in
End-Semester
Examination
Allotted
Module

Hours
Contents

Functions of an Electronic Package, Packaging Hierarchy, Role of

Packaging in Microsystems- Computer industry, Telecommunication
industry, Automotive systems, Medical Electronics, Consumer
Electronics, Micro-Electro-Mechanical Systems products,
I Microelectronic packaging- IC packaging- Wafer to system process, 8 25
IC packaging parameters, Different types of IC packages, Electrical
Package Design- Electrical Anatomy of Systems Packaging, Signal
Distribution, Power Distribution, Electromagnetic Interference,
Design Process
FIRST INTERNAL EXAM
Design for Reliability – Fundamentals, Induced failures- Thermo-
mechanical, Electrical and Chemical, Single chip
packaging- Materials, Processes and Properties, Multichip Packaging-
II Functionality, Advantages, Multichip Modules at the System level,
7 25
Wafer Level Packaging- Technologies, Reliability, Wafer-Level Burn-
In and Test, IC Assembly – Purpose, Requirements, Technologies,
Wire bonding, Tape Automated Bonding, Flip Chip, Discrete,
Integrated and Embedded Passives.
Sealing and Encapsulation- Necessity, Fundamentals, Requirements,
Materials, Processes, Hermetic sealing, Printed Wiring Board –
III Anatomy, Fundamentals, CAD tools for PWB design, Standard PWB
8 25
materials and Fabrication, Microvia Boards, Board Assembly –
Generic Assembly issues, Through-Hole Technology, Surface Mount
Technology, Process Control and Design challenges
SECOND INTERNAL EXAM
Role of Materials in Microsystems Packaging- Packaging Materials
and Properties, Materials Processes- Thick Film, Thin Film, Thermal
Management, Cooling Requirements, Thermal management of IC
IV and PWB packages, Electronic cooling methods. Electrical Testing –
7 25
System level Electrical Testing, Interconnection Tests, Active Circuit
Testing, Design for Testability, Microsystems design for
environment- Environmental Concerns, Influence of Electronics
production, Life Cycle assessment.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

53
 Course No. Course Name L-T-P Credits Year of Introduction

03EC 7033 3-0-0 3 2015

SEMICONDUCTOR MEMORIES

Course Objectives
 To understand various semiconductor memory technology

Syllabus
Random Access Memory Technologies :Static Random Access Memories (SRAMS)- Bipolar SRAM
Technologies, Silicon On Insulator (SOI) Technology, Application Specific SRAMs. Dynamic
Random Access Memories (DRAMs)- DRAM Technology Development, CMOS DRAMs and its
advanced design, BiCMOS DRAMs, Soft Error Failures in DRAMs. Nonvolatile Memories: High
Density ROMs ,Programmable Read-Only Memories Bipolar PROMs-CMOS PROMs, EPROMs
Memory Fault Modeling, Testing, Memory Design For Testability and Fault Tolerance RAM Fault
Modeling, Electrical Testing, Application Specific Memory Testing. Semiconductor memory
reliability and radiation effects : General Reliability Issues in memory and its modelling and testing
methods.

Expected Outcome
 Extend the acquired knowledge to design and develop power efficient, highly
reliable low cost memory circuits.

Reference

1. Ashok K. Sharma, Semiconductor Memories: Technology, Testing, and Reliability, Wiley- IEEE
Press, 2002.
2. Ashok K. Sharma, Semiconductor Memories, Two-Volume Set, Wiley-IEEE Press,
2003.
3. Ashok K. Sharma, Semiconductor Memories: Technology, Testing, & Reliability,
Prentice Hall of India, 1997.
4. Brent Keeth, R. Jacob Baker, DRAM Circuit Design: A Tutorial, Wiley-IEEE Press,
2000.
5. Betty Prince, High Performance Memories: New Architecture DRAMs and SRAMs Evolution &
Function, Wiley, 1999.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

54
 03EC 7033 Semiconductor Memories -COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

Random Access Memory Technologies :Static Random Access

Memories (SRAMS)- SRAM Cell Structures, MOS SRAM Architecture,
MOS SRAM Cell and Peripheral Circuit Operation, Bipolar SRAM 5
Technologies, Silicon On Insulator (SOI) Technology, Application
I 25
Specific SRAMs.
Dynamic Random Access Memories (DRAMs)- DRAM Technology
Development, CMOS DRAMs, DRAMs Cell Theory and Advanced Cell
5
Structures, BiCMOS DRAMs, Soft Error Failures in DRAMs,
Application Specific DRAMs.
FIRST INTERNAL EXAM
Nonvolatile Memories: Masked Read-Only Memories (ROMs),High
Density ROMs. 4
25
II
Programmable Read-Only Memories (PROMs), Bipolar PROMs-CMOS
PROMs, EPROMs ,Floating, Gate EPROM Cell 5

Memory Fault Modeling, Testing, Memory Design For Testability

and Fault Tolerance :RAM Fault Modeling, Electrical Testing, Pseudo
III 25
Random Testing, Megabit DRAM Testing, Nonvolatile Memory, 10
Modeling and Testing ,Application Specific Memory Testing

SECOND INTERNAL EXAM

Semiconductor memory reliability and radiation effects :General
Reliability Issues, RAM Failure Modes and Mechanism, Nonvolatile
IV Memory Reliability, Reliability, Modeling and Failure Rate Prediction, 25
10
RAM Fault Modeling, Electrical Testing, Pseudo Random Testing,
Megabit DRAM Testing, Nonvolatile Memory Modeling and Testing,
Application Specific Memory Testing.
END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

55
 Course No. Course Name L-T-P Credits Year of Introduction

03EC7043 SYSTEM ON CHIP DESIGN 3-0-0 3 2015

Course Objectives
 To learn the various aspects of SoC design
 To familiarize various testing and verification methods used in SoC designs

Syllabus
System On Chip Design Process, Soft IP vs Hard IP, Macro Design Process, Design issues, System
Integration with reusable macros.Design for Testability Fundamentals: Faults in Digital circuits,
Fault models ,Digital test pattern generation , Compaction and Compression., Scan Architectures
and testing, Built in Self Test (BIST):BIST concepts and test pattern generation. SoC Verification:
Verification methodology, languages, approaches and plans. System level and Block level
verification. Hardware/software co-verification and Static net list verification.MPSoCs: Techniques
for designing MPSoCs, Performance and flexibility for MPSoCs design, MPSoC performance
modeling and analysis. System-In-Package (SIP) design.

Expected Outcome
 Extend the acquired knowledge to practical real life scenario

Reference
1. Prakash Rashinkar, Peter Paterson and Leena Singh, SoC Verification-Methodology and
Techniques, .Kluwer Academic Publishers, 2001.
2. Michael Keating, Pierre Bricaud, Reuse Methodology manual for System-On-A-Chip Designs,
Kluwer Academic Publishers, second edition, 2001.
3. Miron Abramovici, Melvin A. Breur, Arthur D. Friedman, Digital systems Testing and testable
Design, Jaico Publishing House, 2001.
4. William K.Lam, Design Verification: Simulation and Formal Method based Approaches,Prentice
Hall.2005
5. Rochit Rajsuman, System-on-a-Chip-Design and Test,ISBN.2000
6. A.A.Jerraya, W.Wolf, Multiprocessor Systems-on-chips, M K Publishers.2008
7. Dirk Jansen, The EDA HandBook, Kluwer Academic Publishers.2003
8. Alfred Crouch, Design for test for digital IC & Embedded Core Systems, Prentice hall.1999
9. Stanley L. Hurst, VLSI Testing: digital and mixed analogue digital techniques, Pub:Inspec / IEE,
1999

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

56
 03EC7043 SYSTEM ON CHIP DESIGN -COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

Contents

System On Chip Design Process: A canonical SoC Design, SoC Design

flow - Waterfall vs spiral, Top-down vs Bottom up, Specification
requirement, Types of Specification, System Design process, System 5
I level design issues- Soft IP vs Hard IP. 25

Macro Design Process: Top level Macro Design, Macro Integration, Soft
Macro productization, Developing hard macros, Design issues for hard 5
macros, Design process, System Integration with reusable macros.

FIRST INTERNAL EXAM

Design for Testability Fundamentals: Faults in Digital circuits, Fault
models ,Digital test pattern generation – ATPG, Roth's D-algorithm,
Vector Simulation- ATPG Vectors, Formats, Compaction and 5
Compression. 25
II
Scan Architectures and testing- , Generic Boundary scan, Full
integrated scan, Syndrome test band signature analysis. Built in Self 5
Test (BIST):BIST concepts and test pattern generation

SoC Verification: Verification technology options, Verification

methodology, Verification languages, Verification approaches and
III 25
Verification plans, System level verification, Block level verification, 10
Hardware/software co-verification and Static net list verification.

SECOND INTERNAL EXAM

MPSoCs: What, Why, How MPSoCs. Techniques for designing
IV MPSoCs, Performance and flexibility for MPSoCs design, MPSoC 25
10
performance modeling and analysis. System-In-Package (SIP) design.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

57
 Course No. Course Name L-T-P Credits Year of Introduction

EC 7053 VLSI INTERCONNECTS 3-0-0 3 2015

Course Objectives
 To Familiarize the current interconnect technology
 To familiarize about modeling of interconnects
 To familiarize the analysis of interconnect performance
 To understand the future trends in interconnect technology

Syllabus
Preliminary Concepts Of VLSI Interconnects: Interconnects for VLSI applications, Copper
interconnections, interconnects modelling methods and delay analysis. Extraction of Parasitic
Resistances, Capacitance and Inductances of interconnects. Approximate formulas for the
estimation of inductances. Interconnection Delay models : micro strip line, Transmission line
analysis for single and multi level interconnections, Analysis of crossing interconnections,
Modeling of lossy parallel and crossing interconnects, High frequency losses in micro strip line.
Cross Talk Analysis :Lumped capacitance approximation, Coupled multi conductor MIS microstrip
line model for single level interconnects, Frequency domain level for single level interconnects,
Transmission line level analysis of parallel multilevel interconnections. Emerging interconnect
technologies and its performance Comparison against copper.

Expected Outcome
 Extend the acquired knowledge to model different VLSI interconnects
 Design and implement efficient algorithms for the prediction interconnect
performance at design level

Reference

1. Askok K Goel, High speed VLSI interconnections, Wiley inter-science, second edition, 2007.
2. J A Davis, J D Meindl, Interconnect technology and design for Giga scale integration, Kluwer
academic publishers.2003
3. Nurmi J, Tenhumen H, Isoaho J, Jantsch A, Interconnect Centric deisgn for advanced SOC and
NOC, Springer.2004
4. C K Cheng, J Lillis, S Lin, N Chang, Interconnect analysis and synthesis, Wiley inter-
science.2000
5. Hall S H, G W Hall and J McCall, High speed digital system design, Wiley inter-science,2000
6. Chung-Kuan Cheng,John Lillis,Shen Lin and Norman H.Chang,Interconnects Analysis and
Synthesis,Wiley-interscience publication,2000

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

58
 EC 7053 VLSI INTERCONNECTS-COURSE PLAN

Hours Allotted

% of Marks in
End-Semester
Examination
Module

EC 5032-Contents

Preliminary Concepts Of VLSI Interconnects: Interconnects for VLSI

applications, Copper interconnections ,Method of images, Method of 4
I moments, Even and odd capacitances. 25%
Transmission line equations, Miller’s theorem, Resistive interconnects
as ladder network, Propagation modes in micro strip interconnects, 6
Slow wave propagations, Propagation delay.

FIRST INTERNAL EXAM

Parasitic Resistances, Capacitance And Inductances: Parasitic
resistances, Capacitances and inductances.
4
Approximate formulas for inductances, Green’s function method: Using
25%
II method of images and Fourier integral approach, Network Analogy
method, Inductance extraction using fast Henry, copper 6
interconnections for resistance modeling.

Interconnection Delays: Metal insulator semiconductor micro strip line,

Transmission line analysis for single level interconnections,
Transmission line analysis for parallel multilevel interconnections,
III 25%
Analysis of crossing interconnections, Parallel interconnection models 10
for micro strip line, Modeling of lossy parallel and crossing
interconnects, High frequency losses in micro strip line, Expressions for
interconnection delays, Active interconnects.
SECOND INTERNAL EXAM
Cross Talk Analysis :Lumped capacitance approximation, Coupled
multi conductor MIS microstrip line model for single level
25%
interconnects, Frequency domain level for single level interconnects, 6
Transmission line level analysis of parallel multilevel interconnections.
IV
Emerging interconnect technologies: Optical interconnects ,Carbon
Nano tubes / Graphenes vs. Copper wires, Comparison of these
4
interconnect technologies against copper.

END SEMESTER EXAM

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

59
Course No. Course Name L-T-P Credits Year of Introduction
03EC7903 Seminar II 0-0-2 1 2015

Course Objectives

• Identify Seminar topic relevant to the project with content suitable for
M.Tech level Presentation.
 Do extensive study and analysis of the problem and solution(s)
 Prepare a comprehensive report
 Make a presentation (20-25 minutes) based on the report

Syllabus
.
No specific Syllabus

Expected Outcome

To student
 gets good exposure to a domain of interest and the research problems in the
domain
 improves his/her writing and presentation skills

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

60
 Course No. Course Name L-T-P Credits Year of Introduction
03EC7913 Project (Phase I) 0-0-12 6 2015

Course Objectives
The main objective of the thesis is to provide an opportunity to each student to do an independent
study and research in the area of specialization under the guidance of a faculty member.
The student is required to explore in depth and a topic of his/her own choice, which adds
significantly to the body of knowledge existing in the relevant field. The student has to undertake
and complete the preliminary work on the stream of specialization during the semester.

Syllabus
.
No specific Syllabus

Expected Outcome
Each student shall identify a project related to the curriculum of study. At the end of the
semester, each student shall submit a project report comprising of the following.

 Aim and objective of the project

 State of art of the related work in the specified area through literature survey

 Application and feasibility of the project

 Complete and detailed design specifications.

 Minimum Project completion status at time of final review

 Root paper implementation and identification open ends and corresponding solution
methodology / Basic system realization at bread board level in case of embedded systems. /
System simulation at HDL level and identification hardware platform required in case of
projects based on FPGA and Bill of materials in standard format and cost model, if
applicable
 Project implementation action plan using standard presentation tools
Students are expected to do the project within the college. However they are permitted
to do the project in an industry or in a government research institute under a qualified supervisor
from that organization. Progress of the project work is to be evaluated at the end of the third
semester. For this a committee headed by the head of the department with two other faculty
members in the area of the project, of which one shall be the project supervisor. If the project is
done outside the college, the external supervisor associated with the student will also be a
member of the committee.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

61
 Course No. Course Name L-T-P Credits Year of Introduction
03EC7914 Project (Phase II) 0-0-21 12 2015

Course Objectives

By the first quarter of the semester, the student should compile his/her work by doing the final
experimentation and result analysis. Towards the middle of the semester there would be a pre-
submission seminar to assess the quality and quantum of work by the department evaluation
committee. This would be the pre-qualifying exercise for the students for getting approval for the
submission of final thesis. The decision of the departmental committee in this regard is final and
binding. The committee can make recommendations to improve the quality or quantity of the work
done. The final evaluation of the thesis would be done by an external examiner. The external
examiner’s comments regarding the quality and quantity of work is an important decisive factor in
the final acceptance/rejection of the thesis.

Syllabus
.
No specific Syllabus

Expected Outcome

In the implementation phase specified in this semester each student should complete following
minimum requirement:

 For hardware projects, practical verification of the design, PCB design, fabrication, design
analysis and testing shall be done.
 For software projects, a proper front end (GUI) if applicable shall be designed. A detailed
algorithm level implementation, test data selection, validation, analysis of outputs and
necessary trial run shall be done.
 Integration of hardware and software, if applicable, shall be carried out.
 A detailed project report in the prescribed format shall be submitted at the end of the
semester. All test results and relevant design and engineering documentation shall be
included in the report.
 The student is expected to publish technical papers related to his/her research in
peer reviewed journals/conferences.

Cluster: 03 Branch:Electronics and communication Engineering Stream: VLSI and Embedded systems

62