Micro Project Report

on
AES Algorithm Using VHDL
SUBMITTED BY

HITESH B. TUMSARE

ENROLLMENT NO:-2200910316

Roll No: 32 (EJ6I)

GUIDED BY:-PROF. R.B. Sathe

Sir ODD-24

(ELECTRONICS AND TELECOMMUNICATION ENGG.)

ACADEMIC SESSION 2023-24

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION

ENGG.
GOVERNMENT POLYTECHNIC SAKOLI
 GOVERNMENT POLYTECHNIC
SAKOLI
DEPARTMENT OF ELECTRONICE ANDTELECOMMUNICATION ENGG.

CERTIFICATE

This is to certify that the Micro Project report titled submitted AES Algorithm
Using VHDL by Hitesh Tumsare of VI semester towards the partial fulfilment
of requirement for the award of diploma in electronics and telecommunication.

DATE:

YEAR: 2023-24

PROF.R.B.Sathe sir PROF.A. A.ALI

GUIDE OF Micro Project H.O.D

 ACKNOWLEDGEMENT

I would like to place on record of our deep sense of gratitude to Prof.R.V.Sakhre

lecturer, Dept. of Electronics & Telecommunication for her generous guidance,
help and useful suggestions.
I express our sincere gratitude to Prof. A. A. Ali, Head of Dept. of Electronics &
telecommunication, for his stimulating guidance, continuous encouragement and
supervision throughout the course of present work.
I am extremely thankful to Prof. S. P. Lambhade, Principal, for providing me
infrastructural facilities to work in, without which this work would not have been
possible.

THANK YOU

Hitesh Tumsare - 2200910316

 INDEX
Sr. no. Content Page No.

1 Introduction

2 Arithmetic Logic Unit

3 Limitation of ALU

4 Floating Point AU

5 Block Diagram

6 Four modules in FPAU

Add, Sub, Div, Multiple
Algorithm.

7 Conclusion

8 Reference
Introduction

Floating-point numbers are widely adopted in many applications due to its dynamic
representation capabilities. Floating-pointRepresentation is able to retain its
resolution and accuracy compared to fixed-point representations. Based on this
standard, floatingpoint representation for digital systems should be platform-
independent and data are interchanged freely among different digital Systems. ALU
is a block in a microprocessor that handles arithmetic operations. It always performs
computation of floating-point Operations. Some CPUs such as AMD Athlon have
more than one floating point unit that handles floating point operations. The Use of
VHDL for modeling is especially appealing since it provides a formal description of
the system and allows the use ofspecific Description styles to cover the different
abstraction levels (architectural, register transfer and logic level) employed in the
design. In the computation of method, the problem is first divided into small pieces;
each can be seen as a submodule in VHDL. Pipelining Is one of the popular methods
to realize high performance computing platform. Implementing pipelining requires
various phases Of floating-point operations be separated and be pipelined into
sequential stages. This increases the throughput and efficiency of The overall
operation. Hence to realize an ALU design, this research proposes a pipeline floating
point ALU design using VHDL To ease the description, verification, simulation and
hardware realization. VHDL is a widely adopted standard and has numerous
Capabilities that are suited for designs of this sort.
ARITHMETIC LOGIC UNIT

An arithmetic logic unit (ALU) is a digital electronic circuit that performs

arithmetic and bitwise logical operations On integer binary numbers. This
is in contrast to a floating-point unit (FPU), which operates on floating
point numbers. An ALU Is a fundamental building block of many types of
computing circuits, including the central processing unit (CPU) of
computers, FPUs, and graphics processing units (GPUs). A single CPU,
FPU or GPU may contain multiple The inputs to an ALU are the data to
be operated on, called operands, and a code indicating the operation to be
performed; the ALU’s output is the result of the performed operation. In
many designs, the ALU also exchanges additional information with a
Status register, which relates to the result of the current or previous
operations.
Signals

An ALU has a variety of input and output nets, which are the shared
electrical connections used to convey digital signals between The ALU
and external circuitry. When an ALU is operating, external circuits apply
signals to the ALU inputs and, in response, the ALU produces and
conveys signals to external circuitry via its outputs.

Data

A basic ALU has three parallel data buses consisting of two input
operands (A and B) and a result output (Y). Each data bus is a Group of
signals that conveys one binary integer number. Typically, the A, B and Y
bus widths (the number of signals comprising Each bus) are identical and
match the native word size of the encapsulating CPU (or other processor).

Opcode

The opcode inputis a parallel bus that conveys to the ALU an operation
selection code, which is an enumerated value that specifies The desired
arithmetic or logic operation to be performed by the ALU.

Status

The status outputs are various individual signals that convey supplemental
information about the result of an ALU operation. These Outputs are
usually stored in registers so they can be used in future ALU operations or
for controlling conditional branching.
Fig. 1: a symbolic representation of an alu and its input and output signals,
indicated by arrows pointing into or out of the ALU, respectively.
Each arrow represents one or more signals

Limitation Of Alu

It operates only on integer values, hence less precise. When forced to be

operated on floating point numbers, then it results in slow operations and
lags in accuracy.

FLOATING POINT AU

A floating-point unit (FPU, colloquially a math coprocessor) is a part of a

computer system specially designed to carry out Operations on floating
point numbers. Typical operations are addition, subtraction,
multiplication, division, square root, and bit Shifting Single-precision
floating-point format is a computer number format that occupies 4 bytes
(32 bits) in computer memory and Represents a wide dynamic range of
values by using a floating point. In IEEE 754-2008 the 32-bit base 2
format is officially referred To as binary32. It was called single in IEEE
754-1985. Double-precision floating-point format is a computer number
format which occupies 8 bytes (64 bits) in computer memory and
Represents a wide, dynamic range of values by using a floating point.
Computers with 32-bit storage locations use two memory Locations to
store a 64-bit double-precision number; each storage location holds a
single-precision number.
Fig. 2: 32-bit single precision floating point number.
III. BLOCK DIAGRAM
There are four modules in FPAU, addition, subtraction, multiplication and
division. The algorithms for each are explained below.

Addition Algorithm

1) Take 2 floating point numbers.

2) Convert them to binary.

3) Normalize them.
4) Floating point is represented as S (sign bit-1), Exponent (*8 bit) and
significant (23 bits).
5) 5.127 is added to each exponent number.
6) The exponent is converted to binary and the smallest binary
exponent is subtracted from the largest and is taken as ‘d’.
7) The number which is the smaller is shifted to right d times.
8) It is then added to the larger number and its exponent is equal to the
larger exponent.

Multiplication Algorithm

1) XOR the sign bits

2) Add exponents and subtract 127 from them
3) Multiply the significant
4) Normalize the result
Subtraction Algorithm

1) Add 127 to each exponents and find difference between them.

2) Shift the smallest significant according to difference of exponent to
the right.
3) Find the twos compliment of largest significant.
4) Add the new significant.
5) Normalize it.
6) Results sign bit will sign bit of greatest significant.

Division Algorithm

5) XOR the sign bits

6) Subtract exponents and add 127 from them
7) Divide the significant
8) Normalize the result
 CONCLUSION

Design and implementation of floating point ALU is used instead of basic

ALU because of its capability to deal with floating Numbers. Also we
have chosen VHDL for simulation and analysis due to its various
advantages. We have studied about FPU, VHDL and about Xilinx
software. Then we studied the algorithm of each operation such as
addition, subtraction, multiplication And division and wrote its
corresponding VHDL code. And later we used Xilinx to simulate it.

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