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Ec 302

The document discusses questions related to VLSI design. It includes questions about fabrication steps for twin-tub CMOS process, scaling effects on MOS devices, relevant capacitances for an NMOS transistor, designing a depletion load inverter, determining voltage at a node in a circuit, and computing switching threshold voltage and rise time for an inverter.

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23 views1 page

Ec 302

The document discusses questions related to VLSI design. It includes questions about fabrication steps for twin-tub CMOS process, scaling effects on MOS devices, relevant capacitances for an NMOS transistor, designing a depletion load inverter, determining voltage at a node in a circuit, and computing switching threshold voltage and rise time for an inverter.

Uploaded by

gauravkumartech0
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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6th SEMESTER B.Tech. [EC]


MID SEMESTER EXAMINATIOON (March-2019)
EC-302 VLSI DESIGN
Time: 11/2 Hours Max. Marks: 20
Note: Answer all questions.
Assume suitable missing data, if any.
. a) Draw and Explain fabrication steps for twin-tub CMOS process. Aid your
answer with suitable diagrams. (3)
b) An NMOS transistor has threshold voltage on 1V. How would you change
threshold voltage to 0.8V and 1.2 V without changing the substrate bias? (Cox = 10

fF/cm). (2)
2. a) Explain the limitations imposed by small device geometries. How do scaling
affect the doping concentrations and power density if constant voltage scaling is
applied to MOS device. Why does VT increase for a short channel device and show
an increasing trend for narrow width device? (3)
b) Consider an NMOS transistor with the following parameters: ta 6 nm, L =
0.24 mm, W = 0.36 mm, drain (LD) and sourçe (Ly lengths = 0.625 mm, Co =

2xi0 F/m, Cavo2.75 10-°F/m. Determine the zero-bias value of all relevant
capacitances. (s=8.85 x 101* F/cm, Eox3.9e, and neglect overlap capacitance). (2)

3. a) Design a depletion load inverter with specifications as: VpD = 5V, VoL 0.2 V,

VTedriver IV and VTload-3V and power consumption of ImW. Find the widths of
driver and load transistor if both transistors have same channel length. 3)
b) Write down the equations (and only those) which are needed to determine the
voltage at node X in Fig. 1. Do NOT plug in any values yet. Neglect short channel
efiects and assume that Ap =0. Detemine the required width of the transistor (for L
=0.25 um) such that Xequals 1.5 V. k=304 AN?, VR--0.4 V. (2)
25 V

R 20 k

Fig.1
4. Consider a CMOS inverter that is designed in a process with the
parameters: ka' = 100uA/V, kp' = 40uAW, VTon= +0.7v and VTop= -0.8v. The
following
transistors have aspect ratios of(WL)»= 10 and (W/L), 15 and the
power supply
=

is chosen to be 5V. () Determine the value of


switching threshold voltage. (ii)
Compute the time it takes to rise from 1V to 4V when connected with CLoas
0.5pF (5)

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