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 Microprocessor is useless or cannot do anything without
peripherals
 It needs peripherals (Input or output devices )
 Input devices
 Keyboard

 Mouse

 Switch etc.

 Output devices
 Monitor

 Printer

 Motor

 LED etc

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 Butthe microprocessor and the peripherals are
mostly incompatible
 Have different speed
 Peripherals are slower
 Different data format
 Microprocessor work on digital data
 Peripherals work on analogue data
 Serial vss. Parallel
 Electrical value incompatibility
 So there is a need for making them compatible in
 Speed or
 Data format

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 I/O can be either:
- Isolated, or
- Memory mapped
 Isolated I/O: uses the dedicated I/O instructions
(IN, OUT) and has its own address space for I/O
ports (0000H-FFFFH)- isolated from the memory
address space
 Memory mapped I/O:
 uses memory reference instructions , e.g. MOV, and a
 So address space is shared between memory and I/O

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 Isolated I/O
 I/O locations are separate from memory locations
 Special I/O instructions are used
 The most common technique for Intel microprocessors
 Advantage: More space for memory
 Disadvantage: Additional control signals (IO/M) and instructions increase
complexity
 Memory-mapped I/O
 I/O devices are treated as memory locations in the memory map
 Any memory transfer instruction can be used (MOV, LDR, STR etc)
 Advantages: Simpler decoding circuitry, no special instructions required
 Disadvantage: A portion of the memory system is used as the I/O map,
reducing the memory available to applications

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Memory and I/O address
Maps for the 8086/8088
Memory: I/O Port specified
MOV in DX, either explicitly or i

a. Isolated I/O I/O:

Port specified immediat

MOV
Range of memory addresses
b. Memory-mapped I/O assigned for I/O transfers
Using ordinary memory
transfer instructions Memory
e.g. MOV

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 The basic output port writes data from the mP data bus
to an output port whenever the mP executes the
correct OUT instruction with the correct I/O port
address
 Must latch the processor data put on the bus during the
I/O instruction to make it available indefinitely for the
port

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 Use 8-LED’s
 Loses the data if not latched
 Solution?
 Use a chip and an address decoder such that the
LED’s will not only respond to the command out
and a specific address (let’s assume that the address
is F000) but will also latch the data

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 Basic 8-bit Output Interface:
Controls 8 LEDs (1: OFF, 0: ON)

From mP
Edge-triggered
latch

No HiZ. OE
Data is latched and remains here until the next OUT
O/P always
enabled instruction to this port is executed
The SEL is generated (for + ive edge triggering) by decoding:
- The address for the I/O port
- The I/O WRITE operation
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 The basic input port connects an external set of bits to
the mP data bus whenever the mP executes the correct
IN instruction with the correct I/O port address
 External device puts data on the mP data bus
 Must include a 3-state (Tri-State) buffer to limit
access to the processor data bus to the duration of
executing the I/O instruction only

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 Basic 8-bit Input Interface:
Reads the status of 8 toggle
Switches (a byte read)
Pull-up
Resistors To mP
Gate

0 1
Toggle switches
3-state buffer
The SEL signal is generated (active low)
By decoding:
- The address for the I/O port
- The I/O READ operation
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 like a memory chip, you can read from an input
device
 You can read from a memory chip using the
command mov al, [bx]
 You can read from an input device using the
command in al, dx

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16
 The 82C55 is a popular interfacing
component, that can interface any TTL-
compatible I/O device to a microprocessor.
 It is used to interface to the keyboard and
a parallel printer port in PCs
 PPI has 24 pins for I/O that are
programmable in groups of 12 pins and has
three distinct modes of operation.

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 Mode 0
 Basic I/O
 Mode 1
 Strobe I/O
 Mode 2
 Bi-Dir Bus
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24
 This functional configuration provides
simple input and output operations for each
of the three ports.
 No “handshaking” is required, data is simply
written to or read from a specified port.

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 This functional configuration provides a means
for transferring I/O data to or from a specified
port in conjunction with strobes or
“handshaking” signals.
 In mode 1, Port A and Port B use the lines on
Port C to generate or accept these
“handshaking” signals

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 Two Groups (Group A and Group B).
 Each group contains one 8-bit data port and one
4-bit control/data port.
 The 8-bit data port can be either input or output
 Both inputs and outputs are latched.
 The 4-bit port C is used for control and status of
the 8-bit data port.

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Signal definitions for Mode
28 1 Strobe Input
 ~STB : The strobe input loads data into the port latch on
a 0-to-1 transition.
 IBF : Input buffer full is an output indicating that the
input latch contain information.
 INTR : Interrupt request is an output that requests an
interrupts.
 INTE : The interrupt enable signal is neither an input nor
an output; it is an internal bit programmed via the PC4
(port A) or PC2 (port B) bits.
 PC7,PC6 : The port C pins 7 and 6 are general purpose
I/O pings that are available for any purpose.

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 ~OBF : Output buffer full is an output that goes low
when data is latched in either port A or port B. Goes
low on ~ACK.
 ~ACK : The acknowledge signal causes the ~OBF pin
return to 0. This is a response from an external
device.
 INTR : Interrupt request is an output that requests
an interrupt.
 INTE : The interrupt enable signal is neither an
input nor an output; it is an internal bit
programmed via the PC6(Port A) or PC2(port B) bits.
 PC5,PC4 : The port C pins 5 and 4 are general-
purpose I/O pins that are available for any purpose.

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33
 This functional configuration provides a means
for communicating with a peripheral device or
structure on a single 8-bit bus for both
transmitting and receiving data (bidirectional
bus I/O).
 “Handshaking” signals are provided to maintain
proper bus flow discipline in a similar manner to
MODE 1.
 Interrupt generation and enable/disable
functions are also available.

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•Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1
Strobed Output Timing diagrams.
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 Used in Group A only.
 One 8-bit, bi-directional bus port (Port A) and a
5-bit control port (Port C).
 Both inputs and outputs are latched.
 The 5-bit control port (Port C) is used for control
and status for the 8-bit, bi-directional bus port
(Port A).

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 INTR : Interrupt request is an output that
requests an interrupt.
 ~OBF : Output Buffer Full is an output indicating
that output buffer contains data for the bi-
directional bus.
 ~ACK : Acknowledge is an input that enables tri-
state buffers which are otherwise in their high-
impedance state.
 ~STB : The strobe input loads data into the port
A latch.

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 IBF : Input buffer full is an output indicating
that the input latch contains information for the
external bi-directional bus.
 INTE : Interrupt enable are internal bits that
enable the INTR pin. BIT PC6(INTE1) and
PC4(INTE2).
 PC2,PC1,PC0 : These port C pins are general-
purpose I/O pins that are available for any
purpose.

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42
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44
45
46
The figure shows the one-byte control word of the 8253/54.
• D0 chooses between a binary number divisor of 0000 to FFFFH or
a BCD divisor of 0000 to 9999H.
• The highest number is 216 for binary and 104 for BCD.
• To get the highest count, the counter is loaded with zeros.
• D1, D2, and D3 are for mode selection.

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• D4 and D5 are for RL0 and RL1
• RL0 and RL1 are used to indicate the size of the divisor, and have
3 options:
1. Read/write MSB only
2. Read/write LSB only
3. Read/write LSB first followed immediately by the MSB.

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49
Mode 0 Interrupt on terminal count
Mode 1 Programmable one-shot
Mode 2 Rate Generator
Mode 3 Square wave rate generator
Mode 4 Software triggered strobe
Mode 5 Hardware trigger strobe

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The output in this mode is initially low, and will
remain low for the duration of the count if GATE = 1.
Width of low pulse = NT
Where N is the the clock count loaded into counter,
and T is the clock period of the CLK input.

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When the terminal count is reached, the output will go high and
remain high until a new control word or new count number is
loaded.
• In this mode, if GATE input becomes low at the middle of the
count, the count will stop and the output will be low.
• The count resumes when the gate becomes high again.
• This in effect adds to the total time the output is low.

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53
54
55
• This mode is also called hardware triggerable one-shot.
• The triggering must be done through the GATE input by sending a 0-to-
1 pulse to it.
• The following two steps must be performed:
1. Load the count registers.
2. A 0-to-1 pulse must be sent to the GATE input to trigger the counter.
• Contrast this with mode 0, in which the counter produces the output
immediately after the counter is loaded as long as GATE = 1.
• In mode 1 after sending the 0-to-1 pulse to GATE, OUT becomes low
and stays low for a duration of NT, then becomes high and stays high
until the gate is triggered again.

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57
58
Mode 2 is also called divide-by-N counter.
• In this mode, if GATE = 1, OUT will be high for the NT clock
period, goes low for only one clock pulse, then the count is reloaded
automatically, and the process continues indefinitely.

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60
In this mode if GATE = 1, OUT is a square wave where the high
pulse is equal to the low pulse if N is an even number.
• In this case the high part and low part of the pulse have the same
duration and are equal to (N/2)T (50% duty cycle)
• If N is an odd number, the high pulse is one clock pulse longer.
• This mode is widely used as a frequency divider and audio-tone
generator.

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62
63
•In this mode if GATE = 1, the output will go high upon loading the
count.
• It will stay high for the duration of NT.
• After the count reaches zero (terminal count), it becomes low for
one clock pulse, then goes high again and stays high until a new
command word or new count is loaded.
• To repeat the strobe, the count must be reloaded again.
• Mode 4 is similar to mode 2, except that the counter is not reloaded
automatically.
• In this mode, the count starts the moment the count is written into
the counter.
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65
66
• This mode is similar to mode 4 except that
the trigger must be done with the GATE input.
• In this mode after the count is loaded, we
must send a low-to-high pulse to the gate to
start the counter.

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•Varies Counting and timing (delay) solution
•Real time clock
•CPU independent delay generation
•E.g. Refreshing SRAM
•Generating Waveform
•DC motor speed and direction control
•Generating music using computer

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