Journal of Electrical Engineering, Vol. 75, No. 1, 2024, pp.

47-55

sciendo
PAPERS______________________________________________________________________________________________________________________

Design and implementation of a current-fed dual active bridge converter

for an AC battery

Tuan Anh Do1,2, Quang Dich Nguyen2, Phuong Vu1*

Home battery has become more and more popular in which the AC battery is a trending product along with the AC-coupled
system. The energy conversion of an AC battery commonly consists of a two-stage power converter to flexibly connect to the
wide-range input battery voltage and different grid or load types. This study specifically concentrates on the DC/DC stage
which plays an important role in transferring power with the battery. In addressing the need for isolation, bidirectional power
flow, and limited battery current ripple, the Current-fed Dual Active Bridge (CFDAB) structure is chosen for this stage. This
paper presents a comprehensive design for the CFDAB converter for an AC battery application, especially a technical solution
focusing on zero voltage switching is applied to increase the efficiency of the converter. Finally, an experimental prototype is
carried out to validate the performance of the CFDAB converter in both two modes of the power flow.
Keywords: AC battery, current-fed dual active aridge, zero voltage switching

1 Introduction lations, flexibility in accommodating additional modu-

les, and isolation for the battery system. Within the AC-
In recent years, home batteries have become
coupled topology, the AC Battery, which combines both
increasingly popular due to their cost-effectiveness in
the battery and the power converter, has been introduced
sharing energy capacity and the growing trend of
by numerous well-known manufacturers. Some products
enhancing self-reliance in energy consumption [1-3].
even incorporate second-life batteries [4-6] for
These domestic applications involve integrating various
economic and environmental purposes. The power
distributed power sources and consumption elements,
converter of the AC battery includes a two-stage energy
such as photovoltaic (PV) systems, battery energy
conversion as shown in Fig. 1: the DC/DC stage con-
storage systems, the grid, and household loads. Two
necting to the battery and the DC/AC stage connecting
common topologies for home batteries are the AC-
to the grid and load. This paper specifically focuses on
coupled and DC-coupled systems. This research speci-
the DC/DC stage, in which a bidirectional isolated
fically focuses on the AC-coupled system based on its
converter is applied to exchange power between the
adaptability to retrofit existing residential PV instal-
battery and the DC-link voltage.

Grid
DC-link L

1-phase
Storage DC/AC
CFDAB Filter
Device Converter
converter
N

Fig. 1. Structure of an AC battery for domestic application using current-fed dual active converter

_______________________
1 School of Electrical and Electronic Engineering, Hanoi University of Science and Technology, Hanoi, Vietnam
2 Institute for Control Engineering and Automation, Hanoi University of Science and Technology, Hanoi, Vietnam
*phuong.vuhoang@hust.edu.vn

https://doi.org/10.2478/jee-2024-0007, Print (till 2015) ISSN 1335-3632, On-line ISSN 1339-309X

© This is an open access article licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives License
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
48 Tuan Anh Do et al.: Design and implementation of a current-fed dual active bridge converter for an AC battery

In recent years, the dual active bridge (DAB) has and smaller gate charge leading to shorter switching
gained attention as an isolated DC/DC converter, attri- times, thus reducing losses due to valve switching, and it
buted to its notable advantages including high-frequency can operate at higher frequencies [19-20]. Therefore, the
isolation capability, soft switching characteristics, and overall losses of SiC mosfet are significantly reduced
bidirectional power flow [7-9]. Nevertheless, a drawback compared to conventional Si technology.
lies in the direct supply of voltage to the power circuit,
To validate the effectiveness of the proposed solution,
leading to a high battery current ripple. This, in turn,
a 3.3 kW experimental system is carried out. The ob-
results in extra bulky filters, increased costs, and a
tained results make a good agreement with the theo-
reduced system lifespan [10]. Additionally, due to DC
retical design: all switches achieve ZVS capability, and
bias issues, series capacitors with the primary
the efficiency of the converter reaches up to 96.5%.
transformer or complex modified modulation are
required to avoid core flux saturation [11].
To address the aforementioned issues, this paper 2 Operation principle
proposes a particular technological solution to optimize Figure 2 presents the structure of the CFDAB
the performance of DC/DC converters used in an AC converter, comprising two primary parts: the interleaved
Battery. Firstly, a current-fed DC/DC converter with a boost circuit and the Dual Active Full-Bridge circuit.
Current Fed Dual Active Bridge (CFDAB) structure Within the interleaved boost circuit, two DC inductors
[12,13] is employed, where the interleaved boost circuit function as distinct current sources. Inductor Ldc1
on the primary side helps reduce current stress, providing collaborates with the left leg with switches Q1 and Q1a,
soft switching capabilities like Zero Voltage Switching which makes the first boost converter. Simultaneously,
(ZVS) to contribute to minimizing switching losses, the right leg, equipped with switches Q2 and Q2a,
especially at high frequencies. This topology could also collaborates with inductor Ldc2 to form the second boost
be flexibly modified for the specific application [14,15]. converter. These boost converters operate with a 180˚
Secondly, silicon carbide (SiC) MOSFET technology phase shift, creating an interleaved boost circuit where
and Litz wire winding are chosen to reduce losses in the boost voltage is maintained constant by the clamp
semiconductor switches and transformers across all capacitor Cc. Besides, the Dual Active Full-Bridge
frequency ranges. Litz wire has recently become a circuit comprises two H-bridge modules positioned on
promising material in the power electronics field, two sides of an isolated high-frequency transformer with
allowing inductors and transformers to operate at high a turn ratio of N:1. The input capacitor and output
currents with low resistance [16], achieving minimal capacitor voltages are defined as the Low-Voltage Side
losses at operating frequencies from tens to hundreds of (LVS) and High-Voltage Side (HVS), respectively. The
kilohertz [17]. The Litz wire also helps minimize the skin direction of the power flow between the LVS and the
effect and reduce losses caused by eddy currents [18], HVS side is determined by the sign of the phase-shifted
lowering the operating temperature of the system and angle. The AC inductor Lr, comprising the primary-
simplifying the heat dissipation design. SiC MOSFET referred transformer leakage inductor and the auxiliary
technology has significant advantages over conventional leakage inductor, functions as a power link connecting
Si MOSFETs: it operates at higher voltage levels with the two sides of the transformer.
greater thermal endurance, lower conduction resistance,

Q1a Q2a S1 S2
Ldc1 iL1 Lr N : N
1 2
c
a
Ldc 2 iL 2 Lm CO
b d V2
i1

V1 Cc
Q1 Q2 S3 S4

Fig. 2. The structure of the CFDAB converter

 Journal of Electrical Engineering, Vol. 75, No. 1, 2024 49

The significant reduction in current ripple by the

interleaved boost part, the isolation with bidirectional
power flow, and the flexible gain factor make the
CFDAB converter suitable for home battery applications
in general and the AC Battery in particular.

2.1 Pulse width modulation method

To address issues related to voltage ratio variations
and minimize conduction losses in power transfer stages,
the PWM plus phase-shifted (PPS) approach is
employed. In this method, the duty cycle for HVS
switches is fixed at 50%, while the duty ratio for the
primary LVS switches Q1 and Q2 is a variable D.
However, during non-power transfer stages of PPS, there
is a notable circulation loss with a high spike in leakage
current.

Sawtooth
Fig. 4. Key waveform of CFDAB converter
under the DPDPS modulation method
Phase shifted

D 2.2 ZVS analysis

Phase shifted
Specifically, at the turn-on interval of each switch,
there should be a sufficient current iZVS to discharge the
parasitic capacitance of the switches within the particular
Phase shifted
dead time. The direction of the leakage current iLr is
chosen to be the same as that of the inductor current iLdc1.
Table 1 illustrates the ZVS condition for each switch of
the converter. These conditions will be analyzed in the
0.5
primary-side and the secondary-side switches of the
converter.
Fig. 3. Modulation technique DPDPS [10]

Table 1. ZVS conditions for 8 switches

In this study, an extra phase shift is introduced
through the PWM plus Double Phase-Shifted (DPDPS) Switches ZVS condition at turn-on interval
method [10] denoted as (2 𝐷 − 1) × 𝑇𝑠 /2, aimed at Q1a iLdc1 – iLr > iZVS
eliminating the spike in leakage current. Figure 3 out- Q1 iLr – iLdc1 > iZVS
lines the modulation strategy for the CFDAB converter, Q2a iLdc2 + iLr > iZVS
specifying that the phase shifts between Q1 – Q2, Q2 – S1, Q2 iLdc2 + iLr < – iZVS
and S1 – S4 are 180˚, 𝜑, and S , respectively. Parameter S1 iLr > iZVS
𝜑𝐸 plays a crucial role in determining power flow and S2 iLr < – iZVS
direction, with 𝜑𝐸 > 0 representing operation in boost S3 iLr < – iZVS
mode where power flows from the LVS to the HVS and S4 iLr > iZVS
vice versa. Through the utilization of DPDPS
modulation, Fig. 4 [10] illustrates eight operational
modes within a single switching period, showcasing the
main current and voltage waveform.
50 Tuan Anh Do et al.: Design and implementation of a current-fed dual active bridge converter for an AC battery

2.2.1 Deadtime calibration

Vgs
Deadtime is commonly applied to avoid the short- Vds

circuit phenomenon. Moreover, in this situation, an No ZVS

ZVS
appropriate deadtime needs to be utilized so that the 180ns
voltage on the parasitic capacitor can be discharged to
zero before the drain current starts to rise. However, a 10V/div
50V/div
10V/div
50V/div

large deadtime could make the current flow in the reverse

direction through the body diode, hence the drain voltage a) b)

Vds then rises again. Fig. 6. Voltage response of switch Q1 with different
DC inductors: a) Ldc=330 μH, b) Ldc=130 μH

Vgs Vgs
Vds Vds With the large DC inductor of 330 μH, the dis-
charging current is not enough and the ZVS cannot be
achieved on switch Q1 as shown in Fig. 6a. By reducing
the inductor value to 130 μH, the current ripple signi-
10V/div
50V/div 10V/div
50V/div
ficantly increases which leads to the higher iZVS and the
ZVS is achieved as shown in Fig. 6b.
a) b)

Fig. 5. Turn-on interval of switch Q1a with different 2.2.3 Determining the additional phase shift Δ𝜑
deadtime: a) Td=0.4 μs, b) Td=0.35 μs
To obtain a bias current ibias for discharging the para-
sitic capacitance of switches S1 and S3 in this interval,
Figure 5 illustrates the drain-to-source voltage Vds and a phase-shift angle Δ𝜑 needs to be set [10]. The bias
the gate voltage Vgs in the turn-on interval of an upper current needs to be chosen large enough so that the
switch Q1a in the open-loop mode with the input voltage parasitic capacitor can be discharged completely within
of 50 V and the resistor of 128 Ω. As per the above the deadtime. However, if the ibias current is too high, it
analysis, the ZVS current for this switch is larger than will increase losses as this is a circulating period. The
that of the lower switch, and the same deadtime is response of switch S1 in boost mode is taken as an
applied for each leg. As a result, the deadtime could to example, with the same scenario outlined in section
larger than the sufficient time to discharge the parasitic 2.2.1, illustrated in Fig 7. Figure 7a shows that the hard-
capacitor. In Fig. 5a, the Vds voltage rises again from zero switching occurs when S1 turns on with a small Δ𝜑 (5°).
to a peak of about 100 V, which generates more At this condition, by increasing Δ𝜑 to 8°, S1 could just
switching loss in the turn-on period. In Fig. 5b, this peak achieve ZVS and this value be selected for the phase-
voltage has decreased significantly by reducing the shifted angle Δ𝜑 instead of continuously increasing to
deadtime from 0.4 μs to 0.35 μs. Hence, a suitable dead- avoid the power losses.
time will be chosen for a particular operating load.

Vgs Vgs
2.2.2 DC inductor selection Vds Vds
No ZVS
The DC inductors L1 and L2 directly determine the ZVS
ripple of the DC-current and the ZVS condition of the
primary-sided switches as shown in Table 1. Moreover,
it is more difficult to achieve ZVS on the lower switches 10V/div
50V/div
10V/div
50V/div

compared to the upper ones. Therefore, the comparison

of the turn-on interval of the lower switch Q1 between 2 a) b)
DC inductor values is given in Fig. 6 with the same test Fig. 7. Turn-on interval of switch S1 with different
condition in section 2.2.1. values of  : a) Δ𝜑 = 5°, b) Δ𝜑 = 8°
 Journal of Electrical Engineering, Vol. 75, No. 1, 2024 51

2.2.4 Leakage inductor selection

Vgs Vgs
Vds Vds
Besides the influence of power transfer, the value of
the leakage inductance also affects the ZVS condition of ZVS
the switches on both sides, particularly on the secondary
0ns
side. Reducing the leakage inductance will increase the
primary-side current ripple and help the primary-sided 10V/div
50V/div
10V/div
50V/div

switches achieve ZVS more easily. However, this

reduction in leakage inductance decreases the stored a) b)
energy in the leakage inductance, making it more
difficult for the secondary-side switches to achieve soft Fig. 8. Turn-on interval of switch S1 with different Lr:
switching. The response of switch S1 in boost mode is a) Lr=13 μH, b) Lr=16 μH
taken for example with the same scenario outlined in
section 2.2.1. With a similar phase-shift angle, a small Therefore, a suitable combination is required among
leakage inductance (13 μH) is insufficient for switch S1 choosing the values of the DC inductor, leakage
to achieve soft switching. However, by increasing the inductor, phase-shift angle, and deadtime to simul-
value of the leakage inductance to 16 μH, switch S1 taneously achieve soft switching of the switches and
begins to achieve ZVS. avoid circulating losses, ultimately aiming to enhance
the efficiency of the converter.

Input and Oscilloscope Output current

Laptop probe
output voltage

Fan Resistive load

Isolated probe
Forceboard
Control board

Fig. 9. Experimental prototype of CFDAB converter

3 Experimental results
To verify the theoretical basis of soft switching and The control algorithm is programmed in the control
the operational principles of the CFDAB converter, kit Launchpad TMS320F28379D. To display and collect
a 3.3 kW experimental prototype has been carried out the data, a GW INSTEK GDS-2104A Digital Oscillo-
with the parameters being presented in Table 2. The ex- scope is used with the isolated voltage probe Micsig
perimental system shown in Fig. 9 includes the CFDAB DP10013 and the current probe Micsig CP2100A.
converter, the control circuit, the resistor load, and a DC
power supply model ITECH IT6018C-1500-40.
52 Tuan Anh Do et al.: Design and implementation of a current-fed dual active bridge converter for an AC battery

Table 2. Key specification of the CFDAB prototype The SiC Mosfets C2M0040120D and C2M0080120D
are respectively utilized for the primary-sided and
Components Parameter secondary-sided switches of the CFDAB converter to
Primary-sided
C2M0040120D, 1200 V, 60 A minimize switching losses and enhance the efficiency of
switches
the converter. For this converter, the total leakage
Secondary-sided
C2M0080120D, 1200 V, 36 A inductor is designed to include the leakage inductor on
switches
Transformer T Ferrite core EE65, turn ratio 4:9 the primary side of the transformer and an auxiliary
Number of primary turns N1=12 leakage inductor Ls. Furthermore, Litz wire is employed
Magnetic inductor Lm=411 µH for winding the main transformer and the auxiliary
leakage inductor Lk=1.5 µH leakage inductance to reduce losses induced by eddy
Auxiliary Ferrite core EC42, 16 turns currents. With the selected frequency for the converter is
leakage inductor Ls=11.5 µH 50 kHz, based on the skin depth relationship, the
Ls corresponding diameter for the Litz wire is 0.1 mm.
Total leakage
Lr = Lk + Ls = 13 µH
inductor Lr
DC inductor 130 µH 3.1 Experimental results in boost mode

Clamp capacitor 50 µF, 920 V The 3-level primary voltage is lagging in phase
Input capacitor 220 µF, 400 V compared to the secondary voltage of the transformer, as
shown in Fig. 11, ensuring energy transfer from the LVS
to the HVS in boost mode. The current through the
leakage inductor has the same waveform in the
theoretical analysis, with an aiding bias current to help
switches S1 and S3 achieve ZVS.

vgs vgs vgs vgs

vds vds vds vds
ZVS ZVS ZVS ZVS
150ns
230ns 5 ns
180ns

50V/div 50V/div
10V/div 50V/div 100V/div
10V/div 10V/div 10V/div

Q1a Q1 S1 S2
vgs vgs vgs vgs
vds vds vds vds
ZVS ZVS
ZVS 170ns ZVS
200ns 170ns
5 ns
50V/div 50V/div
10V/div 10V/div
100V/div 100V/div
10V/div 10V/div

Q2a Q2
a) S3 b) S4

Fig. 10. Experimental results in boost mode

a) ZVS on primary switches, b) ZVS on secondary switches
 Journal of Electrical Engineering, Vol. 75, No. 1, 2024 53

with a larger discharge current iZVS. This is shown by

vab a longer time for the voltage to reach zero before the
vcd
iLr turn-on signal.

250V/div vgs vgs

vds vds
ZVS ZVS

50ns 180ns

ibias
100V/div 10V/div 100V/div
10V/div
50V/div

20A/div

Q1a Q1

vgs vgs
ZVS
vds vds
ZVS
Fig. 11. Transformer voltage Vab, Vcd, and leakage 50ns 180ns

current iLr in boost mode

100V/div 100V/div
10V/div 10V/div

By adjusting the values of the inductors, the phase-

shift angle  , and the deadtime, all 8 switches achieve Q2a Q2
a)
ZVS at a power rate of 3300W, as depicted in Fig. 10.
In this mode, the primary-side switches Q1a, Q2a, and the
secondary-side switches S2, S4 achieve ZVS more easily vgs vgs
compared to other switches with a larger discharge vds vds
ZVS
ZVS
current iZVS. This is illustrated by a longer time for the 130ns 10ns
voltage to reach zero before the turn-on signal. The
converter obtains an efficiency exceeding 94% across the 10V/div
150V/div
10V/div
150V/div

entire power range and a maximum efficiency of 96.4%

at the power rate, as shown in Fig. 12.
S1 S2
Efficiency ( %)
vgs vgs
97
ZVS
vds vds
ZVS
20ns
96 130ns

95 10V/div
150V/div
10V/div
150V/div

94
Boost S3 S4
b)
93
Power (W) Fig. 13. Experimental results in boost mode: a) ZVS
on primary switches, b) ZVS on secondary switches
500 1000 1500 2000 2500 3000

Fig. 12. Efficiency evaluation in boost mode

The 3-level primary voltage is leading in phase
compared to the secondary voltage of the transformer, as
3.2 Experimental results in buck mode shown in Fig. 14, ensuring energy transfer from the HVS
to the LVS in buck mode. The current through the
Similarly, in buck mode, all 8 switches achieve ZVS
leakage inductor has the same waveform in the
at a power rate, as depicted in Fig. 13. The primary-side
theoretical analysis, with an aiding bias current to help
switches Q1, Q2, and the secondary-side switches S1, and
switches S2 and S4 achieve ZVS.
S3 achieve ZVS more easily compared to other switches
54 Tuan Anh Do et al.: Design and implementation of a current-fed dual active bridge converter for an AC battery

Acknowledgment
vab
ab
vcd
cd
iLr
This research is funded by the Hanoi University of
Lr
Science and Technology (HUST) under project number
T2022-TĐ-001.
250V/div

100V/div
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 Journal of Electrical Engineering, Vol. 75, No. 1, 2024 55

[12] P. Vu, D. Anh, H. D. Chinh, “A Novel Modeling and Control Tuan Anh Do received his B.S. and M.S. degrees in
Design of the Current-Fed Dual Active Bridge Converter under
DPDPS Modulation,” Engineering, Technology and Applied
control engineering and automation from Hanoi
Science Research, vol 11, No. 2, pp. 7054-7059, 2021. University of Science and Technology, Ha Noi, Vietnam
doi:10.48084/etasr.4067. in 2019 and 2021, respectively. Since 2022, he has
[13] K. Bathala, D. Kishan, N. Harischandrappa, Soft Switched started to study for his PhD degree in control engineering
Current Fed Dual Active Bridge Isolated Bidirectional Series and automation at Hanoi University of Science and
Resonant DC-DC Converter for Energy Storage Appli-
cations. Energies 2023, 16, 258. Technology, Vietnam. His research interests include
https://doi.org/10.3390/en16010258 power electronics and control systems.
[14] E. Hossain, D. Murtaugh, J. Mody, H. M. R. Faruque, M. S.
Haque Sunny and N. Mohammad, "A Comprehensive Review Quang Dich Nguyen received a B.S. degree in electrical
on Second-Life Batteries: Current State, Manufacturing engineering from the Hanoi University of Technology,
Considerations, Applications, Impacts, Barriers & Potential Hanoi, Vietnam, in 1997. He received an M.S. degree in
Solutions, Business Strategies, and Policies," in IEEE Access, electrical engineering from the Dresden University of
vol. 7, pp. 73215-73252, 2019,
doi: 10.1109/ACCESS.2019.2917859.
Technology, Dresden, Germany, and a Ph.D. from
[15] D. Sha, Y. Xu, J. Zhang and Y. Yan, "Current-Fed Hybrid Dual Ritsumeikan University, Kusatsu, Japan, in 2003 and
Active Bridge DC–DC Converter for a Fuel Cell Power 2010, respectively. Since 2000, he has been with the
Conditioning System With Reduced Input Current Ripple," in Hanoi University of Science and Technology, Vietnam,
IEEE Transactions on Industrial Electronics, vol. 64, no. 8, pp. where he is currently an Associate Professor and
6628-6638, Aug. 2017, doi: 10.1109/TIE.2017.2698376.
[16] A. Rosskopf and C. Brunner, "Enhancing Litz Wire Power Loss Executive Dean of the Institute for Control Engineering
Calculations by Combining a Sparse Strand Element and Automation. His research interests include magnetic
Equivalent Circuit Method With a Voronoi-Based Geometry bearings, self-bearing motors, and sensorless motor
Model," in IEEE Transactions on Power Electronics, vol. 37, control.
no. 9, pp. 11450-11456, Sept. 2022,
doi: 10.1109/TPEL.2022.3169992. Phuong Vu received his B.S., M.S., and Ph.D. degrees
[17] I. Reese and C. R. Sullivan, "Litz wire in the MHz range: from Hanoi University of Science and Technology,
Modeling and improved designs," 2017 IEEE 18th Workshop
on Control and Modeling for Power Electronics (COMPEL),
Vietnam, in 2006, 2008, and 2014, respectively, all in
Stanford, CA, 2017, pp. 1-8 Control Engineering and Automation. Since 2006 he has
[18] T. Guillod, J. Huber, F. Krismer and J. W. Kolar, "Litz wire been employed at Hanoi University of Science and
losses: Effects of twisting imperfections," 2017 IEEE 18th Technology, where he is a lecturer and researcher at
Workshop on Control and Modeling for Power Electronics
School of Electrical Engineering, and currently is an
(COMPEL), Stanford, CA, 2017, pp. 1-8
[19] L. F. S. Alves, P. Lefranc, P.-O. Jeannin and B. Sarrazin, Associate Professor. His research interests include
"Review on SiC-MOSFET devices and associated gate modeling and controlling power electronics converters
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[20] Y. Duan, Y. -L. Zhang, J. Q. Zhang and P. Liu, "Development
of SiC Superjunction MOSFET: A Review," 2022 19th China
International Forum on Solid State Lighting & 2022 8th
International Forum on Wide Bandgap Semiconductors
Received 14 November 2023
(SSLCHINA: IFWS), Suzhou, China, 2023, pp. 13-17, _______________________________
doi:10.1109/SSLChinaIFWS57942.2023.10071020.