Synthesis related questions

1. How many projects did you worked on?

2. What was your latest project and challenges you faced in the latest project.
3. Before starting the floorplan what and all checks you will do?

4. If floating pins are there what will you do?

1. Input pin floating

Error: If any input pins are floating in the design it gives the error, this input causes the logic
functionality change due to coupling capacitance the voltage at input pin may vary between
logic 0 and logic 1 which gives the metastable state and high power dissipation takes place
because of short circuit between power and ground. This could be a major issue.

FIX: This can be eliminated by connecting the floating pin to either logic 0, 1 Or report to the
rtl team.

2. Output pin floating

Error: if the output pin is floating there is no issue because the synthesis tool removes the
path for timing analysis. Because there is no continuity and functionality requirement in the
path from input to output port.

FIX: this error can be fixed while optimizing the design by tool, it removes the paths like
this.This is called pruning.

5. If I gave synthesis netlist, how will you decide that you can start floorplanning?

6. You are working on logic synthesis then when will you take decision that I need to enable
Physical aware synthesis ?
7. What is the extra input file we have to give in PAS and what extra output file we get in
PAS?
8. What exactly fp def file contains?

9. What if there are unclocked registers /combinational loops?

1. Unclocked registers

Error: check timing gives the unclocked registers where clock is not coming to the clk pin of
registers.

Fix: to fix this issue define the clk in the constraints as ‘create_clk -name’.
10. What if there are constant flops? And in which stage tool will remove constant flops?

11.What are the optimization techniques you used in synthesis to get better timing & in which
corner you checked timing in synthesis?
 Path grouping
Multi bit flop

We are only considering the setup analysis in the synthesis stage with an ideal clock(i.e no
skew) which has one clock period for transferring the data between two registers which can
minimize the setup violations after the post CTS and routing stages.

Floorplan related questions :

1. What are the inputs required for floorplan and what is the use of each input?

Inputs required :
1. Gate level netlist in verilog format.
2. Logical (Timing) & Physical views of standard cells & all other IPs used in the design, ndm
file (new data mode) (.lib and .lef of standard cells)
3. Timing constraints (SDC)
4. Power Intent (UPF / CPF)
5. FloorPlan DEF & Scan DEF
6. Technology file (.tf)
7. RC Co-efficient files tlu+ (ITF file)

2. Where you places the IO ports? what are the preferred routing direction?

3. How many macros were there in your design?

My latest block consists of 36 macros.

4 .What was the gate count in your design? Frequency? Macros?

5. What all things you will take care while doing floorplan?
6. How much margin did you keep around the hallo?
7. How many metal layers you used in lasted project ?
13 metal layers.

8. How you placed the macros & IO ports ?

9. What are the preferred routing directions you used in your project ?
M0 will be horizontal because initially P-well and N-well both are horizontal.

10. For which metal layer IO ports are connected ?

11. Based on what factor you are leaving channel space between macros?
12. How many flops you have in your design?
Basically 30% of instance count.

13. How many instances present in your design?

1.5 M

14. What is TLU+ file? What does it contain? How RC calculated ?

15. How will you perform floorplan on given core area?

16. What physical cells you added in floorplan stage?

 1. Endcap
2. Well Tap cells
3. Decap cells
4. spare cells

17. Why do you use De-cap cells in your design?

Decap cells are basically a charge storing device made of the capacitors and used to support
the instant current requirements in the power delivery network.

18. Why we have to place tap cells and end cap cells? What is latch-up ?
 The least resistive path from vdd to gnd due to 2 parasitic transistors npn and pnp is called
Latchup.
By adding tap cells in nwell & p-substrate in order to decrease resistance in nwell &
psubstrate

19. What are different cells other than physical cells, combinational cells and
sequential cells?#
Low power cells

20. What is low power? What are the low power cells ?
Ans. Level shifter
Isolation cells
Always on cells
Power switch
Retention cells
 21. What is power switch cell? Where it placed?
➢ In order to achieve power savings with power gating, power switches must be implemented
in the design to shut-off the power to a particular domain.
➢ This can be achieved by using a switch between the Vdd and the design or between Vss and
the design .

If the supply voltage is gated, the switch/power gate is termed as a header,using

PMOS transistor.
If the ground is gated, the switc/power gate is called as a footer, using NMOS
transistor.

22. What is isolation cell? Where is it placed? Why not it placed from always on domain to
switchable domain?
• Isolation cells should be added only on signals where the driver is moving from the
shutdown domain to the always –on domain.
• Isolation cells are not needed on signals moving from the always on domain to shutdown
domain.

23. What is tie cell? Draw tie cell schematic? How do tie cells give constant signal?

In netlist some of pins have connected with 1’b0(VSS) and 1’b1(VDD), this type connection
should not connected directly with VDD and VSS nets, Must be connected with Tielow and
Tiehigh cells.

24. What is the use of retentional flops and in which domain (always on or switchable) we
place these flops?

➢ When the power domain goes OFF, the state present in the flip flops will also be erased.
Some IPs will need to retain their values for fast wake up. For the previous state to be
preserved, this logic isi used.
➢ This has a flip flop and a state saving latch. The retention mode consumes little more current
than power off mode but always allow fast recovery of the IP after waking up from sleep
mode.
 25. Explain how to add retention and isolation cells during synthesis.

26. What was the utilization in each stage from floorplan to routing?

27. How do you check utilization?

report_utilization -of_objects [get_voltage_areas]

28. What are the checks will do after floorplan?

29. What are the commands you used for floorplan checks?

30. what is the command for padding?

Create_keepout_margin -outer {3333} [get_flat_cells -filter “is_hard_macro==true”]

31. How to select particular port through the cmd.

32. How to select a cell in Innovus ?

selectobj[get_db base_cell:NOR2X1 .base_class]

33. How will you check overlaps in your design in both Innovus and FC? #command

check_legality
34. How will you fix the overlaps for a particular cells in your design in both Innovus and
FC?

legalize_placement -cells
 35. What are the issues we will get in LEC and inputs required to start Lec ?
36. What are the factors you consider while doing FE(floorplan) exit?

Power plan related questions:

1. How did you perform powerplan?

2. What is the structure of the ring, rails and straps in powerplan?
3. What pg drc violation you faced in powerplan?
4. What issues did you face after powerplan?
5. What is internal, switching and leakage power?
6. What is Electro migration and latchup?
7. What is IR drop? what are fixes for dynamic IR drop?

Placement related :

1. Before placement checks?

2. Checks after placement?
Checks:
a. Cells Legalization
b. Congestion
c. Timing (setup)
d. Drv’s
e. HFNS
f. Density
3. What is scan chain ? What is scan chain reordering?
4. In which stage you perform scan chain reordering? And why?

5. Explain the congestion report?

❖ The total overflow value is the total number of wires in the block that do not have a
corresponding track available. The max overflow value is the highest number of overutilized
wires in a single global routing cell.
❖ The GRCs overflow value is the total number of overcongested global routing cells in the
design. The GRCs max overflow value is the number of global routing cells that have the
maximum overflow.

6. Did you face congestion issue in your design? How did you fix it with respect to timing?
7. What is vertical congestion, when we will get it (shape of block related)?
Ans. We will see horizontal congestion when horizontal tracks are less and similarly for
vertical congestion if vertical tracks are less.

8. How the tool will estimate congestion in early stage?

9. In which stage the initial HFNS takes place?
10. How will you fix, if you are seeing congestion at L-bend?
11. What happens in place stage?
12. What is your approach to fix the violation, if you are seeing 200ps in placement stage?
13. Explain about path grouping?
14. What was the run time in placement and how was the timing?
15. Based on which corner tool will calculate tran violation?
16. How you fix max tran violations ?

17. Why we will do only setup check in placement and why not hold check?
As Plcement stage clk is ideal so we will check only setup timing.

18. How to analyze the timing path and what are the things u observed in timing report?
How to fix timing related issues.
• Review the timing report to identify the nets/cells which have significantly more
delay than other cells in the timing path. Check if there are some common cells for a
path group which have a huge delay.
• Check if timing paths go over congested areas. Add cell padding or placement
blockage to relieve congestion.
• Check if timing path caused by bad floorplan, macro placement, small channels. Fix
floorplan.
• If some of the nets not getting optimized, check for dont_touch attribute on them. A
dont_touch attribute prevents both optimization and clock tree synthesis on the
object.
In the timing report, you would see “d” attribute against the net.
To remove the dont_touch attribute from a network, use the set_dont_touch -clear
command.
• Check if the level of logic (LOL) is huge for the path. Talk with the lead and try to get
the path fixed through RTL change.
• Add custom path groups. By default , the flow creates a clock group specific to clocks
in the design, to_mac,from_mac, io_to_reg,reg_to_io.
use “group_path” command to create custom path groups.
• When layer optimization is activated, the place_opt flow assigns long timing critical
nets to upper metal layers to improve timing. Param :-
OPTIMIZATION_USE_LAYER_CONSTRAINT = 1
• After a block has been through an initial placement and optimization with the
place_opt command, you can perform incremental placement and optimization by
using the refine_opt command

19. Issues at placement stage?

 Legality issues
Congestion
DRV’s
Timing

20. Suppose you are seeing huge violations in timing, will you proceed to cts?
NO, In further stages timing will violate more.

21. What are the fixes for timing in placement?

 22. What is the slack value in your design after placement?
23. How you check power in placement?
24. What are the factors need to consider while doing place exit?

CTS:

1. What is global skew?

2. What is local skew?
3. What are NDR rules?
4. What is insertion delay?
5. By default tool optimize global skew or local skew?
6. What are the multi point CTS? Explain the multi point cts?
7. How do you build the clock tree?
8. In which corner tool will build clk tree ?
9. For better timing, how the target skew should be min or max?
10. What was your latency in your projects?
11. What is your skew? How you reduced the skew if it gets violated, how will you optimize
the skew?
12. What checks you performed after cts?
13. Did you get a clock gating violation after cts?
14. Why will we use clock gating cells in design?
15. Skew and latency fixing techniques?
16. Why we need to main the minimum latency?
17. In which report you will find the latency of the block?
18. What are the reasons for high skew in your design?
19. How will you fix the timing violation in CTS stage?
20. You are seeing huge timing violations in cts, how will you fix that?
 21. What are the uncertainty factors and explain about each factor?
22. What is meant by clock pull and push? useful skew method with diagram?
23. What are the factors we need to consider while pushing/pulling the clock?
24. What is the slack for setup and hold you observed in cts stage?
25. What is Cloning? What is ICG cloning? merging of the ICG?
26. Clk gating path is violating in cts...given condition like, but in routing you should not fix
then will you fix it in cts or at the time of ecos?
27. What are the checks after cts?

Timing:

1. Why we need to have arc between reset pin and clk pin interms of asynchronous flop?
2. Have you worked on fixing DRV’s?
3. What is cross talk? Crosss talk and fixing about aggressor and victim using commands ?
4. What is meant by crosstalk and what parameters are included in the crosstalk
report (given by STA)?
5. If you face a noise violation how will you fix it?

6. How did you fix antenna issue ? How layer hopping will clear antenna violation? with
commands
Antenna:
rpts/CbTileANT

-> antenna violation : when manufacturing chip , At mask etching process free
electronics are present on layers (nets), those free electrons try to discharge through gates
only.
-> If Gate Area not sufficient for discharging free charge carriers, Gate will be failed,
so need to add antenna diodes for discharging.
-> Or Break long nets and route with other top layers because mask etching different
time for different layers.
1. Fixes by adding buffers for long nets.
2. Fixes by adding antenna diodes to net near to pin.
3. Layer hopping

7. What is an MPW violation?

Min pulse width violation:

-> pulse width of peaks (either zero or one) are less due to transition is more on driver
pin.
The violation is reported in below file .
rpts/PtTim*Stp/min_pulse_width.rpt.gz
-> possible fixing techniques : swaps from SVT to LVT , upsize Driver cells and add buffer on
route near to driver pin

8. What is crpr?
9. How do you solve the setup and hold issues?
10. Which violation is critical to fix in between setup and hold?
11. What checks are done before upsizing, downsizing and buffering?
12. What are the reasons for bad nets? And how will you fix the long nets in eco stage?
13. What are the fixes for hold violation in eco stage?
14. What is the difference between REG2REG and REG2ICG timing paths?
15. Among sizing /swapping/buffering, which one will you prefer to fix timing violation & why ?
16. Have you worked on ECO’s and what are those? Which tool you used for generation the
ECO’s.
17. What is the difference between insert_buffer and add_buffer_on_route?
18. How will you decide if metal has a longer length?
19. If the data path is frozen how will you fix the setup violation?
20. Chip is ready for the tapout stage, and you can't change the frequency. How will you fix the
setup violation?
21. What is the command for adding the buffer and asked to add the buffer in the real time tool.
22. Can you insert the buffer in the design?
23. What is the command for changing the flavour of a cell?
24. How to use fanout cmd for a cell.
25. How to add a cell for particular location and what is your analysis?
26. How many opens and shorts you got in your design?
27. How many drcs you have seen in your design?
28. What are the commands that you have used to fix timing in innovous?
29. For given prefix name, command to get all cells which have a prefix name?
30. What is the command to check for a particular net having don’t touch attribute or not? And
if they do not have, how to make a net as don’t touch?
31. Have you written eco for tran/cap and for setup, what they given and for hold what they
given ?
32. Write a tcl script to print 1 to 100 numbers ? now print even numbers ?
33. What is the difference between collection & pointer ?
34. There is one main clock which is driving 100 sinks ,one generated clock which
is driving 200 sinks and one output port among these what will tool consider for balancing?
35. The skew of one block is 200ps and skew of another block is 230ps how will you balance
them?
36. If we need some particular cells from timing report how you separate those cell delays >20ps
violations cells only from 1000cells by using Linux what u used to filter.
37. Given scenario like... you have 2 latencies i.e 500ps and 800ps, design is ok with both latency
numbers i.e area, timing, and power. Now which latency number you will take and why ?
38. Did you work on LVS ? If yes , what are the 2 files we will check before LVS?
39. For 10 selected cells, print their inst name and physical status ?