Lab 1

2 VIVADO IDE
Real-Time Imaging and Control

Lab
MSCV/ESIREM Antoine Lavault

antoine.lavault@u-bourgogne.fr
⌈ Lab 1 - Quickstart with Vivado and VHDL ⌋

This goal of this lab are :
• Find technical informations in a manual or datasheet
• Get to know the basic functions of Vivado IDE
• Generate a bit-stream and integrating it on a FPGA board
• Learn the basics of FPGA development flow.
• Use a test-bench as part of a VHDL workflow.

You will use Windows for all of the lab sessions.
Sections marked with a star (⋆)
1 Meet the Nexys 4

The Digilent Nexys 4 board reference manual is available here : https://digilent.com/reference/
programmable-logic/nexys-4/reference-manual
Fill in the quiz
2 Vivado IDE
2.1 Create a new project with Vivado 2021.1
1. Download the require files from Teams. You should have:
• A file named quickstart.vhd

• A file named cstr.xdc
• A folder named board_files
2. Place the contents of the board_files folder into. C:/Xilinx/Vivado/2021.1/data/boards/b

Create the folder if it doesn’t already exist.
3. Open Vivado 2021.1 and create a new project (figure 1)
4. Create a new RTL project (figure 2)
MSCV/ESIREM - Real-Time Imaging and Control Lab - Page 1/5

2.1 Create a new project with Vivado 2021.1 2 VIVADO IDE
Figure 1: Welcome Screen of Vivado
Figure 2: Options to create a project
Figure 3: Adding a source file to the project

2.2 Development Workflow 2 VIVADO IDE
5. Add the quickstart.vhd file to the project (figure 3)
6. Add the cstr.xdc file to the constraints (figure 4
Figure 4: Adding a constraint file to the project
7. Choose the Nexys4 in the hardware target (under the "Board" tab)
8. The creation assistant is now done. Check your project summary to the figure 5
Figure 5: Project Summary
2.2 Development Workflow

1. First, check the RTL Analysis. You can check the schematic produced by the tool.
2. Then, launch the synthesis tool.

2.3 Programming the Nexys 4 3 VHDL AND SIMULATIONS
3. Then, the implementation.
4. Finally, generate the bit-stream file.
2.3 Programming the Nexys 4

Now that we have a compatible bitstream, we will program the Nexys 4 board.
WARNING :
the board will flash its LEDs with an intensity proportional to the activated switches (MSB on the
leftmost switch).
Use the row of switches from right to left until you find an acceptable brightness to avoid discom-
fort and short-term glare.
1. The card is plugged in and the power is switched on.
2. Open the "Hardware Manager" and choose "Auto connect". You should see Vivado recognise the
card.
3. Choose the "Program Device" option.
4. Once programming is acheived, you can play with the switches and button.
The expected behaviour is as follow:
• The LEDs above the switches are on when the switch is in the "high" position.
• The RGB LEDs should blink with an intensity proportionnal to the binary number encoded by the
switches
• The north and south buttons will change the color as well as the east and west and finally, center
too.
3 VHDL and Simulations

For the following exercise, you will have to complete a snippet of code for a 4-bit adder to match an
already available test bench called 4bitadder_tb.vhd.
3.1 Project Setup

Create a new project for the 4bit adder. Import the source file and the test-bench.
Keep the Nexys 4 as the target hardware.
3.2 Adding a test-bench

Use the provided test-bench to test the adder.
1. Check if the provided code file actually passes the test-bench.
2. Modify the code of 4bitadder.vhd to output the correct values if needed if need be.

3.3 Hardware implementation 3 VHDL AND SIMULATIONS
3.3 Hardware implementation

Make sure your code passes through the synthesis and implementation process.
We would like to make use of the switches and LEDs on the board to control the 4-bit adder. We
especially want to :
• use the right-most switches (SW3-SW0) to give the value to a
• use the left-most switches (SW15-SW12) to give the value to b
• use the switch 8 (SW8) as the carry in.
• Output the results on the left-most LEDs (LED15-12)
• Output the carry out result on the right-most LED (LED0)
The switches should read a binary number with the MSB to the left (eg. SW15 encodes the MSB when
SW12 encodes the LSB). Same for the LEDs.
For this, use the I/O Ports tab in the Implementation step.
Once you are done, ask for a lab assistant to check your I/O setup.

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2 VIVADO IDE

Real-Time Imaging and Control

MSCV/ESIREM Antoine Lavault

⌈ Lab 1 - Quickstart with Vivado and VHDL ⌋

• Get to know the basic functions of Vivado IDE

• Generate a bit-stream and integrating it on a FPGA board

• Learn the basics of FPGA development flow.

• Use a test-bench as part of a VHDL workflow.

1 Meet the Nexys 4

• A file named quickstart.vhd

2. Place the contents of the board_files folder into. C:/Xilinx/Vivado/2021.1/data/boards/b

3. Open Vivado 2021.1 and create a new project (figure 1)

4. Create a new RTL project (figure 2)

MSCV/ESIREM - Real-Time Imaging and Control Lab - Page 1/5

Figure 1: Welcome Screen of Vivado

Figure 2: Options to create a project

Figure 3: Adding a source file to the project

MSCV/ESIREM - Real-Time Imaging and Control Lab - Page 2/5

5. Add the quickstart.vhd file to the project (figure 3)

6. Add the cstr.xdc file to the constraints (figure 4

Figure 4: Adding a constraint file to the project

Figure 5: Project Summary

2.2 Development Workflow

2. Then, launch the synthesis tool.

MSCV/ESIREM - Real-Time Imaging and Control Lab - Page 3/5

3. Then, the implementation.

4. Finally, generate the bit-stream file.

2.3 Programming the Nexys 4

1. The card is plugged in and the power is switched on.

3. Choose the "Program Device" option.

The expected behaviour is as follow:

3 VHDL and Simulations

3.1 Project Setup

3.2 Adding a test-bench

1. Check if the provided code file actually passes the test-bench.

MSCV/ESIREM - Real-Time Imaging and Control Lab - Page 4/5

3.3 Hardware implementation

• use the right-most switches (SW3-SW0) to give the value to a

• use the left-most switches (SW15-SW12) to give the value to b

• use the switch 8 (SW8) as the carry in.

• Output the results on the left-most LEDs (LED15-12)

• Output the carry out result on the right-most LED (LED0)

MSCV/ESIREM - Real-Time Imaging and Control Lab - Page 5/5

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