EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Early Design Planning

What are five key activities of the early design planning process? Explain in detail to receive full
credit?

1) Develop metrics from MRD, PRD, architecture specification, HL model, etc.

a. Determine schedule
b. Determine correct process
c. Target frequency, power, die size, etc.

2) Early library characterization

a. Select types of cells to use.
b. Obtain preliminary timing numbers for each library cell

3) Early cluster and die size estimation

a. Data paths -> pitch
b. Memory arrays
c. Custom blocks
d. Standard cell blocks

4) Integration: floor-planning and pin placement

a. Data path track analysis – bit pitch determination
b. Memory array aspect ratio
c. Custom blocks
d. Standard cell blocks

5) Early power estimation

a. Power grid design
b. Power droop metrics

6) Early speed path timing analysis

a. AT/RAT generation
b. Wire delay estimation

7) Clock and reset distribution

a. Skew & jitter metrics

1
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Constant Field Scaling vs. Constant Voltage Scaling

a) Explain what are the main differences between these two scaling theories.

• In constant field scaling the device parameters are scaled such that the electric fields
remain constant from one generation to the next.

• In constant voltage scaling the voltage supply remains constant from one generation
to the next, while the remaining device parameters are scaled.

b) List 2 device parameters which do NOT scale (assuming a Bulk-Silicon process).

• Kt/q
• εox
• Mobility

c) Explain in detail one limitation of Constant Voltage Scaling.

• Constant Voltage Scaling increases the electric fields in the gate oxide and junctions
causing increased leakage and potential breakdown.
• Sub-threshold leakage increases
• Higher junction temperatures

d) What is the numerical difference in Power Density between the two scaling theories?

• Constant Voltage scaling has twice the power density of Constant Field Scaling.

2
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Power equation

Derive the Power = ½ CV2F equation

3
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Gate Delay Derivation

Using an inverter driving a total load C = C- + C+, derive the average delay equation below (for
both transitions). Show all of your work.

C  Vdd  1 1 
 
4  Wn  Idsatn Wp  Idsatp 


4
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Pulsed Latch Timing

• UNIT delays on all INVERTERS, NAND gates, and transmission gates. Both transistors on
the transmission gate must be on before it transmits a signal.
• Assume perfect rise/fall times on all signals.

a) Given Dout in the timing diagram below, draw CLK, Din, PCLK, A, & B waveforms. Each
“tick” on the graph represents one gate delay.

CLK

PCL
K
Di
n
A
B
Dou
t

Din A B Dout

CLK PCLK

a) Why does this latch not work at very low frequencies? How would you fix it?

The storage node (B) is dynamic and won’t hold a charge. Need a weak feed back
device.

b) What limits the maximum frequency of this type of flip-flop?

The five inverters which generate the PCLK pulse limit the max speed of the CLK
signal.
c) What is the approximate hold time for this flop?

Difference between the clock path turning OFF the TG and Din to A
= 8 units delays – 1 unit delay

5
 EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Sequential Elements (20 Points)

15ps

15ps
25ps

15ps
25ps
D 15ps
25ps
Q
15ps
CLK
45ps

15ps
45ps
Clock

15ps 15ps 15ps 15ps 15ps

a) What is the Tsetup time

T setup= difference between the Data path – Clock path to turn-ON TG
Tsetup = 25 – (5*15+45+25) ps = -120ps

b) What is the Thold time?

Thold = Clock path to turn off TG – Din to TG input
Thold = (5*15+45+25) – 25 = 120ps

c) What is the Tclock-q time?

Tcq= earliest clock edge to output
Tcq = 45+25+15+ 45 = 130ps (CLK NAND+ CLK INV + TG + Output inverter)

d) What is the pulse width of the CLK signal?

TPW = 75+ 45 = 120ps

6
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Sequential Elements

a) There is something wrong with this Scan Flip-Flop. Annotate the schematic to fix the
problem

Given the following Scan Flip-Flop:

BCLK
Move wire
to this node

ACLK

Scan_in Scan_out
ACLKB
Disconnect
ACLK wire

ACLKB
ACLK

Din Dout

clock

a) What is wrong with this scan Flip-Flop design? Annotate the schematic to fix the problem.

The inverter cannot drive the tri-state buffer. Need to move the wire to other side of the
inverter.

7
 EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

b) Assuming you fixed the Scan Flip Flop correctly, annotate the following timing diagram for
signal Dout. Assume ACLK and BLCK are low (0.0V)

Assume UNIT delays for the Inverters, N-CH & P-CH devices

Hold time
violation

Clock

Din

Dout

c) Again assuming you fixed the Scan Flip Flop correctly, annotate the following timing
diagram for signal Dout and Scan_out. Assume Clock is low (0.0V)

Assume UNIT delays for the Inverters, N-CH & P-CH devices

ACLK

BCLK

Din

Scan_in

Dout

Scan_out

8
 EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Constant Field Scaling

For this problem we are assuming constant field scaling and the
scaling factor ‘K’ is > 1 i.e.  2

a) Explain why gate capacitance scales by 1/K from one technology

generation to the next?

The thickness of the gate oxide is scaled by 1/K

The width of the gate is scaled by 1/K
The length of the gate is scaled by 1/K

1 / K 1 / K
Cap  A / tox   1/ K
1/ K

b) Explain why resistance of metal wires scale proportionally to K2

Wire resistance per unit length will scale by K2

Rold pL / A
  K * K = K2
Rnew pL / A / K * K

Where p = resistivity L = length (constant) K = scaling factor

c) Explain why metal wire RC delay scales proportionally to K/K (i.e. 1).

The length of the wire is scaled by 1/K

The resistance/unit length scales by K2
The wire capacitance/unit length scales by 1
The RC delay scales by: (K2 * 1/K) * (1 * 1/K) = 1
 
R C

d) Explain why transistor density (trans/mm2 ) scales proportionally to K2

The length and width are scaled by 1/K

Area scales by 1/K2
Transistor density is inversely proportional to Area => 1/1/K2 = K2

9
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Transistor Scaling (25 Points)

Fill out the following table for Constant FIELD Scaling.

NOTE: the scaling factor K is > 1 where K is typically √ 2

Scaling factor
MOSFET device and Circuit Parameters
K>1

Device dimensions ( tox, L, W, xj) 1/K

Doping Concentration (Na, Nd) K

Voltage (V) 1/K

Depletion Layer Width (Wd) 1/K

Electric Field ( ε ) 1

Capacitance (C=εA/t) 1/K

Power Density (P/A) 1

Circuit Density ( proportional to 1/A) K2

Circuit Delay Time (τ ~ CV/I) 1/K

Channel Resistance (R) 1

10
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Device Operation

Derive the analytic expression for Vout as a

function of Vin for regions B and D for the inverter VDD
transfer function shown to the right.
Assume that | Vtp | = Vtn and βn = βp A B

Region nMOS pMOS Vout

A Cutoff Linear C
B Saturation Linear
C Saturation Saturation
D Linear Saturation
D
E Linear Cutoff E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

REGION B:

In region B, the NMOS is saturated and PMOS is

linear:

REGION D:

In region D, the nMOS is linear and the pMOS is saturated:

11
EE382M: VLSI-2: Answers to Example Questions Exam 1 Spring 2018

Device Operation

Derive the analytic expression for Vsw where

Vout=Vin=Vsw (switch point) for region C for the VDD
inverter transfer function shown to the right. A B
Assume that | Vtp | = Vtn and βn = βp
Vout
C

Vsw D
E
0 Vtn VDD/2 VDD+Vtp
Recall that the currents through each transistor are VDD
equal in the switch point region: Vin
The current through the NMOS device in saturation is:

The current through the PMOS device in saturation is:

The switching point where both transistors are saturated (region C) is found by
solving for equal currents. Therefore

Since βp = βn and |-Vtp| = Vtn we get:

Which is what we expected

The real gnarly solution when Bp ≠ Bn and Vtp ≠ Vtn is shown below

12