ML145151 ML145152 ML145155 ML145156 ML145157 ML145158: PLL Frequency Synthesizer Family - CMOS

ML145151 ML145156
ML145152 ML145157
ML145155 ML145158
PLL Frequency Synthesizer Family - CMOS
The devices described in this document are typically used as low–power, phase–locked loop frequency
synthesizers. When combined with an external low–pass filter and voltage–controlled oscillator, these
devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the
device's frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used
between the VCO and the synthesizer IC.
These frequency synthesizer chips can be found in the following and other applications:
CATV TV Tuning
AM/FM Radios Scanning Receivers
Two–Way Radios Amateur Radio
OSC ÷R
CONTROL LOGIC φ
÷A ÷N
EXTERNAL
÷ P/P + 1 VCO
COMPONENTS
OUTPUT
FREQUENCY
CONTENTS
Page
DEVICE DETAIL SHEETS
ML145151 Parallel–Input, Single–Modulus ...........................................................................................2
ML145152 Parallel–Input, Dual–Modulus..............................................................................................5
ML145155 Serial–Input, Single–Modulus ..............................................................................................9
ML145156 Serial–Input, Dual–Modulus...............................................................................................13
ML145157 Serial–Input, Single–Modulus ............................................................................................17
ML145158 Serial–Input, Dual–Modulus...............................................................................................20
FAMILY CHARACTERISTICS
Maximum Ratings..................................................................................................................................23
DC Electrical Characteristics.................................................................................................................23
AC Electrical Characteristics.................................................................................................................25
Timing Requirements.............................................................................................................................26
Frequency Characteristics ......................................................................................................................27
Phase Detector/Lock Detector Output Waveforms................................................................................27
DESIGN CONSIDERATIONS
Phase–Locked Loop – Low–Pass Filter Design ....................................................................................28
Crystal Oscillator Considerations ..........................................................................................................29
Dual–Modulus Prescaling......................................................................................................................30
Page 1 of 35 www.lansdale.com Issue A

ML145151
Parallel-Input PLL
Frequency Synthesizer
Interfaces with Single–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145151

The ML145151 is programmed by 14 parallel–input data
lines for the N counter and three input lines for the R counter. P DIP 28 = YP
The device features consist of a reference oscillator, selec- PLASTIC DIP
CASE 710
table–reference divider, digital–phase detector, and 14–bit 28
1
programmable divide–by–N counter.
• Operating Temperature Range: TA = – 40 to 85°C SO 28W = -6P

SOG PACKAGE
• Low Power Consumption Through Use of CMOS 28
CASE 751F
Technology 1
• 3.0 to 9.0 V Supply Range CROSS REFERENCE/ORDERING INFORMATION

• On– or Off–Chip Reference Oscillator Operation PACKAGE MOTOROLA LANSDALE
• Lock Detect Signal P DIP 28 MC145151P2 ML145151YP
SO 28W MC145151DW2 ML145151-6P
• ÷ N Counter Output Available
• Single Modulus/Parallel Programming Note: Lansdale lead free (Pb) product, as it
• 8 User–Selectable ÷ R Values: 8, 128, 256, 512, 1024, becomes available, will be identified by a part
number prefix change from ML to MLE.
2048, 2410, 8192
• ÷ N Range = 3 to 16383
• “Linearized” Digital Phase Detector Enhances Transfer
Function Linearity PIN ASSIGNMENT
• Two Error Signal Options: Single–Ended (Three–State)
fin 1 28 LD
or Double–Ended
VSS 2 27 OSCin
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
VDD 3 26 OSCout
PDout 4 25 N11
RA0 5 24 N10
RA1 6 23 N13
RA2 7 22 N12
φR 8 21 T/R
φV 9 20 N9
fV 10 19 N8
N0 11 18 N7
N1 12 17 N6
N2 13 16 N5
N3 14 15 N4

LANSDALE Semiconductor, Inc. ML145151
ML145151 BLOCK DIAGRAM
RA2
RA1 14 x 8 ROM REFERENCE DECODER
OSCout RA0
14 LOCK
LD
DETECT
OSCin 14–BIT ÷ R COUNTER
PHASE
DETECTOR PDout
A
fin 14–BIT ÷ N COUNTER

VDD PHASE φV
14 DETECTOR
B φR
T/R TRANSMIT OFFSET ADDER
fV
N13 N11 N9 N7 N6 N4 N2 N0
NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.
PIN DESCRIPTIONS nificant and N13 is the most significant. Pull–up resistors en-
INPUT PINS sure that inputs left open remain at a logic 1 and require only
an SPST switch to alter data to the zero state.
f in
Frequency Input (Pin 1) T/R
Transmit/Receive Offset Adder Input (Pin 21)
Input to the ÷N portion of the synthesizer. f in is typically
derived from loop VCO and is AC coupled into the device. For This input controls the offset added to the data provided at
larger amplitude signals (standard CMOS logic levels) DC the N inputs. This is normally used for offsetting the VCO fre-
coupling may be used. quency by an amount equal to the IF frequency of the trans-
ceiver. This offset is fixed at 856 when T/R is low and gives no
RA0 – RA2 offset when T/R is high. A pull–up resistor ensures that no
Reference Address Inputs (Pins 5, 6, 7) connection will appear as a logic 1 causing no offset addition.
These three inputs establish a code defining one of eight OSCin, OSCout
possible divide values for the total reference divider, as defined Reference Oscillator Input/Output (Pins 27, 26)
by the table below.
Pull–up resistors ensure that inputs left open remain at a These pins form an on–chip reference oscillator when con-
logic 1 and require only a SPST switch to alter data to the zero nected to terminals of an external parallel resonant crystal.
state. Frequency setting capacitors of appropriate value must be con-
nected from OSCin to ground and OSCout to ground. OSCin
Reference Address Code Total may also serve as the input for an externally generated refer-
Divide ence signal. This signal is typically AC coupled to OSCin, but
RA2 RA1 RA0 Value for larger amplitude signals (standard CMOS logic levels) DC
0 0 0 8 coupling may also be used. In the external reference mode, no
0 0 1 128 connection is required to OSCout.
0 1 0 256
OUTPUT PINS
0 1 1 512
1 0 0 1024 PDout
1 0 1 2048 Phase Detector A Output (Pin 4)
1 1 0 2410
1 1 1 8192 Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this pur-
pose (see ΦV and ΦR).
N0 – N11
N Counter Programming Inputs (Pins 11 – 20, 22 – 25) Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
These inputs provide the data that is preset into the ÷ N Frequency fV = fR and Phase Coincidence: High–Imped-
counter when it reaches the count of zero. N0 is the least sig- ance State

φR,φV nally connected to the phase detector input. With this output
Phase Detector B Outputs (Pins 8, 9) available, the ÷ N counter can be used independently.
These phase detector outputs can be combined externally for LD
a loop–error signal. A single–ended output is also available for Lock Detector Output (Pin 28)
this purpose (see PDout). Essentially a high level when loop is locked (fR, fV of same
If frequency fV is greater than fR or if the phase of fV is phase and frequency). Pulses low when loop is out of lock.
leading, then error information is provided by φV pulsing low.
φR remains essentially high. POWER SUPPLY
If the frequency fV is less than fR or if the phase of fV is VDD
lagging, then error information is provided by φR pulsing low. Positive Power Supply (Pin 3)
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both The positive power supply potential. This pin may range
φV and φR remain high except for a small minimum time peri- from + 3 to + 9 V with respect to VSS.
od when both pulse low in phase. VSS
fV Negative Power Supply (Pin 2)
N Counter Output (Pin 10) The most negative supply potential. This pin is usually-
This is the buffered output of the ÷ N counter that is inter- ground.
TYPICAL APPLICATIONS
2.048 MHz
NC NC
OSCin OSCout fin RA2 RA1 RA0

VOLTAGE
ML145151 PDout CONTROLLED
OSCILLATOR
N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
5 – 5.5 MHz
0 1 1 1 0 0 0 1 0 0 0 = 5 MHz
1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz
Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz
LOCK DETECT SIGNAL TRANSMIT: 440.0 – 470.0 MHz

“1” “1” “0” RECEIVE: 418.6 – 448.6 MHz
CHOICE OF (25 kHz STEPS)
DETECTOR
OSCout RA2 RA1 RA0 LD fV ERROR
PDout SIGNALS
OSCin LOOP
+V VDD φR VCO X6
ML145151 FILTER
VSS fV
REF. OSC.
10.0417 MHz fin T: 73.3333 – 78.3333 MHz
T/R
(ON–CHIP OSC. T: 13.0833 – 18.0833 MHz R: 69.7667 – 74.7667 MHz
OPTIONAL) R: 9.5167 – 14.5167 MHz
“0” “0” “1” DOWN
CHANNEL PROGRAMMING MIXER
RECEIVE
TRANSMIT ÷ N = 2284 TO 3484
(ADDS 856 TO
÷ N VALUE)
X6
60.2500 MHz
NOTES:
1. fR = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive.
2. Frequency values shown are for the 440 – 470 MHz band. Similar implementation applies to the 406 – 440 MHz band.
For 470 – 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz).
Figure 2. Synthesizer for Land Mobile Radio UHF Bands
ML145151 Data Sheet Continued on Page 23

ML145152
Parallel-Input PLL
Interfaces with Dual–Modulus Prescalers
Legacy Device: Motorola/Freescale MC145152

The ML145152 is programmed by sixteen parallel inputs
for the N and A counters and three input lines for the R P DIP 28 = YP
counter. The device features consist of a reference oscillator, PLASTIC DIP
CASE 710
selectable–reference divider, two–output phase detector, 28
1
10–bit programmable divide–by–N counter, and 6–bit pro-
grammable ÷ A counter.
SO 28W = -6P
SOG PACKAGE
• Operating Temperature Range: TA = – 40 to 85°C 28
CASE 751F
1
• Low Power Consumption Through Use of CMOS
Technology CROSS REFERENCE/ORDERING INFORMATION
• 3.0 to 9.0 V Supply Range PACKAGE MOTOROLA LANSDALE
• On– or Off–Chip Reference Oscillator Operation P DIP 28 MC145152P2 ML145152YP
SO 28W MC145152DW2 ML145152-6P
• Lock Detect Signal
• Dual Modulus/Parallel Programming Note: Lansdale lead free (Pb) product, as it
• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 512, becomes available, will be identified by a part
1024, 1160, 2048
• ÷ N Range = 3 to 1023, ÷ A Range = 0 to 63
• See Application Note AN980 PIN ASSIGNMENT
fin 1 28 LD
VSS 2 27 OSCin
VDD 3 26 OSCout
RA0 4 25 A4
RA1 5 24 A3
RA2 6 23 A0
φR 7 22 A2
φV 8 21 A1
MC 9 20 N9
A5 10 19 N8
N0 11 18 N7
N1 12 17 N6
N2 13 16 N5
N3 14 15 N4

RA2
OSCout RA0
12
LOCK
LD
OSCin 12–BIT ÷ R COUNTER DETECT
MC
CONTROL PHASE φV
LOGIC DETECTOR φR
fin
6–BIT ÷ A COUNTER 10–BIT ÷ N COUNTER
A5 A3 A2 A0 N0 N2 N4 N5 N7 N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
PIN DESCRIPTIONS tors that ensure that inputs left open will remain at a logic 1.
INPUT PINS OSCin, OSCout
f in Reference Oscillator Input/Output (Pins 27, 26)
Frequency Input (Pin 1) These pins form an on–chip reference oscillator when con-
Input to the positive edge triggered ÷ N and ÷ A counters. nected to terminals of an external parallel resonant crystal.
f in is typically derived from a dual–modulus prescaler and is Frequency setting capacitors of appropriate value must be con-
AC coupled into the device. For larger amplitude signals (stan- nected from OSCin to ground and OSCout to ground. OSCin
dard CMOS logic levels) DC coupling may be used. may also serve as the input for an externally generated refer-
ence signal. This signal is typically AC coupled to OSCin, but
RA0, RA1, RA2 for larger amplitude signals (standard CMOS logic levels) DC
Reference Address Inputs (Pins 4, 5, 6) coupling may also be used. In the external reference mode, no
These three inputs establish a code defining one of eight connection is required to OSCout.
possible divide values for the total reference divider. The total OUTPUT PINS
reference divide values are as follows:
φR,φV
Phase Detector B Outputs (Pins 7, 8)
Reference Address Code Total
Divide These phase detector outputs can be combined externally for
RA2 RA1 RA0 Value a loop–error signal.
0 0 0 8
If the frequency fV is greater than fR or if the phase of fV is
0 0 1 64 leading, then error information is provided by φV pulsing low.
0 1 0 128 φR remains essentially high.
0 1 1 256 If the frequency fV is less than fR or if the phase of fV is
1 0 0 512 lagging, then error information is provided by φR pulsing low.
1 0 1 1024 φV remains essentially high.
1 1 0 1160 If the frequency of fV = fR and both are in phase, then both
1 1 1 2048
φV and φR remain high except for a small minimum time peri-
N0 – N9 od when both pulse low in phase.
N Counter Programming Inputs (Pins 11 – 20) MC
The N inputs provide the data that is preset into the ÷ N Dual–Modulus Prescale Control Output (Pin 9)
counter when it reaches the count of 0. N0 is the least signifi- Signal generated by the on–chip control logic circuitry for
cant digit and N9 is the most significant. Pull–up resistors en- controlling an external dual–modulus prescaler. The MC level
sure that inputs left open remain at a logic 1 and require only a will be low at the beginning of a count cycle and will remain
SPST switch to alter data to the zero state. low until the ÷ A counter has counted down from its pro-
A0 – A5 grammed value. At this time, MC goes high and remains high
A Counter Programming Inputs(Pins 23, 21, 22, 24, 25, 10) until the ÷ N counter has counted the rest of the way down
from its programmed value (N – A additional counts since
The A inputs define the number of clock cycles of f in that both ÷ N and ÷ A are counting down during the first portion of
require a logic 0 on the MC output (see Dual–Modulus Pres- the cycle). MC is then set back low, the counters preset to
caling section). The A inputs all have internal pull–up resis-

their respective programmed values, and the above sequence POWER SUPPLY
repeated. This provides for a total programmable divide value VDD
(NT)=N•P+A where P and P + 1 represent the dual–modulus Positive Power Supply (Pin 3)
prescaler divide values respectively for high and low MC lev-
els, N the number programmed into the ÷ N counter, and A the The positive power supply potential. This pin may range from
number programmed into the ÷ A counter. + 3 to + 9 V with respect to VSS.
LD VSS
Lock Detector Output (Pin 28) Negative Power Supply (Pin 2)
Essentially a high level when loop is locked (fR, fV of same The most negative supply potential. This pin is usually-
phase and frequency). Pulses low when loop is out of lock. ground.
NO CONNECTS
“1” “1” “1” 150 – 175 MHz

LOCK DETECT SIGNAL
10.24 MHz 5 kHz STEPS
NOTE 1 R2 C
OSCout RA2 RA1 RA0 LD R1

φR –
OSCin
R1 VCO
φV +
MC33171
ML145152 R2
MC NOTE 2
+V VDD
fin C
VSS
N9 N0 A5 A0
CHANNEL PROGRAMMING ML12017

÷ 64/65 PRESCALER
NOTES:
1. Off–chip oscillator optional.
2. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter
Design page for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful
not to exceed the common mode input range of the op amp used in the combiner/loop filter.
Figure 1. Synthesizer for Land Mobile Radio VHF Bands

RECEIVER 2ND L.O.

REF. OSC. NO CONNECTS 30.720 MHz
15.360 MHz
(ON–CHIP OSC. X2 RECEIVER FIRST L.O.
OPTIONAL) “1” “1” “1” LOCK DETECT SIGNAL
825.030 → 844.980 MHz
R2 C (30 kHz STEPS)
OSCout RA2 RA1 RA0 LD R1
φR –
OSCin X4
R1 VCO
φV + NOTE 6
+V VDD ML145152 NOTE 7
NOTE 5 R2
MC
VSS
fin C TRANSMITTER X4
MODULATION NOTE 6
N9 N0 A5 A0
ML12017
÷ 64/65 PRESCALER TRANSMITTER SIGNAL
CHANNEL PROGRAMMING
NOTE 6 825.030 → 844.980 MHz
(30 kHz STEPS)
NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receiver/transmit separation.
3. fR = 7.5 kHz; ÷ R = 2048.
4. Ntotal = N 64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63.
5. ML145158 may be used where serial data entry is desired.
6. High frequency prescalers may be used for higher frequency VCO and f ref
implementations.
7. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page for
additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode
input range of the op amp used in the combiner/loop filter.
Figure 2. 666–Channel, Computer–Controlled, Mobile Radiotelephone Synthesizer

for 800 MHz Cellular Radio Systems

ML145155
Serial–Input PLL
Legacy Device: Motorola/Freescale MC145155-2

The ML145155 is programmed by a clocked, serial input,
16–bit data stream. The device features consist of a reference
P DIP 18 = VP
oscillator, selectable–reference divider, digital–phase detector, PLASTIC DIP
14–bit programmable divide–by–N counter, and the necessary CASE 707
18
shift register and latch circuitry for accepting serial input 1
data.
• Operating Temperature Range: TA = – 40 to 85°C SOG 20W = -6P
• Low Power Consumption Through Use of CMOS 20 SOG PACKAGE
Technology 1
CASE 751D
• 3.0 to 9.0 V Supply Range

• On– or Off–Chip Reference Oscillator Operation with CROSS REFERENCE/ORDERING INFORMATION
Buffered Output PACKAGE MOTOROLA LANSDALE
• Compatible with the Serial Peripheral Interface (SPI) on P DIP 18 MC145155P2 ML145155VP
SOG 20W MC145155DW2 ML145155-6P
CMOS MCUs
• Lock Detect Signal Note: Lansdale lead free (Pb) product, as it
• Two Open–Drain Switch Outputs becomes available, will be identified by a part
• 8 User–Selectable ÷ R Values: 16, 512, 1024, 2048,
3668, 4096, 6144, 8192
• Single Modulus/Serial Programming
• ÷ N Range = 3 to 16383
• “Linearized” Digital Phase Detector Enhances Transfer
Function Linearity
• Two Error Signal Options: Single–Ended (Three–State)
or Double–Ended
PIN ASSIGNMENTS
PLASTIC DIP SOG PACKAGE
RA1 1 18 RA0 RA1 1 20 RA0
RA2 2 17 OSCin RA2 2 19 OSCin
φV 3 16 OSCout φV 3 18 OSCout
φR 4 15 REFout φR 4 17 REFout
VDD 5 14 SW2 VDD 5 16 NC
PDout 6 13 SW1 PDout 6 15 SW2
VSS 7 12 ENB VSS 7 14 SW1

LD 8 11 DATA NC 8 13 ENB
fin 9 10 CLK LD 9 12 DATA
fin 10 11 CLK
NC = NO CONNECTION

ML145155 LANSDALE Semiconductor, Inc.
RA2
RA0
OSCout 14 LOCK
LD
DETECT
fR PHASE
DETECTOR PDout
fV A
REFout
fin 14–BIT ÷ R COUNTER
PHASE φV
DETECTOR
B φR
VDD 14
SW2
ENB LATCH LATCH SW1
14
DATA 2–BIT SHIFT
14–BIT SHIFT REGISTER
REGISTER
CLK
PIN DESCRIPTIONS signals SW1 and SW2. The entry format is as follows:
INPUT PINS
f in ÷ N COUNTER BITS
Frequency Input (PDIP – Pin 9, SOG – Pin 10)
Input to the ÷ N portion of the synthesizer. f in is typically
÷ N MSB
÷ N LSB
SW2
SW1
derived from loop VCO and is AC coupled into the device. For
larger amplitude signals (standard CMOS logic levels) DC
coupling may be used.
LAST DATA BIT IN (BIT NO. 16)
RA0, RA1, RA2 FIRST DATA BIT IN (BIT NO. 1)
Reference Address Inputs (PDIP – Pins 18, 1, 2; SOG – ENB
Pins 20, 1, 2) Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)
These three inputs establish a code defining one of eight When high (1), ENB transfers the contents of the shift reg-
possible divide values for the total reference divider, as defined ister into the latches, and to the programmable counter inputs,
by the table below: and the switch outputs SW1 and SW2. When low (0), ENB
inhibits the above action and thus allows changes to be made
Reference Address Code Total in the shift register data without affecting the counter program-
Divide ming and switch outputs. An on–chip pull–up establishes a
RA2 RA1 RA0 Value continuously high level for ENB when no external signal is
0 0 0 16 applied. ENB is normally low and is pulsed high to transfer
0 0 1 512 data to the latches.
0 1 0 1024
0 1 1 2048 OSCin, OSCout
1 0 0 3668 Reference Oscillator Input/Output (PDIP – Pins 17, 16;
1 0 1 4096 SOG – Pins 19, 18)
1 1 0 6144
These pins form an on–chip reference oscillator when con-
1 1 1 8192
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
CLK, DATA nected from OSCin to ground and OSCout to ground. OSCin
Shift Register Clock, Serial Data Inputs may also serve as the input for an externally–generated refer-
(PDIP – Pins 10, 11; SOG – Pins 11, 12) ence signal. This signal is typically ac coupled to OSCin, but
Each low–to–high transition clocks one bit into the on–chip for larger amplitude signals (standard CMOS logic levels) DC
16–bit shift register. The Data input provides programming coupling may also be used. In the external reference mode, no
information for the 14–bit ÷ N counter and the two switch connection is required to OSCout.

ML145155
OUTPUT PINS phase and frequency). LD pulses low when loop is out of lock.
PDout
Phase Detector A Output (PDIP, SOG – Pin 6) SW1, SW2
Three–state output of phase detector for use as loop error Band Switch Outputs (PDIP – Pins 13, 14; SOG – Pins 14, 15)
signal. Double–ended outputs are also available for this pur- SW1 and SW2 provide latched open–drain outputs corre-
pose (see φV and φR). sponding to data bits numbers one and two. These outputs can
Frequency fV > fR or fV Leading: Negative Pulses be tied through external resistors to voltages as high as 15 V,
Frequency fV < fR or fV Lagging: Positive Pulses independent of the VDD supply voltage. These are typically
Frequency fV = fR and Phase Coincidence: High–Imped- used for band switch functions. A logic 1 causes the output to
ance State assume a high–impedance state, while a logic 0 causes the out-
put to be low.
φR, φV
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3) REFout
These phase detector outputs can be combined externally for Buffered Reference Oscillator Output (PDIP, SOG – Pin 15)
a loop–error signal. A single–ended output is also available for Buffered output of on–chip reference oscillator or externally
this purpose (see PDout). provided reference–input signal.
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by fV pulsing low. POWER SUPPLY
fR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is VDD
lagging, then error information is provided by fR pulsing low. Positive Power Supply (PDIP, SOG – Pin 5)
fV remains essentially high. The positive power supply potential. This pin may range
If the frequency of fV = fR and both are in phase, then both from + 3 to + 9 V with respect to VSS.
fV and fR remain high except for a small minimum time peri-
od when both pulse low in phase. VSS
Negative Power Supply (PDIP, SOG – Pin 7)
LD The most negative supply potential. This pin is usually
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9) ground.
Essentially a high level when loop is locked (fR, fV of same
4.0 MHz
UHF/VHF
TUNER OR
CATV
FRONT END φR –
MC120xx fin
ML145155 φV
PRESCALER 1/2 MC1458*
+
DATA CLK ENB
CMOS 3 MC14489
KEYBOARD MPU/MCU
LED DISPLAY
* The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface

ML145155
2.56 MHz
fin φR – TO
FM ML12019
ML145155 φV AM/FM
OSC ÷20 PRESCALER
+ 1/2 MC1458* OSCILLATORS
AM
DATA CLK ENB
OSC
CMOS
KEYBOARD TO DISPLAY
MPU/MCU
* The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
Figure 2. AM/FM Radio Synthesizer

ML145156
Serial–Input PLL

The ML145156 is programmed by a clocked, serial input,
19–bit data stream. The device features consist of a reference
P DIP 20 = RP
oscillator, selectable–reference divider, digital–phase detector, PLASTIC DIP
10–bit programmable divide–by–N counter, 7–bit program- 20 CASE 738
mable divide–by–A counter, and the necessary shift register 1
and latch circuitry for accepting serial input data.

SOG 20W = -6P
• Operating Temperature Range: TA = – 40 to 85°C 20
SOG PACKAGE
• Low Power Consumption Through Use of CASE 751D
1
CMOS Technology
• 3.0 to 9.0 V Supply Range CROSS REFERENCE/ORDERING INFORMATION
• On– or Off–Chip Reference Oscillator Operation with PACKAGE MOTOROLA LANSDALE
Buffered Output P DIP 20 MC145156P2 ML145156RP
SOG 20W MC145156DW2 ML145156-6P
• Compatible with the Serial Peripheral Interface (SPI) on
CMOS MCUs Note: Lansdale lead free (Pb) product, as it
• Lock Detect Signal becomes available, will be identified by a part
• Two Open–Drain Switch Outputs number prefix change from ML to MLE.
• Dual Modulus/Serial Programming
• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 640,
1000, 1024, 2048
PIN ASSIGNMENT
• ÷ N Range = 3 to 1023, ÷A Range = 0 to 127
• “Linearized” Digital Phase Detector Enhances Transfer RA1 1 20 RA0
Function Linearity RA2 2 19 OSCin
• Two Error Signal Options: Single–Ended (Three–State) φV 3 18 OSCout
or Double–Ended φR 4 17 REFout
VDD 5 16 TEST
PDout 6 15 SW2
VSS 7 14 SW1
MC 8 13 ENB
LD 9 12 DATA
fin 10 11 CLK

RA2
RA0
12
LOCK
OSCin 12–BIT ÷ R COUNTER LD
DETECT
OSCout
REFout CONTROL LOGIC fR PHASE

DETECTOR PDout
MC fV A
fin 7–BIT ÷ A COUNTER 10–BIT ÷ N COUNTER PHASE φV

DETECTOR
B φR
VDD 7 10 SW2
ENB ÷ A COUNTER LATCH ÷ N COUNTER LATCH LATCH SW1
7 10
DATA 2–BIT SHIFT
7–BIT SHIFT REGISTER 10–BIT SHIFT REGISTER REGISTER
CLK
PIN DESCRIPTIONS A COUNTER BITS N COUNTER BITS

INPUT PINS
÷N MSB
MSB
N LSB
A LSB
SW2
SW1
f in
÷A
÷
÷
Frequency Input (Pin 10)
Input to the positive edge triggered ÷ N and ÷ A counters. LAST DATA BIT IN (BIT NO. 19)
f in is typically derived from a dual–modulus prescaler and is FIRST DATA BIT IN (BIT NO. 1)
AC coupled into the device. For larger amplitude signals (stan-
ENB
dard CMOS logic levels), DC coupling may be used.
Latch Enable Input (Pin 13)
When high (1), ENB transfers the contents of the shift reg-
RA0, RA1, RA2
ister into the latches, and to the programmable counter inputs,
Reference Address Inputs (Pins 20, 1, 2)
and the switch outputs SW1 and SW2. When low (0), ENB
These three inputs establish a code defining one of eight
inhibits the above action and thus allows changes to be made
possible divide values for the total reference divider, as defined
in the shift register data without affecting the counter program-
by the table below:
ming and switch outputs. An on–chip pull–up establishes a
continuously high level for ENB when no external signal is
Reference Address Code Total applied. ENB is normally low and is pulsed high to transfer
Divide
RA2 RA1 RA0
data to the latches.
Value
0 0 0 8 OSCin, OSCout
0 0 1 64 Reference Oscillator Input/Output (Pins 19, 18)
0 1 0 128 These pins form an on–chip reference oscillator when con-
0 1 1 256
1 0 0 640
1 0 1 1000 Frequency setting capacitors of appropriate value must be con-
1 1 0 1024 nected from OSCin to ground and OSCout to ground. OSCin
1 1 1 2048 may also serve as the input for an externally–generated refer-
for larger amplitude signals (standard CMOS logic levels) DC
CLK, DATA
coupling may also be used. In the external reference mode, no
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
connection is required to OSCout.
Each low–to–high transition clocks one bit into the on–chip
19–bit shift register. The data input provides programming in-
TEST
formation for the 10–bit ÷ N counter, the 7–bit ÷ A counter,
Factory Test Input (Pin 16)
and the two switch signals SW1 and SW2. The entry format is
Used in manufacturing. Must be left open or tied to VSS.
as follows:

ML145156
OUTPUT PINS respective programmed values, and the above sequence repeat-
ed. This provides for a total programmable divide value (NT) =
PDout N • P + A where P and P + 1 represent the dual–modulus
Phase Detector A Output (Pin 6) prescaler divide values respectively for high and low MC lev-
Three–state output of phase detector for use as loop–error els, N the number programmed into the ÷ N counter, and A the
signal. Double–ended outputs are also available for this pur- number programmed into the ÷ A counter.
pose (see φV and φR).
Frequency fV > fR or fV Leading: Negative Pulses LD
Frequency fV < fR or fV Lagging: Positive Pulses Lock Detector Output (Pin 9)
Frequency fV = fR and Phase Coincidence: High–Imped- Essentially a high level when loop is locked (fR, fV of same
ance State phase and frequency). LD pulses low when loop is out of lock.
φR, φV SW1, SW2

Phase Detector B Outputs (Pins 4, 3) Band Switch Outputs (Pins 14, 15)
These phase detector outputs can be combined externally for SW1 and SW2 provide latched open–drain outputs corre-
a loop–error signal. A single–ended output is also available for sponding to data bits numbers one and two. These outputs can
this purpose (see PDout). be tied through external resistors to voltages as high as 15 V,
If frequency fV is greater than fR or if the phase of fV is independent of the VDD supply voltage. These are typically
leading, then error information is provided by φV pulsing low. used for band switch functions. A logic 1 causes the output to
φR remains essentially high. assume a high–impedance state, while a logic 0 causes the out-
If the frequency fV is less than fR or if the phase of fV is put to be low.
lagging, then error information is provided by φR pulsing low.
φV remains essentially high. REFout
If the frequency of fV = fR and both are in phase, then both Buffered Reference Oscillator Output (Pin 17)
φV and φR remain high except for a small minimum time Buffered output of on–chip reference oscillator or externally
period when both pulse low in phase. provided reference–input signal.
MC POWER SUPPLY
Dual–Modulus Prescale Control Output (Pin 8)
Signal generated by the on–chip control logic circuitry for- VDD
controlling an external dual–modulus prescaler. The MC level- Positive Power Supply (Pin 5)
will be low at the beginning of a count cycle and will remain- The positive power supply potential. This pin may range
low until the ÷ A counter has counted down from its pro- from + 3 to + 9 V with respect to VSS.
grammed value. At this time, MC goes high and remains high-
until the ÷ N counter has counted the rest of the way down- VSS
from its programmed value (N – A additional counts since Negative Power Supply (Pin 7)
both ÷ N and ÷ A are counting down during the first portion of The most negative supply potential. This pin is usually-
the cycle). MC is then set back low, the counters preset to their ground.

ML145156
+ 12 V
LOCK DETECT SIGNAL
3.2 MHz
NOTES 1 + 12 V FM B +
AND 2
+V OSCin OSCout RA2 RA1 RA0 LD SW1 SW2 AM B +

OPTIONAL
PDout LOOP
VDD
ERROR SIGNAL
VSS ML145156 φR –
VCO
REFout φV +
CLK DATA ENB fin MC 1/2 MC1458
NOTE 3
KEY– CMOS MPU/MCU

BOARD
ML12019
÷ 20/21 DUAL MODULUS PRESCALER
TO DISPLAY DRIVER (e.g., MC14489)
NOTES:
1. For AM: channel spacing = 5 kHz, ÷ R = ÷ 640 (code 100).
2. For FM: channel spacing = 25 kHz, ÷ R = ÷ 128 (code 010).
3. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the
common mode input range of the op amp used in the combiner/loop filter.
Figure 1. AM/FM Radio Broadcast Synthesizer
3.2 MHz (NOTE 3)
VCO RANGE
NAV = 01
LOCK DETECT SIGNAL NAV: 97.300 – 107.250 MHz
COM = 10
COM–T: 118.000 – 135.975 MHz
COM–R: 139.400 – 157.375 MHz
+V
OSCin OSCout RA2 RA1 RA0 LD SW1 SW2
VDD PDout
VSS ML145156 φR –
VCO
REFout φV +
CLK DATA ENB fin MC MC33171
NOTE 5
R/T CMOS MPU/MCU
ML12016 (NOTES 2 AND 4)

÷ 40/41 DUAL MODULUS PRESCALER
CHANNEL TO DISPLAY DRIVER
SELECTION (e.g., MC14489)
NOTES:
1. For NAV: fR = 50 kHz, ÷ R = 64 using 10.7 MHz lowside injection, N total = 1946 – 2145.
For COM–T: fR = 25 kHz, ÷ R = 128, Ntotal = 4720 – 5439.
For COM–R: f R = 25 kHz, ÷ R = 128, using 21.4 MHz highside injection, Ntotal = 5576 – 6295.
2. A ÷ 32/33 dual modulus approach is provided by substituting an ML12015 for the ML12016. The devices are pin equivalent.
3. A 6.4 MHz oscillator crystal can be used by selecting ÷ R = 128 (code 010) for NAV and ÷ R = 256 (code 011) for COM.
4. ML12013 + MC10131 combination may also be used to form the ÷ 40/41 prescaler .
5. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design
page for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed
the common mode input range of the op amp used in the combiner/loop filter.
Figure 2. Avionics Navigation or Communication Synthesizer

ML145157
Serial–Input PLL

The ML145157 has a fully programmable 14–bit reference
counter, as well as a fully programmable ÷ N counter. The
P DIP 16 = EP
counters are programmed serially through a common data PLASTIC DIP
input and latched into the appropriate counter latch, accord- 16
CASE 648
ing to the last data bit (control bit) entered. 1
• Operating Temperature Range: TA = – 40 to 85°C SOG 16 = -5P

• Low Power Consumption Through Use of CMOS 16
SOG PACKAGE
Technology CASE 751G
1
• Fully Programmable Reference and ÷ N Counters CROSS REFERENCE/ORDERING INFORMATION
• ÷ R Range = 3 to 16383 PACKAGE MOTOROLA LANSDALE
• ÷ N Range = 3 to 16383 P DIP 16 MC145157P2 ML145157EP
SOG 20W MC145157DW2 ML145157-5P
• fV and fR Outputs
• Lock Detect Signal Note: Lansdale lead free (Pb) product, as it
• Compatible with the Serial Peripheral Interface becomes available, will be identified by a part
(SPI) on CMOS MCUs number prefix change from ML to MLE.
• “Linearized” Digital Phase Detector
• Single–Ended (Three–State) or Double–Ended Phase
Detector Outputs PIN ASSIGNMENT
OSCin 1 16 φR
OSCout 2 15 φV
fV 3 14 REFout
VDD 4 13 fR
PDout 5 12 S/Rout
VSS 6 11 ENB
LD 7 10 DATA
fin 8 9 CLK

14
fR
ENB
REFERENCE COUNTER LATCH
LOCK
14 LD
DETECT

PHASE
OSCout PDout
DETECTOR
REFout A
PHASE
fin 14–BIT ÷ N COUNTER φV
DETECTOR
B φR
14
÷ N COUNTER LATCH fV
1–BIT 14
DATA
CONTROL S/Rout
S/R
CLK
PIN DESCRIPTIONS the control bit is at a logic low. A logic low on this pin allows
the user to change the data in the shift registers without affect-
INPUT PINS ing the counters. ENB is normally low and is pulsed high to
transfer data to the latches.
fin
Frequency Input (Pin 8) OSCin, OSCout
Input frequency from VCO output. A rising edge signal on Reference Oscillator Input/Output (Pins 1, 2)
this input decrements the ÷ N counter. This input has an invert- These pins form an on–chip reference oscillator when con-
er biased in the linear region to allow use with AC coupled sig- nected to terminals of an external parallel resonant crystal.
nals as low as 500 mV p–p. For larger amplitude signals (stan- Frequency setting capacitors of appropriate value must be con-
dard CMOS logic levels), DC coupling may be used. nected from OSCin to ground and OSCout to ground. OSCin
may also serve as the input for an externally–generated refer-
CLK, DATA ence signal. This signal is typically AC coupled to OSCin, but
Shift Clock, Serial Data Inputs (Pins 9, 10) for larger amplitude signals (standard CMOS logic levels) DC
Each low–to–high transition of the clock shifts one bit of coupling may also be used. In the external reference mode, no
data into the on–chip shift registers. The last data bit entered connection is required to OSCout.
determines which counter storage latch is activated; a logic
1selects the reference counter latch and a logic 0 selects the OUTPUT PINS
÷ N counter latch. The entry format is as follows:
PDout
Single–Ended Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output pro-
CONTROL
MSB
LSB
duces a loop–error signal that is used with a loop filter to con-

trol a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
FIRST DATA BIT INTO SHIFT REGISTER Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence:
High–Impedance State
ENB
Latch Enable Input (Pin 11) φR, φV
A logic high on this pin latches the data from the shift regis- Double–Ended Phase Detector B Outputs (Pins 16, 15)
ter into the reference divider or ÷ N latches depending on the These outputs can be combined externally for a loop–error
control bit. The reference divider latches are activated if the signal. A single–ended output is also available for this purpose
control bit is at a logic high and the ÷ N latches are activated if (see PDout).

ML145157
If frequency fV is greater than fR or if the phase of fV is REFout

leading, then error information is provided by φV pulsing low. Buffered Reference Oscillator Output (Pin 14)
φR remains essentially high. This output can be used as a second local oscillator, refer-
If the frequency fV is less than fR or if the phase of fV is ence oscillator to another frequency synthesizer, or as the sys-
lagging, then error information is provided by φR pulsing low. tem clock to a microprocessor controller.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both S/Rout
φV and φR remain high except for a small minimum time peri- Shift Register Output (Pin 12)
od when both pulse low in phase. This output can be connected to an external shift register to
provide band switching, control information, and counter pro-
fR, fV gramming code checking.
RCounter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and f in frequency outputs. The POWER SUPPLY
fR and fV outputs are connected internally to the ÷ R and ÷ N
counter outputs respectively, allowing the counters to be used VDD
independently, as well as monitoring the phase detector inputs. Positive Power Supply (Pin 4)
LD The positive power supply potential. This pin may range
Lock Detector Output (Pin 7) from +3 to +9 V with respect to VSS.
This output is essentially at a high level when the loop is
locked (fR, fV of same phase and frequency), and pulses low VSS
when loop is out of lock. Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually
ground.

ML145158
Serial–Input PLL

The ML145158 has a fully programmable 14–bit reference
counter, as well as fully programmable ÷ N and ÷ A counters.
P DIP 16 = EP
The counters are programmed serially through a common PLASTIC DIP
data input and latched into the appropriate counter latch, CASE 648
according to the last data bit (control bit) entered. 16
1
• Operating Temperature Range: TA = – 40 to 85°C SOG 16 = -5P

• Low Power Consumption Through Use of CMOS SOG PACKAGE
Technology 16 CASE 751G
1
• Fully Programmable Reference and ÷ N Counters CROSS REFERENCE/ORDERING INFORMATION
• ÷ R Range = 3 to 16383 PACKAGE MOTOROLA LANSDALE
• ÷ N Range = 3 to 1023 P DIP 16 MC145158P2 ML145158EP
SOG 16 MC145158DW2 ML145158-5P
• Dual Modulus Capability; ÷ A Range = 0 to 127
• fV and fR Outputs Note: Lansdale lead free (Pb) product, as it
• Lock Detect Signal becomes available, will be identified by a part
• Compatible with the Serial Peripheral Interface (SPI) on number prefix change from ML to MLE.
CMOS MCUs
• “Linearized” Digital Phase Detector
• Single–Ended (Three–State) or Double–Ended Phase
Detector Outputs
• Chip Complexity: 6504 FETs or 1626
Equivalent Gates
PIN ASSIGNMENT
OSCin 1 16 φR
OSCout 2 15 φV
fV 3 14 REFout
VDD 4 13 fR
PDout 5 12 MC
VSS 6 11 ENB
LD 7 10 DATA
fin 8 9 CLK

14
fR
ENB
REFERENCE COUNTER LATCH
LOCK
14 LD
DETECT

PHASE
OSCout PDout
DETECTOR
CONTROL LOGIC
REFout A
7–BIT ÷ A 10–BIT ÷ N PHASE φV

fin
COUNTER COUNTER DETECTOR
B φR
7 10
÷ A COUNTER ÷ N COUNTER
fV
LATCH LATCH
1–BIT 7 10
DATA
CONTROL MC
7–BIT S/R 10–BIT S/R
S/R
CLK
PIN DESCRIPTIONS ÷A ÷N
CONTROL
INPUT PINS MSB
MSB
LSB
f in Frequency Input (Pin 8) LSB
Input frequency from VCO output. A rising edge signal on

this input decrements the ÷ A and ÷ N counters. This input has FIRST DATA BIT INTO SHIFT REGISTER
an inverter biased in the linear region to allow use with AC
coupled signals as low as 500 mV p–p. For larger amplitude ENB
signals (standard CMOS logic levels), DC coupling may be Latch Enable Input (Pin 11)
used. A logic high on this pin latches the data from the shift regis-
ter into the reference divider or ÷ N, ÷ A latches depending on
CLK, DATA the control bit. The reference divider latches are activated if the
Shift Clock, Serial Data Inputs (Pins 9, 10) control bit is at a logic high and the ÷ N, ÷ A latches are acti-
Each low–to–high transition of the CLK shifts one bit of vated if the control bit is at a logic low. A logic low on this pin
data into the on–chip shift registers. The last data bit entered allows the user to change the data in the shift registers without
determines which counter storage latch is activated; a logic 1 affecting the counters. ENB is normally low and is pulsed high
selects the reference counter latch and a logic 0 selects the to transfer data to the latches.
÷ A, ÷ N counter latch. The data entry format is as follows:
OSCin, OSCout
Reference Oscillator Input/Output (Pins 1, 2)
÷R These pins form an on–chip reference oscillator when con-
Frequency setting capacitors of appropriate value must be con-
CONTROL
MSB
nected from OSCin to ground and OSCout to ground. OSCin

LSB
may also serve as the input for an externally–generated refer-

for larger amplitude signals (standard CMOS logic levels) DC
FIRST DATA BIT INTO SHIFT REGISTER
coupling may also be used. In the external reference mode, no
connection is required to OSCout.

ML145158
OUTPUT PINS lus prescaler divide values respectively for high and low modu-
lus control levels, N the number programmed into the ÷ N
PDout counter, and A the number programmed into the ÷ A counter.
Phase Detector A Output (Pin 5) Note that when a prescaler is needed, the dual–modulus ver-
This single–ended (three–state) phase detector output pro- sion offers a distinct advantage. The dual–modulus prescaler
duces a loop–error signal that is used with a loop filter to con- allows a higher reference frequency at the phase detector input,
trol a VCO. increasing system performance capability, and simplifying the
Frequency fV > fR or fV Leading: Negative Pulses loop filter design.
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: fR, fV
High–Impedance State R Counter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and fin frequency outputs. The
φR, φV fR and fV outputs are connected internally to the ÷ R and ÷ N
Phase Detector B Outputs (Pins 16, 15) counter outputs respectively, allowing the counters to be used
Double–ended phase detector outputs. These outputs can be independently, as well as monitoring the phase detector inputs.
combined externally for a loop–error signal. A single–ended
output is also available for this purpose (see PDout). LD
If frequency fV is greater than fR or if the phase of fV is Lock Detector Output (Pin 7)
leading, then error information is provided by φV pulsing low. This output is essentially at a high level when the loop is
φR remains essentially high. locked (fR, fV of same phase and frequency), and pulses low
If the frequency fV is less than fR or if the phase of fV is when loop is out of lock.
lagging, then error information is provided by φR pulsing low.
φV remains essentially high. REFout
If the frequency of fV = fR and both are in phase, then both Buffered Reference Oscillator Output (Pin 14)
φV and φR remain high except for a small minimum time peri- This output can be used as a second local oscillator, refer-
od when both pulse low in phase. ence oscillator to another frequency synthesizer, or as the sys-
tem clock to a microprocessor controller.
MC
Dual–Modulus Prescaler Control Output (Pin 12) POWER SUPPLY
This output generates a signal by the on–chip control logic
circuitry for controlling an external dual–modulus prescaler. VDD
The MC level is low at the beginning of a count cycle and Positive Power Supply (Pin 4)
remains low until the ÷ A counter has counted down from its The positive power supply potential. This pin may range
programmed value. At this time, MC goes high and remains from + 3 to + 9 V with respect to VSS.
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts VSS
since both ÷ N and ÷ A are counting down during the first por- Negative Power Supply (Pin 6)
tion of the cycle). MC is then set back low, the counters preset
to their respective programmed values, and the above sequence The most negative supply potential. This pin is usually-
repeated. This provides for a total programmable divide value ground.
(NT) = N • P + A where P and P + 1 represent the dual–modu-
Page 22 of 35 www.lansdale.com #
LANSDALE Semiconductor, Inc. ML1451xx
ML14515X FAMILY CHARACTERISTICS AND DESCRIPTIONS - CONTINUED
MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol Parameter Value Unit These devices contain protection circuitry to
protect against damage due to high static
VDD DC Supply Voltage – 0.5 to + 10.0 V voltages or electric fields. However, precau-
tions must be taken to avoid applications of any
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
voltage higher than maximum rated voltages
except SW1, SW2
to these high–impedance circuits. For proper
Vout Output Voltage (DC or Transient), – 0.5 to + 15 V operation, Vin and Vout should be constrained
SW1, SW2 (Rpull–up = 4.7 kΩ) to the range VSS (Vin or Vout) VDD
except for SW1 and SW2.
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA SW1 and SW2 can be tied through external
per Pin resistors to voltages as high as 15 V, indepen-
IDD, ISS Supply Current, VDD or VSS Pins ± 30 mA dent of the supply voltage.
Unused inputs must always be tied to an
PD Power Dissipation, per Package† 500 mW appropriate logic voltage level (e.g., either V SS
Tstg Storage Temperature – 65 to + 150 C or VDD), except for inputs with pull–up devices.
Unused outputs must be left open.
TL Lead Temperature, 1 mm from Case for 260 C
10 seconds
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
†Power Dissipation Temperature Derating:
Plastic DIP: – 12 mW/ C from 65 to 85 C
SOG Package: – 7 mW/ C from 65 to 85 C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

– 40 C 25 C 85 C
VDD
Symbol Parameter Test Condition V Min Max Min Max Min Max Unit
VDD Power Supply Voltage – 3 9 3 9 3 9 V
Range
Iss Dynamic Supply Current fin = OSCin = 10 MHz, 3 – 3.5 – 3 – 3 mA
1 V p–p AC coupled sine 5 – 10 – 7.5 – 7.5
wave 9 – 30 – 24 – 24
R = 128, A = 32, N = 128
ISS Quiescent Supply Current Vin = VDD or VSS 3 – 800 – 800 – 1600 µA
(not including pull–up Iout = 0 µA 5 – 1200 – 1200 – 2400
current component) 9 – 1600 – 1600 – 3200
Vin Input Voltage – f in, OSCin Input AC coupled sine wave – 500 – 500 – 500 – mV p–p
VIL LowLevel Input V oltage Vout 2.1 V Input DC 3 – 0 – 0 – 0 V
– f in, OSCin Vout 3.5 V coupled 5 – 0 – 0 – 0
Vout 6.3 V square wave 9 – 0 – 0 – 0
VIH High–Level Input Voltage Vout 0.9 V Input DC 3 3.0 – 3.0 – 3.0 – V
– f in, OSCin Vout 1.5 V coupled 5 5.0 – 5.0 – 5.0 –
Vout 2.7 V square wave 9 9.0 – 9.0 – 9.0 –
VIL Low–Level Input Voltage 3 – 0.9 – 0.9 – 0.9 V
– except f in, OSCin 5 – 1.5 – 1.5 – 1.5
9 – 2.7 – 2.7 – 2.7
VIH High–Level Input Voltage 3 2.1 – 2.1 – 2.1 – V
– except f in, OSCin 5 3.5 – 3.5 – 3.5 –
9 6.3 – 6.3 – 6.3 –
Iin Input Current (fin, OSCin) Vin = VDD or VSS 9 ±2 ± 50 ±2 ± 25 ±2 ± 22 µA
IIL Input Leakage Current Vin = VSS 9 – – 0.3 – – 0.1 – – 1.0 µA
(Data, CLK, ENB –
without pull–ups)
IIH Input Leakage Current (all Vin = VDD 9 – 0.3 – 0.1 – 1.0 µA
inputs except fin, OSCin)
(continued)

ML1451xx LANSDALE Semiconductor, Inc.
DC ELECTRICAL CHARACTERISTICS (continued)

– 40 C 25 C 85 C
VDD
IIL Pull–up Current (all inputs Vin = VSS 9 – 20 – 400 – 20 – 200 – 20 – 170 µA
with pull–ups)
Cin Input Capacitance – – 10 – 10 – 10 pF
VOL Low–Level Output Iout 0 µA 3 – 0.9 – 0.9 – 0.9 V
Voltage – OSCout Vin = VDD 5 – 1.5 – 1.5 – 1.5
9 – 2.7 – 2.7 – 2.7
VOH High–Level Output Iout 0 µA 3 2.1 – 2.1 – 2.1 – V
Voltage – OSCout Vin = VSS 5 3.5 – 3.5 – 3.5 –
9 6.3 – 6.3 – 6.3 –
VOL Low–Level Output Iout 0 µA 3 – 0.05 – 0.05 – 0.05 V
Voltage – Other Outputs 5 – 0.05 – 0.05 – 0.05
9 – 0.05 – 0.05 – 0.05
VOH High–Level Output Iout 0 µA 3 2.95 – 2.95 – 2.95 – V
Voltage – Other Outputs 5 4.95 – 4.95 – 4.95 –
9 8.95 – 8.95 – 8.95 –
V(BR)DSS Drain–to–Source Rpull–up = 4.7 kΩ – 15 – 15 – 15 – V
Breakdown Voltage –
SW1, SW2
IOL Low–Level Sinking Vout = 0.3 V 3 1.30 – 1.10 – 0.66 – mA
Current – MC Vout = 0.4 V 5 1.90 – 1.70 – 1.08 –
Vout = 0.5 V 9 3.80 – 3.30 – 2.10 –
IOH High–Level Sourcing Vout = 2.7 V 3 – 0.60 – – 0.50 – – 0.30 – mA
Current – MC Vout = 4.6 V 5 – 0.90 – – 0.75 – – 0.50 –
Vout = 8.5 V 9 – 1.50 – – 1.25 – – 0.80 –
Current – LD Vout = 0.4 V 5 0.64 – 0.51 – 0.36 –
Vout = 0.5 V 9 1.30 – 1.00 – 0.70 –
Current – LD Vout = 4.6 V 5 – 0.64 – – 0.51 – – 0.36 –
Vout = 8.5 V 9 – 1.30 – – 1.00 – – 0.70 –
Current – SW1, SW2 Vout = 0.4 V 5 1.50 – 0.90 – 0.45 –
Vout = 0.5 V 9 3.50 – 2.10 – 1.05 –
Current – Other Outputs Vout = 0.4 V 5 0.64 – 0.51 – 0.36 –
Vout = 0.5 V 9 1.30 – 1.00 – 0.70 –
Current – Other Outputs Vout = 4.6 V 5 – 0.64 – – 0.51 – – 0.36 –
Vout = 8.5 V 9 – 1.30 – – 1.00 – – 0.70 –
IOZ Output Leakage Current – Vout = VDD or VSS 9 – ± 0.3 – ± 0.1 – ± 1.0 µA
PDout Output in Off State
IOZ Output Leakage Current – Vout = VDD or VSS 9 – ± 0.3 – ± 0.1 – ± 3.0 µA
SW1, SW2 Output in Off State
Cout Output Capacitance – PDout – Three–State – – 10 – 10 – 10 pF
PDout

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 10 ns)

VDD Guaranteed Limit Guaranteed Limit
Symbol Parameter V 255C – 40 to 85°C Unit
tPLH, tPHL Maximum Propagation Delay, fin to MC 3 110 120 ns
(Figures 1 and 4) 5 60 70
9 35 40
tPHL Maximum Propagation Delay, ENB to SW1, SW2 3 160 180 ns
9 50 60
tw Output Pulse Width, φR, φV, and LD with fR in Phase with fV 3 25 to 200 25 to 260 ns
(Figures 2 and 4) 5 20 to 100 20 to 125
9 10 to 70 10 to 80
tTLH Maximum Output Transition Time, MC 3 115 115 ns
9 40 60
tTHL Maximum Output Transition Time, MC 3 60 70 ns
9 30 38
tTLH, tTHL Maximum Output Transition Time, LD 3 180 200 ns
(Figures 3 and 4) 5 90 120
9 70 90
tTLH, tTHL Maximum Output Transition Time, Other Outputs 3 160 175 ns
(Figures 3 and 4) 5 80 100
9 60 65
SWITCHING WAVEFORMS
VDD
INPUT 50%
– V SS tw
tPLH tPHL
φR, φV, LD* 50%
OUTPUT 50%
* fR in phase with fV.
Figure 1. Figure 2.
tTLH tTHL
ANY 90%
OUTPUT
10%
Figure 3.
VDD
TEST POINT TEST POINT
OUTPUT OUTPUT 15 kΩ
DEVICE DEVICE
UNDER CL* UNDER CL*
TEST TEST
* Includes all probe and fixture capacitance. * Includes all probe and fixture capacitance.
Figure 4. Test Circuit Figure 5. Test Circuit

TIMING REQUIREMENTS (Input tr = tf = 10 ns unless otherwise indicated)

VDD Guaranteed Limit Guaranteed Limit
Symbol Parameter V 25 C – 40 to 85 C Unit
fclk Serial Data Clock Frequency, Assuming 25% Duty Cycle 3 DC to 5.0 DC to 3.5 MHz
NOTE: Refer to CLK t w(H) below 5 DC to 7.1 DC to 7.1
(Figure 6) 9 DC to 10 DC to 10
tsu Minimum Setup Time, Data to CLK 3 30 30 ns
(Figure 7) 5 20 20
9 18 18
th Minimum Hold Time, CLK to Data 3 40 40 ns
(Figure 7) 5 20 20
9 15 15
tsu Minimum Setup Time, CLK to ENB 3 70 70 ns
(Figure 7) 5 32 32
9 25 25
trec Minimum Recovery Time, ENB to CLK 3 5 5 ns
(Figure 7) 5 10 10
9 20 20
tw(H) Minimum Pulse Width, CLK and ENB 3 50 70 ns
(Figure 6) 5 35 35
9 25 25
tr, tf Maximum Input Rise and Fall Times – Any Input 3 5 5 µs
(Figure 8) 5 4 4
9 2 2
SWITCHING WAVEFORMS
– VDD
tw(H) DATA 50%
– VDD VSS
CLK, tsu
50%
ENB th
1 * VSS
– VDD
4 fclk CLK 50% LAST FIRST
CLK CLK VSS
*Assumes 25% Duty Cycle.
tsu trec
– VDD
Figure 6. ENB 50%
VSS
PREVIOUS
DATA
tr tf
LATCHED
ANY 90% – VDD
OUTPUT
10% VSS Figure 7.
Figure 8.

FREQUENCY CHARACTERISTICS (Voltages References to VSS, CL = 50 pF, Input tr = tf =10 ns unless otherwise indicated)
– 40 C 25 C 85 C
VDD
fi Input Frequency R ≥ 8, A ≥ 0, N ≥ 8 3 – 6 – 6 – 6 MHz
(fin, OSCin) Vin = 500 mV p–p 5 – 15 – 15 – 15
AC coupled sine wave 9 – 15 – 15 – 15
R ≥ 8, A ≥ 0, N ≥ 8 3 – 12 – 12 – 7 MHz
Vin = 1 V p–p AC coupled 5 – 22 – 20 – 20
sine wave 9 – 25 – 22 – 22
R ≥ 8, A ≥ 0, N ≥ 8 3 – 13 – 12 – 8 MHz
Vin = VDD to VSS 5 – 25 – 22 – 22
DC coupled square wave 9 – 25 – 25 – 25
NOTE: Usually, the PLL's propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency limit of the system.
The upper frequency limit is found with the following formula: f = P / (tP + tset) where f is the upper frequency in Hz, P is the lower of the dual
modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and t set is the prescaler setup time in seconds.
For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup time is 16 ns. Thus, if the 64/65
ratio is utilized, the upper frequency limit is f = P / (tP + tset) = 64/(70 + 16) = 744 MHz.
fR VH
REFERENCE
OSC ÷ R VL
fV VH
FEEDBACK
(fin ÷ N) VL
VH
*
PDout HIGH IMPEDANCE
VL
VH
φR
VL
VH
φV
VL
VH
LD
VL
VH = High Voltage Level.

VL = Low Voltage Level.
* At this point, when both fR and fV are in phase, the output is forced to near mid–supply.
NOTE: The PDout generates error pulses during out–of–lock conditions. When locked in phase and frequency the output is high
and the voltage at this pin is determined by the low–pass filter capacitor.
Figure 9. Phase Detector/Lock Detector Output Waveforms

DESIGN CONSIDERATIONS
PHASE–LOCKED LOOP – LOW–PASS FILTER DESIGN
A) PDout KφKVCO
VCO ωn =
R1 NR1C
φR –
C Nωn
ζ =
φV – 2KφKVCO
1
F(s) =
R1sC + 1
B) PDout VCO KφKVCO

R1 ωn =
NC(R1 + R2)
φR – R2
N
φV – C ζ = 0.5 ωn ( R2C + )
KφKVCO
R2sC + 1
F(s) =
(R1 + R2)sC + 1
R2
C) PDout – KφKVCO
ωn =
R1 C NCR1
φR _
ωnR2C
φV +A VCO
ζ =
R1 2
R2 ASSUMING GAIN A IS VERY LARGE, THEN:
C R2sC + 1
F(s) =
R1sC
NOTE: Sometimes R1 is split into two series resistors, each R1 ÷ 2. A capacitor C C is then placed from the midpoint to ground to further
filter φV and φR. The value of C C should be such that the corner frequency of this network does not significantly affect ωn.
The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
DEFINITIONS:
N = Total Division Ratio in feedback loop
Kφ (Phase Detector Gain) = VDD/4π for PDout
Kφ (Phase Detector Gain) = VDD/2π for φV and φR
2π∆fVCO
KVCO (VCO Gain) =
∆VVCO
for a typical design wn (Natural Frequency) 2πfr
(at phase detector input).
10
Damping Factor: ζ ≅ 1
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.

CRYSTAL OSCILLATOR CONSIDERATIONS

The following options may be considered to provide a refer- CinCout
ence frequency to Motorola's or Lansdale’s CMOS frequency CL = + Ca + Co + C1 • C2
Cin + Cout C1 + C2
synthesizers.
where
Use of a Hybrid Crystal Oscillator Cin = 5 pF (see Figure 11)
Cout = 6 pF (see Figure 11)
Commercially available temperature–compensated crystal Ca = 1 pF (see Figure 11)
oscillators (TCXOs) or crystal–controlled data clock oscilla- CO = the crystal's holder capacitance
tors provide very stable reference frequencies. An oscillator (see Figure 12)
capable of sinking and sourcing 50 µA at CMOS logic levels C1 and C2 = external capacitors (see Figure 10)
may be direct or DC coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct–coupled
Ca
square wave having a rail–to–rail (VDD to VSS) voltage
swing. If the oscillator does not have CMOS logic levels on the
outputs, capacitive or AC coupling to OSCin may be used. Cin Cout
OSCout, an unbuffered output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Elec-
Figure 11. Parasitic Capacitances of the Amplifier
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
RS LS CS
Design an Off–Chip Reference
1 2 1 2
The user may design an off–chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the ML12061 MECL device. The reference signal from the CO
MECL device is AC coupled to OSCin. For large amplitude
signals (standard CMOS logic levels), DC coupling is used. 1 Re Xe 2
OSCout, an unbuffered output, should be left floating. In gen-
eral, the highest frequency capability is obtained with a di-
rect–coupled square wave having rail–to–rail voltage swing. NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Use of the On–Chip Oscillator Circuitry
Figure 12. Equivalent Crystal Networks
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source fre-
quency. A fundamental mode crystal, parallel resonant at the The oscillator can be “trimmed” on–frequency by making a
desired operating frequency, should be connected as shown in portion or all of C1 variable. The crystal and associated com-
Figure 10. ponents must be located as close as possible to the OSCin and
OSCout pins to minimize distortion, stray capacitance, stray
inductance, and startup stabilization time. In some cases, stray
Rf FREQUENCY capacitance should be added to the value for Cin and Cout.
SYNTHESIZER Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 12. The drive level specified by the crys-
tal manufacturer is the maximum stress that a crystal can with-
stand without damage or excessive shift in frequency. R1 in
OSCin
R1*
OSCout Figure 10 limits the drive level. The use of R1 may not be nec-
essary in some cases (i.e., R1 = 0 Ω).
To verify that the maximum DC supply voltage does not
C1 C2 overdrive the crystal, monitor the output frequency as a func-
tion of voltage at OSCout. (Care should be taken to minimize
loading.) The frequency should increase very slightly as the
* May be deleted in certain cases. See text.
DC supply voltage is increased. An overdriven crystal will
Figure 10. Pierce Crystal Oscillator Circuit decrease in frequency or become unstable with an increase in
supply voltage. The operating supply voltage must be reduced
For VDD = 5.0 V, the crystal should be specified for a loading or R1 must be increased in value if the overdriven condition
capacitance, CL, which does not exceed 32 pF for frequencies to exists. The user should note that the oscillator start–up time is
approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to proportional to the value of R1.
15 MHz, and 10 pF for higher frequencies. These are guidelines Through the process of supplying crystals for use with
that provide a reasonable compromise between IC capacitance, CMOS inverters, many crystal manufacturers have developed
drive capability, swamping variations in stray and IC input/output expertise in CMOS oscillator design with crystals. Discussions
capacitance, and realistic CL values. The shunt load capacitance, with such manufacturers can prove very helpful (see Table 1).
CL, presented across the crystal can be estimated to be:

Table 1. Partial List of Crystal Manufacturers
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Lansdale and Motorola do not recommend one supplier over another and in no
way suggests that this is a complete listing of crystal manufacturers.
RECOMMENDED READING DESIGN GUIDELINES

Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp. The system total divide value, N total (NT) will be dictated
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and by the application:
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2 N is the number programmed into the ÷ N counter, A is the
Feb.,1969.
D. Kemper, L. Rosine, “Quartz Crystals for frequency into the prescaler
NT = =N• P+A
FrequencyControl”, Electro–Technology, June, 1969. frequency into the phase detector
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966. number programmed into the ÷ A counter, P and P + 1 are the
two selectable divide ratios available in the dual–modulus
DUAL–MODULUS PRESCALING prescalers. To have a range of NT values in sequence, the
÷ A counter is programmed from zero through P – 1 for a par-
OVERVIEW ticular value N in the ÷ N counter. N is then incremented to N
+ 1 and the ÷ A is sequenced from 0 through P – 1 again.
The technique of dual–modulus prescaling is well estab- There are minimum and maximum values that can be
lished as a method of achieving high performance frequency achieved for NT. These values are a function of P and the size
synthesizer operation at high frequencies. Basically, the of the ÷ N and ÷ A counters.
approach allows relatively low–frequency programmable coun- The constraint N ≥ A always applies. If Amax = P – 1, then
ters to be used as high–frequency programmable counters with Nmin ≥ P – 1. Then NT min = (P – 1) P + A or (P – 1) P since
speed capability of several hundred MHz. This is possible with A is free to assume the value of 0.
out the sacrifice in system resolution and performance that
results if a fixed (single–modulus) divider is used for the NTmax = Nmax • P + Amax
prescaler. To maximize system frequency capability, the dual–modulus
In dual–modulus prescaling, the lower speed counters must prescaler output must go from low to high after each group of
be uniquely configured. Special control logic is necessary to P or P + 1 input cycles. The prescaler should divide by P when
select the divide value P or P + 1 in the prescaler for the its modulus control line is high and by P + 1 when its MC is
required amount of time (see modulus control definition). low.
Lansdale's dual–modulus frequency synthesizers contain this For the maximum frequency into the prescaler (fVCOmax), the
feature and can be used with a variety of dual–modulus- value used for P must be large enough such that:
prescalers to allow speed, complexity and cost to be tailored to 1.fVCOmax divided by P may not exceed the frequency
the system requirements. Prescalers having P, P + 1 divide val- capability of f in (input to the ÷ N and ÷ A counters).
ues in the range of ÷ 3/÷4 to ÷128/÷ 129 can be controlled by 2.The period of fVCO divided by P must be greater than the
most Lansdale frequency synthesizers. sum of the times:
Several dual–modulus prescaler approaches suitable for use a. Propagation delay through the dual–modulus prescaler.
with the MC145152 (Motorola), ML145156, or ML145158 are: b. Prescaler setup or release time relative to its MC signal.
c. Propagation time from f in to the MC output for the
ML12009 ÷ 5/÷ 6 440 MHz frequency synthesizer device.
ML12011 ÷ 8/÷ 9 500 MHz A sometimes useful simplification in the programming code
ML12013 ÷ 10/÷ 11 500 MHz can be achieved by choosing the values for P of 8, 16, 32, or
ML12015 ÷ 32/÷ 33 225 MHz 64. For these cases, the desired value of NT results when NT
ML12016 ÷ 40/÷ 41 225 MHz in binary is used as the program code to the ÷ N and ÷ A coun-
ML12017 ÷ 64/÷ 65 225 MHz ters treated in the following manner:
ML12018 ÷ 128/÷ 129 520 MHz
MC12028A ÷ 32/33 or ÷ 64/65 1.1 GHz 1.Assume the ÷A counter contains “a” bits where 2a ≥P.
MC12034 ÷32/33 or ÷64/65 2.0 GHz 2.Always program all higher order ÷A counter bits above
MC12038 ÷127/128 or ÷255/256 1.1 GHz “a” to 0.
ML12052 ÷ 64/65 or ÷ 128/129 1.1 GHz
ML12054A ÷ 64/65 or ÷ 128/129 2.0 GHz

3. Assume the ÷N counter and the ÷A counter (with all the correspond to the LSB of ÷ A. The system divide value, NT,
higher order bits above “a” ignored) combined into a single now results when the value of NT in binary is used to program
binary counter of n + a bits in length (n = number of divider the “new” n + a bit counter.
stages in the ÷N counter). The MSB of this “hypothetical” By using the two devices, several dual–modulus values are
counter is to correspond to the MSB of ÷ N and the LSB is to achievable (shown in Figure 13).
MC
DEVICE A DEVICE B
DEVICE
B
DEVICE A ML12009 ML12011 ML12013
MC10131 ÷ 20/÷ 21 ÷ 32/÷ 33 ÷ 40/÷ 41
MC10138 ÷ 50/÷ 51 ÷ 80/÷ 81 ÷ 100/÷ 101
NOTE: ML12009, ML12011, and ML12013 are pin equivalent.

ML12015, ML12016, and ML12017 are pin equivalent.
Figure 13. Dual–Modulus Values

OUTLINE DIMENSIONS
P DIP 16 = EP
PLASTIC DIP
CASE 648–08
(ML145157EP, ML145158EP)
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0° 10° 0° 10°
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01
P DIP 18 = VP
PLASTIC DIP
CASE 707–02
(ML145155VP)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
18 10 2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
MILLIMETERS INCHES
A DIM MIN MAX MIN MAX
A 22.22 23.24 0.875 0.915
L B 6.10 6.60 0.240 0.260
C C 3.56 4.57 0.140 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
G 2.54 BSC 0.100 BSC
K H 1.02 1.52 0.040 0.060
N J 0.20 0.30 0.008 0.012
J
F D M K 2.92 3.43 0.115 0.135
SEATING L 7.62 BSC 0.300 BSC
H G PLANE M 0° 15° 0° 15°
N 0.51 1.02 0.020 0.040

OUTLINE DIMENSIONS
P DIP 20 = RP
PLASTIC DIP
CASE 738–03
(ML145156RP)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
20 11 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEAD WHEN
1 10 FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
C L FLASH.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
-T- K C 0.150 0.180 3.81 4.57
SEATING D 0.015 0.022 0.39 0.55
PLANE M E 0.050 BSC 1.27 BSC
F 0.050 0.070 1.27 1.77
E N G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
G F J 20 PL 0.110 0.140 2.80 3.55
K
L 0.300 BSC 7.62 BSC
D 20 PL 0.25 (0.010) M T B M
0° 15° 0° 15°
M
0.25 (0.010) M T A M N 0.020 0.040 0.51 1.01
SOG 20 = -6P
SOG PACKAGE
CASE 751D–04
(MC145155-6P, MC145156-6P)
–A– NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
20 11 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
–B– 10X P (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.010 (0.25) M B M
DAMBAR PROTRUSION. ALLOW ABLE
DAMBAR PROTRUSION SHALL BE 0.13
1 10 (0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
20X D MILLIMETERS INCHES

J DIM MIN MAX MIN MAX
0.010 (0.25) M T A S B S A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
F D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
R X 45° J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 10.05 10.55 0.395 0.415
C R 0.25 0.75 0.010 0.029
–T– SEATING
PLANE
18X G M
K

OUTLINE DIMENSIONS
P DIP 28 = YP
PLASTIC DIP
CASE 710–02
(ML145151YP, ML145152YP)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
28 15 2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
B MOLD FLASH.
MILLIMETERS INCHES
1 14 DIM MIN MAX MIN MAX
A 36.45 37.21 1.435 1.465
A C L B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
N F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
H 1.65 2.16 0.065 0.085
J 0.20 0.38 0.008 0.015
H G J K 2.92 3.43 0.115 0.135
K M
F D SEATING
L 15.24 BSC 0.600 BSC
M 0° 15° 0° 15°
PLANE
N 0.51 1.02 0.020 0.040
SO 28W = -6P
SOG PACKAGE
CASE 751F–04
(ML145151-6P, ML145152–6P)
-A-
28 15 NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X P ANSI Y14.5M, 1982.
-B- 0.010 (0.25) M B M 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
1 14 4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
28X D DAMBAR PROTRUSION SHALL BE 0.13
0.010 (0.25) M T A S B S M (0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
R X 45° CONDITION.
MILLIMETERS INCHES
-T- C DIM MIN MAX MIN MAX
A 17.80 18.05 0.701 0.711
-T- B 7.40 7.60 0.292 0.299
26X G SEATING C 2.35 2.65 0.093 0.104
PLANE
D 0.35 0.49 0.014 0.019
K
F F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
J 0.23 0.32 0.009 0.013
J K 0.13 0.29 0.005 0.011
M 0° 8° 0° 8°
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

OUTLINE DIMENSIONS
SOG 20 = -5P
SOG PACKAGE
CASE 751G–02
(ML145157-5P, ML145158-5P)
–A–
16 9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B– 8X P 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
0.010 (0.25) M B M
PROTRUSION.
1 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
J PROTRUSION. ALLOW ABLE DAMBAR
16X D PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
0.010 (0.25) M T A S B S MATERIAL CONDITION.
F MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 10.15 10.45 0.400 0.411
R X 45° B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
C F 0.50 0.90 0.020 0.035
–T– G 1.27 BSC 0.050 BSC
SEATING M J 0.25 0.32 0.010 0.012
14X G K PLANE K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. Typical ” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.

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ML145151 ML145152 ML145155 ML145156 ML145157 ML145158: PLL Frequency Synthesizer Family - CMOS

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ML145151 ML145152 ML145155 ML145156 ML145157 ML145158: PLL Frequency Synthesizer Family - CMOS

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ML145151 ML145156

Page 1 of 35 www.lansdale.com Issue A

Legacy Device: Motorola/Freescale MC145151

• Operating Temperature Range: TA = – 40 to 85°C SO 28W = -6P

• 3.0 to 9.0 V Supply Range CROSS REFERENCE/ORDERING INFORMATION

Page 2 of 35 www.lansdale.com Issue A

ML145151 BLOCK DIAGRAM

fin 14–BIT ÷ N COUNTER

Page 3 of 35 www.lansdale.com Issue A

OSCin OSCout fin RA2 RA1 RA0

Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz

LOCK DETECT SIGNAL TRANSMIT: 440.0 – 470.0 MHz

ML145151 Data Sheet Continued on Page 23

Page 4 of 35 www.lansdale.com Issue A

Legacy Device: Motorola/Freescale MC145152

Page 5 of 35 www.lansdale.com Issue A

ML145152 BLOCK DIAGRAM

6–BIT ÷ A COUNTER 10–BIT ÷ N COUNTER

Page 6 of 35 www.lansdale.com Issue A

“1” “1” “1” 150 – 175 MHz

OSCout RA2 RA1 RA0 LD R1

CHANNEL PROGRAMMING ML12017

Figure 1. Synthesizer for Land Mobile Radio VHF Bands

Page 7 of 35 www.lansdale.com Issue A

RECEIVER 2ND L.O.

Figure 2. 666–Channel, Computer–Controlled, Mobile Radiotelephone Synthesizer

ML145152 Data Sheet Continued on Page 23

Page 8 of 35 www.lansdale.com Issue A

Legacy Device: Motorola/Freescale MC145155-2

• 3.0 to 9.0 V Supply Range

VSS 7 12 ENB VSS 7 14 SW1

Page 9 of 35 www.lansdale.com Issue A

ML145155 BLOCK DIAGRAM

ENB LATCH LATCH SW1

Page 10 of 35 www.lansdale.com Issue A

DATA CLK ENB

Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface

Page 11 of 35 www.lansdale.com Issue A

Figure 2. AM/FM Radio Synthesizer

Page 12 of 35 www.lansdale.com Issue A

Legacy Device: Motorola/Freescale MC145156-2

and latch circuitry for accepting serial input data.

Page 13 of 35 www.lansdale.com Issue A

REFout CONTROL LOGIC fR PHASE

fin 7–BIT ÷ A COUNTER 10–BIT ÷ N COUNTER PHASE φV

ENB ÷ A COUNTER LATCH ÷ N COUNTER LATCH LATCH SW1

PIN DESCRIPTIONS A COUNTER BITS N COUNTER BITS

Page 14 of 35 www.lansdale.com Issue A

φR, φV SW1, SW2

Page 15 of 35 www.lansdale.com Issue A

+V OSCin OSCout RA2 RA1 RA0 LD SW1 SW2 AM B +

KEY– CMOS MPU/MCU

R/T CMOS MPU/MCU

ML12016 (NOTES 2 AND 4)

ML145156 Data Sheet Continued on Page 23

Page 16 of 35 www.lansdale.com Issue A

Legacy Device: Motorola/Freescale MC145157-2

• Operating Temperature Range: TA = – 40 to 85°C SOG 16 = -5P