SERIES 20000 Legacy: Service Manual
SERIES 20000 Legacy: Service Manual
SERIES 20000 Legacy: Service Manual
™* ®
SERIES 20000 LEGACY
SERVICE MANUAL
ALCON SURGICAL
15800 Alton Parkway
Irvine, California 92618-3818 U.S.A.
Telephone: 949/753-1393
800/832-7827
FAX: 949/753-6614
IMPORTANT NOTICE
Equipment improvement is an on-going process and, as such, changes may be made to the equipment after
this manual is printed. Accordingly, Alcon Surgical makes no warranties, expressed or implied, that the
information contained in this service manual is complete or accurate. It is understood that if this manual is
used to perform service on the equipment by other than trained personnel, the user assumes all risks in the
use of this manual.
CAUTION
Pay close attention to warnings and cautions in this manual. Warnings are written to protect individuals
from bodily injury. Cautions are written to protect the instrument from damage.
Alcon Surgical
Technical Services Group
PO BOX 19587
Irvine, CA, USA 92623-9587
All rights reserved. No part of this manual may be reproduced, transmitted, or stored in a retrieval system, in
any form or by any means; photocopying, electronic, mechanical, recording, or otherwise; without prior
written permission from Alcon Surgical.
ii 906-2000-501
SERIES 20000™* LEGACY®
SERVICE MANUAL
SERIES 20000™* LEGACY®
906-2000-501
7/98 D ECN 34142- Removed Service Test Procedure from Section Four. All
pages, except engineering drawings in Sections Six & Seven, changed to
update trademarks and area codes.
906-2000-501 iii
SERIES 20000™* LEGACY®
TABLE OF CONTENTS
TOPIC PAGE #
Important Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Manual Revision Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
iv 906-2000-501
SERIES 20000™* LEGACY®
TABLE OF CONTENTS
TOPIC PAGE #
906-2000-501 v
SERIES 20000™* LEGACY®
LIST OF ILLUSTRATIONS
TITLE PAGE #
vi 906-2000-501
SERIES 20000™* LEGACY®
SECTION ONE
GENERAL INFORMATION
Alcon Surgical’s SERIES 20000™* LEGACY® Section Seven-Parts Lists and Drawings
(STTL) is a sophisticated ophthalmic surgical This section contains parts lists and engineering
instrument manufactured to be durable, reliable, documentation for each major assembly.
safe and easy to operate. This state-of-the-art
instrument has been developed to be user friendly; it Section Eight-Additional Information
combines hardware that is easy to install and This section is for the user of this manual to store
maintain along with computer software that any additional information pertaining to this system.
increases the effectivity of the user.
REFERENCE DOCUMENTS
ABOUT THIS MANUAL... Although this manual provides the necessary
This manual is divided into eight sections as information for maintaining optimum performance
follows: of the STTL, it does not contain all of the operating
procedures or functional descriptions contained in
Section One-General Information the Operator's Manual (PN 905-2000-501). In
This section gives a general description of the STTL addition, the Warnings and Cautions in the
features and components. Also included is an Operator's Manual also apply for this Service
unpacking and installation procedure. Manual. The Operator's Manual supplements
information provided in this manual and should be
Section Two-Theory of Operation available on-site with the system.
This section gives a detailed description of how the
STTL operates starting at the system level and
working down to the PCB (Printed Circuit Board) If you have any questions or require additional
level. Detailed block diagrams are provided at the information, please contact your local Service
end of this section. Representative or the Technical Services
Department at:
Section Three-Parts Location and Disassembly
This section contains parts location diagrams along ALCON SURGICAL
with field level disassembly procedures. 15800 Alton Parkway
Irvine, CA 92718
Section Four-Service Test Procedure (949) 753-1393
This section of the service manual is reserved for (800) 832-7827
storage of the STTL Service Test Procedure and
checklist. The Service Test Procedure is used to test If you are located outside the United States, please
the STTL after repair or preventive maintenance to contact your local authorized Alcon Surgical
ensure the system performs within specifications. distributor.
This procedure is not included with the manual and
is available to trained personnel only. CAUTION
Federal Law restricts this device to sale by or on
Section Five-Maintenance & Troubleshooting the order of a physician.
This section contains system maintenace procedures
and troubleshooting information. END USER LICENSE AGREEMENT:
This product contains software licensed from
Section Six-Schematics Microsoft Corporation.
This section contains the system interconnect
diagram, PCB assembly & schematic drawings, and
cable drawings.
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SERIES 20000™* LEGACY®
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ELECTRICAL IV POLE
The system will auto-select between the following Bottle height at retraction .............................. .2 cm ± 1
voltage: Bottle height when fully raised ..................... 78 cm ± 1
100 Vac nominal ( 88-110 Vac), 47-63 Hz, single ø Bottle height at power-up (default) ............... 65 cm ± 1
120 Vac nominal (102-132 Vac), 47-63 Hz, single ø IV Pole Speed ....................................... 10 ± 2 cm/sec
220 Vac nominal (176-242 Vac), 47-63 Hz, single ø
240 Vac nominal (204-270 Vac), 47-63 Hz, single ø
VACUUM ACCURACY
ACTUAL VACUUM DISPLAYED VACUUM
Maximum power ....................................... ≤ 523 Watts
0 mmHg ................................................... 0 ± 2 mmHg
50 mmHg ............................................ 50 ± 2.5 mmHg
LEAKAGE CURRENT 200 mmHg ......................................... 200 ± 10 mmHg
< 50 µA @120 VAC, per UL544 (includes power cord) 400 mmHg ......................................... 400 ± 20 mmHg
< 100µA @120 VAC, per UL2601 (includes power cord) 500 mmHg ......................................... 500 ± 25 mmHg
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SERIES 20000™* LEGACY®
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REMOTE PANEL/SURGEON
CONTROL SENSOR (6)
(11)
SECONDARY
BOTTLE HEIGHT PARAMETERS
DISPLAY WINDOW
(12) (10)
Panel
BOTTLE HEIGHT 1 PARAMETER
ADJUSTMENT U/S: Pulse ? Surgeon ADJUSTMENT
ARROWS ARROWS
(12) (4)
Asp Rate
U/S: Power %
100 100 ccpm 50 PARAMETER
PARAMETER Max Limit Max Limit ADJUSTMENT
ADJUSTMENT Pulse Rate ARROWS
Vac Level mmHg
ARROWS (4)
(4)
400 400 pps 15
Max Limit Max Limit
MEMORY KEYS
Phaco Pulse I/A MEMORY (16)
U/S TIME
DISPLAY Irr Hydro U/S I/A Vit Coag Custom MODE WINDOW
(13) (3B)
U/S TIME
RESET BUTTON
(15) PRIMARY MODE
SELECTION BUTTONS
(3A)
TEST BUTTON
(17)
STAND-BY
POWER SWITCH
(2)
CASSETTE BEZEL
SPEAKER
(18)
3A. Primary Mode Selection Buttons - These • HYDRO - Used to activate the
seven push-buttons allow selection of HYDROSONICS™* mode which allows
operating modes. They are single-condition the surgeon to use the Auto HydroSonics
(press to turn on) and also allow the operator handpiece.
to scroll through the sub-modes. (Access to
modes is also available by pressing the • U/S - Used to activate the ultrasound
associated symbol on the touch screen or on system while performing emulsification
the remote control.) procedures. There are three submodes of
the U/S mode: Phaco, Pulse, and U/S I/A.
• IRR - Used to select one of two Irrigation US:Phaco is the default mode.
submodes (free flow and footswitch).
IRRIGATION:FOOTSWITCH is the • I/A - Used to activate the Irrigation/
default mode. Aspiration system. There are three
submodes of the I/A mode: I/A Min, I/A
Max, and CapVac. I/A Max is the default
mode.
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SERIES 20000™* LEGACY®
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8. System Status Indicators - Alert the operator 13. U/S Time Display - Records the amount of
to conditions in the unit which occur under U/S power time elapsed during surgery. Time
normal operation (each word illuminates in is given in minutes, to one decimal place, to a
the text window in a specific color): maximum of 30 minutes. U/S power elapsed
• Vent - Appears when the venting system time is retained until the RESET button is
opens and the footswitch goes from pressed, or until the system is turned off.
position 2 to position 1 (fuchsia).
• Reflux - Appears when the footswitch 14. Average U/S Power - Is the reading of the
reflux function is operational (red). average U/S power that was applied. Both U/S
• Occlusion - Appears when the aspiration Time and Average U/S Power Display are
line becomes occluded, the system has automatically accumulated whenever
reached the maximum preset vacuum Ultrasound is in use. To obtain cumulative
limit, and the pump stops (black). dissipated energy (CDE), multiply U/S time
by the average U/S power.
9. Primary Parameters Window - Displays up to
two primary parameters for a selected mode CDE = U/S TIME x AVG U/S POWER
(along with the graphical representation of the
data), including maximum limits. When 15. U/S Time Reset Button - Resets U/S Time
primary parameters are not displayed this area (displayed in the U/S Time display window)
is used for user prompts, user display, and and Average Power Display (displayed in the
user data input. Maximum limits can be Text window) to zero.
adjusted for each parameter by using the up
and down arrows. 16. Memory Keys - Used to recall
preprogrammed settings. When the memory
10. Secondary Parameters Window - Displays up key is pressed, a memory menu will
to two additional parameters for a selected temporarily “pop-up” over the secondary
mode, along with the maximum limit value. parameters window. Four programmed
Maximum limits can be adjusted for each memory selections, plus a default setting
parameter by using the up and down arrows. selection, are available. The currently selected
doctor memory and setting will be displayed
11. Remote Control Sensor - Receives remote at the top of the screen.
control inputs. It is located at the top left of
the unit above the bottle height display; no 17. Test Button - Used to access various functions
operator interface is required. such as PRIMING, TUNING, and CLEAN.
The TEST key is not available when in the
12. Bottle Height Display and Controls (Bottle CUSTOM and COAG modes.
Height Adjustment Arrows) - Displays height
of the irrigation bottle in the display window. 18. Speaker - For audible tones; located under the
Below the display are up and down arrows; movable display screen in center of unit.
these raise and lower the irrigation bottle
(from 2 cm to 78 cm), allowing irrigation
pressure to be adjusted. Adjustments can also
be made from the left and right dual pivot
switches on the footswitch, as well as from the
remote control. The irrigation pole is
positioned at 65 cm ±1 at powerup.
CASSETTE HOUSING (see Figure 1-3) CONNECTOR PANEL (see Figure 1-3)
The cassette housing is located on the upper left The Connector Panel is located to the right of the
side of the system. Two factors contribute to fast cassette housing. It provides three self-locking
and easy installation of the cassette: the cassette “smart” electrical connections for U/S handpieces
housing contains all the connections required for the (U/S); two receptacles for bipolar coagulation
standard disposable fluidics Cassette Pak set, and handpieces to accommodate both coaxial and safety
the cassette was designed with an auto-load feature. banana-type connectors (COAG); and one female
luer lock pneumatic connection for the ATIOP and
the HYDROSONICS™* handpieces (VIT).
Additionally, there is one unlabeled connector for
future expansion. Colors and symbols near the
connectors facilitate handpiece identification.
U/S
HUB ROLLER
U/S
U/S
CONNECTOR
PANEL
LATCHING COAG
MECHANISM
COAG
CASSETTE
HOUSING
VIT
1-8 906-2000-501
SERIES 20000™* LEGACY®
AUTOCLAVABLE
INSTRUMENT TRAY TILTABLE,
(7B) ROTATABLE
FRONT PANEL
(6)
I.V. POLE
(11)
HANDLE
(8)
REAR CONNECTOR
PANEL
(2)
TRAY ASSEMBLY
(7A) CORD WRAP
(5)
STORAGE DRAWER
(9)
POWER SUPPLY
PANEL
(1)
FOOTSWITCH BRACKET
(4)
LOCKING WHEEL
MECHANISM
(10)
FOOTSWITCH
FAN FILTER CONNECTOR
(12) (3)
COMMUNICATION
PORTS
4. Footswitch bracket - Used to hold the 8. Handles (2) - One handle is located on the
footswitch when not in use. Located on the front and another is located on the back of the
rear panel, to the left of the cord wrap. unit. Handles should always be used to move
the unit. For greater safety and control, the
5. Cord Wrap - Used to store both the footswitch unit should be pulled, not pushed.
cord and the power supply cord. Located on
the far right of the rear panel, directly above 9. Storage Drawer - Located on the right side of
the power supply. the unit, it can be used to store handpieces and
accessories.
Other Features
10. Locking Wheel Mechanism - Locks are
6. Tiltable, Rotatable Front Panel - Allows easy located on the two front wheels only. The
maneuverability during setup and surgery. wheels should always be locked when the unit
is in use, and unlocked when being moved.
7A. Tray Assembly - Provides a movable
instrument tray within the sterile field. There 11. I.V. Pole - The bottle of irrigating fluid is
is a curved metal rod on the tray arm for a hung from the hook on top of this pole. Used
sterile bag pouch. The tray is capable of to raise and lower the bottle height.
accommodating a variety of system positions
in the operating room environment: right, left, 12. Fan Filter - Located underneath unit, the fan
front and rear of the surgeon as well as the filter removes particles from incoming air
front of the bed. used for cooling components.
1-10 906-2000-501
SERIES 20000™* LEGACY®
Seven different and clearly distinguishable audible The STTL remote control is wireless and can,
frequencies, in conjunction with multiple tones, are therefore, be used in one of two ways: It can be laid
produced by the STTL. into the articulated arm and tray assembly and
operated through the sterile drape supplied in the
TONE TYPE disposable pak. This offers the Scrub Nurse or
VACUUM TONE CONTINUOUS WHEN ASPIRATION assistant access to the controls from the sterile field.
ACTIVE A sterile, sealed pouch (available in the remote
COAGULATION CONTINUOUS WHEN COAGULATION control aseptic transfer packaging) can also be
ACTIVE utilized to maintain the sterile field if the remote is
REFLUX CONTINUOUS WHEN REFLUX ACTIVE used in a hand-held manner. Programmability and
custom user setup features are functions which
OCCLUSION INTERMITTENT BEEPING TONE DURING
OCCLUSION are not accessible from the remote control.
IV POLE CONTINUOUS DURING IV POLE ADJUST
The error message, “REM BAT LO” is displayed in
FTSW IRRIGATION INTERMITTENT the text window on the front panel when the remote
TONE
batteries are low. (The battery compartment on the
FRONT PANEL INTERMITTENT back holds four AA batteries; to replace batteries,
SWITCH
ACTIVATION loosen the captive screw on the compartment door
with a standard screwdriver.)
CONTINUOUS ONE BEEP FOR ACTIVATION,
IRRIGATION TWO FOR DEACTIVATION
(SECONDARY) PARAMETER
IR TRANSMITTER
ADJUSTMENT KEYS
CUSTOM (PROGRAM)
HT
IG
HE
LE
TT
BO
L
RO
NT
CO
ENTER
(PRIMARY) PARAMETER EN
TE
R
ADJUSTMENT KEYS SC
RO
LL
ST
TE
906-2000-501 1-11
SERIES 20000™* LEGACY®
ON ON
Channel A Channel C
S1 S1
1 2 1 2
ON
S1
1 2
ON ON
Channel B Channel D
S1 S1
1 2 1 2
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SERIES 20000™* LEGACY®
1-14 906-2000-501
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SECTION TWO
THEORY OF OPERATION
The theory of operation includes a system overview In some cases, the theory goes into more detail than
and PCB (Printed Circuit Board) level theory. The shown on the block diagrams. When this occurs,
PCB theory is accompanied by detailed block refer to the schematic diagrams located in Section 5.
diagrams located at the end of this chapter on B size Schematics supersede block diagrams in cases of an
pages (11" x 17"). The figure number for these block inconsistency. The following list contains
diagrams is referenced as a foldout (example: Figure nomenclature and symbols used in the block
FO-1). diagrams and schematics.
RESET* - asterisks (*) after signal name indicates logic level low is active.
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SERIES 20000™* LEGACY®
SYSTEM OVERVIEW
The STTL uses a modular design where each major program memory located on the CPU PCB.
function is divided into a separate subsystem which Inter-module connections are made through the
is controlled by the Host System. These subsystems System Backplane PCB which also distributes all
consist of the following: Front Panel, Fluidics Power Supply voltages to the system. The
(includes Anterior Pneumatics module), and Phaco. Multifunction PCB acts as the interface between the
Assemblies outside these subsystems include the subsystems and the Host. The Video PCB provides
Remote Control, I/V Pole, Footswitch, and the display data direct to the Liquid Crystal Display
Power Supply. Figure 2-1 illustrates the subsystem (LCD).
locations. Refer to System Interconnect drawing The Fluidics, Phaco, and Front Panel subsystems
200-0002-801, located in Section Six-Schematics, contain their own microcontrollers (80C196) and
for subsystem/module interconnections. system software that acquire real-time data critcal to
Figure 2-2 is an overall block diagram of the system operation. Each subsystem is a slave to the
STTL. The Host System is the system master and is Host and communicates to the CPU via the
controlled by real-time, event driven, preemptive, Universal Asynchronous Receiver/Transmitter
and finite state system software which is resident in (UART) located on the Multifunction PCB.
L
NE
T PA
ON EM
FR SYST
B
SU
FLU
I
SUB DICS
SYS -
TEM
ANT
PH E
A PNE RIOR LE
SU CO UMA DU
B- ST TIC MO
SY HO TEM
STE S
M SY
PO I/V P
W O
PCB LE
SU ER &
PP MOT
LY OR
IEW W
T V V IE
O N AR
FR RE
Figure 2-1. Subsystem Locations
2-2 906-2000-501
SERIES 20000™* LEGACY®
CAUTERY PCB
COAG
OPT
SWTCH I/V
POLE
MTR PCB
906-2000-501 2-3
SERIES 20000™* LEGACY®
FRONT PANEL,
FLUIDICS, OR PHACO
HOST SYSTEM SUBSYSTEM
SYSTEM BACKPLANE PCB BACKPLANE PCB
+85 V
(PHACO ONLY)
CPU MULTI- CONTROL
PCB FUNCTION +24 V PCB
-15 V
PCB
+15 V
+13.75 V
+12 V
+5 V
RXD
UART TXD 80C196
PEDALUP
TEST*
RESET*
DISABLE
2-4 906-2000-501
SERIES 20000™* LEGACY®
E000H - FFFFH
PROGRAMMABLE 8K x 8
80C196 4000H - BFFFH
SYSTEM STATIC RAM
CONTROL 32K x 8
READY DEVICE
PROCESSOR FLASH
PSD301
EEPROM
12 V
DATA BUS (0-7)
CONTROL
PROGRAM/ERASE
LP2951
STATUS STATUS
PCB REVISION SWITCH
AND
TYPE DETECT P1 (0-2)
CIRCUIT
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SERIES 20000™* LEGACY®
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HOST SYSTEM
The Host System is the control center of the The Host System controls the three subsystems
STTL and consists of the CPU PCB, Multifunction (Front Panel, Fluidics, and Phaco) and has the
PCB, and the Video PCB (see Figure 2-5). These capability of controlling up to eight subsystems. It
PCBs are connected directly to the System operates similarly to any personal computer with the
Backplane PCB and communicate with each other Video and Multifunction PCBs handling the special
via the ISA (Industry Standard Architecture) bus. input/output (I/O) requirements of the system.
FLUIDICS
SUBSYSTEM
CPU VIDEO
UART
PCB PCB
80386DX
PHACO
or
SUBSYSTEM
80486SX FLAT
PANEL
128K
CNTLR MULTI- SPKR
SRAM FUNCTION
PCB IV
1MB POLE
FLASH ASSY
EPROM
FTSW
FLOPPY
DRIVE POWER STAND-BY
SUPPLY SWITCH
906-2000-501 2-7
SERIES 20000™* LEGACY®
CPU PCB
276-230 (no schematic)
The CPU PCB is built around the Intel 80386DX of replacing the EPROMs. The CPU PCB also
(33MHz) or 80486SX (25 MHz) microprocessor contains 128K of battery-backed SRAM to store
operating on a DOS platform. The change from 386 position saved set-ups (doctor’s settings).
to 486 was done to maintain the availability offered
by the latest microprocessor, and does not improve Upon power-up, the CPU performs the Power On
performance of the system. Self-Test (POST) common to all DOS based
systems. After the CPU successfully performs the
The floppy drive is connected directly to the CPU initial boot cycle, the system software is executed
PCB and is used to upgrade system software. System and the system will boot-up in the default mode
software is downloaded to 1 MB of Flash EPROM (IRR:Footswitch mode). If an error occurs during
which acts as a system “hard drive”. This EPROM is the initial boot cycle, a POST error code will be
electrically erasable which enables the system to displayed on the Multifunction PCB (discussed
install software upgrades via the floppy drive instead further in the Multifunction PCB theory).
2-8 906-2000-501
SERIES 20000™* LEGACY®
MULTIFUNCTION PCB
200-1014-501 (schematic 940-2000-001)
The Multifunction PCB is an IBM-AT compatible After the boot cycle is complete, system software
plug-in board that provides the interface between the can clear the displays, or write system diagnostic
CPU PCB and the various subsystems. All codes to them. Refer to Tables 5-7 and 5-8 in
intelligence on the Multifunction PCB is controlled Section Five-Maintenance and Troubleshooting for a
by the CPU PCB via the ISA bus. In a DOS listing of these error codes.
environment there is a block of addresses reserved
for certain I/O (Input/Output) operations. The SERIAL COMMUNICATIONS INTERFACE
Multifunction PCB is inserted in this address space. A UART (Universal Asynchronous Receiver/
These operations are accessed by system I/O READ Transmitter) is a device which converts parallel
(IOR*) and I/O WRITE (IOW*) cycles. Figure FO-1 information to an asynchronous serial format, and
located at the end of this section is a block diagram serial information to a parallel format. The Octal
of the Multifunction PCB. UART (U29) has four groups of two UARTs which
control serial communications to the various
PAGED ADDRESSING subsystems (8 maximum). The outputs (TX) are
The Multifunction PCB uses a paged address TTL level transmit/receive and are converted to
scheme and pages two distinct groups of devices, differential RS422 by Line Drivers U22 & U26.
those that are paged externally and those that are Incoming RS422 signals (RX) are converted to TTL
paged internally or have an external address bus of level by Line Receivers U21 and U25. The RS422
five or more bits. lines are terminated by a resistor between + and -,
and each is pulled up and down respectively to
The externally paged devices are accessed by prevent oscillations when there is no connection to
writing to the base address of the PCB which is latch those channels. Channels seven and eight may be
U86. U86 receives buffered data (BD0-7) from the switched away from the internal system and directed
ISA bus via bus transceiver U85. Latched data to two optically isolated RS232 ports.
(LD0-7) is decoded and gated with IOR* & IOW*
on decoders U40 & U41 for chip selects of all paged Each group of UARTs has a fully programmable
devices. The value written may be read back for interrupt designated to it. All four interrupts
verification by performing a read at the same base (INT0-4) are wire-ORed together to drive the
address. U87 does this by transferring direction of system’s IRQ10 line (interrupt request). Signal
the LD0-7 bus back out onto the BD0-7 bus. The IRQINH enters logic circuitry that makes IRQ10 an
IOR* cycle reverses the direction of U85 on pin 1, edge trigger for multiple interrupts. As the
thereby placing the data on the ISA bus. interrupts are processed, the IRQINH line is toggled.
If an interrupt occurs while the current one is
The internally paged devices are those that have processing, the rising edge of IRQ10 is regenerated
address buses of more than 4 bits. The address lines indicating there are more interrupts pending.
of these devices are driven by LD0-7. An example
is the octal UART which has an address bus of six Support circuitry for the UART includes a 4-bit
bits that addresses its internal registers. After counter U50 used as a divider for the system bus
latching the address bus, a read or write to that oscillator. The division of 14.31818 MHz by four
register is accomplished. yields a 3.58 MHz clock for driving the UART.
This frequency results in easily programmable baud
POWER ON SELF-TEST (POST) rates for the device.
It is common to all DOS based computers to perform
tests during the boot cycle. Should a test fail, a
failure code is displayed by DS1 & DS2. If the
failure is catastrophic, then the system will halt.
906-2000-501 2-9
SERIES 20000™* LEGACY®
2-10 906-2000-501
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906-2000-501 2-11
SERIES 20000™* LEGACY®
FOOTSWITCH INTERFACE
Figure FO-2 shows the interface between the
STTL footswitch and the system. STTL FOOTSWITCH INTERFACE
As shown on the block diagram, the footswitch
interface is located on the Multifunction PCB. If a STTL footswitch is present, the DAC U17
voltage programs the motor current of the detent
Footswitch control voltages are provided by DAC motor on the footswitch. The motor used in the
™*
U17. It is an 8-bit digital-to-analog converter with an Series 20000 footswitch has a winding of 110Ω,
internal 2.56 reference voltage. The output of the and +24 V applied to one terminal. The other
DAC controls two different things. If a terminal is connected to Q2 on the Multifunction
programmable detent footswitch (Series 20000 ™* PCB which controls the amount of current
footswitch) is present, it is the detent control (proportional to torque) on the motor. This is
voltage. If a standard Line Master or ATFS type accomplished by turning on Q2 and controlling the
footswitch is present, it becomes the Pedal-UP voltage on the emitter resistor RP1 thereby
setpoint voltage. The sequence for determining the controlling the collector current.
function of the DAC is to first read the footswitch
revision resistor. After determining what footswitch Footswitch position is determined by counting the
and revision is plugged into the system, a footswitch digital pulses created by the optical encoder on the
status bit needs to be set that selects Series 20000™* footswitch. The optical encoder outputs, FS_CHA &
or ATFS type footswitches. FS_CHB, are decoded and counted by U63 then sent
to the CPU to determine the appropriate response.
LINEMASTER OR ATFS
FOOTSWITCH INTERFACE SERIES 20000™* FOOTSWITCH
If an ATFS is present, the DAC performs the The Series 20000™* footswitch consists of 4 basic
PEDALUP signal indirectly. A setpoint is functional elements; position encoder, position
programmed to the non-inverting input of feedback, functional switches, and revision control.
comparitor U4. The footswitch voltage is fed into The combination of these elements ensure system
the inverting input of the comparitor and so long as control and provide for IEC/TUV approval,
it is the greater voltage, the comparitor drives its including waterproof criteria based therein.
output to AGND (analog ground). Once the
footswitch voltage becomes less than the setpoint, Positional Encoder
the comparitor releases its output which is pulled up The treadle is the control surface of the footswitch.
to +5VA and the diode portion of the Optical It is attached to a quadrature optical encoder through
Isolator (U10) turns on. The output transistor of the a 5:1 transmission. The optical encoder requires +5V
opto-isolator also turns on effectively bringing power and ground, and transmits two digital pulse
ATFSUP* to a logic low. The final result is trains (FS_CHA & FS_CHB). The digital signals are
PEDALUP being broadcast to all subsystems. 90 degrees out of phase to represent rotation and
direction, depending upon the phase relationship.
The footswitch voltage is also input to ADC U16. The encoder signals are decoded/counted on the
The digital equivalent of this voltage is then read Multifunction PCB as discussed in the Footswitch
and decoded by the system to determine footswitch Interface. By design, the footswitch generates 550
position. counts in the decoder/counter chip with full
depression of the treadle.
2-12 906-2000-501
SERIES 20000™* LEGACY®
906-2000-501 2-13
SERIES 20000™* LEGACY®
IV POLE PCB
The IV Pole PCB is located on the IV Pole OPTO CHANNEL OUTPUTS (CH_A & CH_B)
Assembly and provides system control of IV Pole These signals provide relative position measurement
movement. Refer to FO-3 for a block diagram of the as well as direction of travel. These two lines
IV Pole PCB and its interface with the Multifunction originate from the commutation signals HSNSR1 &
PCB. The following signal descriptions detail how HSNSR3 from the Hall-Effect Sensors on the
the IV Pole is controlled and monitored by the Brushless DC Motor. Each of these lines will toggle
system, and the associated circuitry used to support once for each revolution of motor travel. The ratio of
these functions. pole movement to motor rotation is .50 ±.005 in:1
revolution. The actual counting of these pulses is
ENABLE (EN*) done by Decoder/Counter U73 on the Multifunction
A low level signal from Multifunction PCB enables PCB.
motor operation.
SENSOR OUTPUT (S1*)
DIRECTION (UP*/DN) This signal provides feedback to the system for
A low level signal from Multifunction PCB indicates absolute (home) positioning. The opto channel
upward pole travel. A high level signal indicates outputs explained above only provide a
downward pole travel. measurement of displacement relative to a
predefined “Home” position. Subsequent to any
BRAKE RELEASE (BRKREL*) system reset, the absolute position of the IV pole is
A low level signal from Multifunction PCB lost and the CPU must synchronize its displacement
disengages the IV pole brake solenoid. To start counter to a known position. S1 provides an active
motion of the IV pole, the system first disengages low signal to the Multifunction PCB when the pole
the brake then waits approximately 10 ms before reaches a position of 78 cm.
providing the enable signal. This is done to ensure
that the motor never drives into a braked IV pole. A lower limit sensor, S3 on the schematic diagram,
is installed but not sensed by the system at this time.
The mechanical brake, normally in the on position, In the event a calibration procedure was required,
is used to prevent pole motion under load and while sensor S3 would provide a lower limit to indicate
power to system is off. FET driver U10 drives the pole travel below the allowed minimum of 2 cm.
solenoid brake release.
S1 and S3 are located at fixed points on the
As an additional braking mechanism, the brake stationary vertical structure. When the (moving)
release signal is connected to the BRK line on Motor vertical structure of the IV pole passes by an
Controller U11. On activation of this signal, the N- opto-interrupter, a flag on the vertical structure
channel FETs of U12 are all turned on. This interrupts the light beam between the interrupter’s
effectively shorts the stator windings of the motor LED and photo-transistor, causing the
and provides a means of dynamic braking. It also photo-transistor to turn off. This signal is inverted by
ensures that in the event of a single fault failure of U1 and sensed by the system as an indicator of
the motor enable logic, the motor will not be absolute pole position.
activated.
2-14 906-2000-501
SERIES 20000™* LEGACY®
906-2000-501 2-15
SERIES 20000™* LEGACY®
VIDEO PCB
200-1011-501 (schematic 940-2000-010)
The Flat Panel Controller employs an extension The Flat Panel Controller sends 14 bits of
register set to control its additional capabilities. information to the Front Panel Drivers (U5 & U6)
These registers are initialized by the on-board BIOS which send it through the System Backplane and the
and provide control of the flat-panel interface, Front Panel Controller directly to the color LCD. No
timing, and vertical compensation. further operation is performed on this data.
VIDEO BIOS
The Video BIOS EPROM U4 supports the extended
features of the Flat Panel Controller. During power
up, the CPU accesses the BIOS EPROM and uses
this information to enable the flat panel mode and
disable the CRT mode.
2-16 906-2000-501
SERIES 20000™* LEGACY®
TOUCH SCREEN
FRONT PANEL AND
CONTROLLER LED
LAYER SWITCHES
PCB COLOR
VIDEO PIXEL DATA LCD
TX/RX
80C196 REMOTE
DISPLAY
PCB
The Front Panel Subsystem (FPSS) provides the • Monitoring remote control serial bit stream and
man-machine interface for the STTL. The FPSS is reporting remote key codes.
responsible for the following functions: • Maintaining communication with the host.
906-2000-501 2-17
SERIES 20000™* LEGACY®
The Front Panel Controller PCB controls the FPSS HARD KEY INTERFACE
and communicates with the Host system. The major The hard keys (elastomer buttons on the front panel)
components on this PCB are specified by the are arranged in a 4 row by 5 column matrix. The
Subsystem Kernel Design discussed in the System task of scanning the hard keys is performed by
Overview section of this manual. Additional software through the 82C55 I/O U10. At a rate
components on this PCB are used to interface with (multiples of 10 msec) defined by the Host, the
the rest of the FPSS. 80C196 U16 scans the hard keys. Scanning is
performed by setting all column lines high and then
TOUCH SCREEN INTERFACE scrolling a logic zero through the columns. After
The Touch Screen consists of a two thin sheets of every scroll the signals at ROW0, ROW1, ROW2,
plastic (X and Y screens), each with a special and ROW3 are read and stored away.
coating of transparent resistive material on one side.
The sheets are sandwiched together with the Upon one complete scan, software analyzes the
resistive coating in between, but restrained from stored row data (5 x 4=20 bits). If all bits are high
touching each other by a matrix of small clear then the hard keys are untouched and the task exits.
spacers. In order to detect a valid touch, only one out of 20
bits is allowed to be low. When a valid key is
In order to read the coordinate of a point of touch, detected, its associated key code is stored.
the X screen is biased (VCC at +X, GND at -X) and
the Y screen is floated to become a pickup contact at The hard keys are scanned again in 10 msec. If the
any position over the entire screen. When the same key is found to be depressed, its code value is
screens are touched, a voltage divider is created to placed into a transmit buffer in the proper format to
raise the potential of the floating screen to some be transmitted to the host.
voltage. This voltage is sent through a low pass
filter to the 80C196 internal A/D converter which HARD KEY BACKLIGHTING
yields the X coordinate (XCH). In order to read the Backlighting of the hard keys on the Front Panel is
Y coordinate (YCH), the operation repeats itself accomplished with an illumination panel containing
with the Y screen biased and the X screen floated. one LED per hard key. These LEDs are Pulse Width
Modulated (PWM) in order to obtain maximum
The task of biasing/floating the X/Y screens is brightness. The 80C196 U16 sends the PWM signal
controlled by software through the 82C55 I/O U10. to MOSFET U27 which drives the LEDs located on
The software accomplishes this task by alternatively the illumination panel.
turning a pair of P-MOSFET and N-MOSFET
transistors (U1 and U2) on and off at appropriate +12 V CONTROL TO LCD
times. These devices are logic level controlled. The +12V_EN* signal from the Video PCB controls
+12 V delivered to the LCD. When +12V_EN* is
high, U27 is off and not enabling U14 which is
acting as a switch for the +12 V. When +12V_EN*
is low, U27 enables U14 and allows +12 V to be
delivered to the LCD.
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906-2000-501 2-19
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DISPLAY PCB
200-1026-501 (schematic 940-2000-019)
The Display PCB contains the U/S Time Meter and REMOTE CONTROL RECEIVER
IV Pole position LED displays, and the Infrared The hardware for the infrared detecting signals from
Detect/Decode Interface for the remote control. the remote control is centered around Infrared
Detector U1 located on the Display PCB. This
I/V POLE AND U/S TIME LED DISPLAY device receives the infrared rays through its
The U/S and IV pole data are transmitted in ASCII photo-diode and performs all the necessary
format by the Host. Upon receiving a display amplification, filtering, and pulse detecting
command, the FPSS verifies the data packet, internally. It outputs a TTL compatible signal
performs the ASCII to seven segment conversion representing the envelop of the infrared signal (IR).
and then displays the data.
The output IR is connected to the HSI port on the
All 8-Segment LEDs (DS1-DS6) on the Display 80C196 Control Processor located on the Front
PCB are time multiplexed on common data lines. Panel Controller PCB. HSI.0 is programmed to
The segment data is sent through PORT-A of 82C55 record events on the rising and falling edge. This
U10 on the Front Panel Controller PCB. This data is enables the 80C196 to measure the low and high
then fed into High-Current Driver U11 and sent to pulse durations.
the Display PCB via cable W-131. The segment data
is then presented to the LEDs through current In order to receive a valid command from the
limiting resistors R2-R9. Each LED display has 8 Remote Control, the following conditions must be
data line inputs and 1 common terminal which met:
allows the display to be enabled or blanked. • Valid Low pulse durations
• Valid High Pulse Durations
Since the LEDs share common data lines, only one • Valid Start bit
LED can be enabled at a given time. This is • Valid Data bit complements
accomplished by scrolling a logic 1 through Shift • Valid Packet Checksum
Register U3 by DCLK and DDATA lines. U3 • Valid Address
outputs are then fed into High-Current Driver U2 in
order to enable or disable any given LED. When a valid command is received, its code value is
placed in a transmit buffer to be transmitted to the
Host.
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REMOTE CONTROL
200-4000-501
The remote control transmits packets of information In all cases, the remote infrared beam must have a
to the Display PCB through an infrared link and is path to the front panel sensor either directly or
operational under the following circumstances: through reflection (i.e. wall, floor, sealing) .
• In tray and anywhere tray arm extends.
• Independent of screen tilt and position.
• Anywhere in a 15' x 20' operating room.
• With drape over remote and system.
The Remote Control performs the following The keyboard is scanned again in 35 msec. If the
functions: same key is found to be depressed, its code value is
• Monitors the remote control key board and transmitted to the host. At this point the CPU enters
transmits any valid key entry. a loop 100 msec in duration. After each loop
• Upon usage, monitors the ambient light and iteration, the keyboard is scanned again. If the same
turns on the backlight LED if ambient light key is still depressed, a repeat message is transmitted
intensity is below 5 ±3 lux. to the host. The loop execution continues until either
• Upon usage, monitors the battery and transmits the key is released, a new key is depressed, or an
its status with every packet. illegal entry is detected.
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U6 contains two timers, one for the pyroelectric Resistors R28, R29, and R30 bias U8C to 2 VDC
sensor and one for the keyboard. The two timers are and U8D to 3 VDC. The comparator output
connected in parallel so an output from either generates a negative going pulse for large positive or
powers-up the CPU. negative going signals which exceed the established
threshold levels. This negative pulse is then fed into
POWER DOWN METHOD timer U6A.
Once the CPU is powered up either through key
depression or motion detection, the CPU enters an BACK LIGHT
idle mode waiting for key entry. If no key is pressed Back lighting the keys and icons is accomplished by
3.5 second after the last entry, timer U6 times out LEDs DS20....DS59. One LED is used per key and
and as a result turns power off to the CPU U5. two per icon. LEDs are turned on through CPU port
P3.7 by software. This output is fed into MOSFET
PYROELECTRIC SENSOR U10B in order to provide the current (1 ma) for the
The pyroelectric sensor is a device that responds to LEDs.
the change in temperature (infrared light) caused by
the human body. The object of the pyroelectric COMMUNICATION
sensor is to detect the hand motion near the remote Packets are transmitted via infrared link with the
control and turn the power on to the CPU. system. Packet contents (data bits) are shifted
serially through CPU port P1.7 by software. The
The pyroelectric output is fed into amplifier U8A data bits are then modulated by 40 KHz square wave
which acts as a noninverting amplifier with a voltage by Counter U2. The carrier (modulated data) is the
gain of 21 and frequency response restricted from current amplified through MOSFET driver U1, then
0.3 to 10 Hz. The U8A output is ac coupled to fed into leds DS1-DS4. The LEDs transmit data at
amplifier U8B which acts as an inverting amplifier 950 nm wavelength to the infrared detector on the
with a voltage gain of 21 and frequency response Display PCB.
restricted from 0.3 to 10 Hz. The output of U8B is
then fed into the window comparator U8C and U8D.
2-22 906-2000-501
SERIES 20000™*LEGACY®
FLUIDICS SUBSYSTEM
(FLUIDICS BACKPLANE)
SOLENOIDS
FLUIDICS ASP
CONTROL MTR
PCB CASS. SWITCHES
HANDPIECE
CONNECTOR
80C196 PANEL
ANTERIOR
TX/RX VIT
XDCR PNEUMATIC ASSY LUER
PCB
The Fluidics subsystem controls and monitors the The fluidics subsystem is comprised of 7 major
irrigation and aspiration modes used in the assemblies; the Fluidics Controller PCB, Cassette
STTL. Figure 2-6 illustrates the fluidics flow from Type PCB, Transducer PCB, Backplane PCB,
the IV bottle, through the cassette and handpiece, to Anterior Pneumatics module, Solenoids, and the
the drainage bag. Peristaltic Pump Stepper Motor. Figure FO-6 at the
end of this section is a detailed block diagram of the
Fluidics Subsystem.
BSS ®
CASSETTE
COMPLIANCE
CHAMBER IRR
CV
HANDPIECE
LIQ
VENT
ASP PUMP (Reflux)
FILTER
MT1
XDCR
(Flow Thru)
AIR
BAG VENT
(Prime only)
906-2000-501 2-23
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2-24 906-2000-501
SERIES 20000™*LEGACY®
SOLENOID CONTROL LOGIC AND FET power is used to illuminate the LED within the
DRIVERS switch. The switch return signals, IRRIG_SW &
The Solenoid Control Logic uses logic gates on U20 RFX_SW, are monitored at U9.
& U21, and control signals DISABLE &
CPU_RDY to determine when the Solenoid FET The Air Vent Valve driver current is monitored to
Drivers receive the driving signals (REFLUX, indicate excitation of a feedback device where LOW
IRRIG, & AIR_VENT) from the pulse width equates to closed and HIGH equates to open. Optical
modulation ports on U7. switch U30 is tied to the output of the Air Vent FET
Driver and provides feedback which is monitored at
The solenoid drivers control the voltage lines to the U9.
Irrigation, Reflux, and Air Vent solenoids. Low on
resistance FETs are used as the solenoid drivers to VIT DRIVER BUFFER
provide fast switching times and very low losses. The Vit Driver Buffer U22 provides TTL level
The Irrigation and Reflux solenoids are driven with drive signals to the HEXFET Drivers located on the
a pulse width modulation signal during the on-to-off Anterior Vit Drive PCB. Three of these signals,
and off-to-on transition. This allows a smooth, VIT_A, VIT_B, and VIT_C are sequenced by
controlled operation of the solenoids. The Air Vent software in a manner to provide pneumatic vacuum
solenoid is driven with a pulse width modulation and pressure valve control to the handpiece. The
signal 500 milliseconds after being fully energized. VIT_E signal is controlled for compressor on/off.
This technique utilizes the high holding force of the
solenoid while dissipating much less energy. VIT_A, B, & C signals are controlled by the 80C196
U7 high speed output and the VIT_E signal is
SOLENOID FEEDBACK controlled by the 82C55A U9. These signals are
The Irrigation Valve and the Reflux Valve have an input to U22 and then sent to the Anterior Vit Drive
optical switch on the mechanism to indicate physical PCB when the ENABLE1 signal is high.
information on the state of the valve where LOW
equates to closed and HIGH equates to open. Power VIT DRIVER FEEDBACK
to the Irrigation (IRR_SW_P) and Reflux The excitation current from the HEXFET Drivers on
(RFX_SW_P) optical switches is provided through the Anterior Vit Drive PCB is monitored by U9 on
R25 & R26 on the Fluidics Controller PCB. This the Fluidics Controller PCB. A low feedback signal
(VLV_A_FB, VLV_B_FB, or VLV_C_FB) equates
to valve closed and a high output equates to valve
open.
STEP FREQUENCY
1 2 3 4 1 2 3
PHASE A
PHASE B
PHASE C
PHASE D
906-2000-501 2-25
SERIES 20000™*LEGACY®
SYSTEM CONTROL SIGNALS TEST* signal low overrides the PEDAL_UP signal
The Host system maintains ultimate control over the by forcing U20 pin 11 high and enabling peristaltic
Fluidics subsystem through the following system PHASE A, B, C, & D signals to control the Stepper
control signals; DISABLE3, PEDAL_UP, TEST*, Motor FETS Drivers Q1, Q2, Q5, & Q6.
and RESET3*. Refer to the schematic diagram to
follow the signal descriptions through the various RESET3* low forces the 80C196 U7 into reset,
control logic blocks. which in-turn forces all controlled devices to
become disabled.
DISABLE3 signal high disables the Stepper Motor
FETS Drivers, Vit Driver Buffers, and Solenoid VOLTAGE FEEDBACK
FETS Drivers. Disable high forces U20 output pins The Fluidics Controller PCB supplies two types of
1, 4, &10 low. The combination of U20 pins 1 & 4 voltage feedback. The first type is voltage feedback
low forces U20 pin 13 high, thus disabling peristaltic signals to the controller for subsystem status
PHASE A, B, C, & D signals from controlling the information and master CPU reporting. The second
Stepper Motor FETS Drivers Q1, Q2, Q5, & Q6. is visual indication LEDs for all used voltages
U20 pin 10 low (ENABLE 2) also disables the indicated as follows:
solenoid control signals from driving the Solenoid DS1 = +5 V
FETS Drivers Q3, Q4, & Q8. U20 pin 4 low DS2 = CPU OK (blinks on/off)
(ENABLE 1) also disables the Vit Driver Buffers DS3 = +15 V
U22 and U24. DS4 = -15 V
DS5 = +24 V
When DISABLE3 is low, U20 output pins 1, 4, & 10
are allowed to inversely track the driving input to the
device thus enabling functionality.
2-26 906-2000-501
SERIES 20000™*LEGACY®
The Transducer PCB provides the Fluidics The Cassette Type PCB is used to determine if a
Controller PCB with real time pressure/vacuum cassette is inserted in the instrument and the type of
information. The pressure/vacuum transducers, cassette inserted. The Fluidics Controller PCB uses
MT1A and MT1B, are located just before the air this information to control the peristaltic pump.
vent valve as shown in Figure 2-6. The outputs from
MT1A and MT1A, which are redundant to ensure Two optical switches, SW1 and SW2, are provided
reliability of the system, represent the chamber to detect up to three different types of cassettes.
pressure/vacuum. Power to the optical switches is provided through R8
and R24 on the Fluidics Controller PCB, and is used
Since the full-scale output from the transducers is in to illuminate the LED within the switch. The switch
the millivolt range, and the full-scale signal required return signals, CST_S1 and CST_S2, are monitored
by the Fluidics Controller PCB is 0 to 5 V, each by U7 on the Fluidics Controller PCB.
transducer output is amplified by a gain of 100. The
amplified signals, VAC_X_A and VAC_X_B, FLUIDICS BACKPLANE PCB
contain vacuum information proportional to the 200-1020-501 (schematic 940-2000-004)
voltage of the signal where the voltage scale is
0.0048 volts/mmHg. This information is sent to the The Fluidics Backplane PCB provides a common
Fluidics Controller PCB where they must track each point for the module interconnects. The Fluidics
other within 12% in order for the Fluidics Controller PCB and the Transducer PCB are
Subsystem software to accept the vacuum readings. mounted directly to the Backplane PCB via PCB
On the Fluidics Controller PCB, the vacuum signals connectors. The Cassette Type PCB and the Anterior
are voltage clamped and low pass filtered to protect Vit Driver PCB are satellite assemblies connected to
the 80C196 U7 A/D inputs from ESD or miswiring the backplane through cables W-108 and W-110. All
of the connector. pneumatic components are connected to this
backplane.
Test points are provided for checking the following
signals:
TP1 = 15VRTN
TP2 = VAC_X_B
TP3 = VAC_X_A
906-2000-501 2-27
SERIES 20000™*LEGACY®
The Anterior Pneumatic Module is comprised of the Each valve is supplied with +24 V through
Anterior Vit Drive PCB and the Anterior connector J1 pins 5 and 9. The valves are driven
Compressor. This module supplies the vacuum and open or closed by HEXFET power MOSFETS Q1
pressure used to drive the pneumatic handpieces. through Q3, which in-turn are controlled by the
Figure 2-8 illustrates the air flow from compressor Fluidics Controller PCB signals VIT_A, VIT_B, and
to handpiece. VIT_C (see Figure FO-6). For example: VIT_A
signal high would result in HEXFET Q1 driving
ANTERIOR VIT DRIVE PCB valve K1 open thus sending air pressure towards
200-1030-501 (schematic 940-2000-027) valve K3.
TO
HANDPIECE
K2 K1
TO AIR
VACUUM
COMPRESSOR
PRESSURE
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SERIES 20000™* LEGACY®
PHACO SUBSYSTEM
HANDPIECE
CONNECTOR
(PHACO BACKPLANE) PANEL
U/S 1
PHACO
TX/RX U/S DRIVER PCB U/S 2
CONTROL
PCB U/S 3
+85 V 80C196
COAG
CAUTERY PCB
COAG
The Phaco subsystem consists of 7 assemblies: voltage and frequency, are used to control the stroke
Phaco Controller PCB, U/S Driver PCB, of the ultrasonic handpiece. The voltage control loop
Backplane PCB, Cautery PCB, Cable Connector monitors and maintains the appropriate handpiece
panel (P/N 200-1105-501),and Cable W-107 (P/N drive voltage. The frequency control loop maintains
200-1107-501). See Figure FO-7 at the end of this continuous tuning of the handpiece to compensate
section for a detailed block diagram of the Phaco for handpiece loading and drift. These control loops
Subsystem. are only partially realized within the U/S Driver
PCB. The U/S Driver PCB contains the circuitry to
The Phaco Controller PCB assembly contains the create the sinusoidal drive voltage and frequency
circuitry which controls the U/S Driver PCB as with analog feedback to the Phaco Controller to
well as the Cautery PCB. It is the central point of close the loop. The Phaco Controller digitizes and
all communication within the Phaco Module. Two processes this feedback to provide a continuous
way communication with the Host is achieved by tracking digital control loop. The U/S Driver PCB
an RS422 serial communication link. This is also contains various circuitry to detect fault
accomplished with an RS422 converter I.C. conditions, disable power output and communicate
through the TRANSMIT (TX+, TX-), and the the fault to the Phaco Controller. The Phaco
RECEIVE (RX+, RX-) signals. All system level Controller then communicates this fault to the Host.
commands and data are transferred through this
interface. The only other communication to the The Cautery PCB generates sinusoidal electrical
Host is done with the following system control signals at varying power levels necessary to drive a
signals; FPUP (PEDAL_UP), TEST*, DISABLE, variety of electrosurgical cautery probes. Also, the
and RESET. Cautery PCB contains the safety circuitry to detect a
fault condition within the PCB and communicate
Once a command is received from the Host, the this fault to the Phaco Controller which in turn
Phaco Controller performs the appropriate action disables the Cautery PCB and communicates the
by communication to either the U/S Driver PCB or fault condition to the host. All power adjustments
the Cautery PCB. and control functions are communicated to the
Cautery PCB by the Phaco Controller.
The U/S Driver PCB performs all electrical
processes necessary to drive a variety of ultrasonic
handpieces. Two interdependent control loops,
906-2000-501 2-29
SERIES 20000™* LEGACY®
The Backplane PCB provides the intra-module All electrical output for U/S and cautery handpieces
communication link as well as channeling all d.c. is conducted through cable assembly W-105. There
power to the subsystem. It has a single ground plane are three separate yet functionally identical U/S
which is common to all supplies. The backplane is output ports. The cable supports both the low and
completely passive, i.e. no semiconductors reside on high voltage signals necessary for the ultrasonic
the backplane. However, there is a provision for a “smart” connector. The high voltage signals are
choke (currently not used). This choke may physically separated from the low voltage signals
ultimately be used to smooth current transients on with their own jacketed and shielded cable. Due to
the 85V supply. The Backplane also makes power the sensitivity of the cable capacitance to handpiece/
available to the cooling fan for the U/S Driver PCB. driver performance, the shield is not grounded.
However, redundant chassis grounding is maintained
All electrical power and communication signals to to the panel connector through the connector case as
and from the Host pass through cable W-107. This well as an internal pin connection to a chassis
cable contains shielded twisted pairs of wires for the grounding lug. For the purpose of maintaining
power supply lines to minimize noise generation and necessary creapage distance (IEC601 requirement)
increase noise immunity. The signal lines are also of the high and low voltage signals, the three ports
shielded within a secondary layer. The 85V supply is are separately connected on the U/S Driver PCB (see
routed along side the main harness and is separately Table 2-1 for connections).
connected. This was done to maintain a
commonality of the main harness cable for use with
the other system modules.
2-30 906-2000-501
SERIES 20000™* LEGACY®
906-2000-501 2-31
SERIES 20000™* LEGACY®
2-32 906-2000-501
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906-2000-501 2-33
SERIES 20000™* LEGACY®
MULTIPLYING DIGITAL TO ANALOG signal by clocking the enable signal present at TP5
CONVERTER with the above square wave.
All handpiece voltage adjustments occur through the
12 bit Multiplying DAC U1. U1 takes the voltage (3 Also at this point, the square wave is buffered by
Vrms) and multiplies it by the ratio n/4096. The U16 to create the FREQUENCY (FRQ) signal used
variable n is the 12 bit data written to the in frequency measurements done by the Phaco
Multiplying DAC from the data bus. Thus, the Controller.
voltage presented to the input of the power amp
varies from 0 to a maximum of approximately 3 ULTRASOUND ENABLE LOGIC, RELAY
Vrms. SELECT AND RELAY DRIVERS
The ultrasound enable logic is created by U16 and
ANALOG SWITCH AND ZERO CROSSING U18. The ultrasound enable signal present at TP5 is
DETECTOR a logical function of the following signals: TEST*,
Ultrasound power is enabled by analog switch U2. FPUP, USEN, and DISABLE. Table 2-2
This switch is controlled by the ZEN signal which is summarizes the logic of ultrasound enabling.
created by Zero Crossing Detector circuit created by
U13 and U19. In addition to the enable logic, ultrasound power is
enabled only in a “no ground fault” condition.
The purpose of the zero crossing detector is to
synchronize ultrasound power enable to the instant The USEN and RELAY ENABLES signals are
at which the sinusoidal handpiece voltage crosses created by 8 bit latch U7. These signals are
zero volts. This synchronization prevents the large generated by the Phaco subsystem software to select
current transients which can occur when power is the U/S port and enable U/S power. The relay
enabled at the sinusoidal peak. U13 creates a TTL signals are buffered by U8 prior to activating each of
compatible square wave and U19 creates the ZEN the relays.
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
2-34 906-2000-501
SERIES 20000™* LEGACY®
906-2000-501 2-35
SERIES 20000™* LEGACY®
2-36 906-2000-501
SERIES 20000™* LEGACY®
CAUTERY PCB
200-1018
The Cautery PCB is manufactured by a German DIGITAL-TO-ANALOG CONVERTER (DAC)
company and uses different terminology on some The Up/Down Counter bits are input to DAC IC5 for
components than the rest of the PCBs in the conversion to a corresponding analog voltage from 0
STTL. This terminology was retained in the block Vdc to +5 Vdc based on VREF (pin 3) supplied by
diagram (FO-7) and the following theory to enable IC7. With an input count range of 0-255, this
the user to cross reference to the provided schematic. translates to 19.6 mV/count. The resulting voltage at
Definitions of the terminology used on the Cautery MP1 controls the PWM duty cycle to regulate
PCB are as follows: cautery power.
MP= Measuring Point
TP = Tune Potentiometer FEEDBACK BUFFER
IC = The “U” designator used for Non-inverting Op-Amp IC6 buffers the DAC output
integrated circuits (IC) on all voltage to provide feedback signal
other PCBs. CAUTERY_POWER (CAUT_PWR). This voltage
T = Transistor is monitored by the 80C196 Control Processor U8
on the Phaco Controller to verify PU & PD control
INPUT BUFFER response. On the Phaco Controller schematic, the
Originating from the Phaco Controller via the Phaco CAUT_PWR signal is designated as ACH5.
Backplane, cautery control signal inputs PULSE_UP
(PU), PULSE_DOWN (PD) and CAUTERY_ AMPLIFIER/FILTER
ENABLE (CAUTEN*) enter at edge connector J1. Two stages of Op-Amp IC6 multiply the DAC
These signals are buffered by IC1 and pulled-up by voltage times 4, and low-pass filter the output to
RM1 & RM2 to provide the on-board cautery smooth DAC voltage changes. An output offset of
controls. +2.5V (VREF/2) applied to IC6 & IC7 centers the
PWM input voltage above ground.
UP/DOWN COUNTER
Buffered signals from PU & PD are combined with PULSE WIDTH MODULATOR (PWM)
NAND gates of IC2 to control Up/Down Counters PWM IC7 functions as a switching controller for the
IC3 & IC4 as follows: DC Power Regulator. The PWM oscillates at about
20KHz with a variable Duty Cycle (pulse width)
PU PD IC3&4 determined by the amplified DAC input voltage.
LO LO HOLD COUNT
HI LO STEP UP PWM Functional Sequence:
LO HI STEP DOWN 1) EN* goes LOW at Pin 10 to enable PWM.
HI HI RESET 2) DAC input at Pin 1 sets Duty Cycle.
3) Output square wave at Pin 14 controls DC Pwr
A single count increment/decrement occurs for each Reg.
HI pulse from either PU or PD signal. Both signals 4) Feedback at Pin 1 via TP1 offsets DAC to set
at logic HI reset the counters to zero. Counters IC3 GAIN.
& IC4 output 4 bits each (1 byte) of binary data to
the Digital-to-Analog Converter IC5.
906-2000-501 2-37
SERIES 20000™* LEGACY®
2-38 906-2000-501
SERIES 20000™* LEGACY®
P1
SD0
MULTIFUNCTION PCB P3
SERIAL COMMUNICATIONS INTERFACE
SD0-7 TX2+
BUFFER BD0-7 LATCH LD0-7 TX2-
LINE
SD0-7 U85 U86 OCTAL RX2+
BD0-7 LD0-7 DRIVERS
U87 UART TX1-8 U21,25 RX2-
U29
TX3+
SD7 TX1-8 TX3- SERIAL
WATCH- RX3+ COMMUNICATION
DOG RX1-8 RX3- TO SUBSYSTEMS
LD0-5 LINE
TIMER RX1-8 RECEIVERS
U80 TX4+
COUNTER 3.58MHz U22,26 TX4-
OSC INT0-3
ISA U50 RX4+
BUS RX4-
IOW* RSTAT1*
IOR*
BUFFER
S1* SYSTEM SYSTEM STATUS SYSTEM CONTROL
U60,70, DECODERS INT0-3
RESET U65,66, LOCK* STATUS INTERRUPT P2
75,82 BUFFER
67,72,77 ILIMIT* REG. SYSTEM LOGIC IRQ10 ISA
CONTROL BFAULT* U48 IRQINH
SA0 U52,59 BD0-7 BUS
INTB* BD0-7 CONTROL BLANK
BA0-23 SIGNALS P3
FANFAIL* REG. U83 RSHDN
SA16 SRST1* K1 SHUTDOWN TO POWER
LA17 R_SHTDN* SUPPLY
SYSTEM
DISABLE & SYSTEM
TEST POINTS UNLOCK LOCK
POST CODE DISPLAY DECODERS ULOCK* RESET CONTROL SIGNALS
TP1 TP2 DS1 DS2 FLIP-FLOP TO SUBSYSTEMS
U40,41 DISABLE
DECODER BLANK U38 DISABLE2*
REG.
15 U69 LD0-7 CHIP SELECTS U28 DISABLE3*
BD0-7
DISABLE4*
LOCK
906-2000-501 2-39
SERIES 20000™* LEGACY®
REAR
® PANEL SYSTEM
SERIES 20000 FOOTSWITCH BACKPLANE MULTIFUNCTION PCB
J1 P1 P12 P15 J15 J9 P3
LV LV
SIDE RV RV
SWITCHES LH LH
S3,S4,S5,S6
RH RH
L_HEEL L_HEEL
R_HEEL R_HEEL
TILT-SAFE
(Hg) SWITCH FS_UP FS_UP
FSUP/
SPRING FAIL
SWITCHES W-111
S1/S2 U9
- OPTICAL DECODER/
FS_CHB FS_CHB ISOLATOR CHB COUNTER
+
U11,12 U63 BUFFER.
FS_CHA FS_CHA + U68
CHA
-
ADC
U16
FTSW BD0-7
FS_UP CONTROL UP* STATUS P3
- OPTICAL
LOGIC REG.
U4 ISOLATOR ATFSUP* U19
+24V U43,44
+24V + U10
DAC
U17 PEDALUP
BD0-7
OPTICAL DETENT FSRST*
ENCODER FTSW
MOTOR SYSTEM
CONTROL TGS/ATF*
CONTROL
REG. REFLUX SIGNALS
SOL- U54
SOL- TEST*
+
Q2 U3
-
RP1
24
906-2000-501 2-40
SERIES 20000™* LEGACY®
SYSTEM
MULTIFUNCTION PCB BACK IV POLE PCB
BD0-7 J11 P11 P1 J1 FET J2 P2
P3 J9 PLANE MOTOR BRUSHLESS
DRIVER PHA
CONTROLLER DC MOTOR
DECODER/ IV POLE EN* PCB EN* OPTICAL U11
U12
COUNTER CONTROL EN
BUFFER UP*/DN UP*/DN ISOLATORS
U73 U74 REG U7,8 F/R
FET
U64 PHB
CNTRST* CNTRST* DRIVER
U12
FET PHC
IV POLE DRIVER
STATUS I_LIM* I_LIM* OPTICAL U12 HSNSR1
REG ISOLATOR HSNSR2 HALL-EFFECT
U18 U6
BRK
HSNSR3 SENSORS
DS2
FAULT
+24V
LED
J3 P3 J7 P7
24 DS1 DS3
+24V +5V
906-2000-501 2-41
SERIES 20000™* LEGACY®
VIDEO PCB
VIDEO
BIOS BUFFER
EPROM U9
U4
FLAT
P6 PANEL
VID0-7
FLAT COLOR
SD7 DATA AR0-5 PALETTE
PANEL
BUFFER AD0-15 CONTROLLER AG0-5 U2
SD0-7
U14 U7 AB0-5
SD0
SYSTEM
VIDEO
ADDRESS MEMORY
P7 J7 BACKPLANE J10 P10 P5 J5 FRONT
SA19
ADDRESS
DRAM
R0 PCB PANEL
ISA SA0-15 DATA U8,13
BUS
BUFFER R1 SUBSYSTEM
U12,13 (SEE FPSS
SA0 R2
SA16-19 G0 THEORY FOR
G1 DETAILS)
FRONT
14 PANEL G2 W-129
CLK0 DRIVERS
CLOCK PCLK
OSC CLK1 U5,6
GENERATOR B0
U10 CLK2 DATA_EN*
B1
B2
HSYNC
VSYNC
VOLTAGE OK LEDs
TEST POINTS
DS1 DS2 DS3
TP1 TP2
+24V +15V -15V
+5VRTN CLK0 MULTI-
DS4 DS5 VID_REV
+5V +12V FUNCTION
PCB
REV
906-2000-501 2-42
SERIES 20000™* LEGACY®
P6 J6 J2 P2
DISABLE2 ROW1
PEDALUP ROW2 ELASTOMER
TEST ROW3
ROW4
KEYS
RESET SUBSYSTEM 82C55 COL1
SYSTEM CONTROL RESET2* GENERATOR KERNAL I/O COL2
AND COMMUNICATIONS U13 U10 COL3
LED
FROM MULTIFUNTION PCB U5, U8, U9,
TX+ U10, U11 COL4 ILLUMINATION
TX- DVR/RCVR COL5 LAYER
RX+ U19
RX- J1 P1
TCH SCRN Y+
INTERFACE Y- TOUCH
U1,U2,U7, X+
SCREEN
CR1-4 X-
J7 P7
DRIVER PWM
U27 +12V
J3 P3 J1 P1 DISPLAY PCB
SA
SB LEDs REMOTE CONTROL
SC DS1-6
+12V_EN* SD
LCD POWER ENABLE DRIVER
FROM VIDEO PCB +5V_EN* SE
U11 A/B
SF DRIVER
W-131 SEL
U2 INFRARED
SG S1
LEDs
DP
PHOTOCELL
DS1
DDATA SHIFT V1
DCLK REGISTER AMP
RST* U3 DS2 LED CPU CMPR
IR 87C751 U3
IR DVR
DETECTOR (W/EPROM)
LEDREV U1,U2
U1 DS3 U5
MUX REV
U24
DS4 PWR
Vcc CONTROL
+12V CNTRL J4 P4 SWITCH ON/OFF
+12V LCD12V
P5 J5 U27,U14 U6, U10
LCD5V PYROELECTRIC
BACK- ON/OFF
R0 R0 4 SENSOR U11
+5V LIGHT
R1 +5V CNTRL R1 LEDs AMP
U14 CN1 MEMBRANE CMPR
R2 R2
G0 G0
COLOR KEYS U8
VB
G1 G1 LCD
G2 G2 W-126 BATTERY
VIDEO DATA FROM
VIDEO PCB PCLK PCLK BT1
B0 B0
B1 B1
B2 B2
HSYNC HSYNC
VSYNC VSYNC
J8 P8
906-2000-501 2-43
SERIES 20000™* LEGACY®
906-2000-501 2-44
SERIES 20000™* LEGACY®
PHACO
PHACO CONTROLLER PCB BACK-
U/S DRIVER PCB
J1 P1 P1 J1 J2 P2 +85V
-15V OPTICAL -15VOK
PLANE +85V VBIAS J2
MUX2 SCALE ACH4
+15V ISOLATORS +15VOK
10VREF U3 AMP
TP2
+12V U21,22,23 +12VOK U9
TP3 MUX2*
SCALE
RMS- ACH2
BWR* ENABLE AMP DC
DECODE MUX1* U27 U29
RESET BUFFER BRD* TP4
SUBSYSTEM LOGIC CSREG*
XRST* GENERATOR U13 BALE
KERNAL U22,23,26 FRST
RMS-
U2 U5, U8, U9, BA0 SCALE ACH1
AMP DC
CPU U10, U11 ADDR BA1
BWRITE*/MDAC*
U27 U28
TO PHACO
TX+ LAD0-7 DAC0A*
SUB- TX- DVR/RCVR BUFFER BA2 DAC0B*
+85V CONTROLLER
SYSTEM RX+ U12 U15 BA3 (THRU PHACO
RX- EMULATOR ANALOG BACKPLANE)
DUAL VCO SCALE MULT. VOLTAGE
TEST ROM FINE POWER
AD8-12 DAC U11 AMP DAC SELECT
SOCKET AMP
ACH1 U17 COARSE U10 U1 SWITCH U2 RELAY K5
U6 BD0
ACH2 0-3 0-7 DC 0-3 0-7
AD0-7 BD1 DATA ZEN
ACH3 OFFSET
BD2 BUFFER (SQUARE WAVE) FRQ
ACH4 DATA DATA0-7 ZERO
U/S BD3 &
AD0-7 BUFFER CROSSING STEP-UP
DRIVER/ AD0-15 BD4 LATCH (SINE WAVE)
ACH5 (CAUT_PWR) U14 DETECT XFMR
U21,24 GND
CAUTERY BD5
LDATA0-7 U13,19 T1
FEED- BD6 FAULT
BACK BD7 U/S & LGNDF* DETECT J4
0-7 FF U12
RELAY US1B
FRQ TP5 U19
GFRQ LATCH FRST US1A
FRQGATE* U4 CSREG* USEN U/S
PU* ENABLE OUTPUT
ENABLE
ACH0-P AD0-7 BUFFER PD* FPUP U7 SELECT J5
LOGIC
ENABLE* TEST* RELAYS US2B
U16 U16,18
DISABLE K6, K7 US2A
P1 J1 BUFFER J6 P6
BUFFER AD0-7 1PROG2 RELAY ENABLES
CAUTERY STATUS U8 US3B
U18 1PGND INPUT
STATUS US3A
1PROG0 RELAY
1PROG1 K4
REV1 BDEN1 CALR1 J2
MUX INPUT MUX1*
MUX1 TO PHACO
PCB REV2 AD8-10 DECODER BDEN2 B10VREF BUFFER SCALE ACH3
U7 RELAY U4 AMP CONTROLLER
REV. REV3 U19 BDEN3 U5
P2 J2 K1 U9 REV2
BDEN4 (THRU PHACO
VOLTAGE INDICATOR LEDs 2PROG2 REV
INPUT BACKPLANE)
DS2 DS3 DS4 TEST POINTS 2PGND
DS1 RELAY
CPU OK +24V -15V +15V TP1 TP2 2PROG0 BUFFER
K3 DATA0-3
(BLINKING) 2PROG1 U6
DS5 DS6 +5VRTN +15VRTN CALR2
+5V +12V
B10VREF
J4 P3 J3
P19 3PROG2
W-107 3PGND INPUT
HOST 3PROG0 RELAY
3PROG1 K2
SYSTEM ®
CALR3
J5
P29 B10VREF
W-107
J1 J3
NAND
UP/
8
DAC
CAUTERY PCB
PU DOWN
INPUT GATES IC5
CNTR
BUFFER IC2
PD IC3,4
IC1 DIGITAL MV
EN 340 KHz
CAUTEN* IC8
EN
J2 P2
PWR CAUT_A
FET TO
XFMR
T4 UE1
CAUTERY
CAUT_B CONNECTOR
+85V
REL1
DC J1 J3
AMP/ PWM PWR
FILTER LED STATUS
FILTER IC7 REG COMPLIANCE
L1,C13 D6 TO PHACO
IC6 T1,T2, COMPARATOR
TP1 IC6 REV3 CONTROLLER
REV (THRU PHACO
BACKPLANE)
CAUT_PWR (ACH5)
SECTION THREE
PARTS LOCATION AND DISASSEMBLY
906-2000-501 3-1
SERIES 20000™* LEGACY®
TOP CURVE
16, 17, Remove two 3 mm hex screws securing Top Curve Panel to
2 PANEL
11 & 12 Chassis. Remove Top Curve Panel.
PN 200-1427-001
FRONT BEZEL Remove four 3 mm hex screws securing Front Bezel to front
3 5, 7, 8
PN 200-1143-001 panel chassis. Remove Front Bezel.
DISPLAY BOTTOM Remove three 2.5 mm hex screws securing Display Bottom
5 PANEL CAP -- Panel Cap to Front Panel. Pull Display Bottom Panel Cap down to
PN 200-1193-001 remove.
CAP ENDS 16, 17, Remove 2 mm hex screw from inside of Cap End. Remove Cap
6
PN 200-1264-001 11 & 12, 9 End.
CAUTION
When removing this item, ensure the Back Bezel
standoff (lower left as you face the back of the
system) doesn’t catch the gold ribbon cable as you
BACK BEZEL
8 5, 7 remove the Back Bezel.
PN 200-1194-001
Remove two 3 mm hex screws securing Back Bezel to Front
Panel. Slide Back Bezel up and away from Front Panel to
remove.
3-2 906-2000-501
SERIES 20000™* LEGACY®
TOP ARM 16, 17, Remove four 3 mm hex screws (underside of arm, outside row)
9
PN 200-1209-001 11 & 12 securing Top Arm to arm chassis. Remove Top Arm.
NOTE: The Back Panel (11) and the Top Curve Back
Cover (12) are removed as one piece. They
are attached (inside) by four 2.5 mm hex
screws.
BACK PANEL
PN 200-1426-001
1. Remove three 2.5 mm hex screws securing Top Curve Back
&
11 & 12 16, 17 Cover to chassis .
TOP CURVE BACK
COVER
2. Remove 2.5 mm hex screw securing Top Curve Back Cover
PN 200-1205-001
to chassis at IV Pole opening.
1. Remove drawer.
16, 17, 2. Remove (or loosen) ten 3 mm hex screws securing Right Side
14 RIGHT SIDE PANEL
11 & 12, Panel to front and rear of chassis.
PN 200-1203-001
4, 13
3. Remove one 2.5 mm hex screw securing top of panel to
chassis. Remove Right Side Panel.
1, 4, 16, 17,
15 FRONT TOP LID Remove four 4 mm hex screws securing Front Top Lid to chassis.
11&12, 13,
PN 200-1206-001 Remove Front Top Lid.
14, 18
IV POLE CAP
16 -- Unscrew IV Pole Cap counter-clockwise to remove.
PN 200-1434-001
17 IV POLE SHROUD Pull IV Pole Shroud back toward rear of system until metal
16
PN 200-1432-001 securing tab releases.
18 TRAY ARM Loosen one 2 mm hex screw located in side of arm near Front
--
PN 200-1083-501 Top Lid. Pull up on Tray Arm to remove.
1. Remove drawer.
Not ARM SUPPORT PIN
-- 2. Remove 4 mm hex screw and two washers securing Arm
shown PN 200-1087-001
Support Pin. Turn Pin clockwise until it stops, then pull up to
remove.
906-2000-501 3-3
SERIES 20000™* LEGACY®
FRONT
TOP BEZEL 3
2 CURVE
PANEL
FRONT
CURVED 4
LEFT PANEL
1 SIDE
PANEL
3-4 906-2000-501
SERIES 20000™* LEGACY®
7 DISPLAY TOP
PANEL CAP
BACK BEZEL 8
DISPLAY BOTTOM
5 PANEL CAP BOTTOM ARM 10
BACK PANEL 11
TOP CURVE
12
BACK COVER
TRAY
18 ARM
17 IV POLE
SHROUD
16 IV POLE
CAP REAR 13
PANEL
15 FRONT
TOP LID
RIGHT
14 SIDE
PANEL
906-2000-501 3-5
SERIES 20000™* LEGACY®
1.3 Remove four 2.5 mm hex screws securing touch 5.3 Disconnect connector P2 from Anterior VIT Drive
screen to Front Panel. Remove touch screen from PCB.
system.
5.4 Disconnect clear pneumatic line at white connector.
2 REMOVAL OF DISPLAY PCB.
5.5 Loosen four captive screws securing Anterior
2.1 Remove skins 3, 5, 7, and 8 per Table 3-1. Pneumatic module to chassis. Remove module from
system.
2.2 Disconnect connector P1 from Display PCB.
6 REMOVAL OF FLOPPY DRIVE
2.3 Remove four 2.5 mm hex screws securing Display
PCB to Front Panel. Remove Display PCB from 6.1 Remove skin 13 per Table 3-1.
system.
6.2 Remove two 2.5 mm hex screws securing floppy
3 REMOVAL FRONT PANEL CONTROLLER drive panel to chassis.
PCB
6.3 Disconnect power cable and ribbon cable from floppy
3.1 Remove skins 5, 7, and 8 per Table 3-1. drive.
3.2 Disconnect connectors P1 through P8 from Front 6.4 Remove four 2.5 mm hex screws securing floppy
Panel Controller PCB. drive to panel. Remove floppy drive from system.
CAUTION
Place screwdriver next to standoff when prying
PCB from standoff to avoid damaging PCB.
3-6 906-2000-501
SERIES 20000™* LEGACY®
7 REMOVAL OF IV POLE ASSEMBLY 10.5 Loosen four captive screws securing CPU card cage to
chassis. This is done to provide space for removal of
7.1 If possible, lower IV Pole to lowest position. system fans.
7.2 Remove skins 11 & 12, and 13 per Table 3-1. 10.6 Simultaneously lift CPU card cage and pull system
fans out of system.
7.3 Disconnect connector P1 from IV Pole PCB (top
connector) and ground wire from chassis. 11 REMOVAL OF HOST SYSTEM
MOTHERBOARD
7.4 Loosen three captive screw securing IV Pole assembly
to chassis. 11.1 Remove skin 4 per Table 3-1.
7.5 Lift IV Pole assembly up and out of system. 11.2 Disconnect connectors from CPU, Multifunction, and
Video PCBs.
8 REMOVAL OF IV POLE PCB
11.3 Remove CPU, Multifunction, and Video PCBs from
8.1 Remove skin 13 per Table 3-1. card cage.
8.2 Disconnect connectors P1, P2 and P3 from IV Pole 11.4 Disconnect all cables from Host motherboard and
PCB. route back through card cage as necessary to enable
NOTE: Before removing connectors, ensure that card cage to be removed from system. Note
all connectors are clearly labelled as they can be orientation and position of each connector as it is
mistakenly interchanged when reconnected. disconnected.
8.3 Using a standard screwdriver, carefully pry IV Pole 11.5 Loosen four captive screws securing card cage to
PCB from each standoff. Remove PCB. chassis. Remove card cage/motherboard assembly
from system.
CAUTION
11.6 Remove nine 2.5 mm hex screws securing
To avoid damaging PCB, Place screwdriver next to motherboard to card cage. Remove Host motherboard.
standoff when prying PCB from standoff.
12 REMOVAL OF PHACO SYSTEM
9 REMOVAL OF POWER SUPPLY MOTHERBOARD
9.1 Unplug AC power cord. 12.1 Remove skin 4 per Table 3-1.
9.2 Remove skin 4 per Table 3-1. 12.2 Disconnect connectors from Phaco Controller, U/S
Driver, and Cautery PCBs (see Figure 3-7 for PCB
9.3 Remove 3 mm hex screw securing ground wire. locations).
9.4 Disconnect power supply connectors from power 12.3 Remove Phaco Controller, U/S Driver, and Cautery
supply. PCBs from card cage.
9.5 Loosen two captive screws securing power supply to 12.4 Disconnect all cables from Phaco motherboard and
chassis. route back through card cage as necessary to enable
card cage to be removed from system. Note
9.6 Slide power supply straight out of system. orientation and position of each connector as it is
disconnected.
10 REMOVAL OF SYSTEM FANS
12.5 Loosen four captive screws securing card cage to
10.1 Remove skin 4 per Table 3-1. chassis. Remove card cage/motherboard assembly
from system.
10.2 Remove Power Supply per procedure 9.
12.6 Remove six 2.5 mm hex screws securing motherboard
10.3 Remove two 3 mm hex screws securing front panel to card cage. Remove Phaco motherboard.
latch to chassis. Remove latch from system.
906-2000-501 3-7
SERIES 20000™* LEGACY®
13 REMOVAL OF FLUIDICS MODULE 14.3 Remove selected connector as follows (see Figure
3-3):
13.1 Remove skins 11 & 12, 16, and 17 per Table 3-1.
• Three U/S connectors - loosen 24 mm nut using
13.2 Disconnect connector P1 from Fluidics Backplane modified wrench. Slide connector out of bracket.
PCB.
• Top Coag connector - loosen slotted screw located
13.3 Loosen four captive screws securing Fluidics module in center of connector. Slide connector out of
to chassis. See Table 5-1 for special screwdriver bracket.
specifications.
• Bottom Coag connector - loosen connector using
13.4 Slide Fluidics module toward IV Pole and lift out of small and large counter spanner tools on each side
system when module clears chassis. of the connector. Slide connector out of bracket.
14 REMOVAL OF HANDPIECE CONNECTORS 14.4 Cut tie wraps from cable assembly.
14.1 Remove skins 1, 2, 4, 11 & 12, 16, and 17 per Table 14.5 Remove selected connector and cable assembly.
3-1.
NOTE: For Coag connectors, replace connector only.
14.2 Remove two 3 mm hex screws securing connector
bracket to chassis.
24 mm
nuts
Set screws
(do not move)
Slotted screw
inside connector
Insert small spanner
tool into connector
3-8 906-2000-501
SERIES 20000™* LEGACY®
15 REMOVAL OF FOOTSWITCH CABLE 15.4 Carefully cut tie wrap shown in Figure 3-4.
15.1 Disconnect footswitch from rear of system. 15.5 Disconnect connector P1 from footswitch PCB.
15.2 Remove eight 2.5 mm hex screws securing bottom 15.6 Using modified 24 mm wrench, loosen nut securing
cover to footswitch assembly. Remove bottom cover. cable to footswitch assembly.
15.3 Disconnect ground connection by removing 3 mm hex 15.7 Slide connector P1 through 24 mm nut and hole in
screw. footswitch assembly.
Connector P1
Tie Wrap
24 mm Nut
Ground
Connection
906-2000-501 3-9
SERIES 20000™* LEGACY®
Display PCB
Touch Screen
Ground Connection
for Wriststrap
Host System
Phaco Subsystem
Power Supply
3-10 906-2000-501
SERIES 20000™* LEGACY®
Front Panel
Controller PCB
Fluidics
Controller PCB
Stepper Motor
Transducer PCB
Ground Connection
for Wriststrap Anterior
Compressor
Anterior VIT
Ground Connection
Drive PCB
for Wriststrap
Floppy Drive
IV Pole
PCB
IV Pole
Moter Footswitch
Connection
906-2000-501 3-11
SERIES 20000™* LEGACY®
J25
J28
CPU PCB
J17
J18
J10
J6 J19
J11
J21
J22
J29 J12
J23
J13
P1
J24
P3
P2
3-12 906-2000-501
SERIES 20000™* LEGACY®
SECTION FOUR
SERVICE TEST PROCEDURE
INTRODUCTION
906-2000-501 4-1
SERIES 20000™* LEGACY®
4-2 906-2000-501
SERIES 20000™* LEGACY®
SECTION FIVE
MAINTENANCE AND TROUBLESHOOTING
906-2000-501 5-1
SERIES 20000™* LEGACY®
TABLE 5-1
RECOMMENDED TOOLS
ITEM TOOL DESCRIPTION PART NUMBER
Standard tools including:
• Slotted screwdriver (small & narrow)
• Right angle, ratcheting slotted screwdriver or
offset slotted screwdriver
• Metric ball-end Allen set (1mm, 2mm, 2.5mm,
Standard Service Tool
1 3mm, 4mm, 5mm)
Kit
• Metric nut driver (7mm)
• Static protection wriststrap (ESD)
• Hemostat
• 19mm, deep Socket and Ratchet Wrench
• Allen wrench, 3mm, straight (non-ball end)
1.2mm thick x 1.8mm wide x 175mm long
2 Long Metric Screwdriver Reference PN 51080
Carlton-Bates Co. (501)562-9100
3 24mm Custom Wrench See Figure 5-1 for specifications
4 Counter Spanner Tool Reference PN 25.0022
5 Counter Spanner Tool Reference PN 25.0020
Banana Plug to in-line
6 12" or shorter (qty. 2)
Banana Jack
7 Oscilloscope (optional) Dual Channel, Storage w/isolation plug
AC Volts: 0 to 150
DC Volts: 0 to 150
DVM w/frequency
8 Resistance: 0 to infinite Fluke 8060A or equivalent
counter
Freq. count: 0 to 50 Hz
(Must have current calibration label)
Capable of indicating 0 to >400 mmHg (Must have
9 Vacuum/Pressure Meter Bio-Tek DPM-II or DPM III
current calibration label)
10 Syringe 60 cc
11 Test Auto-Hydro Injector PN 590-4040-501
12 Timer Capable of indicating 1 to 120 seconds Stop Watch or Wrist Watch
Capable of indicating 0 to 40 cc/min (Must have
Flowmeter
current calibration chart)
13 or Gilmont #1200
Capable of indicating 0 to 50 cc (A 60 cc syringe
Graduated Cylinder
body can be used)
14 Tape Measure 100 cm
Reference AMP PN
15 IC Extraction Tool
821981-1
16 Cautery Load 75 ohm ±1% (non-inductive)
SERIES 20000™* U/S
17 PN 200-1301-501
375 (40 KHz) Handpiece
Catalog No. 1006
ATIOP Handpiece
or
18 or
Catalog No. 1005
ATOP Handpiece
5-2 906-2000-501
SERIES 20000™* LEGACY®
TABLE 5-2
SUPPLIES
ITEM DESCRIPTION SPECIFICATIONS PART NUMBER
5 Luer Adapter
7 Tubing 5”
10 T-Fitting
906-2000-501 5-3
SERIES 20000™* LEGACY®
TABLE 5-3
RECOMMENDED SPARES
ITEM PART NUMBER DESCRIPTION QTY
1 200-1461-001 BRACKET, PCB 1
2 200-1297-001 CONNECTOR LABEL 3
3 200-1448-001 GASKET, IV POLE CAP 2
TABLE 5-4
RECOMMENDED HARDWARE
ITEM PART NUMBER DESCRIPTION QTY
1 026-060 CABLE CLAMP, .375 DIA 3
2 026-111 CABLE CLAMP, FLT 2
5 190-008 AA BATTERY 4
5-4 906-2000-501
SERIES 20000™* LEGACY®
TABLE 5-5
FRONT PANEL MESSAGES
ITEM MESSAGE DISPLAYED TYPE PROBABLE CAUSE
1 Mainframe-Comm Buffer Error Fault Front Panel, U/S, or Fluidics Subsystem are not communicating
properly with main CPU. Reboot.
2 Fluidic-Line Down Fault Fluidics module communications not occuring. Possible bad cable
connection or bad Fluidics CPU.
3 Fluidics-Irrigation Valve Error Fault Irrigation valve or sensor not operating properly.
4 24V Failure Fault U/S module detected 24 V error. Could be local or system wide.
5 U/S-Module Down Fault U/S module communications not occuring. Possible bad cable
connection or bad U/S CPU.
6 Fluidics Transducer Error Fault Three “Fluidics Vacuum Reading Errors” have occured (item 7).
8 Front Panel-Line Down Error Front Panel module communications not occuring. Possible bad
cable connection or bad Front Panel CPU.
16 Please Insert Cassette Advisory Cassette sensor (1 or 2) does not detect a cassette.
20 Priming/Tuning OK Advisory
21 1. Check Fittings-Reprime (vac Advisory Vacuum failure-will not build to 400 mmHg.
Fail)
906-2000-501 5-5
SERIES 20000™* LEGACY®
“Check Handpiece Flow” 1. Lack of irrigation flow due 1. Check for kinked tubing and restrictions
message. to kinked or blocked in irrigation line.
tubing.
(caused by system
4 2. Clogged handpiece or tip. 2a. Replace tip sleeve.
sensing flow greater than
150 mmHg vacuum during
2b. Replace handpiece.
flow test)
5-6 906-2000-501
SERIES 20000™* LEGACY®
906-2000-501 5-7
SERIES 20000™* LEGACY®
10 "Tuning Failure" message. 6. U/S Driver PCB failure 6. Replace U/S Driver PCB.
(check +85 V LED on U/S
Driver PCB).
7. Power supply failure 7. Replace power supply.
(check +85 V LED on U/S
Driver PCB).
8. Phaco Controller PCB 8. Replace Phaco Controller PCB.
failure.
9. Interconnection problem: 9. Reseat cables and PCB's.
cable or PCB.
5-8 906-2000-501
SERIES 20000™* LEGACY®
Front Panel Buttons don't 1. Stuck contact on the 1. Replace Touch Screen layer per
14 function but Remote and button layer. Section 3.
Touch Screen work.
Front Panel buttons, touch 1. Faulty Front Panel 1. Replace Front Panel Controller PCB.
15 screen and remote not Controller PCB.
responding.
Memory - lose of all 1. CPU battery dead. 1. • Replace battery per maintenance
17 settings and doctor’s procedure 1.
names. • Reprogram doctor’s settings.
906-2000-501 5-9
SERIES 20000™* LEGACY®
MAINTENANCE PROCEDURES
1.2 Remove brackets securing PCBs in Host System card 2.3 Turn system power ON. The front panel display
cage. illuminates during complete downloading process.
This takes approximately 3 minutes.
1.3 Disconnect connectors from CPU PCB.
2.4 When green light on the floppy disk drive remains off
1.4 Gently pull up on battery to remove from PCB (see for more than 30 seconds, turn system power OFF.
Figure 5-2 for battery location).
NOTE: Once the battery is removed, you have less 2.5 Remove floppy disk by pressing ejection button on
than 15 minutes to install new battery before lower right side of floppy disk drive.
doctor’s settings (if any remain) are lost.
2.6 Turn system power ON.
1.5 Install new battery and replace CPU PCB.
2.7 On power up, verify installed software version that is
1.6 Perform Service Test Procedure located in Section 4. displayed in lower right corner of blue ALCON
screen.
Lithium Battery
Figure 5-2. Lithium Battery on CPU PCB Figure 5-3. Disk Insertion
5-10 906-2000-501
SERIES 20000™* LEGACY®
The touch screen uses a UV cure acrylate coating on the front 5.1 Remove Front Curved Panel per Table 3-1.
polyester (PET) surface. This coating is substantially harder
and more abrasion and chemical resistant than uncoated PET. 5.2 Turn system ON.
The surface of the touch screen should be kept free of dirt, 5.3 Insert a 75 ohm noninductive load into cautery output
dust, fingerprints or other materials that could degrade optical jacks. Connect oscilloscope and DVM to output of
properties. Long term contact with abrasive materials will the load (set DVM for AC volts).
scratch the front surface and image quality will be
detrimentally affected. 5.4 Select COAG mode and set COAG POWER to
100%.
3.1 Apply any commercially available NON-AMMONIA
window cleaner to a NON-ABRASIVE cloth towel. 5.5 Depress footswitch to position 3 and check
oscilloscope for sinusoidal cautery waveform.
CAUTION
5.6 Coarse adjust TP1 on Cautery PCB for DVM reading
Do not apply cleaner directly to touch screen as it is not of approximately 39 VAC.
designed with a water tight bezel and some ingress may occur
from behind the panel. 5.7 Adjust TP2 to maximize reading on DVM. After
adjusting TP2, check oscilloscope waveform. Verify
3.2 Wipe cloth across touch screen until clean. ✓)
period of 2.5 to 3.3 microseconds (300-400 KHz). (✓
NOTE: Perform this procedure when florescent room 5.8 With footswitch in position 3, readjust TP1 for 109-
lighting is interfering with remote control/system 111 Vpp on oscilloscope.
communication.
5.9 Set COAG POWER to 0% (footswitch in position 3).
4.1 Remove Front Bezel per Section 3. Verify output on oscilloscope - 1.0 Vpp (audible tone
✓)
heard from unit). (✓
4.2 Cut a small hole in a piece of electrical tape.
5.9 Set COAG POWER to 10% (footswitch in position
4.3 Place tape over IR window on inside of Front Bezel. 3) and observe Peak-to-Peak voltage on oscilloscope.
4.4 Replace Front Bezel and check remote operation. 5.10 While continuing to depress footswitch, increase
COAG POWER on front panel by 10% steps up to
100%.Verify the following (✓✓ ):
• Oscilloscope voltage increases with each step by 8-
12 Vpp.
• Audible tone from unit through full power range.
906-2000-501 5-11
SERIES 20000™* LEGACY®
TABLE 5-7
80386DX POWER ON SELF-TEST (POST) ERROR CODES
CODE DEFINITION CODE DEFINITION
If error 1C, lE, or 20 (base 64K RAM error) is detected by the BIOS, an additional word of information
will be displayed to the screen and to port 80. This word will reflect the bit or address line which failed.
for example, if “1C 0002” is displayed, address line 1 (represented by bit one) has failed. If “20 1020” is
displayed, then data bits 12 and 5 have failed in the upper 16 bits. Note that error 20 can only occur on
386 systems because they have a 32 rather than 16 bit bus.
The same information will be output to port 80H. The checkpoint code will be output followed by a
delay, the high order byte, another delay, and then the low order byte of the error. This will be repeated
continuous]y.
5-12 906-2000-501
SERIES 20000™* LEGACY®
TABLE 5-8
80486SX POWER ON SELF-TEST (POST) ERROR CODES
CODE DEFINITION CODE DEFINITION
01 ...... Processor register test about to start, and NMI toe 19 ...... Memory Refresh started. Memory Refresh test to be done
disabled. next.
02 ...... NMI is Disabled. Power on delay starting. 1A ...... Memory Refresh line is toggling. Going to check 15 micro
second ON/OFF time.
03 ...... Power on delay complete. Any initialization before
keyboard BAT is in progress. 1B ...... Memory Refresh period 30 micro second test complete.
Base 64k memory test about to start.
04 ...... Any initialization before keyboard BAT is complete.
Reading Keyboard SYS bit, to check soft reset/power-on. 20 ...... Base 64k memory test started. Address line test to be
done next
05 ...... Soft reset / power-on determined. Going to enable ROM.
i.e. disable shadow RAM/Cache is any. 21 ...... Address line test passed. Going to do toggle parity.
06 ...... ROM is enabled. Calculating ROM BIOS checksum, and 22 ...... Toggle parity over. Going for sequential data R/W test.
waiting for KB controller input buffer to be free.
23 ...... Base 64k sequential data vector initialization complete.
07 ...... ROM BIOS checksum passed, KB controller I/B free. ANy setup before Interrupt vector init about to start.
Going to issue the BAT command to keyboard controller
24 ...... Setup required before vector initialization complete.
08 ...... BAT command to keyboard controller is issued. Going to Interrupt vector initialization about to begin.
verify the BAT command.
25 ...... Interrupt vector initialization done. Going to read I/O port
09 ...... Keyboard controller BAT result verified. Keyboard of 8042 for turbo switch (if any)
command byte to be written next.
26 ...... I/O port 8042 is read. Going to initialize global data for
0A ...... Keyboard command byte code is issued. Going to write turbo switch.
command byte data.
27 ...... Global data initialization is over. Any initialization after
0B ...... Keyboard controller command byte is written. Going to interrupt vector to be done next.
issue Pin-23, 24 blocking/unblocking command.
28 ...... Initialization after interrupt vector is complete. Going for
0C ..... Pin-23,24 of keyboard controller is blocked/unblocked. monochrome mode setting.
NOP command of keyboard controller to be issued next.
2A ...... Monochrome mode setting is done. About to go for toggle
0D ..... NOP command processing is done. CMOS shutdown parity before optional rom test.
register test to be done next.
2B ...... Toggle parity over. About to give control for any setup
0E ...... CMOS shutdown register R/W test passed. Going to required before optional video ROM check.
calculate CMOS checksum, and update DIAG byte.
2C ..... Processing before video ROM control is done. About to
0F ...... CMOS checksum calculation is done, DIAG byte written. look for optional video ROM and give control
CMOS init, to begin (if “INIT CMOS IN EVERY BOOT IS
SET”) 2D ..... Optional video ROM control is done. About to give control
to do any processing after video ROM returns control.
10 ...... CMOS initialization done (if any). CMOS status register
about to init for Date and Time. 2E ...... Return from processing after the video ROM control. If
EGA/VGA not found then do display memory R/W test.
11 ...... CMOS Status register initialized. Going to disable DMA
and Interrupt controllers. 2F ...... EGA/VGA not found. Display memory R/W test about to
begin.
12 ...... DMA controller #1,#2, interrupt controller #1,#2 disabled.
About to disable Video display and init port-B. 30 ...... Display memory R/W test passed. About to look for the
retrace checking.
13 ...... Video display is disabled and port-B is initialized. Chipset
init / auto memory detection about to begin. 31 ...... Display memory R/W test or retrace checking failed.
About to do alternate Display memory R/W test.
14 ...... Chipset initialization / auto memory detection over. 8254
timer test about to start. 32 ...... Alternate Display memory R/W test passed. About to look
for the alternate display retrace checking.
15 ...... CH-2 timer test halfway. 8254 CH-2 timer test to be
complete. 33 ...... Video display checking over. Verification of display type
with switch setting and actual card to begin.
16 ...... CH-2 timer test over. 8254 CH-1 timer test to be complete.
34 ...... Verification of display adapter done. Display mode to be
17 ...... CH-1 timer test over. 8254 CH-0 timer test to be complete. set next.
906-2000-501 5-13
SERIES 20000™* LEGACY®
36 ...... BIOS ROM data area check over. Going to set cursor for 52 ...... Memory test above 1M complete. Going to prepare to go
power on message. back to real mode.
37 ...... Cursor setting for power on message id complete. Going to 53 ...... CPU registers are saved including memory size. Going to
display the power on message. enter in real mode.
38 ...... Power on message display complete. Going to read new 54 ...... Shutdown successful, CPU in real mode. Going to restore
cursor position. registers saved during preparation for shutdown.
39 ...... New cursor position read and saved. Going to display the 55 ...... Registers restored. Going to disable gate A20 address line.
reference string.
56 ...... A20 address line disabled successfully. BIOS ROM data
3A ...... Reference string display is over. Going to display the Hit area about to be checked.
<ESC> message.
57 ...... BIOS ROM data area check halfway. BIOS ROM data area
3B ...... Hit <ESC> message displayed. Virtual mode memory test check to be complete.
about to start.
58 ...... BIOS ROM data area check over. Going to clear Hit <ESC>
40 ...... Preparation for virtual mode test started. Going to verify message.
from video memory.
59 ...... Hit <ESC> message cleared. <WAIT...> message dis-
41 ...... Returned after verifying from display memory. Going to played. About to start DMA and interrupt controller test.
prepare the descriptor tables.
60 ...... DMA page register test passed. About to verify from display
42 ...... Descriptor tables prepared. Going to enter in virtual mode memory.
for memory test.
61 ...... Display memory verification over. About to go for DMA #1
43 ...... Entered in the virtual mode. Going to enable interrupts for base register test.
diagnostics mode.
62 ...... DMA #1 base register test passed. About to go for DMA #2
44 ...... Interrupts enabled (if diagnostics switch is on). Going to base register test.
initialize data to check memory wrap around at 0:0.
63 ...... DMA #2 base register test passed. About to go for BIOS
45 ...... Data initialized. Going to check for memory wrap around ROM data area check.
at 0:0 and finding the total system memory size.
64 ...... BIOS ROM data area check halfway. BIOS ROM data area
46 ...... Memory wrap around test done. Memory size calculation check to be complete.
over. About to for writing patterns to test memory.
65 ...... BIOS ROM data area check over. About to program DMA
47 ...... Pattern to be tested written in extended memory. Going to unit 1 and 2.
write patterns in base 640k memory.
66 ...... DMA unit 1 and 2 programming over. About to initialize 8259
48 ...... Patterns written in base memory. Going to find out amount interrupt controller.
of memory below 1M memory.
67 ...... 8259 initialization over. About to start keyboard test.
49 ...... Amount of memory below 1M found and verified. Going to
find out amount of memory above 1M memory. 80 ...... Keyboard test started, clearing output buffer, checking for
stuck key, about to issue keyboard reset command.
4A ...... Amount of memory above 1M found and verified. Going for
BIOS ROM data area check. 81 ...... Keyboard reset error/stuck key found. About to issue
keyboard controller interface test command.
4B ...... BIOS ROM data area check over. Going to check <ESC>
and to clear memory below 1M for soft retest. 82 ...... Keyboard controller interface test over. About to write
command byte and init circular buffer.
4C ..... Memory below 1M cleared. (SOFT RESET) Going to clear
memory above 1M. 83 ...... Command byte written. Global data init done. About to check
for lock-key
4D ..... Memory above 1M cleared. (SOFT RESET) Going to save
the memory size. 84 ...... Lock-key checking over. About to check for memory size
mismatch with CMOS.
4E ...... Memory test started. (NOT SOFT RESET) About to
display the first 64k memory test. 85 ...... Memory size check done. About to display soft error and
check for password or bypass setup.
50 ...... Memory test below 1M complete. Going to adjust memory
size for relocation/shadow 86 ...... Password checked. About to do programming before setup.
5-14 906-2000-501
SERIES 20000™* LEGACY®
TABLE 5-8(continued)
80486SX POWER ON SELF-TEST (POST) ERROR CODES
CODE DEFINITION CODE DEFINITION
87 ...... Programming before setup complete. Going to CMOS 99 ...... Any initialization required after optional ROM test over.
setup program. Going to set up timer data area and printer base address.
88 ...... Returned from CMOS setup program and screen is 9A ...... Return after setting timer and printer base address. Going to
cleared. About to do programming after setup. set the RS-232 base address.
89 ...... Programming after setup complete. Going to display power 9B ...... Returned after RS-232 base address. Going to any
on screen message. initialization before coprocessor test.
8A ...... First screen message displayed. About to display 9C ..... Required initialization before coprocessor is over. Going to
<WAIT...> message initialize the coprocessor next.
8B ...... <WAIT...> message displayed. About to do Main and Video 9D ..... Coprocessor initialized. Going to do any initialization after
BIOS shadow. coprocessor test.
8C ..... Main and Video BIOS shadow successful. Setup options 9E ...... Initialization after coprocessor test is complete. Going to
programming after CMOS setup about to start. check extd keyboard, keyboard ID and num-lock.
8D ..... Setup options are programmed, mouse check and init to be 9F ...... Extd keyboard check is done, ID flag set. Num-lock on/off.
done next. Keyboard ID command to be issued.
8E ...... Mouse check and initialization complete. Going for hard A0 ...... Keyboard ID command issued. Keyboard ID flag to be reset.
disk, floppy reset.
A1 ...... Keyboard IFD flag reset. Cache memory test to follow.
8F ...... Floppy check returns that floppy is to be initialized. Floppy
setup to follow A2 ...... Cache memory test over. Going to display andy soft errors.
90 ...... Floppy setup is over. Test for hard disk presence to be A3 ...... Soft error display complete. Going to set the keyboard
done. typematic rate.
91 ...... Hard disk presence test over. Hard disk setup to follow. A4 ...... Keyboard typematic rate set. Going to program memory wait
states.
92 ...... Hard disk setup complete. About to go for BIOS ROM data
area check. A5 ...... Memory wait states programming over. Screen be cleared
next.
93 ...... BIOS ROM data area check halfway. BIOS ROM data area
check to be complete. A6 ...... Screen cleared. Going to enable parity and NMI.
94 ...... BIOS ROM data area check over. Going to set base and A7 ...... NMI and parity enabled. Going to do any initialization
extended memory size. required before giving control to optional ROM at E000.
95 ...... Memory size adjusted due to mouse support, disk type-47. A8 ...... Initialization before E000 ROM control over. E000 ROM to
Going to verify from display memory. get control next.
96 ...... Returned after verifying form display memory. Going to do A9 ...... Returned from E000 control. Going to do any initialization
any init before C800 optional ROM control. required after E000 optional ROM control.
97 ...... Any init before C800 optional ROM control is over. Optional AA ..... Initialization after E000 optional ROM control is over. Going
ROM check and control will be done next. to display the system configuration.
98 ...... Optional ROM control is done. About to give control do 00 ...... System configuration is displayed. Going to give control to
any required processing after optional ROM returns INT 19h boot loader.
control.
906-2000-501 5-15
SERIES 20000™* LEGACY®
SECTION SIX
SCHEMATICS
TABLE OF CONTENTS
DESCRIPTION PART NUMBER PAGE #
906-2000-501 6-1
SERIES 20000™* LEGACY®
6-2 906-2000-501
SERIES 20000™* LEGACY®
SECTION SEVEN
PARTS LISTS AND DRAWINGS
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER TABLE OF CONTENTS U/M
200-0000-501 Rev. N
SERIES 20000™* LEGACY® ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
7-2 906-2000-501
SERIES 20000™* LEGACY®
200-0000-501 Rev. N
SERIES 20000™* LEGACY® ASSEMBLY - continued
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
906-2000-501 7-3
SERIES 20000™* LEGACY®
200-0000-501 Rev. N
SERIES 20000™* LEGACY® ASSEMBLY - continued
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
200-1062-501 Rev. D
CPU MODULE ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
7-4 906-2000-501
SERIES 20000™* LEGACY®
200-3087-501 Rev. D
IV POLE W/BRONZE BRG BSHG ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
906-2000-501 7-5
SERIES 20000™* LEGACY®
200-3087-502 Rev. E
IV POLE W/BALL BRG BSHG ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
7-6 906-2000-501
SERIES 20000™* LEGACY®
200-1061-502 Rev. G
FRONT PANEL MODULE ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
200-1321-502 Rev. H
LCD DISPLAY PANEL SUB-ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
906-2000-501 7-7
SERIES 20000™* LEGACY®
200-1000-501 Rev. N
FLUIDICS MODULE ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
7-8 906-2000-501
SERIES 20000™* LEGACY®
200-1076-501 Rev. F
ANTERIOR PNEUMATIC MODULE ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
200-1053-502 Rev. G
PHACO/CAUTERY MODULE ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
906-2000-501 7-9
SERIES 20000™* LEGACY®
200-1167-501 Rev. G
REAR CONNECTOR PANEL ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
200-1167-502 Rev. G
REAR CONNECTOR PANEL ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
7-10 906-2000-501
SERIES 20000™* LEGACY®
200-1083-501 Rev. C
ARM TRAY ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
200-1290-501 Rev. G
FAN HOUSING ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
906-2000-501 7-11
SERIES 20000™* LEGACY®
200-1447-501 Rev. G
BASE ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
7-12 906-2000-501
SERIES 20000™* LEGACY®
200-3000-501 Rev. L
SERIES 20000™* FOOTPEDAL ASSEMBLY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
200-3000-501 Rev. L
SERIES 20000™* FOOTPEDAL ASSEMBLY - continued
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
200-4000-501 Rev. E
SERIES 20000™* REMOTE CONTROL ASSY
DWG PART DESCRIPTION QTY STK REMARKS
ITEM NUMBER U/M
7-14 906-2000-501