Unit - 5 (FSMS)

Unit 5: Synchronous sequential
circuits
Mealy and Moore
Sequential circuits
State diagram
State table
General Sequential circuit
State Encoding
❑ Common FSM encoding options:
▪ One-hot code
▪ Binary code
▪ Gray code
▪ Random code
One-hot encoding
An important feature of the one-hot state assignment is that it often leads
to simpler output expressions than do assignments with the minimal
number of state variables. Simpler output expressions may lead to a faster
circuit.
A 0101 Sequence Detector (overlapping)
Design an FSM to detect the pattern 0101 in the input
sequence x
A 0101 Sequence Detector (Cont.)
A 0101 Sequence Detector - Mealy
module melay_fsm(din, reset, clk, y);
input din; input clk; S2: if (din == 1'b1)
input reset; begin nst = S0; y=1'b0; end
output reg y; else
begin nst = S3; y=1'b0; end
reg [1:0] cst, nst; S3: if (din == 1'b0)
parameter S0 = 2'b00, S1 = 2'b01, S2 = begin nst = S1; y=1'b0; end
2'b10, S3 = 2'b11; //all state else
always @(cst or din) begin nst = S2; y=1'b1; end
default: nst = S0;
begin
endcase
case (cst)
end
S0: if (din == 1'b1)
always@(posedge clk)
begin
else
if (reset) cst <= S0;
else cst <= nst;
S1: if (din == 1'b0)
end
endmodule
else
State diagram – Moore (0101)
(non-overlapping)
S 0 S 1 S 0 S 1 S
0 1 2 3 4
0 0 0 0 1
1
0
1
A 0101 Sequence Detector -Moore
module moore_fsm(din, reset, clk, y); S2: begin y=1'b0;
input din; input clk; if (din == 1'b1) nst = S0;
input reset; else nst = S3; end
output reg y; S3: begin y=1'b0;
reg [2:0] cst, nst; if (din == 1'b0) nst = S1;
parameter S0 = 3'b000, S1 = 3'b001, else nst = S4; end
S2 = 3'b010, S3 = 3'b011, S4=3’b100; S4: begin y=1'b1;
//all state if (din == 1'b0) nst = S1;
always @(cst or din) else nst = S0; end
begin default: nst = S0;
case (cst) endcase
S0: begin y=1'b0 ; end
if (din == 1'b1) nst = S0; always@(posedge clk)
else nst = S1; end begin
S1: begin y=1'b0; if (reset) cst <= S0;
if (din == 1'b0) nst = S1; else cst <= nst;
else nst = S2; end end
State diagram – Moore (0101)
(overlapping)
1
S 1 S 0 S 1 S
0 1 2 3
0 0 0 1
0
1
A 0101 Sequence Detector -Moore
module moore_fsm(din, reset, clk, y); S2: begin y=1'b0;
input din; input clk; if (din == 1'b1) nst = S3;
input reset; else nst = S0; end
output reg y; S3: begin y=1'b1;
reg [1:0] cst, nst; if (din == 1'b0) nst = S2;
parameter S0 = 2'b00, S1 = 2'b01, else nst = S0; end
S2 = 2'b10, S3 = 2'b11;
//all state default: nst = S0;
always @(cst or din) endcase
begin end
case (cst) always@(posedge clk)
S0: begin y=1'b0 ; begin
if (din == 1'b1) nst = S1; if (reset) cst <= S0;
else nst = S0; end else cst <= nst;
S1: begin y=1'b0; end
if (din == 1'b0) nst = S2; endmodule
else nst = S0; end
Serial adder
Our task is to design a circuit that will perform serial addition, dealing with a
pair of bits in one clock cycle.
The process starts by adding bits a0 and b0.
In the next clock cycle, bits a1 and b1 are added, including a possible carry
from the bit-position 0, and so on.
This cannot be a combinational circuit because different actions will have to

be taken, depending on the value of the carry from the previous bit position.
Serial adder - Mealy
Serial adder - Mealy
Serial adder - Mealy H : begin
module serial_add(a, b, reset, clk, sum, nst); sum=~(a^b);
input a, b, clk, reset; if(~a&~b)
output reg sum; nst = G;
output reg nst; /// carry out else
reg cst; nst = cst;
parameter G = 1'b0, H = 1'b1; end
default: nst = G;
initial endcase
cst = G; ///initially carry is 0 end // end of first always block
always @(cst,a,b) always@(posedge clk)

begin begin
case (cst) if (reset)
G : begin cst <= G;
sum=a^b; else
if(a&b) cst <= nst;
nst = H; end
else
nst = cst; endmodule
end
Serial adder - Moore
Since in both states, G and H, it is possible to produce two different outputs
depending on the valuations of the inputs a and b, a Moore-type FSM will
need more than two states.
We can derive a suitable state diagram by splitting both G and H into two
states.
Instead of G, we will use G0 and G1 to denote the fact that the carry is 0
and that the sum is either 0 or 1, respectively.
Similarly, instead of H, we will use H0 and H1.

Serial adder - Moore G1 : begin
module serial_add(a, b, reset, clk, sum, c_out); sum=1’b1;
input a, b, clk, reset; if(a&b)
output reg sum; nst = H0;
output reg c_out; /// carry out else if (a^b)
reg [1:0] cst, nst; nst = G1;
parameter G0 = 2'b00, G1 = 2'b01, H = 2'b10, H1= 2'b11; else
nst = G0;
initial cst[1] = G0;
end
H0 : begin
always @(cst,a,b)
sum=1’b0;
begin
if(a&b)
case (cst)
G0 : begin
nst = H1;
sum=1’b0; else if (a^b)
if(a&b) nst = H0;
nst = H0; else
else if (a^b) nst = G1;
nst = G1; end
else
nst = G0;
H1 : begin
sum=1’b1; always@(posedge clk)
if(~a&~b) begin
nst = G1; if (reset)
else if (a^b) cst <= G0;
nst = H0; else
else cst <= nst;
nst = H1; end
end
assign c_out = cst[1];
default: nst = G; endmodule
endcase
end // end of first always block
Serial adder
A key difference between the Mealy and Moore types of FSMs is that in the
former a change in inputs reflects itself immediately in the outputs, while in
the latter the outputs do not change until the change in inputs forces the
machine into a new state, which takes place one clock cycle later.
Modulo-8 Counter
Counter Using the Sequential Circuit Approach
Counter must display the count in the sequence 0, 4, 2, 6, 1, 5, 3, 7, 0, 4, and
so on.
Counter must display the count in the sequence 0, 4, 2, 6, 1, 5, 3, 7, 0, 4, and
so on.
Verilog code – mod-8 counter
Detailed
explanation is in
the text book by
Charles Roth

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Unit 5: Synchronous sequential

The process starts by adding bits a0 and b0.

This cannot be a combinational circuit because different actions will have to

always @(cst,a,b) always@(posedge clk)

Similarly, instead of H, we will use H0 and H1.

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