DUAL-PORT MEMORY

BLOCK DIAGRAM
L R
DATA DATA
DATA DATA
CPU I/O I/O CPU
OR OR
I/O DUAL/PORT I/O
ADDRESS
DEVICE ADDRESS L R DEVICE
ADDRESS
RAM ADDRESS
"L" DECODER MEMORY DECODER
"R"
R/W R/W
CELLS

BUSY, BUSY,
INTERRUPT, CONTROL LOGIC INTERRUPT,
SEMAPHORE SEMAPHORE

1
 DUALL-PORT RAM CELL

L SIDE WRITE DRIVERS R SIDE WRITE DRIVERS

WR WR
1 1
L SELECT R SELECT
(DECODED (DECODED
ADDRESS) ADDRESS)
WR WR
L WRITE R WRITE
0 0

R DATA BIT LINE

L DATA BIT LINE

RD RD

RAM CELL LATCH

L SIDE READ DRIVERS R SIDE READ DRIVERS

2
DUALL-PORT RAM CELL - Read
L SIDE WRITE DRIVERS R SIDE WRITE DRIVERS

WR WR
1 1
L SELECT R SELECT
(DECODED (DECODED
ADDRESS) ADDRESS)
WR WR
L WRITE R WRITE
0 0

R DATA BIT LINE

L DATA BIT LINE

RD RD

RAM CELL LATCH

L SIDE READ DRIVERS R SIDE READ DRIVERS

3
DUALL-PORT RAM CELL - Write

L SIDE WRITE DRIVERS R SIDE WRITE DRIVERS

WR WR
1 1
L SELECT R SELECT
(DECODED (DECODED
ADDRESS) ADDRESS)
WR WR
L WRITE R WRITE
0 0

R DATA BIT LINE

L DATA BIT LINE

RD RD

RAM CELL LATCH

L SIDE READ DRIVERS R SIDE READ DRIVERS

4
 DUALL-PORT RAM
Interrupt Logic

L SIDE WRITE
INTERRUPT
TO R SIDE

ADDRESS
= 3FF
L SIDE
ADDRESS
ADDRESS
= 3FE
R SIDE READ

L SIDE READ
ADDRESS
= 3FF
R SIDE
ADDRESS
ADDRESS
= 3FE

INTERRUPT
TO L SIDE
R SIDE WRITE

5
 DUUALL-PORT RAM
Busy Logic
ADDRESS (L) DELAY BUFFER

DELAY BUFFER ADDRESS (R)

ADDRESS ADDRESS
EQUAL EQUAL
COMPARATOR COMPARATOR

CE (L) CE (R)

L R
BUSY (L) BUSY (R)

WRITE INHIBIT (L) WRITE INHIBIT (R)

A B

6
 DUAL-PORT RAM
Semaphore Logic
L R
DATA DATA
DATA DATA
CPU I/O I/O CPU
OR OR
I/O DUAL/PORT I/O
ADDRESS ADDRESS
DEVICE L R DEVICE
ADDRESS
RAM ADDRESS
"L" DECODER MEMORY DECODER "R"
R/W R/W
CELLS

SEMAPHORE
SEMAPHORE CELLS SEMAPHORE
SELECT SELECT

7
 DUAL-PORT RAM
Semaphore Logic8cell

L D-LATCH R D-LATCH

L REQUEST D D R REQUEST
1 1
Q Q

L WR SEMAPHORE E E R WR SEMAPHORE

GRANT (L) GRANT (R)

SEMAPHORE
ARBITRATION
LATCH