PCIPCI EXPRESS

EXPRESS PACKET
PACKET GENERATOR
GENERATOR

DATASHEET

OVERVIEW
Packet Generator is a software tool that will be running on a Host computer and generate traffic patterns.

PCIe packet generator is a product that generates series of Transaction Layer Packets (TLPs) which can be used by emulator platform
to generate traffic on DUTs interfaces. Also, it can be used on Simulation platform to generate traffic on simulation environment on
DUTs interface.

FEATURES
• It works on three types of configuration modes: Memory
BENEFITS
Packet, Configuration Packet and I/O Packet (for legacy
• These methods can be used for verification of most
devices).
complex hardware design to simple hardware design
• All PCIe Packet generation logic generates
o 3DW header bits for Memory-Read (MRD) and Memory- • Easy to use solution, plug and play type solutions
Write (MWR) with 32-bit addressing, Config-Read (CFGRD),
Config-Write (CFGWR), I/O-Read (IORD), I/O-Write (IOWR) • Software packet generators are very cost-effective
o 4DW header bits for Memory-Read (MRD), Memory-Write solutions, they are cheaper compared to high
(MWR) with 64-bit addressing license costing software products available in the
market.
• The key aspects of the Transaction Layer are:
o A pipelined full split-transaction protocol
• Creates beautiful Emulation environment, which can
o Mechanisms for differentiating the ordering and processing mimic many simulation verification scenarios.
requirements of TLPs
o Credit-based flow control • Detect bug in Pre-silicon phase, which can save
o Optional support for data poisoning and end-to-end data millions of dollars of re-spinning silicon cost.
integrity detection
• The above TLPs generated will pass through Datalink Layer • Post-silicon also software portion can be used for
and then to Physical Layer to finally generate a serial data validation
stream. Physical layer have 2 sub blocks named logical and
• Help to build a parallel structure to simulation to
physical sub block.
find more design bugs quickly.
• The Data Link Layer is responsible for reliably conveying
Transaction Layer Packets (TLPs) supplied by the Transaction • The overall runtime can be reduced to as much as
Layer across a PCI Express Link to the other component’s 10 times than long SOC simulations. This can speed
Transaction Layer. Services provided by the Data Link Layer up TAPE OUT of the chip.
include:
o Data Exchange • Scoreboarding and traffic analysis can be done very
o Error Detection and Retry well in the Software solution.
o Initialization and Power Management
• The logical sub-block has two main sections: a Transmit section that prepa res outgoing information passed from the Data Link
Layer for transmission by the electrical sub -block, and a Receiver section that identifies and prepares received information
before passing it to the Data Link Layer.
• PCI Express uses 8b/10b encoding when the data rate is 2.5 GT/s or 5.0 GT/s. For data rates greater than or equal to 8.0 GT/s, it
uses a per-lane code along with physical layer encapsulation.

CONFIGURATIONS
There are three configurations mode for packet generation: Memory Packet
• Memory Packet – Mode 1 Memory Packet comprises of both memory read and write with
a. Memory Read (32-bit addressing) – Mode 11 both 32 and 64 bit addressing header fields.
b. Memory Write (32-bit addressing) – Mode 12 Memory packet format is as shown below,
• 32-bit addressing memory header
c. Memory Read (64-bit addressing) – Mode 13
It is a 3DW sized packet
d. Memory Write (64-bit addressing) – Mode 14
• 64-bit addressing memory header
• Configuration Packet – Mode 2
It is a 4DW sized packet.
a. Config Read – Mode 21
b. Config Write – Mode 22
• I/O Packet – Mode 3
a. I/O Read – Mode 31
b. I/O Write – Mode 32

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 PCI EXPRESS PACKET GENERATOR

DATASHEET

Host Emulator

Transactor Transactor
Glue Transmitter Receiver
(SW) (HW)
Logic DUT

Mode X

Transaction Layer
Monitor
Datalink Layer

Physical Layer
PCI E X PRE S S P AC KE T GE N E RA T OR

Figure 1: PCIe PACKET GENERATOR in EMULATION PLATFORM

Configuration Packet generation logic follows below rules o TH is not applicable to I/O Request and the bit is
• Configuration Requests route by ID, and use a 3 DW Reserved Attr[2] is Reserved Attr[1:0] must be 00b
header o AT[1:0] must be 00b. Receivers are not required or
• In addition to the header fields included in all Memory, encouraged to check this
I/O, and Configuration Requests and the ID routing o Length[9:0] must be 00 0000 0001b
fields, Configuration Requests contain the following o Last DW BE[3:0] must be 0000b
additional fields
Receivers may optionally check for violations of these rules
o Register Number[5:0]
(but must not check reserved bits). These checks are
o Extended Register Number[3:0] independently optional. If a Receiver implementing these
• Configuration Requests have the following restrictions: checks determines that a TLP violates these rules, the TLP is a
o TC[2:0] must be 000b Malformed TLP. If checked, this is a reported error associated
o LN is not applicable to Configuration Requests and with the Receiving Port.
the bit is Reserved
o TH is not applicable to Configuration Requests and Datalink Layer Packet Format
the bit is Reserved The packets generated from Transaction layer comes to
o Attr[2] is Reserved Datalink layer which send then to receiver’s datalink layer.
o Attr[1:0] must be 00b Apart from the TLPs coming from upper layer, Datalink layer
o AT[1:0] must be 00b. Receivers are not required or itself have its own packets for link managements.
encouraged to check this
o Length[9:0] must be 00 0000 0001b The following DLLP Types are used to support Link operations:
o Last DW BE[3:0] must be 0000b
• Ack DLLP: TLP Sequence number acknowledgement; used
Receivers may optionally check for violations of these rules to indicate successful receipt of some number of TLPs
(but must not check reserved bits). These checks are
• Nak DLLP: TLP Sequence number negative
independently optional. If a Receiver implementing these
acknowledgement; used to initiate a Data Link Layer
checks determines that a TLP violates these rules, the TLP is a
Retry
Malformed TLP. If checked, this is a reported error associated
with the Receiving Port. • InitFC1, InitFC2, and UpdateFC DLLPs: For Flow Control
• DLLPs used for Power Management
I/O Packet
I/O Packet generation logic follows below rules,
Tools & Technologies: Verilog,
• I/O Requests route by address, using 32-bit Addressing
SystemVerilog, C, DPI, UVM
• I/O Requests have the following restrictions:
EDA Tools
o TC[2:0] must be 000b
Emulators
o LN is not applicable to I/O Requests and the bit is
Reserved

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