Solid State 12
Solid State 12
Solid State 12
(b)
Ɛ = Ɛ𝑆 . Ɛ𝑂
Q+ = Q- = q𝐴𝑁𝐷 𝑋𝑛𝑜
𝑊
𝑋𝑃 =
𝑁
1+ 𝐴
𝑁𝐷
𝑤
𝑋𝑛 =
𝑁
1+ 𝐷
𝑁𝐴
𝒒𝑵𝑫 𝑿𝒏
E(x) =
Ɛ𝒔 Ɛ𝒐
Solution
A = 1mm× 1𝑚𝑚.
ρ =10−3 Ω m at 27°C.
L =10mm
µn = 0.03𝑚−2 /vs
Ф= 10V
10
(a) E = = 1000 𝑉 ⁄𝑚
10×10−3
1 1
Б= = = 103 ℧⁄𝑚
𝜌 10−3
Б = q. p.µ.
Б = (1.602× 10−19 )p× 0.03
103
P=( = 2.0807 × 1023
1.602×10−19)×0.03
(b) V = µ𝑛 × Ɛ
V = 0.03× 1000 = 30m/s
𝑆 𝑙 10×10−3
(c) V = = = = 3.33 × 10−4 𝐴⁄𝑐𝑚2
𝑟 𝑣 30
(d) I = 𝐽𝑑𝑟𝑓𝑡𝑝 × 𝐴
𝐽𝑑𝑟𝑓𝑡𝑝 = б . 𝐸
J = 10 × 103 × 1000
J = 1M𝐴⁄𝑚2
2 𝑛2 𝑖
𝑛1 𝑝1 = 𝑛 𝑖 =
𝑛1
(1.5×1010)2
𝑝0 = = 2.25× 106or 2.25M eV
1014
(1.5×1010)2
𝑃𝐼 = = 2250 𝑒𝑉
1017
𝑑𝑝 2.25 × 106 − 0
= = 2.25 × 1011 𝑒𝑉
𝑑𝑥 1× 10−5 −0
𝑑𝑛 1017−1014
= = 9.99 × 1021 𝑒𝑉
𝑑𝑥 1×10−5−0
Solution
𝑁𝐷 = 2 × 1017
n-type
𝑉𝐹𝐵 = Ф𝑚 − Ф𝑠
vfB
𝐸𝑔
Ф𝑠 = 𝑥 + − 𝑞𝑉𝑛
2
Ф𝑀 > Ф𝑆 𝑖𝑓 𝑛 − 𝑡𝑦𝑝𝑒 𝑟𝑒𝑐𝑡𝑖𝑓𝑒𝑟𝑖𝑛𝑔
Ф𝑚 < Ф𝑆 𝑂ℎ𝑚𝑖𝑐
𝑁𝐷
𝑞𝑉𝑛 = 𝐾𝑇 𝐼𝑛( )
𝑛𝑖
Example 5: A nMOS device with L = 5µm, 100µm, mobility µ = 1×
103 𝑐𝑚2 /𝑉 s and gate oxide capacitance of 3.48× 10−8 𝐹/𝑐𝑚2 is made
on p-type substrate doped to 1016 𝑐𝑚−3 . The saturation trans
conductance measured at𝑉𝑔𝑠 = 3𝑉 produced 1.50Ms.
(a) Draw the schematic diagram of the device.
(b) Estimate the threshold voltage of the device.
(c) If 𝑉𝑔𝑠 = 𝑉𝑑𝑠 = 5𝑉 𝑖𝑠 𝑎𝑝𝑝𝑙𝑖𝑒𝑑 , 𝑤ℎ𝑎𝑡 𝑤𝑜𝑢𝑙𝑑 𝑏𝑒 the source drain
current if the device is operated in the linear region?’
(d) An nMOS is biased to conduct at 𝑉𝑑𝑠 = 5𝑉 𝑎𝑛𝑑 𝑉𝑔𝑠 = −2𝑉.
Solution
L = 5µm W = 100µm
L = 5× 10−6 W = 100× 10−6
L = 5× 10−4 𝑐𝑚 W = 100× 10−4 cm.
Cox = 3.48× 10−8 F/𝑐𝑚2
𝑁𝐷 = 1016𝑐𝑚−3
𝑔𝑚 = 1.5𝑚𝑆 𝑎𝑡 𝑉𝑔𝑠 = 3𝑉.
(𝑎 )
D S G D
G
S
∈𝑠 11.8×8.85×10−14
𝐶𝑑 = = = 2.5 × 10−8 𝐹/𝑐𝑚
𝑊𝑚 4.15×10−5
𝑞𝐴𝐷 𝐵 𝑝 𝑊𝑏
𝐼𝐸𝑝 = 𝑝𝐵 𝑛 𝑐𝑡𝑛ℎ 𝑒𝑞𝑉𝐸𝐵 /𝐾𝑇
𝐿𝐵 𝑝 𝐿𝐵 𝑃
𝐿𝐸𝑝 𝐿𝐸𝑛
𝛾= = [1 + ]−1
𝐿𝐸𝑛 + 𝐿𝐸𝑝 𝐿𝐸𝑝
𝐷𝐸 𝑛
𝐿𝐸 𝑛 𝑛𝐸 𝑝 𝑊𝑏 −1 𝑛𝐸 𝑝 𝑛𝐵 𝑛
=[1 + 𝐷𝐵 𝑝
𝑡𝑎𝑛ℎ ] (𝑢𝑠𝑒 = )
𝐿𝑝 𝑝𝐵 𝑛 𝑝𝐸 𝑝
𝐿𝐵 𝑝 𝑝𝐵 𝑛
18.13×1.08×10−2×1015
𝛾=[1 + 𝑡𝑎𝑛ℎ9.26 × 10−3 ]−1 = 0.99885
11.66×1.35×10−3×1017
𝑊𝑏
B= 𝑠𝑒𝑐ℎ = 𝑠𝑒𝑐ℎ9.26 × 10−3 = 0.99996
𝐿𝑝
𝛼 = 𝛽 = (0.99885)(0.99996) = 0.9988.
𝛼 0.9988
𝛽= = = 832.
1−𝛼 0.0012