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4-1 MOV Revisited: Chapter 4: Data Movement Instructions

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4-1 MOV Revisited: Chapter 4: Data Movement Instructions

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Chapter 4: Data Movement Instructions

4–1 MOV Revisited


• In this chapter, the MOV instruction introduces
machine language instructions available with
various addressing modes and instructions.
• It may be necessary to interpret machine
language programs generated by an
assembler.
• Occasionally, machine language patches are
made by using the DEBUG program available
with DOS and Visual for Windows.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey

١
Machine Language
• Native binary code microprocessor uses as its
instructions to control its operation.
– instructions vary in length from 1 to 13 bytes
• Over 100,000 variations of machine language
instructions.
– there is no complete list of these variations

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Figure 4–1 The formats of the 8086–Core2 instructions. (a) The


16-bit form and (b) the 32-bit form.

– 80386 and above assume all instructions are 16-


bit mode instructions when the machine is
operated in the real mode (DOS).
– in protected mode (Windows), the upper byte of
the descriptor contains the D-bit that selects either
the 16- or 32-bit instruction mode
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٢
The Opcode
• Selects the operation (addition, subtraction,
etc.,) performed by the microprocessor.
– either 1 or 2 bytes long for most instructions
• Figure 4–2 illustrates the general form of the
first opcode byte of many instructions.
– first 6 bits of the first byte are the binary opcode
– remaining 2 bits indicate the direction (D) of the
data flow, and indicate whether the data are a
byte or a word (W)

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Figure 4–2 Byte 1 of many machine language instructions,


showing the position of the D- and W-bits.

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٣
Figure 4–3 Byte 2 of many machine language instructions,
showing the position of the MOD, REG, and R/M fields.

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Barry B. Brey

MOD Field
• Specifies addressing mode (MOD) and
whether a displacement is present with the
selected type.

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٤
Register Assignments

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Figure 4–4 The 8BEC instruction placed into bytes 1 and 2 formats from Figures 4–2
and 4–3. This instruction is a MOV BP,SP.

– the opcode is 100010, a MOV


instruction

– D and W bits are a logic 1, so a word moves into


the destination register specified in the REG field
– REG field contains 101, indicating register BP, so
the MOV instruction moves data into register BP

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Barry B. Brey

٥
R/M Memory Addressing
• Table 4–4 lists the memory-addressing modes
for the R/M field when MOD is a 00, 01, or 10
for the 16-bit instruction mode.

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Figure 4–5 A MOV DL,[DI] instruction converted to its machine


language form.

• This instruction is 2 bytes long and has an opcode


100010, D=1 (to REG from R/M), W=0 (byte),
MOD=00 (no displacement), REG=010 (DL), and
R/M=101 ([DI]).
• If the instruction changes to MOV DL, [DI+1], the
MOD field changes to 01 for 8-bit displacement
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٦
4–3 LOAD EFFECTIVE ADDRESS
• LEA instruction loads any 16-bit register with
the offset address
– determined by the addressing mode selected
• LDS and LES load a 16-bit register with offset
address retrieved from a memory location
– then load either DS or ES with a segment
address retrieved from memory

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Load-effective address instructions

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٧
LDS, LES, and LSS
• Load any 16- or 32-bit register with an offset
address, and the DS, ES, or SS segment
register with a segment address.

• Figure 4–17 illustrates an example LDS


BX,[DI] instruction.

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Figure 4–17 The LDS BX,[DI] instruction loads register BX from addresses 11000H
and 11001H and register DS from locations 11002H and 11003H. This instruction is
shown at the point just before DS changes to 3000H and BX changes to 127AH.

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٨
4–4 STRING DATA TRANSFERS

• Five string data transfer instructions: LODS,


STOS, MOVS, INS, and OUTS.
• Each allows data transfers as a single byte,
word, or double word.
• Before the string instructions are presented,
the operation of the D flag-bit (direction), DI,
and SI must be understood as they apply to
the string instructions.

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The Direction Flag


• The direction flag (D, located in the flag
register) selects the auto-increment or the
auto-decrement operation for the DI and SI
registers during string operations.
– used only with the string instructions
• The CLD instruction clears the D flag and the
STD instruction sets it .
– CLD instruction selects the auto-increment mode
and STD selects the auto-decrement mode

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Barry B. Brey

٩
DI and SI
• During execution of string instruction, memory
accesses occur through DI and SI registers.
– DI offset address accesses data in the extra
segment for all string instructions that use it
– SI offset address accesses data by default
in the data segment
• Operating in 32-bit mode EDI and ESI
registers are used in place of DI and SI.
– this allows string using any memory location in
the entire 4G-byte protected mode address space
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LODS
• Loads AL, AX, or EAX with data at segment
offset address indexed by the SI register.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,


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١٠
Figure 4–18 The operation of the LODSW instruction if DS=1000H, D=0,11000H,
11001H = A0. This instruction is shown after AX is loaded from memory, but before SI
increments by 2.

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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey

STOS
• Stores AL, AX, or EAX at the extra segment
memory location addressed by the DI register.
• STOSB (stores a byte) stores the byte in AL
at the extra segment memory location
addressed by DI.(DI=DI±1)
• STOSW (stores a word) stores AX in the
memory location addressed by DI.(DI=DI±2)
• After the byte (AL), word (AX), or doubleword
(EAX) is stored, contents of DI increment or
decrement.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey

١١
MOVS
• Transfers a byte, word, or doubleword from
data segment addressed by SI to extra
segment location addressed by DI.
– pointers are incremented or decremented, as
dictated by the direction flag
• Only the source operand (SI), located in the
data segment may be overridden so another
segment may be used.
• The destination operand (DI) must always be
located in the extra segment.

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Barry B. Brey

• The only memory‐to‐memory transfer


allowed.
• MOVSB transfers byte from data segment
to extra segment.
• MOVSW transfers word from data
segment to extra segment.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,


Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
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Barry B. Brey

١٢
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey

INS
• Transfers a byte, word, or doubleword of data
from an I/O device into the extra segment
memory location addressed by the DI register.
– I/O address is contained in the DX register
• Useful for inputting a block of data from an
external I/O device directly into the memory.
• One application transfers data from a disk
drive to memory.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,


Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey

١٣
• Three basic forms of the INS.
• INSB inputs data from an 8-bit I/O device and
stores it in a memory location indexed by SI.
• INSW instruction inputs 16-bit I/O data and
stores it in a word-sized memory location.
• INSD instruction inputs a doubleword.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,


Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,


Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey

١٤
OUTS
• Transfers a byte, word, or doubleword of data
from the data segment memory location
address by SI to an I/O device.
– I/O device addressed by the DX register as with
the INS instruction
• OUTSB
• OUTSW
• OUTSD
• INS and OUTS instructions not available on
8086/8088microprocessors.
The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,
Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,


Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Copyright ©2009 by Pearson Education, Inc.
Architecture, Programming, and Interfacing, Eighth Edition Upper Saddle River, New Jersey 07458 • All rights reserved.
Barry B. Brey

١٥

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