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    6 lpc2103 SPI

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    Khải Nguyễn
    The document discusses SPI (Serial Peripheral Interface) bus timing and modes, and describes the SPI registers and functions on the LPC2103 microcontroller, including the SPCR control register, SPSR status register, SPDR data register, SPCCR clock control register, and SPINT interrupt flag register.

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    6 lpc2103 SPI

    Uploaded by

    Khải Nguyễn
    13 views11 pages
    The document discusses SPI (Serial Peripheral Interface) bus timing and modes, and describes the SPI registers and functions on the LPC2103 microcontroller, including the SPCR control register, SPSR status register, SPDR data register, SPCCR clock control register, and SPINT interrupt flag register.

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    6_lpc2103_SPI

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    The document discusses SPI (Serial Peripheral Interface) bus timing and modes, and describes the SPI registers and functions on the LPC2103 microcontroller, including the SPCR control register, SPSR status register, SPDR data register, SPCCR clock control register, and SPINT interrupt flag register.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    13 views11 pages

    6 lpc2103 SPI

    Uploaded by

    Khải Nguyễn
    The document discusses SPI (Serial Peripheral Interface) bus timing and modes, and describes the SPI registers and functions on the LPC2103 microcontroller, including the SPCR control register, SPSR status register, SPDR data register, SPCCR clock control register, and SPINT interrupt flag register.

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    © All Rights Reserved
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    4.4.

    Thiết kế các thành phần cơ


    bản của bộ xử lý nhúng
    (datasheet LPC2103)
    + SPI
    SPI BUS
    • Clock and data lines shared between devices
    • Independent «slave select» lines: one per slave device
    • Clock signal generated by master
    SPIbus timing (POL=0, PHA=0) SPImode 0

    • Both in master and slave:


    – Output signals change on falling SCKedges.
    – Input signals are sampled on rising SCKedges
    – D7 is valid as soon as /SS is low. No SCKedge needed
    SPIbus timing (POL=0, PHA=1) SPImode 1

    • Both in master and slave:


    – Output signals change on rising SCK edges.
    – Input signals are sampled on falling SCK edges
    – D7 is valid after the first SCK edge
    SPIbus timing (POL=1, PHA=0) SPImode 2

    • Both in master and slave:


    – Output signals change on rising SCK edges.
    – Input signals are sampled on falling SCK edges
    – D7 is valid as soon as /SS is low. No SCK edge needed
    SPIbus timing (POL=1, PHA=1) SPImode 3

    • Both in master and slave:


    – Output signals change on falling SCK edges.
    – Input signals are sampled on rising SCK edges
    – D7 is valid after the first SCK edge
    LPC2xxx SPI. Registers
    • Replace “x” with the SPI port number (i.e. 0 for SPI0 and so
    on)
    • The SSPperipheral can also operate in SPI mode, but it is a
    different and more versatile synchronous serial port.
    • All registers are addressable as 32-bit words.
    Register Access Function
    SxSPCR R/W Control Reg.
    SxSPSR RO Status Reg.
    SxSPDR WR Data TX
    RD Data RX
    SxSPCCR R/W Clock Control Reg.
    SxSPINT R/W Interrupt Flag
    LPC2xxx SPI. SxSPCR(Control Reg.)
    • Master mode: SCK and MOSI are outputs. MISO is input. /SS not
    used (usually programmed as GPIO) or input (see mode fault,
    next slide). Timing generated internally.
    • Slave mode: SCK, MOSI and /SS are inputs. MISO is output. Timing
    controlled by SCK.
    Bit Symbol meaning
    2 BitEnable 0 = 8-bit transfer 1 = variable length
    3 CPHA Clock phase (SPI mode)
    4 CPOL Clock polarity (SPI mode)
    5 MSTR 0 = Slave 1 = Master
    6 LSBF 0 = MSB first 1 = LSBfirst
    7 SPIE 0 = INT disabled 1 = INT enabled
    11:8 BITS Transfer Length (1000=8,… 1111=15, 0000=16)
    rest reserved Do not write “1” to reserved bits
    LPC2xxx SPI. SxSPSR(Status Reg.)
    • Slave abort happens if /SS is raised before the end of the data
    • Mode fault happens on a Master SPI if /SS is forced low externally (another master
    is selecting us). This should never happen in a properly designed system. Also, /SS is
    seldom used in a master, with /SS usually being programmed as GPIO
    • Read overrun happens if data is received while SPIF is high (old data already in
    the buffer)
    • Write collision happens if SxSPDRis written while a transfer is in progress (no
    buffer for TX)
    • SPIF is not the interrupt flag (see SxSPINT)
    Bit Symbol Meaning Action to clearbit
    3 ABRT 1= Slave abort Read SxSPSR
    4 MODF 1= Mode Fault Read SxSPSR+ write SxSPCR
    5 ROVR 1=Read Overrun Read SxSPSR
    6 WCOL 1=Write Collision Read SxSPSR+ R/W SxSPDR
    7 SPIF 1=SPI transfer complete Flag Read SxSPSR+ R/W SxSPDR
    LPC2xxx SPI. Other Registers
    • SxSPDR:Dataregister.
    • Up to 16 bit long
    • A write to SxSPDRstarts atransfer.
    • After the transfer is complete (SPIF=1), SxSPDRcontains the data sent
    from the other device.
    • SxSPCCR:Clock Counter register.
    • 8-bit clock frequency divider
    • Fsck=PCLK/SxSPCCR
    • Only even values ≥8 are valid
    • SxSPINT: Interrupt Flagregister.
    • Bit 0: Interrupt flag. When set it request an interrupt to the VIC
    • Set when SPIF=1 (transfer complete) or WCOL=1 (writecollision)
    • Cleared by writing an 1 to this bit. (It has to be done in the interrupt
    routine)
    Example

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