Memory Organization

Memory Organization
Module-IV
Sridhar,CSE,BIT Mesra
Memory
• The topics to be discussed in this chapter aid
programmers by creating the illusion of
unlimited fast memory.
• Principle of locality
CONT.
Memory Technologies
• Semiconductor
Registers,SRAM,DRAM,FLASH {all Random Access}
• Magnetic {all Random +sequential}

FDD,HDD
•Optical
CD
DVD
Memory Hierarchy Analysis
• Memory
• Capacity
• Unit cost
• Total cost
• Access time
• Hit ratio
• Effective time
https://networkinterview.com/sram-vs-dram/
Cache memory
• How do you know if the data item is in the cache?
• If it is how do we find it?
• If each word can go in exactly one place in the cache, then it is
straightforward to find the word if it is in the cache.
• The simplest way to assign a location in the cache for each
word in the memory is to assign the cache location based on
the address of the word in the memory.This cache structure is
called direct mapped,since each memory location is mapped
directly to exactly one location in the cache
Direct-Mapped Cache
Direct Mapping
• If the entries in the cache is a power of two,the modulo can
be computed simply by using the lower order
log2(𝑐𝑎𝑐h𝑒 𝑠𝑖𝑧𝑒 𝑖𝑛 𝑏𝑙𝑜𝑐𝑘𝑠) bits of the address;hence the
cache may be accessed directly with the lower-order bits.
• Because each cache location can contain the contents of a
number of different memory locations,how do we know
whether the data in the cache corresponds to a requested
word?(i.e how do we know that the requested word is in
cache or not?)
• Answer: adding a set of tags to the cache.The tags(upper
portion of the address) contains the address information
required to identify whether a word in the cache corresponds
to the requested word.
• Valid bit:When a processor starts up the cache does not have
good data and the tag fields will be meaningless.
• Even after executing many instructions, some of the cache
entries may still be empty, thus the tag for such entries to be
ignored.
• The most common method is to add a valid bit to indicate
whether an entry contains a valid address.
Accessing a cache
• When the word at the address 18(10010) is brought into the
cache block 2 ,the word at 26(11010) replaced
All direct mapped caches use the mapping
Cache access mechanism
Cache with four words
Direct-mapped cache
Main Memory Cache Memory
Memory address Data

00000 1220 Index Tag Data
address
000 00 1220
00777 2340
01000 3450
777 02 6710
01777 4560
02000 5670
02777 6710
• The disadvantage of direct mapped cache is that the hit ratio
can drop considerably it two or more words whose addresses
have the same index but different tags are accessed
repeatedly.But this possibility is minimized by the fact that
such words are relatively far apart in the address range.
direct mapped cache with block
size of 8 words(512 word cache)
index tag data
000 01 3450
block0 007 01 6578

010
Tag Block word
block1
017 index
.
.
block 63 770 02
777 02 6710
• Disadvantage of direct mapping is that two
words with the same index in their address
but with different tags cannot reside in cache
memory at the same time.
• Improvement :Set Associative Mapping
Two-way Set Associative Mapping
Index Tag Data Tag Data

000 01 3450 02 5670
777 02 6710 00 2340

• The hit ratio will improve as the set size increases because
more words with same index but different tags can reside in
cache.An increase in the set size increases the number of bits
in words of cache and requires more complex comparison
logic.
• For replacement when miss occurs uses FIFO,LRU,random
replacement algorithms.
1.No of blocks=Cache size/block size= 2^12,
Byte Offset=32 B=5 bits
No of sets=No of blocks/associative=2^10,setoffset=10 bits,Tag=32-10-5=17
2.Tag Dir size=2^12 X Tag bits
Transfering blocks to/from memory
Designing the memory system to support
the cache
Intrinsity FastMATH Processor
• Intrinsity FastMATH Processor: It is a fast embedded
microprocessor that uses the MIPS architecture and a simple
cache implementation.
• This processor has a 12 stage pipeline. when operating at

peak speed the processor can request both an instruction
word and data on every clock cycle.To satisfy the demands of
the pipeline without stalling,separate instruction and data
caches are used.Each cache is 16KB,or 4K words,with 16 word
blocks
Measuring and improving the cache
performance
• Two different techniques for improving cache
performance:
)Reduce the miss rate by reducing the
probability that two different memory bocks will
contend for the same cache location.
2)Reduce the miss penalty by adding an
additional level to the hierarchy.(multilevel
caching)
• A computer system has an L1 cache ,an L2 cache, and a main
memory unit connected and at time 4 words can be
transferred through data bus.The block size in L1 cache is 4
words .The block size in L2 cache is 16 words. The memory
access times are 2 ns, 20ns and 200 ns for L1 ,L2 and main
memory unit respectively.
• i)When there is a miss in L1 cache and a hit in L2 cache,a block
is transferred from L2 cache to L1 cache. What is the time
taken for this transfer?
• ii)When there is a miss in both L1 and L2,first a block is
transferred from main memory to L2 and then L2 to
L1.What is the total time taken for these transfers?
• A computer has a memory unit of 64K X 16
and a cache memory of 1K words.The cache
uses direct mapping with a block size of four
words. The number of bits in the
tag,index,block,word field and number of
blocks is respectively:
Calculating Cache Performance
• Let us Speed up the computer by reducing CPI from 2 to 1
without changing the clock rate,which might be done with
improved pipeline:
Cache performance with increased clock ra
Locating block in a cache
Sizes of tags vs set associativity
Choosing which block to replace
• Commonly used scheme:LRU

• As associativity increases ,implementing LRU
gets harder
Performance of multilevel caches

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Memory Organization

• Magnetic {all Random +sequential}

Memory address Data

block0 007 01 6578

Index Tag Data Tag Data

777 02 6710 00 2340

• This processor has a 12 stage pipeline. when operating at

• Commonly used scheme:LRU

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