Serdes Design and Modeling Over 25 GB S Serial Link

44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA
SerDes Design and Modeling over 25+ Gb/s Serial Link

Pervez M. Aziz pervez.aziz@lsi.com
Adam Healey adam.healey@lsi.com
Cathy Liu cathy.liu@lsi.com
Freeman Zhong freeman.zhong@lsi.com
Alex Zabroda alex.zabroda@lsi.com
LSI Corporation
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Abstract
In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy
environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced
equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced
signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation
systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level
circuit simulation are also discussed.
Key words: SerDes, DFE, Modulation, FEC, DSP, integrity challenges such as high insertion loss, low
ADC, Modeling return loss, crosstalk and noise, high speed circuit
design at 25-28 Gb/s, and technology limitations. Fig.
1. Introduction 4 is the frequency response of channel A, which were
considered as reference channel models for a 25-28
Future data center needs require 100 Gb/s Gb/s system. At the fundamental frequency for a
Ethernet (100GbE) connectivity to meet the 25.78125 Gb/s signaling rate (12.9 GHz), the LR
increasing set of applications and bandwidth which channel loss is about 30 dB dB and the insertion loss
commands System on chip (SoCs) to drive hundreds to crosstalk ratio (ICR) is only 14 dB.
of Gb/s links within and outside the system. This
paper focuses on solutions for signal integrity To overcome such high channel loss and noisy
challenges within the SoCs. environment, serializer/deserializer (SerDes) need to
implement a significant amount of equalization to
Today’s 100GbE interface is based on the achieve operation at a low bit error ratio (BER), e.g.
aggregation of 10 lanes with each lane’s data rate of 10-18 or below. Multi-tap decision feedback
10.3125 Gb/s. To create higher density and lower equalization (DFE) has been used in most SerDes
cost system, systems are looking at 4 lanes of 25 Gb/s receivers to mitigate inter-symbol interference (ISI)
(4 x 25 Gb/s) to support 100GbE. The IEEE 802.3TM over lossy channels at link rates of 10 Gb/s or higher.
Ethernet Working Group has recently established a However, DFE error propagation caused by decision
new task force to consider this problem. Other feedback nature has been a point of concern as well
industry standard bodies are also merging their next as design challenges at 25-28 Gb/s link rates .
technology points to a common infrastructure of 25- Alternative signaling beyond NRZ such as PAM-4
28G Gb/s serial electrical links such as the OIF and advanced signal processing such as floating tap
Common Electrical I/O (CEI), INCITS T11 Fibre DFE and forward error correction (FEC) coding are
Channel 32GFC, and Infiniband EDR. investigated in Section 2 to address above challenges.
Furthermore, low power and high speed interleaved
1.1. 4 x 25 Gb/s Interface Challenges ADC technology enables digital signal processing
(DSP) architecture to extend equalization capability.
With the link rate increasing to 25-28 Gb/s, This will be discussed in Section 3.
serial link systems need to address multiple signal
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With the complexity growth in SerDes N

architecture and circuit implementation, accurate w(n) = y (n) − ∑ b(l )v(n − l ) Eq 2-1
behavioral modeling methodology is another chapter l =1
to explore. In Section 4, a circuit-level (RTL and
SPICE) correlated behavioral modeling methodology This has been the traditional DFE architecture used in
is explained and followed by simulation results. most Serdes links. Taps l=1 through N are chosen to
cancel the post-cursor inter symbol interference (ISI)
2. Advanced Equalization and Signal Processing from the equalized pulse shape corresponding to the
AEQ output.

Many technical challenges for high-speed serial
link design remain unsolved [1][2][3]. At rates as Device package/terminations are not shown
high as 25 to 28 Gb/s, the receiver is required to explicitly for simplicity but can be properly
recover the signal properly in environments where embedded in the channel model by concatenating the
the channel insertion loss and noise are high (e.g. S parameter response of the physical transmission
insertion loss at the fundamental frequency larger medium with the S parameter response of the
than 30 dB and insertion loss to crosstalk ratio less package/terminations. The upper path of Fig. 1 is for
than 15 dB). The major challenge is how to the normal transmission path. The lower paths on the
efficiently improve SNR further than existing left side of the figure represent the various crosstalk
equalization schemes like continuous time linear paths which impair the through path. Various other
equalizer (CTLE) and fixed-tap decision feedback impairments are also modeled and shown in the block
equalizer (DFE). diagram: TX duty cycle distortion (DCD) injected on
the TX signal, AEQ output referred noise, sinusoidal
2.1. System Architecture Model and random jitter in the sampling of the received
signal. We analyze the system performance for the
In this section we examine advanced link described in Fig. 1 using a methodology similar
equalization schemes within the paradigm of today’s to that described in [3]. First equalizer parameters
NRZ signaling format. Before describing specific such as the TX tap values, VGA gain, AEQ peaking,
equalization architectures, let us first examine a and DFE tap values are optimized to minimize the
generic system analysis block diagram and model of minimum mean square error (MMSE) or MMSE
the Serdes link. Fig. 1 shows a block diagram of the derived metrics at the input to the DFE slicer. With
system including transmitter (TX), channel, and this set of optimum equalizer parameters, the
receiver (RX). The TX provides equalization using a equalized waveform can be obtained at the input to
3 tap finite impulse response (FIR) filter consisting of the DFE slicer. Statistical post-processing of this
pre-cursor, main-cursor, and post-cursor taps c(-1), waveform is done in a manner similar to that of [3] to
c(0), c(1) respectively. The receiver consists of a incorporate the effects of impairments such as cross
variable gain adjustment circuit (VGA), analog talk, noise, and jitter. The final result is a statistical
equalizer (AEQ) and decision feedback equalizer eye diagram which quantifies the vertical and
(DFE). The VGA maintains the signal level such that horizontal margins at various symbol error rates. Fig.
the mean equalized signal at the input of the DFE 2 shows an example eye diagram. The system model
slicer is at a desired target value. The VGA has some also produces an equalized pulse shape which
nominal operating range such as -8 dB to +8 dB. The represents the inter symbol interference terms at the
AEQ provides high frequency peaking / boosting and AEQ output.
works in conjunction with the DFE. The AEQ
transfer function is of the form in [4] and provides up 2.2 Advanced DFE Architectures
to 12dB of peaking for the scope of this paper. Let
y(t) be the input to the DFE from the output of the We now consider two advanced DFE
analog front end. The DFE equalized signal is then architectures which can enhance the performance of
w(t) which is the DFE input from which the DFE the standard DFE system and are useful components
feedback terms are subtracted. Let w(n) be the of the equalization solution space which can address
sampled version of the DFE equalized signal. The 25 Gb/s and higher operation.
DFE operation can then be described by Eq 2-1
where N is the number of DFE taps and b(l) are the 2.2.1 Floating Tap DFE
DFE tap weights or values.
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The first architecture is what is known as z (t ) = y (t ) − g v(n − L) exp(−t / τ ) Eq 2-3

floating tap architecture [5] where the DFE consists
of a fixed number of taps N as before. In addition, N
w(n) = z (n) − ∑ b(l )v(n − l ) − Eq
there are additional ‘floating taps’ which provide ∑ b(l )v(n − l ) 2-4
feedback correction at locations which can be at l =1 l =l 1,l 2 ,l 3,l 4
arbitrary positions away from the main tap. This

architecture is particularly suited to channels which A block diagram showing additional paths for
contain substantial reflections in the equalized pulse floating tap DFE feedback and IIRDFE is shown in
shape. Reflections which occur far away from the Fig. 3.

main tap can still be cancelled by the DFE without
the need for a full fledged DFE with the same 2.3 Channel Models
number of taps as the furthest reflection. The floating
tap DFE is described in Eq 2-2 for the example of a 4 We consider several backplane channels which
floating tap DFE where floating tap locations are at are targeted for a 25.78125 Gb/s system. The Nyquist
l=l1,l2,l3,l4. or fundamental frequency is 12.9GHz. In addition,
we consider a relatively smooth channel to show the
N
Eq effectiveness of IIRDFE.
w(n) = y (n) − ∑ b(l )v(n − l ) − ∑ b(l )v(n − l )
l =1 l =l1,l 2 ,l 3,l 4 2-2
Figs 4-7 show the magnitude spectra of several
channels. The blue solid curves show the insertion
This is shown in Eq. 2-2 where the first summation
loss spectra and the blue dashed curves the return loss
represents the contributions from the fixed DFE taps
spectra. The red curves show the cross talk responses.
and the second summation represents the contribution
Channel A is a high loss channel with 30dB insertion
from the 4 floating taps at floating tap positions l1, l2,
loss at the Nyquist frequency. The cross talk is
l3, l4. The floating tap positions are optimized by
significant with insertion loss to cross talk ratio (ICR)
examining the equalized pulse shape in the context of
at the Nyquist frequency being only 13 dB. Channel
the system analysis framework above.
B has a bit lower insertion loss, 26dB insertion loss at
Nyquist. However, the cross talk is still significant
2.2.2 Infinite Impulse Response DFE (IIRDFE)
with an ICR of 13 dB. Channel C has 22dB insertion
loss and a more relaxed ICR. However, the channel
The second architecture is an infinite impulse
spectrum is not as smooth as the other channels and
response DFE (IIRDFE). This architecture is
the resulting time domain response will contain a
particularly suited to cancelling ISI from channels
relatively large number of reflections as we will
whose loss profile is relatively smooth and whose
observe through the equalized pulse shape. Finally,
corresponding equalized pulse shape decays in a
channel D is a smooth channel which has about 27
smooth fashion over at least some region. For the
dB insertion loss at the Nyquist frequency.
IIRDFE portion, the DFE decision is fed back with
some decision delay, L, and is processed by a low-
2.4 Simulation Analysis Results
pass filter with some gain and time constant before
being subtracted from the AEQ output. A single first
We now examine the performance of the various
order low-pass filter corresponds to an exponential
channels with the standard DFE and advanced DFE
decay in the time domain with time constant τ. This
architectures. Table 1 lists the impairment parameters
scheme is similar to the continuous time feedback
used for the simulations.
DFE (CTDFE) [6] and [7]. Note that here although
Table 1: Simulation parameters
the low-pass filter is a continuous time filter, the
TX Launch 800mV diff p2p (400mV diff pk)
feedback driving the filter is synchronous to the DFE
TX DCD 0.035T p2p
decision with some delay of L baud symbols. Eq 2-3
describes the IIRDFE operation, with z(t) being the TX SJ 0.105T p2p
difference of the AEQ output and the IIRDFE output. TX RJ 310fs r.m.s.
Test pattern CLS52TP2 (from IEEE 802.3AP
The IIRDFE filter time constant is τ. The signal z(t) standards) – pattern is
can be further equalized by the fixed DFE feedback representative of 64B/66B encoding
section and floating tap DFE as before and as shown TX/RX LSI package model added
in Eq 2-4.
Package
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Termination RC model similar to that of Channel A. Although the insertion

Symbol rate 25.78125 Gb/s loss is several dB lower, the performance of this
channel is not necessarily significantly better as other
Table 2: Channel A simulation results impairments such as cross talk and jitter dominate the
BER Target 10-18 BER Target 10-12 overall performance. The equalized pulse shape is
DFE Vert. Horiz. Vert. Horiz. similar to that of channel A.
Architecture Margin Margin Margin Margin
Choice Table 4: Channel C simulation results
Fixed 6 tap 52 0.24 70 0.32 BER Target 10-18 BER Target 10-12

DFE DFE Vert. Horiz. Vert. Horiz.
Fixed 10 tap 62 0.3 80 0.36 Architecture Margin Margin Margin Margin
DFE Choice
Fixed 6 + 64 0.3 82 0.36 Fixed 6 tap 42 0.16 62 0.22
Floating 4 DFE
Tap DFE Fixed 10 tap 46 0.20 68 0.26
DFE
Table 2 shows the performance of channel A Fixed 6 + 60 0.22 80 0.28
which is the 30 dB loss channel. In Tables 2-5, Floating 4
vertical margin values are reported as mV differential Tap DFE
peak to peak and horizontal margin values are
reported as T peak to peak. With a fixed tap DFE we Table 4 shows the performance of Channel C.
obtain 52mV and 0.24T vertical and horizontal Even though the Nyquist insertion loss for this
margins respectively at 10-18 error rate. The margins channel is only 22 dB, fixed 6 tap DFE or 10 tap DFE
are better at 10-12 error rate. The use of a fixed 10 tap yield considerably worse performance than either
DFE can provide modest improvements to the Channel A or B. This is due to the significant number
performance margins, achieving 62mV and 0.3T of reflections as see in the impulse response and also
vertical/horizontal margin. Applying 4 floating taps the equalized pulse shape shown in Fig. 9. The fixed
in addition to 6 fixed taps also provides modest 6 tap DFE with 4 floating taps in this case provides a
performance improvement, achieving 64mV and 0.3T much bigger improvement in performance over a
margins. However, note that the performance of the fixed DFE. This is consistent with the fact that the
fixed 10 taps and the fixed 6 + 4 floating taps are equalized pulse shape as shown in Fig. 9 displays
comparable. This is not surprising based on the larger values beyond even tap position 10.
equalized pulse shape shown in Fig. 8 where the
green circles represent the fixed and floating tap For channels A, B, and C the use of IIRDFE in
positions chosen. It is clear that three of the four addition to a fixed 6 tap DFE was attempted to
higher magnitude taps already fall within 10 taps of determine whether or not it could improve the results
the pulse main cursor position at time index 0. beyond the fixed 6 DFE taps. The improvements
were extremely small aligned with the fact that there
Table 3: Channel B simulation results is no section of the equalized pulse shapes of Figs 8-9
BER Target 10-18 BER Target 10-12 which can be totally cancelled by a smooth
DFE Vert. Horiz. Vert. Horiz. exponential IIRDFE feedback term.
Architecture Margin Margin Margin Margin
Choice The conclusions regarding IIRDFE are; however,
Fixed 6 tap 55 0.26 76 0.32 quite different when we consider channel D. Table 5
DFE shows the results for channel D. In this study, we
Fixed 10 tap 68 0.28 86 0.34 examine the benefits of IIRDFE in the presence of
DFE weaker equalization from the RX analog equalizer
Fixed 6 + 68 0.3 86 0.36 and DFE. Here the RX AEQ is constrained to provide
Floating 4 only several dB of peaking at the Nyquist frequency.
Tap DFE With this constrained AEQ and only a 2 tap DFE the
performance is very poor: 8mV and 0.18T margins.
Table 3 shows the performance of channel B A fixed 6 tap DFE improves it significantly;
which is the 26 dB loss channel – here the trends are achieving margins of 30mV and 0.24T. A DFE with
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6 fixed taps and 4 floating taps achieves significantly format and analog based DFE receiver might not be
better performance of 56mV and 0.34T. However, an good enough to support XLR applications with large
only 2 tap DFE in conjunction with IIRDFE can channel loss beyond 35dB in terms of performance
perform nearly as well as the floating tap DFE! The and design limitations. People agree that NRZ is a
addition of more fixed DFE taps in the presence of good signaling format for 10 Gb/s links. Thus 10
IIRDFE improves performance slightly over the 2 Gb/s serial Ethernet operation over Electrical
fixed tap + IIRDFE case as shown in the last row of Backplanes (10GBASE-KR) specified NRZ signaling
Table 5. format to support about 24dB channel loss at 5GHZ.
If simply scaling 10 Gb/s link to 25 Gb/s, the channel

Table 5: Channel D simulation results. Analog loss could be easily over 35dB. As will be discussed
equalizer constrained to provide only several dB in 2.5.1, analysis shows that multi-level signaling like
of peaking at Nyquist. PAM-4 outperforms NRZ especially for XLR
BER Target 10-18 BER Target 10-12 applications when channel loss beyond 35dB. Two
DFE Vert. Horiz. Vert. Horiz. solution spaces to address XLR application
Architecture Margin Margin Margin Margin challenges, alternative signaling and advanced FEC
Choice schemes will be studied in following sub sections.
Fixed 2 tap 8 0.18 22 0.22
DFE 2.5.1. Multi-level Modulation
Fixed 6 tap 30 0.24 42 0.28
DFE Next generation systems can reduce printed
Fixed 6 + 56 0.34 70 0.40 circuit board (PCB) trace lengths or use improved
Floating 4 materials to enable non-return-to-zero (NRZ)
Tap DFE modulated backplane links at 25 Gb/s. However, such
Fixed 2 + 52 0.32 63 0.37 measures can prove to be costly or impose unwanted
IIRDFE constraints on the system topology. Furthermore, the
Fixed 6 + 56 0.34 68 0.40 ability to extend the life of a backplane designed to
IIRDFE support 10 Gb/s is likely to be highly valued.
We found that Channels A & B achieve In the latter case, these so-called legacy channels
reasonable performance with the use of 10 fixed DFE can exhibit insertion losses much greater than 30 dB
taps. Channel C which is highly reflective requires at 12.9 GHz. This frequency is significant because it
the use of a floating tap DFE to not be performance is the approximate fundamental frequency for a 25
limited with only fixed taps. For these channels Gb/s link encoded with the 64B/66B block code
IIRDFE did not yield any noticeable performance (3.125% protocol overhead) which is used by a
benefits. However, in the case of the smooth channel number of industry standards. The recovery of NRZ
D, IIRDFE could achieve good performance with modulated signals by a receiver in such an
very few DFE taps. It is clear that the architecture environment is a very challenging task. Instead, it is
choice which achieves reasonable performance can worthwhile to consider increasing the modulation
be dependent on the class of channels it is required to efficiency (encode multiple bits per transmitted
operate with. Thus the architecture choice should be symbol) and reduce the symbol rate such that the
made with this consideration as well as area/power channel impairments are reduced. The simplest
tradeoffs. From an area/power standpoint, IIRDFE is extension of NRZ modulation is multi-level pulse
the lowest cost solution, followed by an architecture amplitude modulation (PAM).
requiring more fixed taps. A floating tap DFE is
requires the highest area / power. The use of In order to investigate the merits of this approach,
additional DFE taps or the use IIRDFE or floating tap four backplane channels are considered [8]. The
DFE are all architecture tools which can be employed backplane channels are indexed 1 through 4 and have
with the proper performance / area / power tradeoff. insertion losses of approximately 25, 30, 35, and 40
dB respectively at 12.9 GHz. The channel SDD21
2.5. Extra Long Reach (XLR) Applications magnitudes are shown in Fig. 10. Each channel also
includes 8 far-end crosstalk aggressors. The ICR is
To address challenges for high speed and even shown in Fig. 11.
larger channel loss, the traditional NRZ signaling
2.5.1.1. Probability of Symbol Error
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derived by Salz [9] and given by Eq 2-7. It is an

Consider a serial link utilizing NRZ modulation appropriate upper bound for link performance since
where the distance between symbols is 2d and there the DFE is a staple equalizer architecture for high
is additive white Gaussian noise with standard speed serial links.
deviation σ. The probability of a symbol error is
π
given by Eq 2-5. 1
SNRSalz =
π ∫ 10 log
0
10 ( S hh (θ ) + 1)dθ Eq 2-7
1 ⎛ Q ⎞
Pe = erfc⎜ ⎟ Eq 2-5
2 ⎝ 2⎠

In Eq 2-7, Shh(θ) is the folded SNR spectrum sampled
In Eq 2-5, the variable Q is also referred to as the at the output of at the matched filter once every
signal-to-noise ratio (SNR) and it is defined to be d/σ. symbol period T.
NRZ modulation may also be considered to be 2-
level pulse amplitude modulation (PAM-2). The K
S ff [(θ − 2πk ) 2π T ]
S hh (θ ) = ∑ Eq 2-8
expression for the probability of a symbol error can k =0 S nn [(θ − 2πk ) 2π T ]
be generalized to PAM-L, where L is the number of
amplitude levels, as shown in Eq 2-6.
In Eq 2-8, Sff(θ) is the power spectral density of the
signal at the receiver input, Snn(θ) is the power
L −1 ⎛ Q ⎞ spectral density of the noise at the receiver input, K is
Pe ( L) = erfc⎜⎜ ⎟ Eq 2-6
⎟ the number of times the spectrum is folded, and the
L ⎝ 2 ( L − 1) ⎠
range of θ is [−π, π).
The factor of (L−1)/L is associated with the fact that For a first look at the potential advantages of
the inner symbols in the PAM-L constellation are multi-level signaling, the Salz SNR for each
more prone to error. In addition, the argument of the backplane channel is computed. Device packages and
complementary error function is reduced by a factor on-die terminations are concatenated with each
of 1/(L−1) to account for the reduction in the distance channel prior to the SNR computation. Larger device
between symbols when the peak amplitude d is held packages are considered which introduce
constant. The probability of error for various values approximately 2.5 dB of loss at 12.9 GHz for both
of L is shown in Fig. 12. the transmitter and receiver. The noise power spectral
density includes −150 dBm/Hz of additive white
It is clear that for increasing L, the SNR required Gaussian noise in addition to the crosstalk.
to achieve a target probability for symbol error also
increases. Comparing NRZ modulation and PAM-4, The results in Fig. 13 are presented as margin
one can see that the SNR must be 9.6 dB larger for relative to the SNR required for a symbol error ratio
PAM-4 to achieve the same symbol error probability of 10-12. The advantage of multi-level modulation
as NRZ. However, since each PAM-L symbol can becomes evident for channel 3 and more prominent
convey log2(L) bits of information, the symbol rate is for channel 4 which have insertion losses of
reduced accordingly. approximately of 35 and 40 dB respectively at 12.9
GHz.
It is clear that for PAM-L to have an advantage
of PAM-2, the reduction in symbol rate must yield an These results imply that multi-level modulation
improvement in SNR that overcomes the increased should be considered for higher loss channels. PAM-
SNR requirement for the same symbol error ratio. 3 offers the best performance for these examples but
SNR improvement may be realized in a variety of performance degrades for larger L as the increasing
ways and is not limited to the effective reduction in SNR requirements begin to outweigh any SNR
the channel insertion loss. improvement from operating at the lower symbol rate.
PAM-4 modulation is chosen for subsequent analysis
2.5.1.2. Achievable Signal-to-Noise Ratio since it offers good performance and neatly packs
two bit per symbol.
The maximum achievable SNR at the decision
point of an ideal minimum mean-squared-error 2.5.1.3. Practical Considerations
decision feedback equalizer (MMSE-DFE) was
000049
for the PAM-4 solution is scaled to be half of the

Given that the Salz SNR is a theoretical bound bandwidth of the NRZ CTLE so that less noise is
on performance, practical implementations may only integrated by the receiver.
be expected to approach it and not necessarily
achieve it. Practical considerations that degrade In both cases, the CTLE gain peaking, equalizer
performance include limitations to the equalizer coefficients, and sampling times are chosen to
complexity, timing jitter, latch metastability, and minimize the mean-squared error (or maximize the
quantization error. SNR) at the decision point. The results are
summarized in Fig. 14.

To quantify the magnitude of the performance
degradation, two architectures are considered. The The degradation relative to Salz SNR is
first architecture is based on NRZ modulation. The significant. The SNR degradation for the NRZ
on-die terminations, device packages, and solution is larger than the PAM-4 solution owing to
background noise considered in the Salz SNR the challenges of high-speed design. Equalizer
calculation are also considered here. Equalization is complexity is limited by speed and power
distributed between the transmitter and the receiver. considerations and the impact of jitter, device
The transmitter includes feed-forward equalizer (FFE) packaging, and other impairments is more significant.
with 4 symbol-spaced taps. The receiver includes a Based on the fact that the SNR advantage for PAM-4
continuous time linear equalizer (CTLE) which can grows for increasing channel insertion loss, PAM-4 is
provide up to 10 dB of gain peaking and a 10-tap a superior solution for high loss channels.
DFE. Transmitter timing error includes 780 ps of
even-odd jitter (sometimes referred to as duty cycle 2.5.1.4. Considerations for Forward Error Correction
distortion), and 250 fs of RMS random jitter. The (FEC)
receiver adds another 250 fs of RMS random jitter
and 3.9 ps of peak-to-peak sinusoidal jitter to verify Both the NRZ and PAM-4 solutions fail to
timing margin. To account for latch metastability, a achieve the SNR required for the desired minimum
simple but conservative overdrive model is used. In symbol error probability. The symbol error
this model, the signal must overdrive the threshold by probability for either solution could be improved with
the specified amount for the latch to capture the the application of FEC. One can observe that the
correct result otherwise an error occurs. For this coding gain required for the NRZ solution must be
analysis, the latch overdrive is assumed to be 10% of approximately 5 dB whereas the required coding gain
the target or 0.1d. for the PAM-4 solution is closer to 0.5 dB. This
implies an advantage for PAM-4 even when the
The second architecture is based on PAM-4 with channel impairments require the use of FEC to meet
digital signal processing (DSP). The on-die the error rate objectives.
termination and device packages are again the same.
A more complex receiver may be realized as a result As will be discussed in 2.5.2, FEC codes require
of the reduced symbol rate the DSP-based additional overhead to transport the parity check
architecture. In this case, the receiver includes an symbols. This overhead implies a higher symbol rate
FFE with 8 symbol-spaced taps and a 10-tap DFE. but at the same time higher symbol rates imply more
The receiver analog front-end includes a CTLE, parity check symbols and hence a higher coding gain.
again with 10 dB peaking capability, and an analog- Fig. 15 repeats the experiment of the previous section
to-digital converter (ADC) with 5.2 effective bits for increasing data rates (recall that the symbol rate
(ENOB). The transmitter does not include for PAM-4 is half of the data rate). In each case, one
equalization and latch overdrive requirements are not can see that the SNR degrades by approximately 1 dB
relevant to this architecture. for a 2 Gb/s increase in data rate. The relative SNR
difference is preserved. Naturally, if the coding gain
The additive noise and timing error are identical exceeds the SNR loss due to the required overhead, a
for the two architectures based on the premise that net SNR benefit results.
low noise and low jitter techniques used to realize the
NRZ solution may be leveraged by the PAM-4 For example, considering a strong FEC with 6.5
solution. This means, for example, that the jitter dB coding gain but with overhead such that a data
terms are half as large for the PAM-4 solution rate must increase to 27.8 Gb/s, the net SNR benefit
relative to the symbol period. The CTLE bandwidth is 5.5 dB. For channel 4, this implies that the SNR
000050
margin considering forward error correction could be • Number of information (data) symbols: k=n-2t
as high as 5 dB. • Minimum distance: dmin=2t+1
In general, a t-error-correcting RS can correct a

2.5.2. FEC for 25+Gb/s Serial Link burst error up to (t-1)*m+1 bits or multiple
random/burst errors. Its error correction capability is
To mitigate DFE error propagation and improve much stronger than OIF CEI-P Fire code FEC and
system margin, both the OIF Common Electrical I/O BASE-R QC FEC. Compared with TCM and LDPC
Protocol (CEI-P) and 10GBASE-KR adopted burst FEC schemes, hard decision decoding RS provides

error correcting FEC into their specifications. OIF good tradeoff between coding gain and
CEI-P fire code (1604, 1584) and BASE-R QC code complexity/latency.
(2112, 2080) both belong to shortened cyclic code
family. OIF CEI-P FEC provides correction for a Assume memory-less Binary Symmetric
single 1 to 7 bit burst error in each 1584 bit frame. Channel (BSC) with Gaussian noise, the coding gain
10GBase-KR FEC provides correction for a single 1 of RS codes with different t can be calculated. Two
to 11 bit burst error in each 2080 bit frame and about classes of RS are chosen for this paper with m=8 and
2.5dB random error coding gain [12]. m=10. Both of them are shortened in terms of code
block length to meet the striping principles from
With data rate growth, residual ISI after Gustlin proposal [14]. Fig. 16 showed BER verses
equalization and un-equalizable impairments such as SNR for RS codes with shortened k=208 over GF(28).
crosstalk, far-end reflections, and random jitter We can see that with t=1, RS(210, 208, 1) code has
become the bottleneck to achieve low BER. As a about 2.3dB coding at BER 10-15. To achieve larger
post-processing stage, FEC provides a tradeoff to coding gain of 5dB, t=5 is required. Similarly, Fig. 17
reduce the requirement for a complicated showed another class of RS codes over GF(210) with
equalization and crosstalk cancellation schemes [13]. k=260. Since the code length are comparable, GF(28)
Therefore, to target 4 x 25 Gb/s interface, more RS codes showed the similar coding gain trend as
powerful FEC codes with larger coding gain than GF(210) RS codes.
OIF CEI-P Fire code FEC and BASE-R QC FEC are
demanded. As discussed in 2.5.1.4, with the help of 5dB
coding gain from FEC, larger system margin or
To achieve the most coding gain, soft decision longer channel trace length are expected. On the
decoding FEC and iterative decoding FEC such as other hand, as a post-processing stage FEC is able to
trellis coded modulation (TCM) and low density provide a tradeoff to reduce the front-end design
parity check code (LDPC) have been adopted to complexity and requirement such as reducing DFE
multiple communication systems such as tap numbers and relaxing jitter requirements [13].
telecommunication, wireless and hard disk drive read
channel systems. However, Ethernet tight application 3. Digital Signal Processing (DSP) Based SerDes
requirements such as low coding overhead, low Architecture
encoder/decoder complexity and small
encoder/decoder latency simply make TCM and As we have discussed in Section 2, equalization
LDPC not suitable for 4x25 Gb/s interface complexity growth and multi-level modulation make
application at least with current or near term analog based SerDes architecture become less
technologies. favorable to 25+ Gb/s data rate and XLR application.
Low power and high speed analog-to-digital
Reed-Solomon (RS) codes are the most notable converter (ADC) design combined with DSP-based
single and burst error correction FEC that is widely architecture is becoming more attractive for these
applied in telecommunication systems, especially applications.
computer networks and the Internet. A t-error-
3.1. Analog to Digital Converter (ADC)
correcting RS code with symbols from GF(2m) has
the following parameters: Analog to digital converter (ADC) is one of the
m
most critical components in DSP-base SerDes. The
• Block length: n=2 -1, fundamental challenges are high sampling rate, low
• Number of parity check symbols: n-k=2t
000051
conversion error rate, and low system power is used for the entire ADC to achieve ultra-low power
specification. In order to meet requirements of target consumption. However, new circuit topologies have
data rate, bit error rate, receiver jitter and frequency to be introduced to address design requirements of
offset tolerance, and system power consumption, the bandwidth, linearity and signal-to-noise ratio (SNR)
specification of ADC for this 100G Ethernet of these circuits.
application is tabulated in Table 6.
Conversion error rate of ADC is another critical
Table 6 Specification of 16Gs/s 6bit ADC parameter that impacts bit error rate (BER)
performance of DSP-based SerDes. The target BER

In order cope with these challenges, a four-time of this 25 Gb/s transceiver is 10-17 that requires the
interleaved successive-approximation ADC array is conversion error rate of ADC must be lower than the
proposed as shown in Fig. 18. It consists of an input target BER. The conversion error is typically caused
buffer, 4 interleaved track-hold circuits, 4 sub-ADCs by the metastability of analog circuits, especially
with 32-successive-approximation ADC array, clock comparators in the successive-approximation ADC
generator with phase skew calibration, and array. A comparator with small metastable window
background calibration circuits. and robust metastability detection scheme are
employed in this design to achieve conversion error
The system power budge requires the power rate lower than 10-19.
consumption of entire ADC less than 120mW that
presents huge challenges to the ADC design. The ADC is designed and implemented in
Typically, ultra-high-speed converters utilize either TSMC 28nm CMOS process. Fig. 19 shows the
conversion results with 4GHz sinusoidal input signal
Parameter Min Typ Max Unit at 16G sampling rate, and Fig. 20 shows the its
harmonic distortion spectrum of the entire ADC. The
Resolution 6 bit simulation results over PVT reveal that the ADC
Conversion Rate 2 14 16 Gs/s design meets the target specifications.
Conversion error 3.2. Digital Signal Processing (DSP)
10-19
rate
Power consumption Recent deployments of 10 Gb/s serial links using
@ max frequency digital signal processing (DSP) technology have been
(Typical PV, @ 80o 100 mA enabled by enhancements to analog-to-digital
C ) from 0.85V converter (ADC) performance and the scaling of
supply CMOS technologies. DSP-based receivers have
advantages over their analog counterparts in several
full-flash or time-interleaved architectures. Flash areas. Equalizer structures that are challenging to
ADC exhibits less architectural complexity but large realize in the analog domain have relatively straight-
power consumption, especially, considering the forward digital counterparts. A simple example is the
potential large comparator offsets when implemented feed-forward equalizer (FFE). While this structure is
with small-geometry devices to maximize the circuit realizable in the analog domain, the delay line is
bandwidth in conventional high-speed ADC design. subject to variation due to process, voltage, and
As an alternative to full-flash architecture, time temperature and does not readily scale with data rate.
interleaved architecture, which employs massively Analog multiplication must be carefully implemented
parallel slow ADCs to aggregate the overall to achieve sufficient linearity and resolution. Finally,
conversion throughput, trades component complexity the bandwidth limitations and noise accumulation of
for architectural complexity, and component design these cascaded components has an adverse effect on
becomes much crucial to ADC performance and the SNR. All of these elements are trivial operations
power consumption. In this design, time-interleaved in the digital domain, and the digital architecture
architecture of 32-successive-approximation ADC readily scales with speed (within the bounds of the
array is chosen and component design complexity is digital clock rate).
addressed by introducing new circuit topologies. For
example, in contrast to usage of higher supply This simple example highlights essential benefits
voltage in an input buffer and track&hold circuit of of the DSP-based architecture. The first is a lower
typical ADC design, a single power supply of 0.85V sensitivity to power, voltage, and temperature
000052
variation. While this is still a consideration for the and model digital and analog circuit behavior. The
ADC, once the signal is rendered as a sequence of analog components are simulated at an oversampled
digital values, the processing is consistent regardless rate for accurate operation. The adaptation of analog
of the corner case. Not only is the processing is more component parameters are controlled by adaptation
consistent, it is also more predictable. Cycle accurate blocks which are modeled in fixed point arithmetic
models are readily generated that are not reliant on and thus can be bit/cycle accurate with the actual
analog models that must account for variation of a RTL design. The adaptive blocks operate at the
number of parameters and at times may not be very symbol rate or less. The system model produces
precise. Furthermore, correct implementation of the various adaptation states or waveforms at various

signal processing path may be checked with robust points in the analog front end.
digital verification techniques. Finally, a DSP-based 4.1. Verification of Digital Datapath Functionality
implementation is inherently portable to other
process nodes without the need for extensive analog The desired functional operation of digital
re-work. Porting into smaller process geometries datapath circuits can be verified through extensive
holds the promise of faster digital clock rate, a bit/cycle accurate verification using system model
smaller receiver, lower power, or some combination generated test vectors. For the digital block
thereof. component being verified, both the architectural
model and RTL circuits are driven with common
However, DSP-based receivers present their own input stimuli produced by the architectural model and
set of challenges. The most obvious challenge is the the corresponding internal states and outputs are
upper limits on the digital clock frequency for a given compared between the architectural model and the
technology node. Well known techniques such as RTL circuit. A discrepancy between the two usually
pipelining and parallelism can circumvent these results in a bug fix to the RTL circuit or can
problems in many cases. However, if we consider the sometimes require annotation of changes to the
feedback structure of the DFE, the iteration bound architectural model to match the RTL circuit
presents a challenge for high-speed operation that functionality. An example of the latter might be if the
cannot be addressed by pipelining alone. For this circuit designer had to insert additional latency in the
particular example, look-ahead techniques [10] can circuit to meet the timing constraints. In such
be employed to relax the iteration bound but this situations, the back annotated architectural model
particular architecture scale exponentially for an would be resimulated to ensure there is no significant
increasing number of DFE taps. For a PAM-4 degradation in system performance as a result of the
receiver based on DFE, the need to resolve 4 levels additional latency in the circuit.
and propagate 2-bit decisions (each symbol represent
2 bits) translates to a implementation that requires An example of such digital data path verification
twice the complexity of the corresponding NRZ is shown in Fig. 21. Fig. 21(a) shows the adaptation
receiver with half as many taps. One approach to the accumulator output from the architectural system
scaling problem is to shift more emphasis to the FFE model as well the corresponding RTL circuit output
and limit the number of DFE taps. Other novel for a receive analog equalizer (AEQ). The outputs
architectures could be considered that achieve match exactly to within a known understood delay.
performance comparable to DFE with superior Fig. 21(b) shows the corresponding accumulator most
scaling properties [11]. significant bits (MSBs) which control the actual AEQ
analog circuit parameters. Again, the outputs match
4. Serdes Modeling Accuracy and Simulation Results exactly to within a known understood delay. A
similar verification exercise is conducted for all
The first step in an overall Serdes design flow is critical digital circuit nodes such as digital clock/data
to define a system architecture which meets the recovery (CDR) adaptation states and digital
desired performance targets. Circuit designers then adaptation states of the other equalizer components in
design the various components which constitute that the system such as the DFE.
architecture. These components are designed to meet
various system specified performance metrics or in
the case of digital circuits, to meet functionality 4.2. Analog Circuit Correlated System Modeling
documented through fixed point accurate block
diagrams. A time step simulation based system Validating the proper operation of analog circuits
model is used to evaluate system level performance requires careful modeling of those circuits and an
000053
assessment of the impact to system performance saturated for high values of x. Other types of non-
based on the practical circuit implementation.. In this linearity functions can also be considered and used if
section we describe a system modeling methodology necessary to ensure accurate matching between the
which incorporates analog components whose circuit and the model.
behavior is correlated to the corresponding circuit
simulation results. The resulting system model’s Fig. 23(b) shows a section of a PRBS7 input
performance can be evaluated with ideal component waveform driving the AEQ, the resulting output of
models or circuit correlated component models. The the AEQ circuit, and the resulting output of the AEQ
model can also be incorporated into an overall IBIS- circuit correlated system model. The AEQ circuit

AMI Serdes model. output is generated by transistor level post-layout
simulations. The waveform matching is very good
Fig. 22 shows the methodology through which a based on the concatenation of the fitted AC response
system model for analog components is developed. and non-linear tanh model. Fig. 24 shows the
The circuit for the analog component is first designed corresponding eye diagrams of the entire PRBS7
based on system specifications which are typically in waveform. Fig. 24(a) is the output of the AEQ
the form of a prototype desired transfer function. The circuit and Fig. 24(b) is the output of corresponding
circuit is then simulated to produce an AC response circuit correlated AEQ system model. The eye
(magnitude, phase). This AC response is then fitted diagrams also correlate well between the circuit
to a modeled finite zero/pole response using least output and the model output.
squares fitting.
4.4 Performance Regression
The circuit is also driven with a pseudo-random
(PR) sequence based waveform which produces the Once the practical functionality of all analog
corresponding circuit transient response or waveform components is captured using circuit correlated
output. The same PR sequence drives the modeled system models, the overall system model needs to be
AC response which was fitted to the circuit. A re-evaluated with these models and the system
practical circuit has some non-linear compression performance (vertical or horizontal) margin can be
effect. To account for this behavior, a compression compared with the performance obtained using the
model is concatenated to the fitted AC response original system specified “ideal” models. Any
model and its parameters are chosen to produce good significant degradation in performance needs to be
correlation between the circuit correlated system addressed by circuit redesign.
model and the actual circuit waveform output.
4.5 IBIS AMI Model Delivery
4.3 Case Study: Analog Equalizer
Using the system modeling methodology we
Let us consider the analog equalizer (AEQ) to arrive at transmitter (TX) and receiver (RX) system
illustrate the component modeling methodology. The models which are correlated to the circuit behavior.
AEQ provides programmable high frequency peaking These models typically are written as a C program
or boost. Fig. 23(a) shows the AC magnitude and can be made compliant with the IBIS-AMI standard
phase response of the AEQ circuit and the and interfaced to EDA tools which are also compliant
corresponded fitted response of a pole/zero model with the IBIS-AMI standards. This arrangement is
matched to the AEQ AC response. Enough pole/zero shown in Fig. 25. A user who simulates a serial link
terms are chosen to obtain the near exact match under control of the EDA platform provides
shown in the figure. The AC response is next transmitter settings to the platform which creates an
concatenated with a non-linear operation as discussed input waveform, tx_wave_in, stimulus to the IBIS-
in the previous section to provide an overall AEQ AMI compliant TX model. The TX model produces
model. For the example considered here, the non- the TX output as tx_wave_out and communicates that
linear model is a simple tanh() function to the EDA platform. The EDA platform then
processes the TX waveform through a user specified
y = A tanh( x / A) Eq 4-1 channel model and produces the resulting channel
output, rx_wave_in, which will become the
where x is the input amplitude, y is the output waveform input, to the IBIS-AMI compliant RX
amplitude and A is value to which the input signal is model,. In addition, the EDA platform user can
specify certain RX control information. The RX
000054
model then produces the resulting output waveform, [5] S. Quan, F. Zhong, W. Liu, P. Aziz et al, “A
rx_wave_out along with a set of corresponding 1.0625-to-14.025Gb/s Multimedia Transceiver with
recovered clock time stamps for each sample in the Full-rate Source-Series-Terminated Transmit Driver
waveform. The EDA platform can post-process the and Floating Tap Decision Feedback Equalizer in
RX output waveform along with the time stamps to 40nm CMOS”, Digest of Technical Papers, IEEE Intl.
produce a statistical eye diagram of the system. The Solid States Circuits Conf., pp. 348-349, Feb, 2011.
RX also sends converged RX adaptation state values
to the EDA platform for display. [6] C. Y. Liu and J. Caroselli, “Comparison of
Signaling and Equalization Schemes in High Speed

5. Conclusions SerDes (10-25Gbps),” Proceedings, IEC DesignCon,
2007.
In this paper, signal integrity challenges for high [7] P. Crespo, M. Honig, “Pole Zero Decision
speed serial links at 25+ Gb/s, such as lossy channel, Feedback Equalization with a Rapidly Converging
and noisy environment were discussed. Solution Adaptive IIR Algorithm”, IEEE Jnl. On Selected
spaces such as advanced equalization schemes, Areas in Communications, pp. 817-828, Aug., 1991.
alternative signaling format and forward error
correction have been investigated. For long reach [8] P. Patel and B. Barnett, “Experimental Test
interconnection with channel IL 30dB or below, Fixture S-parameters 100 Gb/s Backplane Study
advanced equalization schemes like floating tap DFE Group,” IEEE 802.3 100 Gb/s Backplane and Copper
IIR DFE improve performance margin. Meanwhile, Cables Study Group, May 2011.
PAM-4 signaling and FEC coding are able to
improve SNR to support extra long reach (XLR) [9] J. Salz, “Optimum mean-square decision
application with channel IL over 35dB. ADC and feedback equalization,” Bell Syst. Tech. J., vol. 52, no.
DSP based SerDes architecture is described to further 8, p. 1342, Oct. 1973.
extend equalization capability. Modeling
methodologies used in SerDes behavioral models like [10] K. Parhi, “Design of Multiplexer-Loop-Based
IBIS-AMI to ensure good correlation with transistor Decision Feedback Equalizers,” IEEE Trans. VLSI
level circuit is also discussed. These modeling Sys., vol. 13, no. 4, Apr. 2005.
methodologies can be applied to 25+ Gb/s SerDes
design and performance analysis. [11] A. Pola et al., “A New Low Complexity Iterative
Equalization Architecture for High-Speed Receivers
Reference: on Highly Dispersive Channels: Decision
[1] C. Y. Liu and J. Caroselli, “Comparison of Feedforward Equalizer (DFFE),” Proceedings ISCAS
Signaling and Equalization Schemes in High Speed 2011, May 2011.
SerDes (10-25Gbps),” Proceedings, IEC DesignCon
2007. [12] A. Szczepaek, I. Ganga, C. Liu and M.
Valliappan,” 10GBASE-KR FEC Tutorial,”
[2] C. Zhong, C. Y. Liu, W. Jin, A. Malipatil, G. IEEE802.3 Plenary meeting, July 2006.
Tang, and F. Y. Zhong, “Design considerations in
high speed SerDes (25 Gbps),” Proceedings, IEC [13] C. Y. Liu, W. Jin and A. Healey, “Forward Error
DesignCon 2008. Correction (FEC) for high-speed SerDes Link System
of 25-28Gbps,” Proceedings, IEC DesignCon, 2011.
[3] P. Aziz, A. Healey and G. Sheets, “Semi-analytic
performance of NRZ/PAM4/PR2 modulation across [14] M. Gustlin, “FEC Striping Options for 100 Gb/s
8.5-25 Gb/s backplanes with analog equalization,” Backplane and Copper Task Force,” 100 Gb/s
Proceedings, IEC DesignCon 2009. Backplane and Cable Task Force, IEEE 802.3,
September 2011.
[4] P. Aziz, A. Malipatil, “Adaptation Algorithms for
a Class of Continuous Time Analog Equalizers With
Application to Serial Links”, Proceedings, IEEE Intl.
Symp. On Circuits and Systems, pp. 1383-1386, May
2011.
000055

Figure 1 System architecture and model block
diagram.
Figure 4 Channel A magnitude spectra and

impulse response.
Figure 2 Example statistical eye diagram, voltage
margin vs. sample phase at different symbol error
rates.
Figure 3 System architecture and model block

diagram showing additional feedback paths for
floating tap DFE and IIRDFE.
Figure 5 Channel B magnitude spectra and

impulse response.
000056
Figure 8 Channel A equalized pulse shape.

Figure 9 Channel C equalized pulse shape.
0
1
-10
Figure 6 Channel C magnitude spectra and 2
impulse response. 3
-20
4
Magnitude, dB
-30
-40
-50
-60
0 5 10 15 20
Frequency, GHz
Figure 10 SDD21 magnitude of select backplane

channels.
80
70
60 2
3
50
4
ICR, dB
40
30
20
1
10
0 -1 0 1 2
10 10 10 10
Figure 7 Channel D magnitude spectra and Frequency, GHz
impulse response. Figure 11 Insertion loss to crosstalk ratio of select
backplane channels.
000057
SER = 10-12, DCD = 0.8 ps, N /2 = -150 dBm/Hz, UJ = 1.4 ps

0
0 0
10 0
L=2
L=3 -1
-5 L=4
10
-2
L=5 L=4
Probability of error
ENOB = 5.2
SNR margin, dB
L=6 N = 10
-3 b L=2
-10 L=7 N =8 N = 10
10 w b
N =4
L=8 w
-4 OD = 0.1

-15 -5
10
-6
-20
10 -7
10 15 20 25 30 35 40 25 25.5 26 26.5 27 27.5 28
SNR, dB R, Gb/s
Figure 12 Symbol error probability as a function Figure 15 SNR degradation with increasing data
of SNR. rate.
-12
R = 25.7813 Gb/s, N /2 = -150 dBm/Hz, SER = 10
0 0 SNR vs. BER for RS(208+2t, 208, t) over GF (28) with t=1:10
14
L=2 uncoded
RS(260+2*t,260,t)
L=3 -5
12 10
L=4
L=5
10
Salz SNR margin, dB
-10
10
8
BER
6 -15
10
-20
10
2
0
1 2 3 4 -25
10
Channel index 11 12 13 14 15 16 17 18 19 20
SNR (dB)
Figure 13 Maximum achievable SNR margin.

Figure 16 BER verses SNR for RS codes with
SER = 10
0
-12
, R = 25.7813 Gb/s, DCD = 0.8 ps, N/2 = -150 dBm/Hz, UJ = 1.4 ps
0
shortened k=208 over GF(28).
4 SNR vs. BER for RS(260+2t, 260, t) over GF (210) with t=1:10
L=4
3 ENOB = 5.2 uncoded
N = 10 RS(260+2*t,260,t)
b 10
-5
2 N =8
w
1
SNR margin, dB
0 10
-10
-1 L=2
N = 10
b
BER
-2 N =4
w
-15
OD = 0.1 10
-3
-4
-20
10
-5
-6
1 2 3 4
Channel index -25
10
11 12 13 14 15 16 17 18 19 20
Figure 14 Comparison of NRZ and PAM-4 SNR (dB)
considering implementation constraints.

Figure 17 BER verses SNR for RS codes with
shortened k=260 over GF(210).
000058
LF Calibration Calibration
CLOCK bits
State
control
INPUT bits BACKGROUND
CLOCK CALIBRATION
CLOCK State
GENERATOR Delay, offset,
gain calibration
control
bits
rate CLOCK
rate CLOCK
Fractional Offset, gain

Fractional
Fractional
rate CLOCK calibration

Delay
T&H<3> <7:0>ADC n
State Subchannel
Delay
control calibration
bits
Fractional
rate CLOCK <7:0>ADC n

T&H<1>
Delay Subchannel
Offset, gain
ADC data interface

INPUT Delay calibration
calibration MUX
INP Offset, gain
BUFFER calibration
Delay
<7:0>ADC n
LEGEND T&H<2> Subchannel
Delay
Analog IO calibration
Analog Internal Fractional

rate CLOCK
Clock External T&H<0> <7:0>ADC n
Delay Subchannel
Clock Internal
Offset, gain
Delay calibration
Serial digital IO
calibration
Digital Data
State
Internal Calibration Bits Test Out
control
Analog
bits
State Control Bits
Test
Figure 18 Top-level block diagram of 16Gs/s 6bit

ADC.
Figure 21 Illustration of bit/cycle digital

verification of the AEQ block functionality
showing (a) accumulator output (b) accumulator
MSBs.
Figure 19 ADC Conversion Results with Fin =

4GHz and Fclk = 16GHz.
Figure 22 Modeling methodology and validation

for typical analog circuit components.
Figure 20 ADC Harmonic Distortion Spectrum

with Fin = 4GHz and Fclk = 16GHz.
000059

Figure 23 (a) AEQ magnitude (upper) and phase
(lower) responses for a high peaking setting. Blue Figure 24 Input is PRBS7, AEQ at a high peaking
is circuit simulation, red is the system model fitted setting (a) Eye diagram of the AEQ circuit output
to the circuit simulation. (b) Waveform overlay of waveform. (b) Eye diagram of the AEQ circuit
a section of a PRBS7 input signal, the AEQ circuit correlated model output.
output signal, and the AEQ circuit correlated
model output.
Figure 25 System TX & RX models interfaced to

be IBIS-AMI compliant to an EDA platform.
000060

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44th International Symposium on Microelectronics | October 9-13, 2011 | Long Beach, California USA

SerDes Design and Modeling over 25+ Gb/s Serial Link

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With the complexity growth in SerDes N

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The first architecture is what is known as z (t ) = y (t ) − g v(n − L) exp(−t / τ ) Eq 2-3

arbitrary positions away from the main tap. This

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Termination RC model similar to that of Channel A. Although the insertion

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derived by Salz [9] and given by Eq 2-7. It is an

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for the PAM-4 solution is scaled to be half of the

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In general, a t-error-correcting RS can correct a

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Figure 4 Channel A magnitude spectra and

Figure 3 System architecture and model block

Figure 5 Channel B magnitude spectra and

Figure 8 Channel A equalized pulse shape.

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Figure 10 SDD21 magnitude of select backplane

SER = 10-12, DCD = 0.8 ps, N /2 = -150 dBm/Hz, UJ = 1.4 ps

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Figure 13 Maximum achievable SNR margin.

considering implementation constraints.

Fractional Offset, gain

rate CLOCK calibration

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ADC data interface

Analog Internal Fractional

Figure 18 Top-level block diagram of 16Gs/s 6bit

Figure 21 Illustration of bit/cycle digital

Figure 19 ADC Conversion Results with Fin =

Figure 22 Modeling methodology and validation

Figure 20 ADC Harmonic Distortion Spectrum

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Figure 25 System TX & RX models interfaced to

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