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    R19 ECE-DLD Set 2

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    kisnamohan
    The document is an exam for a digital electronics and logic design course. It contains questions about binary arithmetic, Boolean logic, multiplexers, shift registers, encoders/decoders, Karnaugh maps, adders/subtractors, flip flops, registers/counters, programmable logic arrays and digital logic families.

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    R19 ECE-DLD Set 2

    Uploaded by

    kisnamohan
    5 views2 pages
    The document is an exam for a digital electronics and logic design course. It contains questions about binary arithmetic, Boolean logic, multiplexers, shift registers, encoders/decoders, Karnaugh maps, adders/subtractors, flip flops, registers/counters, programmable logic arrays and digital logic families.

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    R19 ECE-DLD set 2

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    The document is an exam for a digital electronics and logic design course. It contains questions about binary arithmetic, Boolean logic, multiplexers, shift registers, encoders/decoders, Karnaugh maps, adders/subtractors, flip flops, registers/counters, programmable logic arrays and digital logic families.

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    © All Rights Reserved
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    5 views2 pages

    R19 ECE-DLD Set 2

    Uploaded by

    kisnamohan
    The document is an exam for a digital electronics and logic design course. It contains questions about binary arithmetic, Boolean logic, multiplexers, shift registers, encoders/decoders, Karnaugh maps, adders/subtractors, flip flops, registers/counters, programmable logic arrays and digital logic families.

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    © All Rights Reserved
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    You are on page 1of 2

    CODE: 19CA04301

    CHADALAWADA RAMANAMMA ENGINEERING COLLEGE


    (AUTONOMOUS)
    Chadalawada Nagar, Renigunta Road, Tirupati – 517 506
    B. Tech II Year I Semester (R19) Supplementary Examinations, October - 2021
    DIGITAL ELECTRONICS & LOGIC DESIGN
    (ECE)
    Time: 3 hours Max Marks: 70
    PART – A
    1. Answer any ten questions (10 x 2 = 20 Marks)
    (a) Subtract the following hexadecimal numbers: F27-B9E.
    (b) Why are complements used in binary arithmetic? What are the advantages and
    disadvantages of using 2’s complement notation in binary arithmetic?
    (c) Write down the truth tables for Ex-OR gate and Ex-NOR gate.
    (d) State and explain about duality theorem. List Boolean laws and their duals.
    (e) What is multiplexer? What are the applications of multiplexers?
    (f) Compare a decoder with a demultiplexer.
    (g) What is the drawback of SR latch?
    (h) What are the basic types of shift registers?
    (i) Compare ROM and RAM
    (j) What is the basic architecture of PAL and PLA
    (k) What is minterm?
    Find the minterm expansion of f(a, b, c, d) = a’(b’ + d) + acd’.
    (l) Define encoder and decoder.
    PART - B
    Answer all five units (5 x 10 = 50 Marks)

    UNIT-I
    2. (a) Given the two binary numbers X = 1010100 and Y = 1000011, Solve the subtraction:
    (i) X – Y. (ii) Y - X by using 2’s complements.
    (b) What is hamming code? How is the hamming code word tested and corrected?
    OR
    3. Translate the following numbers as indicated and fill the blanks with converted value:
    Decimal Binary Octal Hexadecimal
    i. 29.25 ______ ______ ______
    ii. ______ 101.1001 ______ ______
    iii. ______ ______ 4.07 ______
    iV _______ ______ ______ D.82
    Continued in Page 2
    Page 1of 2
    CODE: 19CA04301

    UNIT-II

    4. (a) Use K-map method reduces the expression


    F=A’BC’D’+A’BC’D+ABC’D’+ABC’D+AB’C’D+A’B’C’D’
    (b) Using K-map, determine the minimal Product-of-Sums expression for the
    following minterms:
    m1 + m3 + m5 + m7 + m12 + m13 + m8 + m9
    OR
    Use Boolean theorems and properties to reduce the following Boolean expressions
    5.
    i) x(x’+y) ii) x+x’y
    iii) (x+y)(x+y’) iv) xy+x’z+yz
    v) (x+y)(x’+z)(y+z)

    UNIT-III
    6. Draw and explain about 4-bit magnitude comparator.
    OR

    7. Draw the truth table, logic expressions and logic circuit for full adder and subtractor.

    UNIT-IV

    8. Draw the logic symbol, characteristics table and derive characteristics equation of JK
    flipflop.
    OR

    9. Explain in detail about registers and counters with an example.

    UNIT-V
    10. Implement the following two Boolean function with a PLA

    i) F1(A,B,C)= Σm(0,1,2,4)

    ii) F2(A,B,C)= Σm(0,5,6,7)

    OR

    11. Discuss about DTL and TTL logic circuits with example.

    *****

    Page 2 of 2

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