Introduction to Microprocessors

Chapter 4 – 8086 Hardware Description

Dr. Adnan Ismail Al-Sulaifanie

Department of Electrical and Computer Engineering

University of Duhok, Iraq

Objectives

ä 8086 hardware specifications.

ä Operation modes.

ä Pin descriptions.

ä Memory cycles.

ä Processor interface to memory and I/O devices.

ä Memory address decoding

ä I/O address decoding

References

1. Brey, The Intel Microprocessors, chapters 4, 7 & 8.

2. Triebel, 8088 and 8086 microprocessors: Programming, Interfacing, Hard-

ware, chapter 7

3. Rafiquzzaman, Fundamentals of Digital Logic and Microcomputer Design

, chapter 9.

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1 Pin-outs of 8086 Processor

The pins of 8086 processor can be divided into different groups such as:

1. Address bus.

2. Data bus.

3. Control signals for memory and IO devices.

4. Interrupt pins

5. ...

Some pins have dual function. Why?

2 Concept of Bus Multiplexing

ä 8086 processor is packaged in 40 pin dual-inline-package (DIP). Since the re-

quired number of pins is much higher, therefore the concept of pins multiplexing
is utilized.

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 ä The address/data and address/status buses are multiplexed to reduce the device
pin count. These buses are used to convey more than one signals at different
times.

The 20 pins (AD15 − AD0 and A19 /S6 − A16 /S3 ) are used to convey address,
data, and status signals.

ä The bus can be de-multiplexed using latches, transceivers, and control signals
to separate data and status signals from address signals.

ä Three signals ALE, DEN , and DT /R are used to control the operation of latches
and transceivers.
ALE used to store address in external latch
DEN indicates that valid data is available on the bus. It is used to enable
transceivers.
DT /R specify the direction of data flow through transceiver. DT /R = 1 in write
cycle and 0 for read cycle

3 8086 Operating Modes

8088 and 8086 microprocessors can be configured to run in one of two modes:

3.1 Minimum mode

ä Pull M N /M X to logic 1

ä Typically smaller systems and contains a single microprocessor.

ä The 8086 directly produces the control signals for interfacing to memory and I/O
devices.

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Minimum mode Pin Description

ä AD15-AD0: (Multiplexed) address(ALE = 1)/data bus(ALE = 0).

ä A19/S6 – A16/S3: (multiplexed) High order 4 bits of the 20-bit address OR

status bits S6 – S3.

ä Address latch enable ALE: used along with 74LS373 latches to demultiplex
address data bus.

ä M/IO: Indicates if address is a Memory or IO address.

ä RD: when 0, read data from memory or an I/O device.

ä WR: microprocessor is driving data bus to memory or an I/O device. When 0,

data bus contains valid data.

ä Status signals S7 – S3:

ã S5 : Indicates condition of IF flag bits.

ã S6 = 0 : indicate that 8086 is on the bus
ã S7: Spare (not used)
ã S4 – S3 : Identify which internal segment used to generate physical ad-
dress.

S4 – S3 Function
00 Extra segment
01 Stack segment
10 Code or no segment
11 Data segment

ä Reset: cause 80867 processor to terminate its present activity and perform
reset sequence.

ä Ready: used by memory and I/O device to indicate the presence of data on
the bus.

ä INTR, NMI, and INTA: these signals related to hardware interrupt.

ä Hold and HLDA: these signal used with DMA controller.

ä Bank High Enable BHE: this signal used with A0 to identify M/IO access as
follows:-

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3.2 Maximum Mode

ä Pull M N /M X logic 0

ä Larger system, designed to be used when 8087 coprocessor.

ä Control signals are encoded in the status lines and need to be decoded externally
(8288 bus controller).

ä The 8086/8088 operate in maximum mode, so they are configured primarily for
multiprocessor operation or for working with 8087 coprocessor.

ä This chip is used with 8086 to generate necessary control signals.

Input signals: S0 , S1 , S2
Output signals: M RDC, M W T C, IORC, IOW C, ...

S2 S1 S0 Processor state 8288 command

0 0 0 Interrupt Acknowledge IN T A
0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOW C and AIOW C
0 1 1 Halt None
1 0 0 Code access M RDC
1 0 1 Read memory M RDC
1 1 0 Write memory M W T C and AM W C
1 1 1 Passive None

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4 Bus Cycle and Time States

ä The processor communicates with memory/IO devices via the system bus to
transfer data or fetch instructions. This process is called bus cycle.

ä A bus cycle defines the sequence of operations performed by processor access

memory or IO device.

ä Types of bus cycle: memory read, memory write, input/output read and in-
put/output write.

ä During these operations, a series of control signals are also produced by the
processor to control the direction and timing of the bus.

ä Each bus cycle consists of at least four clock periods, T1, T2, T3, and T4. These
1
clock periods are also called the T-States ⇒ T =
f requency
ä The transfer rate depends on the operating frequency of the 8086 processor (5,
6, and 8 MHz) and data bus sizes.

1
T = = 200 ns
5 M Hz
Bus cycle = 4T = 800 ns
f bus − width
Data transfer rate = ∗ bytes per second.
n 8
5 16
For 16 bit data bus and f = 5 MHz, the maximum transfer rate = ∗ = 2.5
4 8
Mbyte/s

ä Each access to memory or IO device requires at least four clocks (each called T
state). During each clock period one or more operations are performed.

ä The following sequence of operation are performed to complete read/write op-

eration:

T1

1. The 8086 outputs the 20-bit address on the multiplexed address/data/status bus
via AD0 − AD15 and A19 /S6 − A16 /S3 .

2. ALE = 1 to store the address in the external latches.

3. DEN = 1 disable data transceivers

4. M/IO is actiated to show the intended deice memory or I/O deice.

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 5. BHE is used to enable/disable high memory bank.

T2

1. The processor removes address from the bus.

2. Output S3 − S6 on A16 − A19 .

3. For the read cycle, AD15 − AD0 floated as input waiting for data from mmeory.
RD is delayed to provide time for floating.
For write cycle, data appears on the bus. WR becomes active at the beginning
of T2.

4. The DEN = 0 to turn the transceiver on. It remains active from the middle of
T2 to the middle of T4 .

5. READY signal is sampled at the end of T2. If memory is not ready (READY = 0),
T2 is repeated (T3 become wait state) until it READY become 1

T3

1. Read or write is completed at end of this period.

T4

1. Data remains on the bus until the middle of T4

2. All bus and control signals are deactivated in preparation for the next clock cycle.

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5 Memory Interface and Address Decoding

ä An address decoder is needed when the processor is connected to multiple mem-

ory chips.

ä Address decoder circuit is used to activate the intended device when the output
address is within its address range.

ä Unused pins are used to enable/disable memory. The output of the decoder is
connected to the CS (chip select) or OE (output enable) pins.

ä Address decoding makes the memory function at a unique section or partition of

the memory map.

ä Every device has its address decoder logic.

ä The address bus lines are split into two sections:

1. the N most significant bits are used to generate the CS signal.

2. the M least significant bits are passed to the memory as address.

ä A single address decoder with n address input bits can serve up to 2n devices of
same size.

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 ä Address decoding circuits can be implemented with three different methods:

1. Logic gates.
2. Decoders
3. Programmable logic devices (PLDs) such as PLA, PAL, FPGA, and ASIC.

Example 1 - It is required to connect a processor with 10 bit address bus to 8

memory chips of of 128 bytes. Design a suitable decoder circuit.

Example 2 - design a decoder circuit to connect 20 bit processor to 512 K byte

RAM, 256 K byte ROM, and 256 K byte EPROM

Example 3 - design an interface between 8086 and

1. Two chips of 16 K x 8 EPROM. Select starting address probably.

2. Two chips of 32 K x 8 RAM. The RAM must start at 00000h.

6 I/O Interface and Address Decoding

ä The I/O port address decoder is much like the memory address decoder, except
the I/O port decoder decodes only a l6-bit or 8 bit address.

ä There are two methods to connect CPU to the I/O devices:

1. Isolated I/O
2. Memory mapped I/O

6.1 Isolated I/O

ä The address space for I/O is isolated from that for memory. The full range of
addresses available for memory and I/O devices.

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 ä The I/O operations are performed by IN and OUT instructions).

ä 8-bit port address is used to access devices located on the system board (timer,keyboard)

ä 16-bit port address used to access (external devices), such as serial, parallel,
video card, and disk drive.

ä Disadvantages: data accessed by special instructions (IN,OUT) and separate

control signal used, so complex hardware required.

IN and OUT instructions

ä These instructions are used to communicate with input/output devices.

ä Depending on the length of port address, there are two type of addresses:

1. Fixed address port: use 8 bit address.

2. Variable address port: use 16 bit address should be stored in DX register.

8 bit data 16 bit data

Fixed address IN AL/AX, PORT8 IN AL, E4 IN AX, E4
Fixed address OUT PORT8, AL/AX OUT PORT8, AL OUT PORT8, AX
Variable address IN AL/AX, DX IN AL, DX IN AX, DX
Variable address OUT DX, AL/AX OUT DX, AL OUT DX, AX

6.2 Memory mapped I/O

ä The address space is participated by memory and I/O devices (i.e. The CPU
treats the status, control, and data register as memory locations).

ä The same machine instructions are used to access both memory and I/O module.

ä Advantages: easy for programming and design.

ä Disadvantages:

1. Not all memory locations available for the user.

2. Complex decoding circuit and OS
3. Dealing with memory is slower than I/O.

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Isolated versus Memory-mapped I/O

Separate I/O Memory mapped

Address space two address spaces single address space
Instructions IN and OUT any data transfer instruction
CPU complexity more complex simpler hardware
Address decoding complexity complex simpler

Example 4 - interface an input port 74LS245 to read the status of switches SW1-
SW8. Store status in BL register. The address of the port is 0740h.

MOV DX, 0740

IN AL, DX
MOV BL, AL

Example 5 - design an interface of an input port 74LS245 (port address 0008h) to

read the status of switches SW1-SW8. Display a number of key pressed on seven seg-
ment display using 74LS373 (port address 000Ah). Assume only one key is pressed
at a time.

XOR CL, CL
IN AL, 08
next1: RCR AL, 1
JC next2

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 INC CL
JMP next1
next2: MOV AL, CL
OUT 0Ah, AL

Homework 1 - design an address decoding circuit to connect processor to an I/O

devices using port addresses F0 - F3

Homework 2 - design an address decoding circuit to connect processor to 32 KB

memory starting at address A0000h

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