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Prototyping Advanced Control Systems on FPGA

Article in EURASIP Journal on Embedded Systems · January 2009

DOI: 10.1155/2009/897023 · Source: DBLP

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Hindawi Publishing Corporation
EURASIP Journal on Embedded Systems
Volume 2009, Article ID 897023, 12 pages
doi:10.1155/2009/897023

Research Article
Prototyping Advanced Control Systems on FPGA

Stéphane Simard, Jean-Gabriel Mailloux, and Rachid Beguenane

Department of Applied Sciences, University of Quebec at Chicoutimi, 555 boul. de l’Université, Chicoutimi, QC, Canada G7H 2B1

Correspondence should be addressed to Rachid Beguenane, rbeguena@uqac.ca

Received 19 June 2008; Accepted 3 March 2009

Recommended by Miriam Leeser

In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs) promise to supplant older technologies, such
as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for
skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex
algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the
amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping
platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing.
The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog
I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx
Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of
a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC’s MEMS prototyping
platform, now used by several Canadian laboratories.

Copyright © 2009 Stéphane Simard et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly
cited.

1. Introduction embedded SoCs. Exploiting the FPGA technology benefits

for industrial electrical control systems has been the source of
The use of advanced control algorithms depends upon being intensive research investigations during last decade in order
able to perform complex calculations within demanding to boost their performances at lower cost [3, 4]. There is
timing constraints, where system dynamics can require still, however, much work to be done to bring such power
feedback response in as short as a couple tens of microsec- in the hands of control specialists. In [5], it is stated that the
onds. Developing and implementing such capable feedback potential of implementing one FPGA chip-based controller
controllers is currently a hard goal to achieve, and there is has not been fully exploited in the complicated motor
much technological challenge in making it more affordable. control or complex converter control applications. Until
Thanks to major technological breakthroughs in recent years, now, most related research works using FPGA devices are
and to sustained rapid progress in the fields of very large focusing on designing specific parts mainly to control power
scale integration (VLSI) and electronic design automation electronic devices such as space vector pulse width modula-
(EDA), electronic systems are increasingly powerful [1, tion (SVPWM) and power factor correction [6, 7]. Usually
2]. In the latter paper, it is rightly stated that FPGA these are implemented on small FPGAs while the main
devices have reached a level of development that puts control tasks are realised sequentially by the supervising
them on the edge of microelectronics fabrication technology processor system, basically the DSP. Important and constant
advancements. They provide many advantages with respect improvement in FPGA devices, synthesis, place-and-route
to their nonreconfigurable counterparts such as the general tools, and debug capabilities has made FPGA prototyping
purpose micropocessors and DSP processors. In fact, FPGA- more available and practical to ASIC/SoC designers than
based digital processing systems achieve better performance- ever before. The validation of their hardware and software
cost compromise, and with a moderate design effort they on a common platform can be accomplished using FPGA-
can afford the implementation of a powerful and flexible based prototypes. Thanks to the existing and mature tools
2 EURASIP Journal on Embedded Systems

that provide automation while maintaining flexibility, the

FPGA prototypes make it now possible for ASIC/SoC designs
to be delivered on time at minimal budget. Consequently,
FPGA-based prototypes could be efficiently exploited for
motion control applications to permit an easy modification
of the advanced control algorithms through short-design
Analog I/Q
cycles, simple simulation, and rapid verification. Still the daughter card
implementation of FPGA-based SoCs for motion control
results in very complex tasks involving SW and HW skilled
developers. The efficient IP integration constitutes the main
difficulty from hardware perspective while in software side AP1000 board Digital outputs
the issue is the complexity of debugging the software that from the FPGA
runs under real-time operating system (RTOS), in real hard-
ware. This paper discusses the choice, adaptation, and use of Figure 1: Rapid prototyping station equiped with FPGA board and
multichannel analog I/O daughter card.
a rapid prototyping platform and design flow suitable for the
design of on-chip motion controllers and other SoCs with a
need for analog interfacing. Section 2 describes the chosen
prototyping platform and the methodology that supports PC (3.4 GHz Xeon CPU with 2.75 GB of RAM) equiped
embedded application software coupled with custom FPGA with the Amirix AP1000 PCI FPGA development board,
logic and analog interfacing. Section 3 presents the strategy to support a multichannel analog I/O PMC daughter card
for simulating and prototyping any control algorithm using (Figure 1) to communicate with exterior world.
Xilinx system Generator (XSG) along with Matlab/Simulink. The AP1000 has lots of features to support complex
A vector control for induction motor is taken as a running system prototyping, including test access and expansion
example to explain some features related to the cosimulation. capabilities. The PCB is a 64-bit PCI card that can be
Section 4 describes the process of integrating the designed inserted in a standard expansion slot on a PC motherboard
controller, once completely debugged, within an SoC archi- or PCI backplane. Use of the PMC site requires a second
tecture using Xilinx Platform Studio (XPS) and targeting chassis slot on the backside of the board and an optional
the chosen FPGA-based platform. Section 5 discusses the extender card to provide access to the board I/O. The AP1000
complex task of PCI initialization of the analog I/O card platform includes a Xilinx Virtex-II Pro XC2VP100 FPGA
and controller setup by software under embedded Linux and is connected to dual banks of DDR SDRAM (64 MB)
operating system. Section 6 takes the induction motor vector and SRAM (2 MB), Flash Memory (16 MB), Ethernet and
control algorithm as an application basis to demonstrate other interfaces. It is configured as a single board computer
the usefulness of the chosen FPGA-based SoC platform to based on two embedded IBM PowerPC processors, and it is
design/verify on-chip motion controllers. The last section providing an advanced design starting point for the designer
concludes the paper. to improve time-to-market and reduce development costs.
The analog electronics are considered modular, and can
either be external or included on the same chip (e.g., when
2. The FPGA-Based Prototyping Platform for fabricated into an ASIC). On the prototyping platform,
On-Chip Motion Controllers of course, they are supplied by the PMC daughter card.
It is a General Standards PMC66-16AISS8A04 analog I/O
With the advent of a new generation of high-performance board featuring twelve 16-bit channels: eight simultaneously
and high-density FPGAs offering speeds in the 100 seconds sampled analog inputs, and four analog outputs, with input
of MHz and complexities of up to 2 megagates, the FPGA- sampling rates up to 2.0 MSPS per channel. It acts as a two-
based prototyping becomes appropriate for verification of way analog interface between the FPGA and lab equipment,
SoC and ASIC designs. Consequently the increasing design connected through an 80-pin ribbon cable and a breakeout
complexities and the availability of high-capacity FPGAs board to the appropriate ports of the power module.
in high-pin-count packages are motivating the need for The application software is compiled with the free
sophisticated boards. Board development has become a task Embedded Linux Development Kit (ELDK) from DENX
that demands unique expertise. That is one reason why Software Engineering. Since it runs under such a complete
commercial off-the-shelf (COTS) boards are quickly becom- operating system as Linux, it can perform elaborated func-
ing the solution of choice because they are closely related tions, including user interface management (via a serial
to the implementation and debugging tools. During many link or through networking), and real-time supervision and
years, and under its System-on-Chip Research Network adaptation of a process such as adaptive control.
(SOCRN) program, CMC Microsystems provided canadian The overall platform is very well suited to FPGA-in-
universities with development tools, various DSP/Embedded the-loop control and SoC controller prototyping (Figure 2).
Systems/multimedia boards, and SoC prototyping boards The controller can either be implemented completely in
such as Amirix AP1000 PCI FPGA development platform. digital hardware, or executed on an application-specific
In order to support our research on on-chip motion instruction set processor (ASIP). The hardware approach has
controllers, we have managed the former plateform, a host a familiar design flow, using the Xilinx System Generator
EURASIP Journal on Embedded Systems 3

General standards PMC analog

AC Power I/Q card with 12-16 bit analog
induction module channels: 4 outputs, and 8
motor simultaneously sampled inputs

Digital PMC Ethernet RJ45

outputs
(PMW,etc)
PCI
bridge
Application
software + HW logic driver
under Linux User
PowerPC SDRAM logic
405 controller Interface Bridge
PLB

RS232 Interrupt Bridge

RJ45 UART controller
Xcvr Figure 3: Virtex-4 ML402 SX XtremeDSP evaluation platform.
OPB
FPGA Virtex-II Pro XC2VP100 External
local
AP1000 FPGA board bridge We begin with a conventional, floating-point, simu-
lated control system model, and corresponding fixed-point
Figure 2: Architecture of the embedded platform driving a power hardware representation is then constructed using the XSG
system (schematic not to scale). blockset, leading to a bit-accurate FPGA hardware model
(Figure 4), and XSG generates synthesizable HDL targetting
Xilinx FPGAs. The XSG design, simulation, and test pro-
cedure is briefly outlined below. Power systems including
(XSG) blockset and hardware/software cosimulation features motor drives can be simulated using the SimPowerSystems
in Matlab/Simulink. An ASIP specially devised for advanced (SPS) blockset in Simulink.
control applications is currently under development within
our laboratory. (1) Start by coding each system module individually with
the XSG blockset.
(2) Import any user-designed HDL cores.
3. Matlab/Simulink/XSG Controller Design
(3) Adjust the fixed-point bit precisions (including bit
It is well known that simulation of large systems within widths and binary point position) for each XSG block
system analysis and modelling software environments takes of the system.
a prohibitive amount of time. The main advantage of a rapid
(4) Use the Xilinx Gateway blocks to interface a floating-
prototyping design flow with hardware/software cosimula-
point Simulink model with a fixed-point XSG design.
tion is that it provides the best of a system analysis and
The Gateway-in and Gateway-out blocks, respec-
modelling environment while offering adequate hardware
tively, convert inputs from Simulink to XSG and
acceleration.
outputs from XSG to Simulink.
Hardware/software cosimulation has been introduced
by major EDA vendors around year 2000, combining (5) Test system response using the same input stimuli for
Matlab/Simulink, the computing, and Model-Based Design an equivalent XSG design and Simulink model with
software, with synthesizable blocksets and automated hard- automatic comparision of their respective outputs.
ware synthesis software such as DSP Builder from Altera,
and System Generator from Xilinx (XSG). Such a design Commonly, software simulation of a complete drive
flow reduces the learning time and development risk for model, for a few seconds of results, could take a couple of
DSP developers, shortens the path from design concept to days of computer time. Hardware/software cosimulation can
working hardware, and enables engineers to rapidly create be used to accelerate the process of controller simulation,
and implement innovative, high-performance DSP designs. thus reducing the computing time to about a couple of hours.
The XSG cosimulation feature allows the user to run a It also ensures that the design will respond correctly once
design on the FPGA found on a certain platform. An impor- implemented in hardware.
tant advantage of XSG is that it allows for quick evaluation
of system response when making changes (e.g., changing 4. System-on-Chip Integration in Xilinx
coefficient and data widths). As the AP1000 is not supported Platform Studio
by XSG among the preprogrammed cosimulation targets, we
use the Virtex-4 ML402 SX XtremeDSP Evaluation Platform FPGA design and the SoC architecture are managed with
instead (Figure 3). The AP1000 is only targetted at the SoC Xilinx Platform Studio (XPS), targetting the AP1000. We
integration step (see Section 4). have customized the CMC-modified Amirix baseline design
4 EURASIP Journal on Embedded Systems

Hardware Software
Matlab/Simulink libraries
library
modeling and drivers
component

Co-simulation data link

Baseline Controller
SoC synthesis
architecture in XSG

Application- Integration of the

specification Source-level Application-
components specific code
hardware integration
to the SoC
components
Embedded Linux
Hardware/software operation system
co-simulation Low-level
Hardware Functional
software Software
design flow simulation
simulation design flow

FPGA prototype

Figure 4: Controller-on-chip design flow.

to support analog interfacing, user logic on the Processor read multiplexer. This allows to decide which data is provided
Local Bus (PLB), and communication with application when a read request is sent to the user logic peripheral by
software under embedded Linux. XPS generates the corre- another peripheral in the system. While a greater number
sponding .bin file, which is then transferred to the Flash may be used, our pilot application, the vector control, only
configuration memory on the AP1000. The contents of this use four slave registers. The user logic peripheral has a
memory is used to reconfigure the FPGA. We have found specific base address (C BASEADDR), and the four 32-
an undocumented fact that, on the AP1000, this approach bit registers are accessed through C BASEADDR + register
is the only practicable way to program the FPGA. JTAG offset. In this example, C BASEADDR + 0x0 corresponds
programming is proved inconvenient, because it suppresses to the control and status register, which is composed of the
the embedded Linux, which is essential to us for PCI following bits:
initialization. Once programmed, user logic awaits a start
signal from our application software following analog I/O 0–7 : the DIP switches on the AP1000 for
card initialization. debugging purposes,
To accelerate the logic synthesis process, the mapper and 8 : used by user software to reset, start, or
place and route options are set to STD (standard) in the stop the controller,
implementation options file (etc/fast runtime.opt), found in 9–31 : reserved.
the Project Files menu. If the user wants a more aggressive
effort, these options should be changed to HIGH, which As for the other 3 registers, they correspond to
requires much more time. Our experiments have shown that
it typically amounts to several hours. C BASEADDR + 0x4: Output to analog
channel 1
4.1. Bus Interfacing. The busses implemented in FPGA logic C BASEADDR + 0x8: Output to analog
follow the IBM CoreConnect standard. It provides master channel 2
and slave operation modes for any instanciated hardware C BASEADDR + 0xC: Reserved (often used for
module. The most important system busses are the Processor debugging purposes)
Local Bus (PLB), and the On-chip Peripheral Bus (OPB).
The implementation of the vector control scheme 4.1.2. Master Model Control. The master model control
requires much less of generality, and deletes some commu- state machine is used to control the requests and responses
nication stages that might be used in other applications. It is between the user logic peripheral and the analog I/O card.
easier to start from such a generic design, dropping unneeded The latter is used to read the input currents and voltages
features, than to start from scratch. This way, one can quickly for vector control operation. The start signal previously
progress from SoC architecture in XPS down to a working mentioned in slave register 0 is what gets the state machine
controller on the AP1000. out of IDLE mode, and thus starts the data acquisition
process. In this specific example, the I/O card is previously
4.1.1. Slave Model Register Read Mux. The baseline XPS initialized by the embedded application software, relieving
design provides the developer with a slave model register the state machine of any initialization code. Analog I/O
EURASIP Journal on Embedded Systems 5

initialization sets a lot of parameters, including how many

active channels are to be read. IDLE Start signal
The state machine operates in the following way
(Figure 5). Stop signal
le ted
comp Adresses
(1) The user logic waits for a start signal from the user Setu p setup
through slave register 0.
BCR and AIO
(2) The different addresses to access the right AIO card Trigger ACK
status trigger
fields are set up, namely, the BCR and read buffer.
(3) A trigger is sent to the AIO card to buffer the values Read another Read
of all desired analog channels. All channels active channel cycle
read
(4) A read cycle is repeated for the number of active
PAUSE
channels previously defined. One active channel
read
(5) Once all channels have been read, the state machine
falls back to trigger state, unless the user chooses to Figure 5: Master model state machine.
stop the process using slave register 0.

4.2. Creating or Importing User Cores. User-designed logic Table 1: The Two Intel StrataFlash Flash memory devices.
and other IPs can be created or imported into the XPS design
Bank Address Size Mode Description
following this procedure.
1 0x20000000 0x1000000 (16 MB) 16 Program Flash
(1) Select Create or Import Peripheral from the Hard- 2 0x24000000 0x1000000 (16 MB) 8 Config. Flash
ware menu, and follow the wizard (unless otherwise
stated below, the default options should be accepted).
Table 2: AP1000 flash configurations.
(2) Choose the preferred bus. In the case of our vector
controller, it is connected to the PLB. Region Bank Sectors Description
(3) For PLB interfacing, select the following IPIF ser- 0 2 0–39 Configuration 0
vices: 1 2 40–79 Configuration 1
2 2 80–127 Configuration 2 (Default Config.)
(a) burst and cacheline transaction support,
(b) master support,
(c) S/W register support. 4.4. BIN File Generation and FPGA Configuration. To config-
ure the FPGA, a BIN file must be generated from the XSG
(4) The User S/W Regitser data width should be 32. project. Since JTAG programming disables the embedded
Linux, the BIN file must be downloaded directly to onboard
(5) Accept the other wizard options as default, then click
Flash memory. There are two Intel Strataflash Flash memory
Finish.
devices on the AP1000, one for the configuration, and one
(6) You should find your newly created/imported core in for the U-boot bootstrap code (which should not be crushed)
the Project Repository of the IP Catalog; right click (Table 1).
on it, and select Add IP. The configuration memory (Table 2) is divided into three
(7) Finally go to the Assembly tab in the main System sections. Section 2 is the default Amirix configuration, and
Assembly View, and set the base address (e.g., should not be crushed. Downloading the BIN file to memory
0x2a001000), the memory size (e.g., 512), and the bus is done through a network cable using the TFTP protocol.
connection (e.g., plb bus). For this purpose, a TFTP server must be set up on the
host PC. The remote side of the protocol is managed by
U-boot on the AP1000. Commands to U-boot to initiate
4.3. Instantiating a Netlist Core. Using HDL generated by the transfer and to trigger FPGA reconfiguration from a
System Generator may be inconvenient for large control designated region are entered by the user through a serial link
systems described with the XSG blockset, as it can require terminal program. Here is the complete U-boot command
a couple of days of synthesis time. System Generator sequence:
can be asked to produce a corresponding NGC binary
netlist file instead, which is then treated as a black box setenv serverip 132.212.202.166
to be imported and integrated into an XPS project. This setenv ipaddr 132.212.201.223
considerably reduces the synthesis time needed. The process erase 2 : 0–39
of instantiating a Netlist Core in a custom peripheral (e.g., Send tftp 00100000 download.bin
user logic.vhd), performed following the steps documented Send cp.b 00100000 24000000 00500000
in XPS user guide. Send swrecon
6 EURASIP Journal on Embedded Systems

5. Application Software and Drivers volatile u32 ∗base addr;

struct pci dev ∗dev;
One of the main advantages of using an embedded Linux struc resource ∗ctrl res;
system is the ability to perform the complex task of PCI
initialization. In addition, it allows for application software dev = pci find device(VENDORID,
to provide elaborated interfacing and user monitoring DEVICEID, NULL);
through appropriate software drivers. Initialization of the .
analog I/O card on the PMC site and controller setup are .
among such tasks that are best performed by software. .
pci enable device (dev);
get revision (dev);
5.1. Linux Device Drivers Essentials. Appropriate device
base addr = (volatile u32 ∗)
drivers have to be written in order to use daughter cards
pci resource start (dev, 2);
(such as an analog I/O board) or custom hardware com-
ctrl res = request mem region (
ponents on a bus internal to the SoC, and be able to
(unsigned long)base addr,
communicate with them from the embedded Linux. Drivers
0x80L,"control");
and application software for the AP1000 can be developed
bcr = (u32 ∗) ioremap nocache (
with the free Embedded Linux Development Kit (ELDK)
(unsigned long)base addr,
from DENX Software Engineering, Germany. The ELDK
0x80L);
includes the GNU cross development tools, along with
prebuilt target tools and libraries to support the target
system. It comes with full source code, including all patches, The readl() and writel() functions are defined to access
extensions, programs, and scripts used to build the tools. PCI memory space in units of 32 bits. Since the PowerPC
A complete discussion on writing Linux device drivers is is big-endian while the PCI bus is by definition little-
beyond the scope of this paper, and this information may be endian, a byte swap occurs when reading and writing PCI
found elsewhere, such as in [8]. Here, we only mention a few data. To ensure correct byte order, the le32 to cpu() and
important issues relevant to the pilot application. cpu to le32() functions are used on incoming and outgoing
data. The following code example defines some macros to
To support all the required functions when creating a
read and write the Board Control Register, to read data from
Linux device driver, the following includes are needed:
the analog input buffer, and to write to one of the four analog
output channels.
#include <linux/config.h>
#include <linux/module.h> volatile u32 ∗bcr;
#include <linux/pci.h>
#include <linux/init.h> #define GET BCR() (le32 to cpu(\\
#include <linux/kernel.h> readl (bcr)))
#include <linux/slab.h> #define SET BCR(x) writel(\\
#include <linux/fs.h> cpu to le32(x), bcr)
#include <linux/ioport.h> #define ANALOG IN()le32 to cpu(\\
#include <linux/ioctl.h> readl (&bcr[ANALOG INPUT BUF]))
#include <linux/byteorder/ #define ANALOG OUT(x,c) writel(\\
big endian.h> cpu to le32(x), \\
#include <asm/io.h> &bcr[ANALOG OUTPUT CHAN 00+c])
#include <asm/system.h>
#include <asm/uaccess.h>
5.3. Cross-Compilation with the ELDK. To properly compile
with the ELDK, a makefile is required. Kernel source code
5.2. PCI Access to the Analog I/O Board . The pci find should be available in KERNELDIR to provide for essential
device() function begins or continues searching for a PCI includes. The version of the preinstalled kernel on the
device by vendor/device ID. It iterates through the list of AP1000 is Linux 1.4. Example of a minimal makefile:
known PCI devices, and if a PCI device is found with
a matching vendor and device, a pointer to its device TARGET= thetarget
structure is returned. Otherwise, NULL is returned. For OBJS= myobj.o
the PMC66-16AISS8A04, the vendor ID is 0x10e3, and the
device ID is 0x8260. The device must then be initialized with #EDIT THE FOLLOWING TO POINT TO
pci initialize device() before it can be used by the driver. #THE TOP OF THE KERNEL SOURCE TREE
The start address of the base address registers (BARs) can be KERNELDIR = ∼ /kernel-sw-003996-01
obtained using pci resource start(). In the example, we get
BAR 2 which gives access to the main control registers of the CC = ppc 4xx−gcc
PMC66-16AISS8A04. LD = ppc 4xx−ld
EURASIP Journal on Embedded Systems 7

DEFINES = −D— KERNEL— −DMODULE\\ This is described by equations in the synchronously rotating
−DEXPORT SYMTAB reference frame (d, q) as
INCLUDES= −I$(KERNELDIR)/include\\
−I$(KERNELDIR)/include/Linux\\ d M d
−I$(KERNELDIR)/include/asm usd = Rs isd + σLs isd −σLs ωisq + Ψr ,
dt Lr dt
FLAGS =−fno-strict-aliasing \\   
Dd
−fno-common\\
−fomit-frame-pointer\\ d M
−fsigned-char
usq = Rs isq + σLs isq +σLs ωisd + ωΨr ,
dt Lr
  
CFLAGS = $(DEFINES) $(WARNINGS)\\ Dq
$(INCLUDES) $(SWITCHES)\\ (1)
$(FLAGS) d R
all: $(TARGET).o Makefile Ψr = r (Misd − Ψr ),
dt Lr

$(TARGET).o: $(OBJS) MRr

ω = P p ωr + isq ,
$(LD) −r -o $@$∧ Ψ r Lr
dωr 3 M D T
= Pp Ψr isq − ωr − l ,
5.4. Software and Driver Installation on the AP1000. For ease dt 2 JLr J J
of manipulation, user software and drivers are best carried on
a CompactFlash card, which is then inserted in the back slot where usd and usq are d and q components of stator voltage
of the AP1000 and mounted into the Linux file system. The us , isd , and isq are d and q components of stator current is , Ψr
drivers are then intalled, and the application software started, is the modulus of rotor flux modulus, and θ is the angular
as follows: position of rotor flux, ω is the synchronous angular speed of
the (d, q) reference frame (ω = dθ/dt), and Ls , Lr , and M
are stator, rotor, and mutual inductances, Rs , Rr are stator
mount /dev/discs/disc0/part1 /mnt and rotor resistances, σ is the leakage coefficient of the motor,
insmod /mnt/logic2/hwlogic.o and P p is the number of pole pairs, ωr is the mechanical rotor
insmo /mnt/aio.o speed, D is damping coefficient, J is the inertial momentum,
cd /dev and Tl is torque load.
mknod hwlogic c 254 0
mknod aio c 253 0 6.2. RFOC Algorithm. The derived expressions for each block
/mnt/cvecapp composing the induction motor RFOC scheme, as shown in
Figure 6, are given as follows:

6. Application: AC Induction Motor Control Speed PI Controller:

Given their well-known qualities of being cheap, highly 

robust, efficient, and reliable, AC induction motors currently i∗sq = k pv v + kiv v dt; v = ωr∗ − ωr . (2)
constitute the bulk of the motion industry park. From the
control point of view, however, these motors have highly
Rotor Flux PI Controller:
nonlinear behavior.

6.1. FPGA-Based Induction Motor Vector Control. The i∗sd = k p f  f + ki f  f dt;  f = Ψ∗
r − Ψr . (3)
selected control algorithm for our pilot application is the
rotor-flux oriented vector control of a three-phase AC
Rotor Flux Estimator:
induction motor of the squirrel-cage type. It is the first
method which makes it possible to artificially give some 
linearity to the torque control of induction motors [9]. Ψr = Ψ2rα + Ψ2rβ , (4)
RFOC algorithm consists in partial linearization of the Ψrβ
Ψrα
physical model of the induction motor by breaking up the cos θ = , sin θ = , (5)
stator current is into its components in a suitable reference Ψr Ψr
frame (d, q). This frame is synchronously revolving along
with
with the rotor flux space vector in order to get a separate
control of the torque and rotor flux. The overall strategy Lr Lr 
then consists in regulating the speed while maintaining Ψrα = (Ψsα − σLs isα ), Ψrβ = Ψsβ − σLs isβ , (6)
M M
the rotor flux constant (e.g., 1 Wb). The RFOC algorithm  
is directly derived from the electromechanical model of Ψsα = (usα − Rs isα ), Ψsβ = usβ − Rs isβ , (7)
a three-phase, Y-connected, squirrel-cage induction motor.
8 EURASIP Journal on Embedded Systems

VDC
sp ah
ωr∗ + Speed PI i∗
sq + Q-current vsq sp al
+ + usq ∗ 3-φ
− controller −
PI controller Inverse usα SVPWM sp bh
voltage
Decoupling usd transform u∗ module sp bl
Ψ∗
r + Rotor flux i∗sd + D-current vsd park
sβ
gating sp ch
PWM
+ + inverter
− PI controller − PI controller sp cl

i sd isα i sa
Park Clarke
i sq transform isβ transform i sb

cos θ Rotor
sin θ usα Clarke usa
flux
Ψr estimator usβ transform usb
ω
ω estimator IM
ωr
Speed measure

Figure 6: Conceptual block diagram of the system.

and using Clarke transformation Inverse Park Transformation:

1 2
isα = isa , isβ = √ isa + √ isb , (8) ⎡ ⎤ ⎡ ⎤⎡ ⎤
3 3 u∗sα cos θ − sin θ usd
1 2 ⎣ ⎦=⎣ ⎦⎣ ⎦. (16)
usα = usa , usβ = √ usa + √ usb . (9) u∗sβ sin θ cos θ usq
3 3
To be noticed that sine and cosine, of (5), sum up to a
division, and therefore do not have to be directly calculated. In the above equations, for x standing for any variable
such as voltage us , current is or rotor flux Ψr , we have the
Current PI Controller: following.
 (x∗ ) Input reference corresponding to x.
vsd = k pi isd + kii isd dt; isd = i∗
sd − isd , (10) (x ) Error signal corresponding to x.
(k px , kix ) Proportional and integral parameters corre-
 sponding to the PI controller of x.
vsq = k pi isq + kii isq dt; isq = i∗
sq − isq . (11) (xa , xb , xc ) a, b, and c three-phase components of x in the
stationary reference frame.
Decoupling: (xα , xβ ) α and β two-phase components of x in the
stationary reference frame.
usd = σLs vsd + Dd ; usq = σLs vsq + Dq , (12) (xd , xq ) d and q components of x in the synchronously
rotating frame.
with
The RFOC scheme features vector transformations
M d M (Clarke and Park), 4 IP regulators, and space-vector PWM
Dd = −σLs ωisq + Ψr , Dq = +σLs ωisd + ωΨr . generator (SVPWM). This algorithm is of interest for its
Lr dt Lr
(13) good performances, and because it has a fair level of
complexity which benefits from a very-high-performance
Omega (ω) Estimator: FPGA implementation. In fact, FPGAs make it possible to
execute the loop of a complicated control algorithm in a
MRr matter of a few microseconds. The first prototype of such
ω = P p ωr + isq . (14) a controller has been developed using the method and
Ψ r Lr
platform described here, and has been implemented entirely
Park Transformation: in FPGA logic [10].
⎡ ⎤ ⎡ ⎤⎡ ⎤
Commonly used mediums prior to the advent of today’s
isd cos θ sin θ is large FPGAs, including the use of DSPs alone and/or special-
⎣ ⎦=⎣ ⎦⎣ α ⎦. (15) ized microcontrollers, led to a total cycle time of more than
isq − sin θ cos θ isβ 100 μs for vector control. This lead to switching frequencies
EURASIP Journal on Embedded Systems 9

as the replaced block does not require a lot of steps for

completion. If the XSG design requires more steps to process
Dynamo with
the data which is sent than what is necessary for the next data
optical speed
encoder to be ready for processing, a costly (time wise) adjustment
has to be made. The Simulink period for a given simulated
Squirrel-cage FPGA clock (one XSG design step) must be reduced, while
Encoder
induction motor the rest of the Simulink system runs at the same speed as
cable
before. In a fixed step Simulink simulation environment, this
Resistive load High-voltage means that the fixed step size must be reduced enough so
power module
that the XSG system has plenty of time to complete between
Power
supply two data acquisitions. Obviously, such lenghty simulations
Digital I/O
from FPGA
should only be launched once the debugging process is
Cable interface finished and the controller is ready to be thouroughly tested.
to analog I/O card Once the control algorithm is designed with XSG, the
HW/SW cosimulation procedure consists of the following.
Figure 7: Experimental setup with power electronics, induction (1) Building the interface between Simulink and FPGA-
motor, and loads. Based Cosimulation board.
(2) Making a hardware cosimulation design.
in the range of 1–5 kHz, which produced disturbing noise in (3) Executing hardware cosimulation.
the audible band. With today’s FPGAs, it becomes possible to When using Simulink environment for cosimulation, one
fit a very large control system on a single chip, and to support should distinguish between the single-step and free-running
very high switching frequencies. modes, in order for debugging purposes, to get much shorter
simulations times.
6.3. Validation of RFOC Using Cosimulation with XSG. A Single-step cosimulation can improve simulation time
strong hardware/software cosimulation environment and when replacing one part of a bigger system. This is espe-
methodology is necessary to allow validation of the hardware cially true when replacing blocks that cannot be natively
design against a theoretical control system model. accelerated by Simulink, like embedded Matlab functions.
As mentioned is Section 3, the design flow which has Replacing a block with an XSG cosimulated design shifts the
been adopted in this research uses the XSG blockset in burden from Matlab to the FPGA, and the block no longer
Matlab/Simulink. XSG model of RFOC block is built up remains the simulation’s bottleneck.
from (2) to (16) and the global system architecture is shown Free-running cosimulation means that the FPGA will
in Figure 8 where Gateway-in and Gateway-out blocks pro- always be running at full speed. Simulink will no longer
vide the necessary interface between the fixed-point FPGA be dictating the speed of an XSG step as was the case
hardware that include the RFOC and Space Vector Pulse in single-step cosimulation. With the Virtex-4 ML402 SX
Width Modulation (SVPWM) algorithms and the floating- XtremeDSP Evaluation Platform, that step will now be a fixed
point Simulink blocksets mainly the SimPowerSystems (SPS) 10 nanoseconds. Therefore, even a very complicated system
models. In fact to make the simulations more realistic, the requiring many steps for completion should have ample time
three-phase AC induction motor and the corresponding to process its data before the rest of the Simulink system does
Voltage Source Inverter were modelled in Simulink using its work. Nevertheless, a synchronization mechanism should
the SPS blockset, which is robust and well proven. To be always be used for linking the free-running cosimulation
noticed that SVPWM is a widely used technique for three- block with the rest of the design to ensure an exterior start
phase voltage-source inverters (VSI), and is well suited for signal will not be mistakenly interpreted as more than one
AC induction motors. start pulse. Table 3 shows the decrease of simulation time
At runtime, the hardware design (RFOC and SVPWM) afforded by the free-running mode for the induction motor
is automatically downloaded into the actual FPGA device, vector control. This has been implemented using XSG with
and its response can then be verified in real-time against that the motor and its SVPWM-based drive being modeled using
of the theoretical model simulation done with floating-point SPS blockset from Simulink. For the same precision and the
Simulink blocksets. An arbitrary load is induced by varying same amount of data to be simulated (speed variations over
the torque load variable Tl as a time function. SPS receives a period of 7 seconds), a single-step approach would require
a reference voltage from the control through the inverse 100.7 times longer to complete, thus being an ineffective
Park transformation module. This voltage consists of two approach. A more complete discussion of our methodology
quadrature voltages (u∗sα , u∗sβ ), plus the angle (sine/cosine) for rapid testing of an XSG-based controller using free-
of the voltage phasor usd corresponding to the rotor flux running cosimulation and SPS, has been given in [11].
orientation (Figure 6).
6.5. Timing Analysis. Before actually generating a BIT file
6.4. Reducing Cosimulation Times. In a closed loop setting, to reconfigure the FPGA, and whether the cosimulation is
such as RFOC, hardware acceleration is only possible as long done through JTAG or Ethernet, the design must be able to
10 EURASIP Journal on Embedded Systems

System generator blockset domain Power system blockset domain

(fixed point) (floating point)

fu_pul_ou Out u Out1

is_abc In1
vqs fire_u fu_in Gateway Out6
fu_pulbar_o ubar Out2
vds fire_v Out
Gateway Out9 wm In2 Out3
START fire_w v
fv_pul_ou Out
Firing_Signals Gateway Out17 Sensors
vbar
fv_in fv_pulbar_o Te>
Out
Gateway Out10 w
fw_pul_ou Out volt_mea>
wbar
Gateway Out13
fw_pulbar_o Motor_Drive
Out
fw_in Gateway Out11
start_contr

Gating

fu ua

fv ub
In
prediction_uab vqs_in1
In
vds_in1
y
spd_ref In Wref
vqs_in
x Speed_Ref
uA flux_ref In
vds_in
isa phiref

Rotor_Flux_Ref

uB
usa

usb Discrete,
Ts = 2.5e- 006 s

READY aq_done Syestem Resource

generator estimator
m_w In
Vector_control vds_in2

Figure 8: Indcution motor RFOC drive, as modelled with XSG and SPS blocksets.

Table 3: Simulation times and methods being fully designed, analysed (timing wise), and debugged
Type of simulation Simulation time
through the aforementioned FPGA-in-the-loop simulation
platform, the corresponding NGC binary netlist file or
Free-running cosimulation 1734 s
VHDL/Verilog code are automatically generated. These
Single-step cosimulation 174610 s (48 hours) could then be integrated within the SoC architecture using
Xilinx Platform Studio (XPS) and targetting the AP1000
platform. Next section describes the related steps.
run at 100 MHz (10 nanoseconds step time). As long as the
design is running inside Simulink, there are never any issues
with meeting timing requirements for the XSG model. Once 6.6. Experimental Setup. Figure 7 shows the experimental
completed, the design will be synthesized, and simulated on setup with power electronics, induction motor, and loads.
FPGA. If the user launches the cosimulation block generation The power supply is taken from a 220 V outlet. The high
process, the timing errors will be mentioned quite far into voltage power module, from Microchip, is connected to the
the operation. This means that, after waiting for a relatively analog I/O card through the rainbow flex cable, and to
long delay (sometimes 20–30 minutes depending on the the expansion digital I/Os of the AP1000 through another
complexity of a design and the speed of the host computer), parallel cable. Signals from a 1000-line optical speed encoder
the user notices the failure to meet timing requirements with are among the digital signals fed to the FPGA. As for the
no extra information to quickly identify the problem. This loads, there is both a manually-controlled resistive load box,
is why the timing analysis tool must always be run prior to and a dynamo coupled to the motor shaft.
cosimulation. While it might seem a bit time-consuming, From the three motor phases, three currents and three
this tool will not simply tell you that your design does not voltages (all prefiltered and prescaled) are fed to the analog
meet requirements, but it will give you the insight required I/O board to be sampled. Samples are stored in an internal
to fix the timing problems. The control algorithm once input buffer until fetched by the controller on FPGA. Data
EURASIP Journal on Embedded Systems 11

exchange between the FPGA and the I/O board proceeds suitable for the design of on-chip motion controllers and
through the PLB and the Dual Processor PCI Bus Bridge to other SoCs with a need for analog interfacing. It supports
and from the PMC site. embedded application software coupled with custom FPGA
The process of generating SVPWM signals continuously logic and analog interfacing, and is very well suited to FPGA-
runs in parallel with controller logic, but the speed at which in-the-loop control and SoC controller prototyping. Such
these signals are generated is greater than the speed required platform is suitable for academia and research communauty
for the vector control processing. As a consequence, these that cannot afford the expensive commercial solutions for
two processes are designed and tested separately before being FPGA-in-the-loop simulation [12, 13].
assembled and tested together. A convenient FPGA design, simulation, and test proce-
Power gating and motor speed decoding are continuous dure, suitable for advanced feedback controllers, has been
processes that have critical clocking constraints beyond the outlined. It uses the Xilinx System Generator blockset in
capabilities of bus operation to and from the I/O board. Matlab/Simulink and a simulated motor drive described with
Therefore, even though the PMC66-16AISS8A04 board also the SPS blockset. SoC integration of the resulting controller is
provides digital I/O, both the PWM gating signals and the done in Xilinx Platform Studio. Our custom SoC design has
input pulses from the optical speed encoder are directly been described, with highlights on the state machine for bus
passed through FPGA pins to be processed by dedicated interfacing, NGC file integration, BIN file generation, and
hardware logic. This is done by plugging a custom-made FPGA configuration.
adapter card with Samtec CON 0.8 mm connectors into the Application software and drivers development for
expansion site on the AP1000. While the vector control uses embedded Linux are often needed to provide for PCI and
data acquired from the AIO card through a state machine, analog I/O card initialization, interfacing, and monitoring.
the PWM signals are constantly fed to the power module We have provided here some pointers along with essential
(Figure 6). Those signals are sent directly through the general information not easily found elsewhere. The proposed design
purpose digital outputs on the AP1000 itself instead of going flow and prototyping platform have been applied to the
through the AIO card. This ensures complete control over analysis, design, and hardware implementation of a vector
the speed at which these signals are generated and sent controller for three-phase AC induction motors, with very
while targeting a specific operating frequency (16 kHz in good performance results. The resulting computation times,
our example). This way, the speed calculations required for of about 1.5 μs, can in fact be considered record-breaking for
the vector control algorithm are done using precise clocking such a controller.
without adding to the burden of the state machine which
dictates the communications between FPGA and the AIO
card. The number of transitions found on the signal lines Acknowledgments
between the FPGA and speed encoder are used to evaluate
the speed at which the motor is operating. This research is funded by a Grant from the National
Sciences and Engineering Research Council of Canada
6.7. Timing Issues. Completion of one loop cycle of our vec- (NSERC). CMC Microsystems provided development tools
tor control design, takes 122 steps leading to a computation and support through the System-on-Chip Research Network
time of less than 1.5 μs. To be noticed that for a sampling rate (SOCRN) program.
of 32 kHz, the SVPWM signal has 100 divisions (two zones
divided by 50), which has been chosen as a good compromise
between precision and simulation time. The simulation References
fixed-step size is then 625 nanoseconds, which is already [1] “Accelerating Canadian competitiveness through microsys-
small enough to hinder the performance of simulating the tems: strategic plan 2005–2010,” Tech. Rep., CMC Microsys-
SPS model. Since PWM signal generation is divided into tems, Kingston, Canada, 2004.
two zones, for every 50 steps of Simulink operations (PWM [2] J. J. Rodriguez-Andina, M. J. Moure, and M. D. Valdes,
signal generation and SPS model simulation), the 122 vector “Features, design tools, and application domains of FPGAs,”
control steps must complete. The period of the XSG— IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp.
Simulink system must be adjusted in order for the XSG 1810–1823, 2007.
model to run 2.44 times faster than the other Simulink [3] R. Dubey, P. Agarwal, and M. K. Vasantha, “Programmable
components. The simulation fixed-step size becomes 2.56 logic devices for motion control—a review,” IEEE Transactions
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words, since the SPS model and PWM signals generation take [4] E. Monmasson and M. N. Cirstea, “FPGA design methodology
little time (in terms of steps) to complete whereas the vector for industrial control systems—a review,” IEEE Transactions on
control scheme requires numerous steps, the coupling of the Industrial Electronics, vol. 54, no. 4, pp. 1824–1842, 2007.
two forces the use of a very small simulation fixedstep size. [5] D. Zhang, A stochastic approach to digital control design and
implementation in power electronics, Ph.D. thesis, Florida State
University College of Engineering, Tallahassee, Fla, USA, 2006.
7. Conclusion [6] Y.-Y. Tzou and H.-J. Hsu, “FPGA realization of space-vector
PWM control IC for three-phase PWM inverters,” IEEE
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and use of a rapid prototyping platform and design flow 1997.
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[7] A. de Castro, P. Zumel, O. Garcı́a, T. Riesgo, and J. Uceda,

“Concurrent and simple digital controller of an AC/DC
converter with power factor correction based on an FPGA,”
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pp. 334–343, 2003.
[8] “Developing device drivers for Linux Kernel 1.4.,” Tech. Rep.,
CMC Microsystems, Kingston, Canada, 2006.
[9] B. K. Bose, Power Electronics and Variable-Frequency Drives:
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[13] National Instruments, “Creating Custom Motion Control and
Drive Electronics with an FPGA-based COTS System,” 2006.
 Photographȱ©ȱTurismeȱdeȱBarcelonaȱ/ȱJ.ȱTrullàs

Preliminaryȱcallȱforȱpapers OrganizingȱCommittee
HonoraryȱChair
The 2011 European Signal Processing Conference (EUSIPCOȬ2011) is the MiguelȱA.ȱLagunasȱ(CTTC)
nineteenth in a series of conferences promoted by the European Association for GeneralȱChair
Signal Processing (EURASIP, www.eurasip.org). This year edition will take place AnaȱI.ȱPérezȬNeiraȱ(UPC)
in Barcelona, capital city of Catalonia (Spain), and will be jointly organized by the GeneralȱViceȬChair
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) and the CarlesȱAntónȬHaroȱ(CTTC)
Universitat Politècnica de Catalunya (UPC). TechnicalȱProgramȱChair
XavierȱMestreȱ(CTTC)
EUSIPCOȬ2011 will focus on key aspects of signal processing theory and
TechnicalȱProgramȱCo
Technical Program CoȬChairs
Chairs
applications
li ti as listed
li t d below.
b l A
Acceptance
t off submissions
b i i will
ill be
b based
b d on quality,
lit JavierȱHernandoȱ(UPC)
relevance and originality. Accepted papers will be published in the EUSIPCO MontserratȱPardàsȱ(UPC)
proceedings and presented during the conference. Paper submissions, proposals PlenaryȱTalks
for tutorials and proposals for special sessions are invited in, but not limited to, FerranȱMarquésȱ(UPC)
the following areas of interest. YoninaȱEldarȱ(Technion)
SpecialȱSessions
IgnacioȱSantamaríaȱ(Unversidadȱ
Areas of Interest deȱCantabria)
MatsȱBengtssonȱ(KTH)
• Audio and electroȬacoustics.
• Design, implementation, and applications of signal processing systems. Finances
MontserratȱNájarȱ(UPC)
Montserrat Nájar (UPC)
• Multimedia
l d signall processing andd coding.
d
Tutorials
• Image and multidimensional signal processing. DanielȱP.ȱPalomarȱ
• Signal detection and estimation. (HongȱKongȱUST)
• Sensor array and multiȬchannel signal processing. BeatriceȱPesquetȬPopescuȱ(ENST)
• Sensor fusion in networked systems. Publicityȱ
• Signal processing for communications. StephanȱPfletschingerȱ(CTTC)
MònicaȱNavarroȱ(CTTC)
• Medical imaging and image analysis.
Publications
• NonȬstationary, nonȬlinear and nonȬGaussian signal processing. AntonioȱPascualȱ(UPC)
CarlesȱFernándezȱ(CTTC)
Submissions IIndustrialȱLiaisonȱ&ȱExhibits
d i l Li i & E hibi
AngelikiȱAlexiouȱȱ
Procedures to submit a paper and proposals for special sessions and tutorials will (UniversityȱofȱPiraeus)
be detailed at www.eusipco2011.org. Submitted papers must be cameraȬready, no AlbertȱSitjàȱ(CTTC)
more than 5 pages long, and conforming to the standard specified on the InternationalȱLiaison
EUSIPCO 2011 web site. First authors who are registered students can participate JuȱLiuȱ(ShandongȱUniversityȬChina)
in the best student paper competition. JinhongȱYuanȱ(UNSWȬAustralia)
TamasȱSziranyiȱ(SZTAKIȱȬHungary)
RichȱSternȱ(CMUȬUSA)
ImportantȱDeadlines: RicardoȱL.ȱdeȱQueirozȱȱ(UNBȬBrazil)

P
Proposalsȱforȱspecialȱsessionsȱ
l f i l i 15 D 2010
15ȱDecȱ2010
Proposalsȱforȱtutorials 18ȱFeb 2011
Electronicȱsubmissionȱofȱfullȱpapers 21ȱFeb 2011
Notificationȱofȱacceptance 23ȱMay 2011
SubmissionȱofȱcameraȬreadyȱpapers 6ȱJun 2011

Webpage:ȱwww.eusipco2011.org

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