ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-2700: Digital Logic Design Winter 2020

Solutions - Homework 1
(Due date: January 23rd @ 5:30 pm)
Presentation and clarity are very important! Show your procedure!

PROBLEM 1 (30 PTS)

a) Simplify the following functions using ONLY Boolean Algebra Theorems. For each resulting simplified function, sketch the
logic circuit using AND, OR, XOR, and NOT gates. (14 pts)
✓ 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥𝑦̅𝑧 + 𝑦(𝑥 ̅̅̅̅̅̅̅
+ 𝑧) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
✓ 𝐹 = 𝐴(𝐵 ̅ 𝐶̅ ) + 𝐵̅
✓ 𝐹 = (𝐵̅ + 𝐴)(𝐶̅ + 𝐵̅ )(𝐶 + 𝐴) + 𝐶𝐴 ✓ 𝐹(𝑋, 𝑌, 𝑍) = ∏(𝑀1 , 𝑀3 , 𝑀6 , 𝑀7 )

✓ 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑥𝑦̅𝑧 + 𝑦(𝑥 + 𝑧) = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅ + 𝑧) + 𝑥𝑦̅𝑧 = ̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅
𝑦(𝑥 𝑦(𝑥 + 𝑧). ̅̅̅̅̅
̅̅̅̅̅̅̅ 𝑥𝑦̅𝑧 = (𝑥 + 𝑦̅ + 𝑧)(𝑥̅ + 𝑦 + 𝑧̅)
𝐹 = 𝑥𝑥̅ + 𝑥𝑦 + 𝑥 𝑧̅ + 𝑧𝑥 ̅ + 𝑧𝑦 + 𝑧𝑧̅ + 𝑦̅𝑥̅ + 𝑦̅𝑦 + 𝑦̅𝑧̅ = 𝑥𝑦 + 𝑥𝑧̅ + 𝑧𝑥̅ + 𝑧𝑦 + 𝑦̅𝑥̅ + 𝑦̅𝑧̅
𝐹 = 𝑥𝑧̅ + 𝑥̅ 𝑦̅ + 𝑦̅𝑧̅ + 𝑥𝑦 + 𝑥̅ 𝑧 + 𝑧𝑦 = 𝑥𝑧̅ + 𝑥̅ 𝑦̅ + 𝑥𝑦 + 𝑥̅ 𝑧 + 𝑧𝑦
𝐹 = 𝑥𝑧̅ + 𝑥𝑦 + 𝑦𝑧 + 𝑦̅𝑥̅ + 𝑥̅ 𝑧 = 𝑥𝑧̅ + 𝑥𝑦 + 𝑦𝑧 + 𝑦̅𝑥̅ = 𝑧𝑦 + 𝑧̅𝑥 + 𝑥𝑦 + 𝑦̅𝑥̅ = 𝑧𝑦 + 𝑧̅𝑥 + 𝑦̅𝑥̅
x y

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
✓ 𝐹 = 𝐴(𝐵 ̅ 𝐶̅ ) + 𝐵̅ = ̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅
𝐴(𝐵̅ 𝐶̅ ). 𝐵 = (𝐴̅ + (𝐵̅ 𝐶̅ )) . 𝐵 = (𝐴̅ + 𝐵𝐶 + 𝐵̅ 𝐶̅ ). 𝐵 = 𝐴̅𝐵 + 𝐵𝐶 + 𝐵𝐵̅ 𝐶̅ = 𝐴̅𝐵 + 𝐵𝐶
A

B
C

✓ 𝐹 = (𝐶 + 𝐴)(𝐶̅ + 𝐵
̅ )(𝐴 + 𝐵̅ ) + 𝐶𝐴 = (𝐶 + 𝐴)(𝐶̅ + 𝐵̅ ) + 𝐶𝐴
(𝐶 + 𝐴)(𝐶̅ + 𝐵 ̅ + 𝐶̅ 𝐴 + 𝐴𝐵
̅) + 𝐶𝐴 = 𝐶𝐵 ̅ + 𝐶̅ 𝐴 + 𝐶𝐴 = 𝐶𝐵
̅ + 𝐶𝐴 = 𝐶𝐵 ̅+𝐴

✓ 𝐹(𝑋, 𝑌, 𝑍) = ∏(𝑀1 , 𝑀3 , 𝑀6 , 𝑀7 ) = ∑(𝑚0 , 𝑚2 , 𝑚4 , 𝑚5 ) = 𝑋̅𝑌̅𝑍̅ + 𝑋̅𝑌𝑍̅ + 𝑋𝑌̅𝑍̅ + 𝑋𝑌̅𝑍 = 𝑋̅𝑍̅ + 𝑋𝑌̅

X Y Z

1 Instructor: Daniel Llamocca

 ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Winter 2020

b) Given the following circuit with inputs 𝑥0 , 𝑥1 , 𝑦0 , 𝑦1 , 𝑐0 : (16 pts) 𝑥1 𝑦1 𝑥0 𝑦0

▪ Provide the Boolean expression (based on the circuit

inputs) for 𝑠0 , 𝑠1 , 𝑐1 , 𝑐2 . (7 pts)

▪ For 𝑠0 and 𝑐1 : (9 pts)

✓ Express the Boolean functions using both the
minterms and maxterms representations. (4 pts)
✓ Provide the Boolean functions using the Canonical 𝑐0
Sum of Products (SOP), and Product of Sums 𝑐 2 𝑐1
(POS).
✓ Sketch the logic circuits as Canonical Sum of
Products and Product of Sums. (3 pts)

𝑠1 𝑠0
𝑠0 = 𝑥0 𝑦0 𝑐0
𝑐1 = 𝑥0 𝑦0 + (𝑥0 + 𝑦0 )𝑐0 = 𝑥0 𝑦0 + 𝑥0 𝑐0 + 𝑦0 𝑐0
𝑠1 = 𝑥0 𝑦0 𝑐1 = 𝑥0 𝑦0 (𝑥0 𝑦0 + 𝑥0 𝑐0 + 𝑦0 𝑐0 )
𝑐2 = 𝑥1 𝑦1 + (𝑥1 + 𝑦1 )𝑥0 𝑦0 + (𝑥1 + 𝑦1 )(𝑥0 + 𝑦0 )𝑐0

Minterms and maxterms:

x0 y0 c0 c1 s 0
 𝑐1 (𝑥0 , 𝑦0 , 𝑐0 ) = ∑(𝑚3 , 𝑚5 , 𝑚6 , 𝑚7 ) = ∏(𝑀0 , 𝑀1 , 𝑀2 , 𝑀4 )
 𝑠0 (𝑥0 , 𝑦0 , 𝑐0 ) = ∑(𝑚1 , 𝑚2 , 𝑚4 , 𝑚7 ) = ∏(𝑀0 , 𝑀3 , 𝑀5 , 𝑀6 ) 0 0 0 0 0
0 0 1 0 1
Sum of Products: 0 1 0 0 1
𝑐1 = ̅̅̅𝑦
𝑥0 0 𝑐0 + 𝑥0 ̅̅̅𝑐
𝑦0 0 + 𝑥0 𝑦0 𝑐̅0 + 𝑥0 𝑦0 𝑐0 0 1 1 1 0
𝑠0 = 𝑥
̅̅̅0 ̅̅̅𝑐
𝑦0 0 + ̅̅̅𝑦
𝑥0 0 𝑐̅0 + 𝑥0 𝑦
̅̅̅𝑐
0 ̅0 + 𝑥0 𝑦0 𝑐0 1 0 0 0 1
1 0 1 1 0
Product of Sums: 1 1 0 1 0
𝑐1 = (𝑥0 + 𝑦0 + 𝑐0 )(𝑥0 + 𝑦0 + 𝑐̅0 )(𝑥0 + ̅̅̅
𝑦0 + 𝑐0 )(𝑥̅̅̅0 + 𝑦0 + 𝑐0 ) 1 1 1 1 1
𝑠0 = (𝑥0 + 𝑦0 + 𝑐0 )(𝑥0 + ̅̅̅
𝑦0 + 𝑐̅0 )(𝑥
̅̅̅0 + 𝑦0 + 𝑐̅0 )(𝑥 ̅̅̅0 + 𝑐0 )
̅̅̅0 + 𝑦

𝑥0 𝑦0 𝑐0 𝑥0 𝑦0 𝑐0

𝑐1 𝑐1

𝑠0 𝑠0

2 Instructor: Daniel Llamocca

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Winter 2020

PROBLEM 2 (24 PTS)

a) Complete the truth table describing the output of the following circuit and write the simplified Boolean equation (6 pts).
t f

𝑥 1 1
0 1
𝑧
f 0 1
1 1
1 1
𝑦 t 0 1
0 0
𝑓 = 𝑥̅ + 𝑦̅ + 𝑧
1 1

b) Complete the timing diagram of the logic circuit whose VHDL description is shown below: (5 pts)

library ieee;
use ieee.std_logic_1164.all; a

entity circ is
port ( a, b, c: in std_logic; b
f: out std_logic);
end circ;
c
architecture struct of circ is
signal x, y: std_logic;
x
begin
f <= y xnor (not a); y
x <= a xor (not b);
y <= x nand c;
end struct; f

c) The following is the timing diagram of a logic circuit with 3 inputs. Sketch the logic circuit that generates this waveform.
Then, complete the VHDL code. (8 pts)

library ieee;
use ieee.std_logic_1164.all;
a
entity wave is
port ( a, b, c: in std_logic;
f: out std_logic);
end wave;
c
architecture struct of wave is
signal x: std_logic;
begin f
x <= not(a) and b and not(c);
f <= (not(b) and c) or x;

end struct;

a b c f
ab
0 0 0 0 01 11 10
c
0 0 1 1
0 1 0 1 0 0 1 0 0
0 1 1 0
1 1 0 𝑐 𝑓
1 0 0 0
1 0 1 1
1 1 0 0 𝑓 = ̅𝑐 + ̅ 𝑐̅
1 1 1 0

3 Instructor: Daniel Llamocca

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Winter 2020

d) Complete the timing diagram of the following circuit: (5 pts)

b
a
x
b c
f
x
y

f
PROBLEM 3 (10 PTS)
▪ A majority gate has an output value of 1 if there are more 1’s than 0’s on its inputs. The output is 0 otherwise.
▪ Design (provide the simplified Boolean equation and sketch the logic circuit) a 4-input majority gate with inputs a, b, c, d,
and output f.
The function break ties in favor of zeros when the number of inputs is even. Example: abcd=1100 → f = 0.

x y z w f xy
00 01 11 10
0 0 0 0 0 zw
𝑓 = 𝑦𝑧𝑤 + 𝑥𝑧𝑤 + 𝑥𝑦𝑤 + 𝑥𝑦𝑧
0 0 0 1 0 00 0 0 0 w
0 0 1 0 0 z
0 0 1 1 0 01 0 1 0 z w 𝑦
0 1 0 0 0 w 𝑧
0 1 0 1 0 𝑤
11 0 1 1 1 z w
0 1 1 0 0 𝑥
z
0 1 1 1 1 10 0 1 0
𝑓
z w
1 0 0 0 0
1 0 0 1 0 x y x y x y x y
1 0 1 0 0
1 0 1 1 1 x
1 1 0 0 0
1 1 0 1 1 y y y
1 1 1 0 1
1 1 1 1 1

PROBLEM 4 (11 PTS)

▪ Design a logic circuit (simplify your circuit) that opens a lock (𝑓 = 1) whenever the user presses the correct number on each
numpad (numpad 1: 9, numpad 2: 4). The numpad encodes each decimal number using BCD encoding (see figure). We
expect that the 4-bit groups generated by each numpad be in the range from 0000 to 1001. Note that the values from
1010 to 1111 are assumed not to occur.
Suggestion: Create two circuits: one that verifies the first number (9), and another that verifies the second number (4).
Then perform the AND operation on the two outputs. This avoids creating a truth table with 8 inputs.
a
BCD code Number b F
c
x y z w
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
pressed
0
1
2
3
1
x y z w

2
5 6 x y z w
d
e
f
g
h
?
0 1 0 0 4 7 8 9 3
0 1 0 1 5
0 1 1 0 6 0 4 5 6
0 1 1 1 7
Numpad 1 7 8
1 0 0 0 8
1 0 0 1 9
Numpad 2
4 Instructor: Daniel Llamocca
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Winter 2020

xy
00 01 11 𝑓1 = 𝑥𝑤
zw
f1 f2
0 0 X 0
0 0 numpad 1
0 0 01 0 0 X 1
0 0 X W
0 0 11 0 0 X X
𝑑
0 1
0 0 10 0 0 X
0 0 f1
0 0
0 0 xy F
00 01 11 10
1 0 𝑓2 = 𝑦𝑧̅𝑤
̅
X X 00 0 1 X 0
X X
f2
X X 01 0 0 X
X X
X X 11 0 0 X 𝑓 𝑔 ℎ
X X
10 0 0 X X Z W

numpad 2
𝐹 = 𝑑𝑓 ̅𝑔ℎ̅

PROBLEM 5 (25 PTS)

▪ A numeric keypad produces a 4-bit code as shown below. We want to design a logic circuit that converts each 4-bit code to
a 7-segment code, where each segment is an LED: A LED is ON if it is given a logic ‘1’. A LED is OFF if it is given a logic ‘0’.

✓ Complete the truth table for each output ( , , 𝑐, 𝑑, 𝑒, 𝑓, 𝑔).

✓ Provide the simplified expression for each output ( , , 𝑐, 𝑑, 𝑒, 𝑓, 𝑔). Use Karnaugh maps for , , 𝑐, 𝑑, 𝑒 and the Quine-
McCluskey algorithm for 𝑓, 𝑔. Note it is safe to assume that the codes 1010 to 1111 will not be produced by the keypad.

a
0 1 2 𝑥 f b
4 5 𝑦 7
𝑧
6 7 8 𝑤 e c
9 d

Value x y z w a b c d e f g
0 0 0 0 0 0: 2: 3: 4:
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0 6: 7: 8: 9:
9 1 0 0 1 1 1 1 1 0 1 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

5 Instructor: Daniel Llamocca

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Winter 2020

Value x y z w a b c d e f g a b
xy
00 01 10 00 01 11 10
0 0 0 0 0 1 1 1 1 1 1 0 zw zw
1 0 0 0 1 0 1 1 0 0 0 0 00 1 0 X 1 00 1 1
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1 01 0 1 X 1 01 1 0 X 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
11 1 1 X X 11 1 1 X X
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 1 10 1 1 X 0 X X
8 1 0 0 0
9 1 0 0 1 1 1 1 1 0 1 1
1 0 1 0 X X X X X X X c d
1 0 1 1 X X X X X X X xy xy
00 01 11 10 00 01 11 10
1 1 0 0 X X X X X X X zw zw
1 1 0 1 X X X X X X X 00 1 1 00 1 0 X 1
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X 01 1 1 X 1 01 0 1
= 𝑦̅𝑤̅ + 𝑤𝑦 + 𝑥 + 𝑧
= 𝑦̅ + 𝑧̅𝑤
̅ + 𝑧𝑤 11 1 1 X X 11 1 0 X
𝑐 = 𝑦 + 𝑧̅ + 𝑤
𝑑 = 𝑥 + 𝑧𝑤 ̅ + 𝑦̅𝑧 + 𝑤
̅𝑦̅ + 𝑧̅𝑤𝑦 1 X X 10 1 1 X X
𝑒=𝑤 ̅𝑦̅ + 𝑧𝑤̅
e
xy
00 01 11
zw
1 0 X 1

01 0 0 X 0

11 0 0 X X

10 1 1 X
▪ 𝑓 = ∑ 𝑚(0,4,5,6,8,9) + ∑ 𝑑(10,11,12,13,14,15).

Number 4-literal 3-literal 2-literal 1-literal

of ones implicants implicants implicants implicants
m0,4 = 0-00 ✓ m0,4,8,12 = --00
0 m0 = 0000 ✓ m0,8,4,12 = --00
m0,8 = -000 ✓
m4,5,12,13 = -10-
m4,12,5,13 = -10-
m4,5 = 010- ✓ m4,6,12,14 = -1-0
m4,6 = 01-0 ✓ m4,12,6,14 = -1-0
m4 = 0100 ✓ m4,12 = -100 ✓ m8,9,10,11 = 10--
1 m8,10,9,11 = 10—
m8 = 1000 ✓ m8,9 = 100- ✓
m8,10 = 10-0 ✓ m8,9,12,13 = 1-0- ✓
m8,12 = 1-00 ✓ m8,12,9,13 = 1-0-
m8,10,12,14 = 1--0 ✓
m8,12,10,14 = 1—-0 m8,10,12,14,9,13,11,15 = 1---
m5,13 = -101 ✓ m8,9,12,13,10,14,11,15 = 1---
m6,14 = -110 ✓
m5 = 0101 ✓
m9,11 = 10-1 ✓
m6 = 0110 ✓
m9,13 = 1-01 ✓ m9,13,11,15 = 1--1 ✓
2 m9 = 1001 ✓
m10,11 = 101- ✓ m10,14,11,15 = 1-1- ✓
m10= 1010 ✓
m10,14 = 1-10 ✓
m12= 1100 ✓
m12,13 = 110- ✓
m12,14 = 11-0 ✓
m11= 1011 ✓
3 m13= 1101 ✓ m11,15 = 1-11 ✓
m14= 1110 ✓
4 m15= 1111 ✓

6 Instructor: Daniel Llamocca

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Winter 2020

𝑓 = 𝑧̅𝑤
̅ + 𝑦𝑧̅ + 𝑦𝑤
̅ + 𝑥𝑦̅ + 𝑥

Minterms
Prime Implicants
0 4 5 6 8 9
m0,4,8,12 𝑧̅𝑤
̅ X X X
m4,5,12,13 𝑦𝑧̅ X X
m4,6,12,14 𝑦𝑤̅ X X
m8,9,10,11 𝑥𝑦̅ X X
m8,10,12,14,9,13,11,15 𝑥 X X

𝑓 = 𝑧̅𝑤
̅ + 𝑦𝑧̅ + 𝑦𝑤
̅+𝑥

▪ 𝑔 = ∑ 𝑚(2,3,4,5,6,8,9) + ∑ 𝑑(10,11,12,13,14,15).
Too many minterms. We better optimize: 𝑔̅ = ∑ 𝑚(0,1,7) + ∑ 𝑑(10,11,12,13,14,15)

Number 4-literal 3-literal 2-literal 1-literal

of ones implicants implicants implicants implicants
0 m0 = 0000 ✓ m0,1 = 000-
1 m1 = 0001
m10,11 = 101- ✓ m10,14,11,15 = 1-1-
m10= 1010 ✓ m10,14 = 1-10 ✓ m10,11,14,15 = 1-1- ✓
2
m12= 1100 ✓ m12,13 = 110- ✓ m12,14,13,15 = 11--
m12,14 = 11-0 ✓ m12,13,14,15 = 11-- ✓
m7 = 0111 ✓ m7,15 = -111
m11= 1011 ✓ m11,15 = 1-11 ✓
3
m13= 1101 ✓ m13,15 = 11-1 ✓
m14= 1110 ✓ m14,15 = 111- ✓
4 m15= 1111 ✓

𝑔̅ = 𝑥̅ 𝑦̅𝑧̅𝑤 + 𝑥̅ 𝑦̅𝑧̅ + 𝑦𝑧𝑤 + 𝑥𝑧 + 𝑥𝑦

Minterms
Prime Implicants
0 1 7
m1 𝑥̅ 𝑦̅𝑧̅𝑤 X
m0,1 𝑥̅ 𝑦̅̅𝑧 X X
m7,15 𝑦𝑧𝑤 X
m10,14,11,15 𝑥𝑧
m12,14,13,15 𝑥𝑦

𝑔̅ = 𝑥̅ 𝑦̅𝑧̅ + 𝑦𝑧𝑤  𝑔 = (𝑥 + 𝑦 + 𝑧)(𝑦̅ + 𝑧̅ + 𝑤

̅)

7 Instructor: Daniel Llamocca