ELEN 665 (Edgar Sánchez-Sinencio)

A M S C

Analog and Mixed-Signal Center

Receiver Architectures:

Fundamentals and Properties

1
Analog and Mixed Signal Center- Texas A&M University (ESS)

How can we relax or solve this image rejection

problem ?

A possible solution is the use of more than one IF stage. This can
relax the specs of the filters and other building blocks. How many
IF stages are required ?
This depends on the design specs, a rule of thumb is to keep the ratio between
the operating frequency before and after a downcoversion should be lower than
10. Say for a signal at 900 MHz can be first downconverted to an IF of 250
MHz, then filter out unwanted signal and second downconverted to 50 MHz
and in a third downconversion the IF is 10 MHz.
2
How complex will be the filtering, power consumption and cost?
 Automatic Gain
LNA Control
X Y Z
BPF BPF BPF

Band Select Channel Channel

ωLO1 Select ωLO2 Select

X
ω0 ω

LO1
ωLO1 ω

Y
ω0- ωLO1 ω

LO2
ωLO2 ω

Z
ωo-ωLo1-ωLo2 ω
3
Double Superheterodyne Architecture
 Multi-Stage IF Receivers
• From stage to stage the desired signal is further and further
downconverted until the desired final IF is obtained.

• The ratio between the operating frequency before and after

downconversion is usually kept lower than 10, say 4. For instance
a 1800 MHz signal is first downconverted to a first IF of 450 MHz,
then consecutively to 90 MHz and finally to 18 MHz.
• Note that each downconvertion stage has the same mirror frequency
trouble than the single-stage IF receiver.
• Significant filtering between stages is required. This filtering is done
with off chip filters to further complicate the sensitivity to parasitic
components, also the power consumption will be high.
4
How are the ωLO and ωIF selected?
– Key consideration is the so-called image frequency.

– Ideally ωIF should be high enough such that ωIMA never falls in band.

– There are two possible choices for ωLO

ωLO = ωRF + ωIF High side injection

or
ωLO = ωRF − ωIF Not a good choice

• Regarding ωIF , one has to consider the VCO tuning range.

Assume the AM case {530 to 1,610} KHz = BW

BW
ω IF =
2
(1,610 − 530)
ω IF = KHz = 540 KHz ≠ 455 KHz
2
5
 Case 1. {75 to 1,155}KHz
75KHz = ( 530 - 455) KHz
1,155KHz = (1,610 - 455) KHz
ωLO frequency span 15.4

Case 2. {985 to 2,065) KHz High side injection

985KHz = 530KHz + 455 KHz
2,065KHz = (1,610 + 455) KHz

ωLO frequency span 2.01

For VCO tuning reason, Case 2 is more attractive.

-Explore the case of FM VCO range.

Aside, there is a trade-off in IF selection; low IF improves the selectivity due to a

Lower Q requirement of the SAW filter, while a high IF enhances the sensitivity due
to higher attenuation that can be offered by the image-rejection filter.
6
 IMAGE FREQUENCY PROBLEM

y(t)
LPF
x1(t)
x2(t)
ωLO x2(t)=cos ωLO t
ω
Desired ωLO ωIF
Spectrum
Image
x1(t) x2(t) x1(t)
ω
ωRF ωIM
ωIF ωIF
X X X

How to tackle this image frequency problem?

• Add a filter before and after

x1(t) IR y(t) Channel z(t)

Filter Select
Filter
IRF x2(t)
Channel
ω1
ω Select
ωIM
2ωIF ω 7
The conventional receiver (RX) Architectures are:

1. Superheterodyne

2. Image Reject RX: Hartley and Weaver

3. Zero-Intermediate Frequency (IF)

4. Low –Intermediate Frequency (IF)

These are the most used architectures in CMOS Receivers reported in the
literature. The selection of the architecture is partially dependent on the standards.
However some standard such as the GSM/DCS/PCS/EDGE have been designed
using options 1, 3 and 4. Others such as Bluetooth have been dominated by low-IF
Architecture. In other cases for multi-standards for instance the 802.11a/b/g the
Zero-IF has been the dominant architecture for their implementations.

Next we discuss these architectures and their pros and cons.

8
Super Heterodyne Receiver with Quadrature Down-conversion

PGA D/A
Image Channel 90o
Reject Selection
A
Filter Filter D
C D
LNA AGC 90 S
A P
D
Band C
Selection PGA
Filter PLL PLL 0o
D/A
• Good performance in terms of image and spurious suppression.
• A complex mixer is required.
• In the DSP a complex non-linear algorithm control the DC-level dynamically.
• Low integration due to the use of SAW filters.
• Limited multi-standard ability.

Due to the difficulty to design broadband I/Q phase shifters an alternative solution (Weaver)
solution is next discussed. 9
Analog and Mixed Signal Center, TAMU
 HARTLEY Image Rejection RX
I
AGC
IF
Sine
LNA
AGC +
Band
Selection
Q
Filter 900

Cosine

I Q
LO

• Ideally the image is rejected, in practice the static gain/phase

mismatches are 0.2 to 0.6 db/10 to 50, corresponding to an image
rejection of roughly 30 to 40dB.
10
 Image Rejection Mixer Analysis
I (t ) = cos(ω LO t ) ⋅ cos(ω RF t )
Image Reject Mixer
= 0.5{cos[(ω LO − ω RF t )] + cos[(ω LO + ω RF )t ]}
cos (ωRFt) Q(t) Adjacent
Channel
Q(t ) = sin(ω LO t ) ⋅ cos(ω RF t )
= 0.5{sin[(ω LO − ω RF )t ] + sin[(ω LO + ω RF )t ]}
LPF
Qlp(t) Filter

BPF LNA
I lp` (t ) = 0.5 cos[(ω LO − ω RF )t ] = 0.5 cos(ω IF t )
-90 + BPF
Ilp(t)

Qlp (t ) = 0.5 sin[(ω LO − ω RF )t ] = 0.5 sin(ω IF t )

I(t)
LPF -90
Ilp’(t)

cos (ωLOt) ~ (ωLO > ωRF)

( )
I lp (t ) = 0.5 cos ω IF − 90 o = 0.5 sin(ω IF t )

v o (t ) = I lp (t ) + Qlp (t ) = sin(ω IF t ).

The image input signal, for high-side injection of the LO, is vl,lm(t)=cos[(ωLO + ωIF)t].

I (t ) = cos[(ω LO + ω IF )t ] ⋅ cos(ω LO t ) = 0.5{cos(ω IF t ) + cos[(2ω LO + ω IF )t ]}

I lp` (t ) = 0.5 cos(ω IF t )
I lp (t ) = 0.5 sin(ω IF t )
Q(t ) = sin(ω LO t ) ⋅ cos[(ω LO + ω IF )t ] = 0.5 sin(− ω IF t ) + 0.5 sin[(2ω LO + ω IF )t ]
Qlp (t ) = − 0.5 sin(ω IF t )

vo ,Im (t ) = I lp (t ) + Qlp (t ) = 0 ; Image response can be completely suppressed.

11
The Barber-Weaver Receiver
RF 0 or Low
IF1
Mixers IF1 Filter
Mixers
AGC IF2 Filter
and ADC
sin ω1t sin ω2t
LNA
AGC +

• Double the silicon area

and power dissipation
cos ω1t cos ω2t
0 or Low
I Q IF1 Filter I Q
LO1 LO2
• Difficult Matching of I & Q Paths ; - No phase shifter (900) needed
• Operates with low IF1 and IF2 ; - overhead in area for LO2, mixers. 12
 +j +j

Signals in the Weaver +j/2

0 ω
Architecture 0
ω
ω2
-j -j −ω2
0

Desired
BPF I
Channel A C -j/2
Image

sinω1 t sinω2 t - VIF

cosω1 t cosω2 t +
-ω1 0 ω1 ω + 0 ω
B D +1/2 -1/2
BPF

Main drawback of this architecture is −ω2 ω2

0
incomplete image rejection due to phase
0 ω
and gain mismatch. Harmonics of the second
LO frequency may downconverted unfiltered
interferers from the first IF to the second. 0 ω
13
Analog and Mixed Signal Center, TAMU
Problem of Secondary Image
XD
XC
VIF=XD-XC 0 ω
0 ω

0 ω
0 ω

RF Input
ω
0 ω1 2ω2−ωin+2ω1 ωin

First IF

ω
0 2ω2−ωin+ω1 ω2 ωin-ω1

Second IF

ω
0 ωin-ω1-ω2
14
 What other receiver structures
alternatives can be considered
and with what properties ?

Can we make the IF very low, say to DC ?

How and at what price ?

15
Direct Conversion or Zero-IF front end Receiver
PGA

AGC ADC
ω0 ω I

Sine
LNA
0
PGA
Band
Selection
Filter ADC
Cosine Q

I Q
LO
Frequency Synthesizer

16
Direct Conversion or Zero-IF front end Receiver

• The LPF can be integrated. No image signal exists

• The RF spectrum is translated to the baseband in the first downconversion.
• The LO is equal to the input carrier frequency.
ω
• This architecture operates only with double-sideband AM signals because it
overlaps negative and positive parts of the input spectrum.
• For frequency and phase-modulated signals, the downconversion needs
quadrature outputs. Two sides of FSK (or QPSK) carry different information.

17
Direct Conversion Front End Receiver With Quadrature
Down-Conversion for FSK (digital) Demodulation
Phase Detector
Limiting and
Tone
I I Detector
LPF
LNA

sinω0 t D
BPF
cosω0 t
Ck
Q
LPF
Q
Zero IF

• No image rejection filter is needed.

• Offset voltages can degrade the S/N and

saturate the following stages. Isolation between ports is not ideal.
• I/Q mismatch degrades the downconversion constellation 18
Analog and Mixed Signal Center, TAMU
 FSK Direct Conversion Receiver.-
The frequency shift keyed signals appear with opposed relative
phase at the phase detector, giving a binary mark or space output
according to weather the input signal is lower or higher than the
local oscillator frequency. Let assume these inputs (mark and space)
signals are:
S M = cos( ω + ω D )t
S S = cos( ω − ω D )t
The quadrature oscillator signals to the mixers are:
LO I = cos ω t
LO Q = sin ω t
The mixer outputs when a mark is sent are:
I M = S M ⋅ LO I = cos( ω + ω D )t ⋅ cos ω t
I M = 0 .5[cos( ω + ω D ) + cos ω D t ] 19
 QM = S M ⋅ LOQ = cos(ω + ω D )t ⋅ sin ωt
QM = 0.5[sin(2ω + ω D )t − sin ω D t ]
Similarly when a space is sent:
I S = 0.5[cos ω D t + cos(2ω + ω D )t
QS = 0.5[sin(2ω − ω D )t + sin ω D t ]
The double frequency components of I and Q are removed in the LPF
of each channel, yielding:
I M = +0.5 cos ω D t
QM = −0.5 sin ω D t
I S = +0.5 cos ω D t
QS = +0.5 sin ω D t 20
Direct-Conversion Receiver (continues)
An alternative implementation

A
AGC D
C D
LNA 90 S
A P
D
AGC
C

9Allow for high level integration.

9 Low power consumption. PLL
9 Eliminate passive IF filters
9 Good for SSB digital modulation
9 Good Multi-standard ability.
¾ DC offset problem.
¾ Increased ADC dynamic range.
Because of limited filtering
¾ Need of a high-Q VCO. • Moves design efforts to baseband.
• Unprotected LO leakage into antenna.
• I/Q match required over high gain range
21
Analog and Mixed Signal Center, TAMU
 Low IF Receiver Architecture

• All advantages of direct conversion.

• More difficult image rejection.
• DC spur (offset) outside the signal bandwidth.
• Digital processing includes adjacent channel image rejection.
• All weakness of direct conversion without the DC offset problem.
• In Band image rejection.

22
0.35μm CMOS Bluetooth Low-IF Receiver IC:
An example of a Low-IF topology
2.4GHz 2MHz Demodulator

RF filter LNA Offset

Q Polyphase Cancellation
Filter /Decision
PLL

Developed in about 1 ½ years by:

Authors: Wenjun Sheng, Bo Xia, Ahmed Emira, Chunyu Xin, Ari Valero-Lopez, Sung Tae
Moon and Edgar Sanchez-Sinencio.

23
0.35μm CMOS Bluetooth Low-IF Receiver IC

• Publications:
– 2002 RFIC Conference, Best Student Paper Award (third place).
– Journal of Solid-State Circuits: January 2003 (Receiver) and
August 2003 (Demodulator).
– Transactions on Circuits and Systems – II: November 2003
(Complex Filter). 24
 TRANSCEIVER CELLULAR RADIO BLOCK DIAGRAM

Antenna Power
Amplifier
Data, Voice
A/D and D/A Frequency
Duplexer Transmitter Converters Interface

Digital Signal
Receiver Processor (DSP)

Reference Frequency
Oscillator Synthesizer μ Processor

25
 GSM RECEIVER SYSTEM REQUIREMENTS
Signal Level
(dBm)
0
Blocking
-23 dBm
Blocking
-43 dBm
-40

Wanted-120dBm
-80

-120 f
fo +1MHz +2MHz +3MHz

Gain of wanted signal > 100 dB

Noise Figure of LNA input less than 8 dB

26
 Subsampling Receiver
IF to Baseband
RF Stage
RF to IF Digital Mixer
RF=1846MHz I
Digital
LPF
Subsampling
AGC fs
o
RF LNA IMG IF BPF ADC 90
BPF REJ

246 MHz
Digital Q
RF LO LPF
1.6 GHz
LO
Example: 1.8 GHz GSM Specifications: IF carrier frequency = 246 MHz,
Channel BW = 200 KHz, Input Dynamic Range = 90 dB.
‰ 2 digital low frequency mixers, no noise and distortion.
‰ Easier I&Q matching.
‰ No DC offset and 1/f noise. Aliasing
‰ More digital means easier integration on a CMOS process.
‰ SNR degradation due to noise folding
‰ ADC & SH have to run at high clock to minimize noise
27
folding.
 Sub-sampling Receiver: Basic Idea
fs/4
fs/4
BW

fs 2fs 4fs f
IF=246MHz

Aliased signal IF Signal

to baseband

• The sampling rate, fs, can be much less than

the IF carrier.
• But, fs > 2×BW must be satisfied (to avoid
destructive aliasing). 28
Examples of Standards ( simplified versions)

802.11b (Wi- HomeRF

Bluetooth
Fi)
Data rate 1Mb/s 1-11Mb/s 1Mb/s, 5Mb/s

Power Lower Higher Variable

Modulation FH-GFSK DSSS-CCK FH-GFSK

Frequency 2.401 –
2.4 – 2.48GHz 2.401-2.480 GHz
Band 2.48GHz

29
 IEEE 802.15.4 (“Zigbee”)

Parameter North America North America Europe

Frequency 2402-2480 902-928 MHz 2412-2472

Range MHz MHZ
Channel 5 MHz 5 MHz 5 MHz
spacing

Multiple access CSMA/CA CSMA/CS TDMA

method
Duplex method FDD FDD FDD

Users per 255 255 255

channel
Modulation OPQSK, OPQSK, GFSK,BT=0.5
BT=0.5 BT=0.5
Peak bit rate 250 kHz 40 kHz 250 KHz
30
Parameter 800 MHz 1900 MHz Asia

Summary of IS-95 CDMA

Mobile-to-base 824-849 MHz 1850-1910 1920-1980
frequency MHz MHz
Base-to-mobile 869-894 MHz 1930-1990 2110-2170
frequency MHz MHz
Channel 1250 kHz 1250 kHz 1250 kHz
spacing
Number of 20 48 48
channels
Multiple access CDMA/FDM CDMA/FDM CDMA/FDM
method
Duplex method FDD FDD FDD

Users per More than 15 More than 15 More than 15

channel
Modulation QPKK/OQPSK QPKK/OQPSK QPKK/OQPSK

Channel bit 1.2288 Mb/s 1.2288 Mb/s 1.2288 Mb/s

31
rate (chip rate)
 UMTS/DCS1800 Specifications

DCS1800 UMTS
Frequency Band 1805 - 1880 MHz 2110 - 2170 MHz
Channel BW 200 kHz 5 MHz
System Sensitivity -102 dBm -117 dBm(@32ksps)
BER 1e-3 1e-3
600 - 800 kHz: -43 dBm 10 - 15 MHz: -56 dBm
Blocking 800 - 1600 kHz: -43 dBm 15 - 60 MHz: -44 dBm
Characteristics 1600 - 3000 kHz: -33 dBm 60 - 85 MHz: -30 dBm
> 3000 kHz: -26 dBm > 85 MHz: -15 dBm
Cochannel: -9 dBc
Adjacent Channel 200 kHz: 9 dBc 5 MHz: -52 dBm
Interference 400 kHz: 41 dBc
600 kHz: 49 dBc
32
 Multi-Channel, Multi-Mode Dynamic
Range (1) DCS1800

-15 dBm BW=2170-1805 BW=max(band)

=365 MHz =75 MHz
-99 dBm -114 dBm
LNA Amp ADC
0 dBm -4 dBm 13 dBm

-84 dBm -60 dBm

-99 dBm -77 dBm

Gain: 15 dB Gain: 10 dB Gain: 17 dB Fullscale Voltage:

Input 1dB Input 1dB Input 1dB 2 Vpp
compression: -13 dBm compression: 2 dBm compression: 0 dBm

33
 Multi-Channel, Multi-Mode Dynamic
Range (2) DCS1800
Blocker PB = 13 dBm
PB CW carrier

Wanted Signal
Px = -60 dBm
Px
Noise PSD To ensure that the quantization noise
power is negligible compared to that of
In channel interferers and other sources of thermal
quantization noise BW=200 kHz and device noise, choose
SNRQF = 20 dB
With Fs = 150 MHz, calculated resolution of ADC is 11 bits.
The SFDR (for single blocker) can be calculated by:
SFDR = PB - Px + SNRQF = 93 dB
Required ADC Spec.: FS >= 150 MHz, b = 11, SFDR = 93 dB
Current State of the art ADC:
Fs = 80 MHz, b = 14, SFDR = 100 dB(AD6644)
34
 Receiver Technology Trends

Traditional Superheterodyne Increasing Integration

Borrows from handset chip integration,
or new architecture like direct-conversion.

IF-Sampling/Digital I&Q
Reduces receiver size by eliminating IF stages
New architectures using more digital processing

Multi-mode, Wideband
Large reduction in receiver size
Major architectures shift to DSP-intensive radio, highly programmable
35
 Software Receiver

LNA ADC DDC DSP

Band Select High Intercept High Intercept Wide Dynamic Fixed Function Fast DSP
Filter Point Amplifiers Point Mixers Range ADC DSP digitally with on-chip
Remove Amplify signals translate digitize entire selects and Memory
unwanted without the input spectrum spectrum for filters the demodulates
spectrum introduction of to ADC signal digital channel channel of signal
significant bandwidths selection interest
intermodulation
products

36
Analog and Mixed Signal Center, TAMU
TRADITIONAL RADIO[3]

RF Modulation Coding Framing Processing

Hardware Software

SOFTWARE RADIO

RF Modulation Coding Framing Processing

Hardware Software

COGNITIVE RADIO

RF Modulation Coding Framing Processing

Hardware
Intelligence( Sense, Learn, Optimize) Software
37
 SOFTWARE RADIO

Antenna Digital
RF bitstream
(1-2 GHz) LNA+
BPF VGA ADC DSP

¾ Idea introduced in 1991 by Joe Mitola

¾ Direct RF digitization
¾ Single / multiple channels sets ADC BW
¾ Reconfiguration by DSP software programs 38
 SOFTWARE DEFINED RADIO

Antenna IF
RF
(1-2 GHz) (100-200 MHz)
Digital
IF bit stream
BPF LNA VGA
ADC

LO1

¾ IF digitization
¾ No specific standard for IF location
¾ Reduced DC offset, flicker noise problems 39
 Literature survey
Ref Type Fo Fs SNR Power Tech
GHz GHz 1 MHz BW (mW)
Vessal (JSSC 04) Nyquist (FI) 0 - 0.7 2 48 dB 83500 SiGe
HBT
Kaplan (CICC 03) CT BP ΣΔ 1.3 4.3 962 dB 86200 InP HBT

Chandrasekaran SC LP ΣΔ 0.9 0.1 25 dB 30 0.25µm

(CICC 02) with mixer (bad SNDR) CMOS

Cherry (TCAS 2000) CT BP ΣΔ 1 4 51 dB 450 0.5µm

SiGe
Gao (VLSI 98) CT BP ΣΔ 1 4 48 dB 350 0.5µm
SiGe
Jayaraman (GaAs 97) CT BP ΣΔ 0.8 3.2 55 dB 1800 GaAs

40
 REFERENCES
[1] P-I. Mak, S-P U, and R.P Martins,” Transceiver Architecture Selection: Review, State-of-the-Art Survey
and Case Study”, IEEE Circuits and Systems Magazine, vol. 7, No. 2,pp. 6-25 Second Quarter 2007

[2] T. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University
Press, 1998.

[3] A. Baker, S. Ghosh, , A. Kumar, and M. Bayoumi, “ LDPC Decoder: A Cognitive Radio Perspective for
neXt Generation (XG) Communication,”, IEEE Circuits and Systems Magazine, vol. 7, No. 3,pp. 24-37,
Third Quarter 2007

[4] B. Razavi, RF Microelectronics, Prentice Hall, Upple Saddle River,NJ 1998

[5] A. Bensky, “ Short-range Wireless Communication: Fundamentals of RF System Design and

Application”, 2nd Edition, Amsterdam, -Newnes-Elsevier 2004

[6] W. Sheng, Bo Xia, A.E., Emira, C. Xin, A.Y Valero-Lopez,., Sung Tae Moon, E. Sanchez-Sinencio, "A
3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC", IEEE Journal of Solid-State Circuits , Volume: 38 Issue:
1 , Jan 2003, Page(s): 30 -42

[7] A. Emira, A. Valdes-Garcia, B. Xia, A. N. Mohieldin, A. Y. Valero-Lopez, S. T. Moon, C, Xin, and E.

Sanchez-Sinencio.; "A Dual Mode 802.11b/Bluetooth Receiver in 0.25um BiCMOS", IEEE International
Solid-State Circuits conference, pp. 153-154 San Francisco, February , 2004.

Analog and Mixed Signal Center- Texas A&M University (ESS) 41