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FORMATION AND ANALYSIS OF SWITCHED-
CAPACITOR CONVERTER SYSTEMS WITH
MODULAR CIRCUIT CONFIGURATION
FONG YAT CHI
PhD
The Hong Kong Polytechnic University
2019
The Hong Kong Polytechnic University
Department of Electrical Engineering
Formation and Analysis of Switched-Capacitor Converter

Systems with Modular Circuit Configuration
FONG Yat Chi
A thesis submitted in partial fulfilment of the requirements for

the degree of Doctor of Philosophy
August, 2018
Abstract
Abstract
Switched-capacitor (SC) converter has been reported for fully integrated design
because only capacitor is used for energy storage. Recently, the SC concept has been
extended to medium power processing. A novel power conversion technique based on
the SC technology is investigated in this thesis matching the demand of the revolution
in smart mobility and renewable energy (RE). The merits and shortcomings of SC
power conversion are identified by an overall review of previous development of the
SC technology and the features of existing SC converters. Control techniques and
circuit configurations are developed to address the limitations and weaknesses of
traditional SC converters. The associated analysis and design of power converters
based on systems of SC units for DC-DC and DC-AC applications are discussed.
The development of SC converter systems can be divided into two sections. The
former part of this thesis focuses on the design of DC-DC power conversion systems
based on zero-current switching (ZCS) SC units; the latter part explores the design of
step-up DC-AC multilevel inverters (MLIs) based on the series-parallel SC technique.
The principle of ZCS SC DC-DC converter is reviewed; the analysis is extended to
the parallel-mode operation with a varying number of active SC converter units. Based
on the system modeling, a series of centralized control techniques is developed.
Featuring inherent voltage conversion ratio and voltage droop characteristic by the SC
topology, these centralized control methods are robust and easy to be implemented.
Besides, a family of balancing systems for energy storage system (ESS) based on the
multi-port SC conversion system is presented. On top of the well-known
auto-balancing feature offered by the SC technology, feasibility of improving the
I
Abstract
balancing speed by an alternative ZCS SC structure with the presence of supervisory
control from a centralized management system is examined. The design and analysis
of the single-input multi-output and multi-input single-output, as well as, the
corresponding mutations of string-to-cells, cells-to-string and cells-to-cells
configurations are developed.
Investigation on the topics of SC DC-DC converters provides the theoretic
foundation and working principle of SC based power processing. Attractive features
of the modular SC approach motivates the development of MLIs based on the SC
building blocks. A hybrid SCMLI topology offering a high number of output levels
based on the ideas of series-parallel SC unit and bidirectional switched MLI is
developed. Compared to independent DC sources, series-connected sources have
higher availability, especially for the applications which ESS is partaking. In addition,
the cell balancing issue with the hybrid SCMLI is tackled by combining the switched-
ladder structure with an SC unit. Furthermore, the weaknesses of common SCMLIs
such as the requirement of high voltage unfolding H-bridge is mitigated by proposing
a series of modular SCMLI topologies based on the two-phase, cascaded bipolar
series-parallel as well as the cross-switched structures. The charge-up power loss is
alleviated by the soft-charging technique with a resonant inductor. This thesis aims at
exploration and provision of the SC based power processing solutions for the
applications in mobility as well as small scale power distribution systems integrated
with RE and ESS through the idea of modular circuit configuration.
II
List of Publications
Journal Papers
1. Y.C. Fong, K.W.E. Cheng, Y. Ye and Y.C. Chan, "Centralized Regulation

Scheme for a Parallel-Mode Switched-Capacitor Converter System With Simple
Unit Commitment," IEEE Transactions on Industrial Electronics, vol. 64, no. 8,
pp. 6149-6158, Aug. 2017.
2. Y.C. Fong, K.W.E. Cheng, S.R. Raman and X. Wang, "Multi-port Zero-Current
Switching Switched-Capacitor Converters for Battery Management
Applications," Energies, vol. 11(8), 1934, Jul. 2018.
Conference Papers
1. Y.C. Fong and K.W.E. Cheng, "An adaptive modulation scheme for fundamental
frequency switched multilevel inverter with unbalanced and varying voltage
sources," 2015 6th International Conference on Power Electronics Systems and
Applications (PESA), Hong Kong, 2015.
2. Y.C. Fong and K.W.E. Cheng, "An ESS charge balancing method based on
current allocation with multi-source power converters for electric microcars,"
2015 6th International Conference on Power Electronics Systems and
Applications (PESA), Hong Kong, 2015.
3. Y.C. Fong, Y. Ye, S.R. Raman and K.W.E. Cheng, "A hybrid multilevel inverter
employing series-parallel switched-capacitor unit," 2017 IEEE Applied Power
Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2565-2570.
4. Y.C. Fong and K.W.E. Cheng, "A switched-capacitor step-up inverter for
bidirectional wireless charging applications in electric microcar," 2017 7th
International Conference on Power Electronics Systems and Applications - Smart
Mobility, Power Transfer & Security (PESA), Hong Kong, 2017.
5. Y.C. Fong, S.R. Raman, M.M. Chen and K.W.E. Cheng, "A novel switched-
capacitor multilevel inverter offering modularity in design," 2018 IEEE Applied
Power Electronics Conference and Exposition (APEC), San Antonio, TX, 2018,
pp. 1635-1640.
6. Y.C. Fong, K.W.E. Cheng, S.R. Raman and J. Hu, "A Single Source Cascaded
Multilevel Inverter Based on Switched-capacitor with Series and Parallel
Connectivity", 2018 IEEE Energy Conversion Congress and Exposition (ECCE),
Portland, OR, United States. (Accepted)
III
Under Review/Preparation
1. Generalized Topology of a Hybrid Switched-capacitor Multilevel Inverter for

High-Frequency AC Power Distribution
2. A Current Allocation Based Charge Balancing Technique for a Single Phase
Multilevel Inverter with Series Voltage Source String
3. A Soft-Charging Step-Up Switched-Capacitor Multilevel Inverter with Reduced
Ripple Loss for High-frequency AC Applications
IV
Acknowledgements
Acknowledgements
First of all, I would like to express my sincere gratitude to my supervisor, Professor
Ka Wai Eric Cheng, for his continuous guidance, support and encouragement
throughout the course of my study. His academic guidance is very useful and
beneficial. His suggestions are always inspiring thinking and problem solving in
innovative ways.
Secondly, I would like to thank the members in the Power Electronics Research
Center of the Hong Kong Polytechnic University for all their helps and technical
supports. They are Mr. K.Y. Tse, Mr. Jones Chan, Dr. Xiangdang Xue, Dr. James Ho,
Dr. Cuidong Xu, Mr. Daohong Wang, Mr. Raghu Raman, Ms Xiaolin Wang, Mr.
Moonson Chen and Mr. Jie Mei.
Also, I gratefully thank to the Research Office of the University and the General
Office of the Department for their professional service and support during the entire
period of my research study.
Special thanks go to the alumni and former colleagues in the research center:
Dr. Yuanmao Ye and Dr. Jiongkang Lin, for their generosity in sharing their valuable
research experience and ideas; Mr. Y.C. Chan, for his assistance with great efforts.
Last but not least, I would like to deeply thank my family and friends for their
immeasurable supports.
V
Table of Contents
Table of Contents
Chapter 1 Introduction ......................................................................................... 1

1.1. Basic Features and Principle of SC Converters ............................................ 2
1.2. SC DC-DC Converters .................................................................................. 3
1.2.1. ZCS Technique for SC DC-DC Conversion ........................................... 5
1.2.2. Voltage Equalizer Based on the SC Technology .................................... 6
1.3. SC DC-AC Converters .................................................................................. 8
1.4. Modular Design of Electric Power Conversion System ............................. 10
1.5. Thesis Objectives ........................................................................................ 12
1.6. Thesis Outline ............................................................................................. 12
Chapter 2 Centralized Regulation Control for Parallel Mode SC DC-DC
Converter ................................................................................................................ 16
2.1. Review on the Parallel-Mode SC Technology for DC-DC Conversion
Applications ................................................................................................... 17
2.2. Analysis of ZCS SC DC-DC Converter ...................................................... 18
2.3. Centralized Regulation Control by Varying the Number of Active Units
......................................................................................................................... 22
2.3.1. Discrete Unit Control with Current Feedback ...................................... 22
2.3.2. Discrete Unit with Hysteresis Voltage Control .................................... 24
2.3.3. Hybrid Unit Control Using PD-PWM .................................................. 26
2.4. Simulation and Experimental Verification .................................................. 31
2.4.1. Simulation Results ................................................................................ 32
2.4.2. Prototype of the Parallel SC converter System ..................................... 37
2.4.3. Results of the Unit Control Schemes .................................................... 39
2.5. Summary ..................................................................................................... 47
Chapter 3 Development of Multi-port SC Converters for Energy Storage
Equalization Applications ..................................................................................... 48
3.1. Background of Power Electronics for Energy Storage Management and SC
Equalization Technology ............................................................................... 49
3.2. Overview of the SIMO and MISO SC Converters ..................................... 52
VI
Table of Contents
3.3. SC Modeling and Analysis ......................................................................... 53

3.4. Circuit Alteration with Non-Isolated DC-DC Converter ............................ 58
3.5. Simulation Study on the Multi-port SC Converters ................................... 60
3.6. Experimental Verification .......................................................................... 69
3.7. Summary ..................................................................................................... 74
Chapter 4 Hybrid SC MLI Employing Series-connected Sources .................. 76
4.1. Review on the Traditional MLI and SCMLI Topologies ........................... 77
4.2. Working Principle of the Hybrid SC MLI Topology ................................. 79
4.2.1. Topology Description ........................................................................... 79
4.2.2. Symmetric (Equal Voltage) Series-parallel SC Configuration ............ 82
4.2.3. Asymmetric (Unequal Voltage) Series-parallel SC Configuration ...... 82
4.2.4. Modulation Technique for the Staircase Output Voltage ..................... 83
4.2.5. Reduction on Active Components for High Power Factor Applications
............................................................................................................... 88
4.3. Capacitor Voltage Ripples & Loss Analysis .............................................. 89
4.3.1. Voltage Ripples of the SC Cells .......................................................... 90
4.3.2. Power Loss Analysis ............................................................................ 92
4.4. Simulation and Experimental Verification ................................................. 98
4.5. Summary ................................................................................................... 110
Chapter 5 Cell Voltage Balancing with Conventional and SC MLIs ........... 113
5.1. Review on the MLI Cell Balancing Methods ........................................... 114
5.2. MLI Topologies Employing Series Voltage Sources ............................... 115
5.3. Current Allocation and Analysis of Series Sources Based MLIs under
Staircase Modulation ................................................................................... 120
5.3.1. Current Allocation in Diode-clamped Inverter or Switch-ladder Inverter
............................................................................................................. 121
5.3.2. Current Allocation in the Altered Hybrid SCMLI ............................. 124
5.3.3. Ripple Analysis and Capacitor Sizing ................................................ 127
5.4. Simulation and Experimental Verifications .............................................. 129
5.5. Summary ................................................................................................... 141
VII
Table of Contents
Chapter 6 Development of SC MLIs Offering Modularity in Design ........... 143

6.1. Configuration of Typical SC MLIs ........................................................... 144
6.2. Elimination of the High Voltage H-bridge ............................................... 146
6.2.1. Two-phase Structure ........................................................................... 146
6.2.2. Cascaded Structure with Bipolar Series-parallel Conversion ............. 150
6.2.3. Cross-switched Structure .................................................................... 153
6.3. Comparative Study .................................................................................... 156
6.4. Simulation Study and Experimental Results ............................................. 159
6.5. Summary ................................................................................................... 172
Chapter 7 Design of a Soft-Charging SC MLI with Reduced Ripple Power
Loss ........................................................................................................................ 174
7.1. Background of Developing Soft-Charging Technique for SCMLI .......... 175
7.2. Circuit Description and Operating Principles ........................................... 177
7.3. Voltage Ripples and Analysis ................................................................... 179
7.3.1. Voltage Ripples of the Capacitors under Staircase Modulation ......... 180
7.3.2. Soft-Charging Analysis ...................................................................... 181
7.4. Design Consideration ................................................................................ 186
7.4.1. Selection of Resonant Inductance ....................................................... 186
7.4.2. Power Supplies for Floating Gates ..................................................... 188
7.5. Simulation Study ....................................................................................... 189
7.6. Experimental Verification ......................................................................... 194
7.7. Summary ................................................................................................... 198
Chapter 8 Conclusion ........................................................................................ 199
8.1. Contributions of the Thesis ....................................................................... 199
8.2. Recommendations for Future Work .......................................................... 203
References ............................................................................................................. 205
VIII
List of Figures
List of Figures
Fig. 1.1. A basic SC DC-DC converter

Fig. 1.2. The SC DC-DC converters for different voltage conversion ratios
Fig. 1.3. Typical voltage and current waveforms of the switched-capacitor in a
unity-mode SC converter
Fig. 1.4. SC balancing topologies and the corresponding equivalent circuit
models
Fig. 1.5. Operation of a series-parallel SC cell
Fig. 1.6. A typical MLI based on the series-parallel SC technique
Fig. 1.7. Outline of the topics included in this thesis
Fig. 2.1. A ZCS double-mode switched-capacitor converter
Fig. 2.2. Equivalent circuit during the charging and discharging cycles of an SC
converter
Fig. 2.3. Functional block diagram of discrete unit control with current
feedback (DUCC)
Fig. 2.4. Functional block diagram of discrete unit control with hysteresis
voltage-band (DUCV)
Fig. 2.5. Hysteresis triggering of the number of active SC converter units in
DUCV
Fig. 2.6. Implementation of the Level-shifted pulse-dropping PWM (PD-
PWM) signal
Fig. 2.7. Functional block diagram of hybrid unit control (HUC)
Fig. 2.8. Equivalent circuit of the SC converter system regulated by the hybrid
unit control
Fig. 2.9. Schematic of the setup for the parallel-mode SC converter
Fig. 2.10. A load current ramp starts from 0.9 A to a peak value of 10.9 A
Fig. 2.11. The simulation results
Fig. 2.12. The output voltage and unit current ripples of HUC at light load
Fig. 2.13. Simulated voltage droop characteristic and current allocation
Fig. 2.14. Open-loop response of the simulated SC converter system under HUC
IX
List of Figures
Fig. 2.15. Experimental setup of the parallel double-mode SC converter system

Fig. 2.16. Output response of the SC converter system with all units enabled
Fig. 2.17. Output response of the SC converter system with DUCC
Fig. 2.18. Output response of the SC converter system with DUCV
Fig. 2.19. Output response of the SC converter system with HUC
Fig. 2.20. Output characteristic of the SC converter system with different
centralized regulation schemes
Fig. 2.21. Measured efficiency of the SC converter system prototype
Fig. 3.1. Generalized topology of the multi-port SC converter
Fig. 3.2. Behavioral model of the SC converter
Fig. 3.3. Equivalent circuits of the charging/discharging paths of the switched-
capacitor
Fig. 3.4. Circuit alteration of the multi-port SC converters
Fig. 3.5. Efficiency of the SC converter model at different current and voltage
Fig. 3.6. Schematic of the setup for the multi-port SC balancing circuit
Fig. 3.7. EDLC cell voltage, charged by the open-loop SIMO SC converter with
a 3.4 V voltage source
Fig. 3.8. Zoomed waveforms of the switched-capacitor voltage and current at
about t=0.5s
Fig. 3.9. EDLC cell voltage, charged by the closed-loop SIMO SC converter
Fig. 3.10. EDLC cell voltage, charged by the CC-CV charger with the string-to-
cell balancer altered from the SIMO SC converter
Fig. 3.11. Tapped inductor version for the buck-boost stage to achieve higher
voltage conversion ratio
Fig. 3.12. EDLC cell voltage, charged by the CC-CV charger with the altered
multi-port SC converters
Fig. 3.13. Major components in the experiment setup
Fig. 3.14. Measured EDLC cell voltage, charged by the SIMO SC converter
Fig. 3.15. Measured voltage and current waveforms of the switch-capacitor and
the gate-source voltage of T0
Fig. 3.16. Voltage and current waveform of the power inductor, Lb
X
List of Figures
Fig. 3.17. Measured EDLC cell voltage, charged by the CC-CV charger with the
string-to-cells balancer prototype
Fig. 4.1. General structure of the proposed hybrid SCMLI topology
Fig. 4.2. Series-parallel conversion
Fig. 4.3. Enable asymmetric SC voltage by inserting diodes between SC units
Fig. 4.4. Staircase voltage waveform; and the expressions of firing angles θcj,
for jth capacitor and the corresponding output voltage levels, Vbj; and
peak output voltage, Vp, for symmetric and asymmetric configurations
Fig. 4.5. Synthesis of staircase output voltage waveform from voltage
components Vs and Vsc
Fig. 4.6. Substituting active switches with diodes for high power factor loads
Fig. 4.7. Equivalent circuits of the SCMLI
Fig. 4.8. Circuit configuration of the SCMLI prototype and simulation model
Fig. 4.9. Experimental setup
Fig. 4.10. Simulated voltage and current waveforms of the SCMLI
Fig. 4.11. Effect of the fundamental output frequency on the energy efficiency
of the SCMLI with different RC parameters
Fig. 4.12. Simulated and theoretical efficiencies of the SCMLI at different
operating conditions
Fig. 4.13. Measured voltage and current waveforms of the SCMLI prototype
Fig. 4.14. Measured waveforms of the 19-level SCMLI driving 110Ω-1mH load
at 400 Hz
at 400 Hz
Fig. 4.16. Measured efficiency of the SCMLI
Fig. 5.1. Multilevel inverter topologies cooperating with series string of voltage
sources
Fig. 5.2. The modified hybrid SC DC-AC inverter
Fig. 5.3. The stepped output voltage waveform produced by an MLI with
staircase modulation
XI
List of Figures
Fig. 5.4. The flowchart of the current allocation strategy for charge balancing
with single-phase switch-ladder inverter
with the proposed hybrid MLI
Fig. 5.6. Configuration of the simulation model
Fig. 5.7. The OCV-SOC curve of the Li-ion battery model
Fig. 5.8. Simulated output voltage and current waveforms of the switch-ladder
inverter
Fig. 5.9. The battery SOC and voltages throughout the discharge process
Fig. 5.10. Simulated output voltage, current and switched-capacitor voltage
waveforms of the modified hybrid MLI
Fig. 5.11. The cell SOC and voltages throughout the discharge process
Fig. 5.12. Major components of the experimental set-up
Fig. 5.13. Output voltage, current and capacitor voltage waveforms of the MLI
prototype at 400 Hz operation
Fig. 5.14. Measured voltages of the EDLC cells throughout the discharge
process with current allocation control
Fig. 6.1. A series-parallel SC cell
Fig. 6.2. A typical SCMLI employing an SC multilevel converter and an H-
bridge inverter
Fig. 6.3. The SCMLIs with hybrid configurations
Fig. 6.4. A generalized SCMLI with a two-phase configuration
Fig. 6.5. Working principle of the SCMLI with a two-phase structure
Fig. 6.6. Varieties of a series-parallel SC cell
Fig. 6.7. A bipolar series-parallel SC cell combing positive and negative stack
operations
Fig. 6.8. Working principle of the bipolar series-parallel SC cell
Fig. 6.9. A cascaded SCMLI topology constituted of bipolar SC cells and half-
bridges
Fig. 6.10. Generalized topology of the cross-switched SCMLI
Fig. 6.11. Working principle of the cross-switched SCMLI
XII
List of Figures
Fig. 6.12. Simulated output voltage, output current and switched-capacitor

voltage waveforms with different topologies and operating
frequencies
Fig. 6.13. Simulated total capacitor power loss for the three SCMLI variants at
different loading conditions
Fig. 6.14. Simulated energy efficiency for the three SCMLI variants at different
loading conditions
Fig. 6.15. Prototype of the 9-level SCMLI
Fig. 6.16. Measured waveforms of the 9-level two-phase SCMLI prototype
Fig. 6.17. Measured waveforms of the 9-level cascaded SCMLI prototype
Fig. 6.18. Measured waveforms of the 9-level cross-switched SCMLI prototype
Fig. 6.19. Measured efficiency of the SCMLI prototypes
Fig. 7.1. A basic series-parallel SC unit
Fig. 7.2. Generalized topology of the proposed SCMLI with a two-phase
structure
Fig. 7.3. Equivalent circuit of the SC charging path
Fig. 7.4. Simplification of the RC network in the SC charging path
Fig. 7.5. Simplified RLC charging path of the SC units
Fig. 7.6. Relationship between the soft-charging factor and the damping factor
of the proposed soft-charging SCMLI
Fig. 7.7. Bootstrap design for the floating gate drivers in the two-phase SCMLI
Fig. 7.8. Simulated waveforms of the 9-level SCMLI at 1 kVA load with
lagging power factor of 0.7
Fig. 7.9. Simulated performance of the 9-level SCMLI with different resonant
inductance value and loading conditions
Fig. 7.10. Experimental setup for the 9-level SCMLI prototype with two-phase
structure
Fig. 7.11. Output voltage, output current and the capacitor voltage waveforms of
the 9-level SCMLI prototype at 1 kVA load with lagging power factor
of about 0.7
Fig. 7.12. Measured efficiency of the 9-level SCMLI prototype at different
resonant and load settings
XIII
List of Tables
List of Tables
Table 2.1. Parameters of the simulated SC converter System
Table 2.2. Specification of the SC converter system prototype
Table 3.1. Key parameters of the simulation model
Table 3.2. Key parameters of the experimental setup
Table 4.1. Switching states of the symmetric SC voltage based inverter at

different output voltage levels
Table 4.2. Switching states of the asymmetric SC voltage based inverter
Table 4.3. Summary of the proposed SCMLI operation for staircase voltage
output
Table 4.4. Specification and components of the SCMLI prototype
Table 5.1. Properties of different MLI topologies with n series-connected voltage

sources
Table 5.2. Parameters of different simulation settings
Table 5.3. Parameters of the experimental MLI prototype
Table 6.1. Working states of a (2n+3)-level SCMLI with a two-phase structure
Table 6.2. Working states of the cascaded SCMLI
Table 6.3. Working states of the cross-switched SCMLI
Table 6.4. Key parameters of different SCMLI topologies
Table 6.5. Parameters of the 9-level SCMLI simulation models
Table 6.6. Parameters of the 9-level SCMLI prototype
Table 7.1. Working States of the (2n+3)-level SCMLI with the two-phase
structure
Table 7.2. Parameters of the 9-level SCMLI simulation model with the two-phase
structure
Table 7.3. Parameters of the 9-level SCMLI prototype
XIV
List of Acronyms
List of Acronyms
AC alternating current
BSC bidirectional switched converter
BMS battery management system
CC constant current
CCR current conversion ratio
CCU central control unit
CHBI cascaded H-bridge inverter
CLK clock
CV constant voltage
DC direct current
DUCC current-based discrete unit control
DUCV voltage-based discrete unit control
EDLC electric double-layer capacitor
EMI electromagnetic interference
ESR equivalent series resistance
ESS energy storage system
EV electric vehicle
FFT fast Fourier transform
HBI H-bridge inverter
HFAC high-frequency alternating current
HUC hybrid unit control
MAX maximum
MIN minimum
MISO multi-input single-output
MLI multilevel inverter
MMC modular multilevel converter
MOSFET metal-oxide-semiconductor field-effect transistor
OCV open-circuit voltage
OSC oscillation, oscillating
PD-PWM pulse-dropping pulse-width modulation
PFM pulse-frequency modulation
PI proportional-integral
XV
List of Acronyms
PWM pulse-width modulation

RE renewable energy
RLC resistor-inductor-capacitor
SC switched-capacitor
SHE selective harmonic elimination
SMD surface-mounted device
SMPC switched-mode power converter
SOC state of charge
SOH state of health
SIMO single-input multi-output
SPDT single-pole double throw
THD total harmonic distortion
UPS uninterruptable power supply
ZCS zero-current switching
XVI
List of Symbols
List of Symbols
Bi battery (i=1, 2,…,n)

C, C capacitor, capacitance
Di diodes (i=1, 2,…,n)
D, d duty cycle
E energy
e error
f frequency
fs switching frequency
fr resonant frequency
I, i current
Ich charging current
Idch discharging current
Io output current
L, L inductor, inductance
Lr, Lr resonant inductor, resonant inductance
M modulation index
P power
Po output power
PL power loss
Q electric charge
R, r resistance
RC, rc ESR of capacitor
Rch resistance of SC charging path
Rdch resistance of SC discharging path
RD, rd diode resistance
RL ESR of inductor
Ro, Ro loading resistor, loading resistance
RSC equivalent resistance of SC circuit
XVII
List of Symbols
R’SC average SC equivalent resistance

RT on-state resistance of transistor
Si, Ti, Qi active switches (i=1, 2,…,n)
T, t period, time
V voltage
VB battery voltage
VC capacitor voltage
VD diode voltage
VG gating voltage
Vh voltage hysteresis width
Vm, VM modulation voltage
Vi input voltage
VS source voltage
∆V voltage ripple
𝛼 neper frequency
ems mean-square error
η efficiency
θ angle
φ phase angle
ρ charging duration factor (Chapter 4)
modulation index correction factor (Chapter 5 and 7)
ζ damping factor
ξ soft-charging factor
ω angular frequency
ωr resonant angular frequency
i, j, k, n, m integers
XVIII
Chapter 1 Introduction
Chapter 1
Introduction
The switched-capacitor (SC) converter is a subset of switched-mode power converters
(SMPCs) featuring compact design. By eliminating the need of bulky magnetic
components, the SC converter shows high potential in applications demanding small
footprint and fully integrated design. Besides, as a result of relying on capacitors as
the main energy storage element, simple circuit design and control is one of the key
advantages offered by the SC based power converters. By arranging the SC circuits
in different ways, the SC converters can be diversified into various applications of
voltage conversion and transformation between AC and DC.
This thesis explores the design of power converter systems formed by a cluster
of SC circuits. For the DC-DC voltage conversion, higher current output capability
and voltage regulation are achieved by the parallel-mode operation of zero-current
switching (ZCS) SC resonant converters with simple centralized controls. Multi-port
converters can be formed with a cluster of series-parallel SC units for energy storage
management applications. Besides, the cascaded series-parallel SC circuits offer an
alternative of constructing multilevel inverters featuring voltage step-up and self-
voltage-balance. In this chapter, an overview of the SC power conversion techniques,
1
including the features and fundamental principle is recited by reviewing the traditional
SC converters and the recent development on the SC technology.
1.1. Basic Features and Principle of SC Converters
Switched-mode power converters (SMPCs) enable efficient and flexible electric
power conversion by cooperating switching devices like diodes and transistors with
energy storage devices such as capacitors and inductors. Switched-capacitor (SC)
converters employ capacitors as the primary energy storage devices for power
processing. Unlike the other conventional SMPCs, the SC converters realize different
voltage conversion ratios by the ways of connecting the capacitors as defined by the
topologies and controlling the amount of charges transferred through the capacitors.
By eliminating the bulky inductor, the SC based converters can achieve small
footprint with high power density easily [1-3]. Furthermore, fully integrated SC
converters have been adopted in industry and commercial products [4-9].
S1 S2
Vo
VS CS CL Io
Fig. 1.1. A basic SC DC-DC converter.
A basic SC converter [7, 10] is illustrated in Fig. 1.1, CS and CL represent the
switched-capacitor and the loading capacitor, respectively. The charges are
transported from the voltage source, VS, to CL through CS and the two switches, S1
and S2, which are triggered by complementary pulse signals. At equilibrium, the
2
current transferred from CS to CL equals to the load current, Io. The steady-state output
voltage, Vo, across CL is determined by the switching frequency and duty cycles of the
complementary pulse signals, the parasitic resistances and inductances, as well as the
magnitude of the load current. For the topology shown in Fig. 1.1, the ideal voltage
conversion ratio at no-load condition is 1.
1.2. SC DC-DC Converters
CS CS1 CS3
VS CL Io VS CL Io
CS2
(a) (b)
CS CS
VS CL Io VS CL Io
(c) (d)
Fig. 1.2. The SC DC-DC converters for different voltage conversion ratios;
(a) double-mode; (b) triple-mode; (c) half-mode; (d) inverting-mode.
Depending on the configurations of the SC cells, in addition to the unity mode
depicted in Fig. 1.1, the SC DC-DC converters with different voltage gains (Fig. 1.2),
such as half-mode, double mode, and inverting mode [11, 12] are also available.
Moreover, by coordinating multiple SC cells, the higher order varieties of SC DC-DC
converters including the Dickson voltage multiplier [13, 14] and Fibonacci converter
3
[15-17] are derived for achieving higher voltage conversion ratios. Furthermore, the
SC cells can also be employed to interface between the voltage sources and form a
multi-input DC-DC converter performing voltage summation [18], voltage
subtraction [19], or voltage balancing [20-24].
Although the voltage gains of the aforementioned SC DC-DC converters are
determined by the topologies, the actual output voltage deviates from the maximum
attainable voltage as the load increases. In general, the phenomenon of voltage drop,
or the energy loss, in SC DC-DC converters is modeled by the equivalent resistances,
RSC, [25-27] of the SC circuits. In the traditional hard-switched SC converters, the
magnitude of the charging or discharging current of the switched-capacitor is mainly
limited by the parasitic resistances such as the on-state resistances of the switches and
the equivalent series resistance (ESR) of the capacitor. This results in current spikes
at the switching transients that not only reduces the conversion efficiency but also
brings about the issue of electromagnetic interference (EMI). If the overhead losses
such as the gate driving loss and the switching loss are neglected, the conversion
efficiency of an SC DC-DC converter is directly proportional to the loaded voltage
conversion ratio [26, 28, 29].
One demerit of typical SC DC-DC converter is the limited flexibility in voltage
turning. Certain extend of voltage regulation can be realized by pulse-width
modulation (PWM) [30], pulse-frequency modulation (PFM) [31, 32], or hysteretic
control [33] which control the output voltage by increasing RSC and sacrifice the light
load efficiency [28, 29]. To address this limitation, hybrid DC-DC converters
combining SC units with inductor stages were contrived in [34] and [35]. Moreover,
4
SC converters with an adaptive number of stages had been developed in [36] and [37]
which alter the voltage conversion ratio by dynamically transforming the internal
connections of SC units. On the other hand, by enabling continuous conduction mode
with a resonant inductor, voltage regulation with improved efficiency can be achieved
in certain types of soft-switching SC DC-DC converters [38, 39] with phase-shift and
frequency control. However, this design requires higher resonant inductance; also, the
continuous current can only be maintained at a specific range of loading condition.
1.2.1. ZCS Technique for SC DC-DC Conversion
Hard-switching
VS
VCs
Vo
ZCS Resonant
Hard-switching
ICs
ZCS Resonant
Logic: S1
ON
OFF
time
Fig. 1.3. Typical voltage and current waveforms of the switched-capacitor in a

unity-mode SC converter.
The main shortcomings of conventional hard-switching SC converters are the
discontinuous current and the generation of pulsation current spikes during the charge
and discharge cycles of the switched-capacitors [28, 40]. To overcome these issues,
researchers have developed the soft-switched SC converters based on the ideas of
quasi-resonant technique to achieve zero-current switching (ZCS) [11, 12].
5
The resonant-type SC converters operating in ZCS mode presented by Cheng et
al. [11, 12] have shown a dramatic improvement in the efficiency and EMI
performance by inserting a small resonant inductor which reserves a small portion of
energy and limits the magnitude of the switched-capacitor current during the charge
and discharge cycles. Fig. 1.3 illustrates the comparison of the typical capacitor
waveforms of a hard-switching SC circuit and a ZCS resonant SC circuit. Analyses
on the effects of parasitic resistance and inductance in both hard-switching and
resonant SC converters had been shown in [26-29, 41-45]. Ye et al. [26] elucidated
the differentiation between hard-switched and soft-switched operations based on the
theories of over-damped and underdamped circuits and suggested an optimal design
methodology of SC converters according to the coefficients accounting the frequency,
capacitance and resistance of the SC circuit.
1.2.2. Voltage Equalizer Based on the SC Technology
With specific arrangements, SC circuits can perform voltage balancing for the series-
connected cells in an energy storage system (ESS). Energy storage devices play an
important role in numerous emerging electrical systems including electric vehicles
(EVs) and the modern power system collaborating with renewable energy (RE)
resources. As an alternative of the dissipative methods [46], isolated flyback, forward
[47, 48], or the non-isolated buck-boost [20, 49] converters, the SC technique [20-23,
50] offers an effective voltage equalization solution for ESSs without the need of
bulky magnetic devices.
6
Bn
Bn
Bn−1 RSC
CS
Bn−1
RSC
CS
...
...
...
...
...
B2
B2
B1 RSC
CS
B1
(a)
CS Bn RSC
Bn
CS Bn−1 RSC
Bn−1
...
...
...
...
...
CS B2 RSC
B2
CS B1 RSC
B1
(b)
CS
Bn RSC
Bn
CS
Bn−1 RSC
Bn−1
...
...
...
...
...
CS
B2 RSC
B2
CS
B1 RSC
B1
(c)
Fig. 1.4. SC balancing topologies and the corresponding equivalent circuit
models; (a) chain-structure; (b) star-structure; (c) series-parallel structure.
7
Early development of SC cell equalizers was initiated by Pascual et. al. [21]
who suggested the use of single-pole double-throw (SPDT) switches for balancing the
cell voltages in a series-connect battery stack with a capacitor string. Being a voltage
copier, the SC equalizer realizes voltage balance for series-connected cells without
precise component matching or complicated sensing circuitries. This auto-balancing
feature has attracted research attention on developing various SC based voltage
equalization techniques, including the double-tiered [20], star [23], series-parallel [51]
structures and their soft-switching alternatives [24, 50] for improving the balancing
performance. Fig. 1.4 illustrates several existing structures of SC voltage balancers
and their equivalent circuit models.
1.3. SC DC-AC Converters
S3 S3 CS S3 CS
S2 CS S2 S2
Vo Vo
S1 S1 S1
VS VS VS
(a) (b) (c)

Fig. 1.5. Operation of a series-parallel SC cell; (a) a basic SC cell; (b)
parallel operation; (c) series operation.
Reconfiguration of SC cells can also be applied to the formation of multilevel output
voltage. Series-parallel operation (Fig. 1.5) of an SC cell produces two different
voltage levels. At the same time, it refreshes the voltage across the capacitor. This
method provides an effective way for deriving multilevel inverter (MLI) topologies.
8
Mak et al. [52] demonstrated the early application of SC cells in forming high power
density MLIs; Hinago et al. [53] formulated the MLI topology (Fig. 1.6) with voltage
step-up feature and self-balancing of the capacitor voltage based on series-parallel SC
units.
CS
...
CS
Vo
VS
CS
...
CS
Fig. 1.6. A typical MLI based on the series-parallel SC technique.
By implementing the parallel state of SC units at the corresponding output levels,
the capacitors are charged to approximately the same voltage as the DC source in
every cycle. In addition to elimination of isolated DC sources and reduction of the
component count, this technique solves the capacitor voltage imbalance issue taking
places in many conventional MLI topologies [54, 55]. Because of these attractive
features, the SC based MLIs have received increasing attention in recent years. Since
2010s, varieties of new MLIs [56-62] had been derived based on the series-parallel
SC technique. For example, Ye et al. [61] developed an alternative configuration of
SC units to attain an optimal number of active components for high power factor
applications; Barzegarkhoo et al. [57] and Liu et al. [58] proposed the hybrid
9
configurations with SC MLI sub-modules and independent DC sources; Zamiri et al.
[62] suggested an improved series-parallel conversion of SC cells featuring
asymmetric capacitor voltages; and Raman et al. [59] formulated the multi-input
MLIs cooperating SC cells with common-grounded DC sources.
However, typical SC cells are only capable of producing DC voltage steps. As
a result, most of the existing SC based MLIs work with a high voltage H-bridge or
other inverter to unfold the DC steps into multilevel AC output. This denies the
advantage of component voltage rating reduction characterized by the multilevel
configuration. Besides, the series-parallel SC technique is a double-edged sword in
power conversion: it can realize self-balance of the capacitor voltages by simply
connecting the SC cells in parallel with the voltage source; but it may, on the other
hand, generate capacitor voltage and current ripples that bring about extra power loss
and EMI. This limits the voltage and power ratings of SC base inverters. As the ripple
magnitudes are inversely proportional to the operating frequency of the SC cells, the
SCMLIs are more suitable to high-frequency AC (HFAC) applications.
1.4. Modular Design of Electric Power Conversion System
Modular approach of system design offers numerous benefits including improving the
system reliability by the provision of redundancy, the reduction in production cost by
permitting the options of utilizing more economic power semiconductor devices and
standardization of modules, increasing system flexibility and scalability with a
reconfigurable and extendable design [63-65]. Moreover, the cascaded structure of
converter modules extends the voltage conversion ratio and enables medium-to-high
voltage applications with low-voltage components [63-66].
10
The research in [63-65] demonstrated definite designs of modular DC-DC
power conversion systems with series-input output-parallel converter modules. The
input voltage rating of a module is substantially reduced by the series configuration
while the output current rating can be shared among the modules by paralleling the
output terminals of the converter units. Also, the modular concept has been adopted
in various DC-AC or AC-DC conversion applications demanding higher voltage and
power ratings. The modular multilevel converter (MMC) and multicell converter [67-
73] structures have been employed to overcome the voltage and power limits of
semiconductors. Besides, the cascaded MLIs [54, 55, 74-76] improve the power
quality by mitigation of EMI and harmonics with reduced switching steps.
Furthermore, with standardization of the converter building blocks, it is possible to
synthesize multilevel and multiphase converters for a variety of applications [77].
The modular power conversion systems can be categorized into magnetically
coupled (isolated) and electrically coupled (non-isolated) converters [78]. The former
category usually requires complicated peripheral circuits and bulky magnetic
components whereas relatively simple peripheral circuits are needed by the later
system configuration. Also, elimination of magnetic coupling result in a low-cost and
concise design [66, 78-82]. The SC technique is an ideal candidate for constructing
non-isolated power conversion systems with modularity in design. The level-shifting
feature enables voltage step-up and step-down easily without the need of isolating
components, which permits building higher voltage output from low voltage sources.
Similar to other types of converters, the current driving capability can be directly
11
increased by parallel operation. The current sharing among SC modules can be
determined by the corresponding equivalent resistance characteristic.
1.5. Thesis Objectives
The main objective of this thesis is to design the electric power conversion systems
based on clusters of generalized SC circuits. This approach offers flexibility and
scalability in system design. Also, it potentially reduces the production cost by
unification of converter modules and facilitation of integrated system design. Analysis
and design of power converters based on systems of SC units for DC-DC and DC-AC
applications are discussed. The control techniques and circuit configurations,
addressing the limitations and weaknesses of the traditional SC converters are given.
The contributions of this thesis aim at provision of power conversion solutions for
emerging technologies including electrified mobility, microgrid and distributed
generation.
1.6. Thesis Outline
This thesis focuses on the analysis and design of the control techniques as well as the
circuit topologies for SC converter systems formed by multiple SC units. The content
can be outlined as Fig. 1.7 and is organized as follows.
Chapter 1 gives an overall review of the previous development of the SC
technology and the features of existing SC based power converters. By identifying the
merits and shortcomings of the SC converters with a literature review, the motivation
and objectives of this research are directed. Also, this chapter outlines the content of
this thesis.
12
In chapter 2, the design of centralized regulation control methods for a parallel-
mode SC DC-DC converter system is presented. The principle of the ZCS SC DC-DC
converter is reviewed. The analysis is extended to the parallel-mode operation with a
varying number of active SC converter units. Based on the system modeling, a series
of centralized control techniques for this type of SC DC-DC converter is developed.
Featuring inherent voltage conversion ratio and voltage droop characteristic, these
centralized control methods are robust and easy to be implemented with the SC
technology.
Chapter 3 presents a family of multi-port SC converters for energy storage
equalization applications based on the ZCS SC units. Unlike the conventional SC
equalizers based on auto-voltage-balancing, the proposed multi-port SC equalizer
relies on the central control of a battery management system (BMS). With the
coordinated operation with a BMS, the equalization process can be accelerated by
adjusting the source voltage and a respective control of individual SC output channel.
The design, circuit characteristic as well as the performance of the multi-port SC
equalizer are discussed.
Chapter 4 proposes a hybrid SCMLI topology employing series-parallel SC
units and series-connected voltage sources. Compared to independent DC sources,
there is higher availability for series-connected sources, especially for the applications
which ESS is partaking. By combining the ideas of SC inverter and bidirectional
switched MLI, a novel inverter topology offering a high number of output levels is
developed. Detailed circuit analysis and operation of the SCMLI with the nearest
switching staircase modulation are elucidated.
13
Chapter 5 suggests a charge balancing method for series-connected cells in the
hybrid SCMLI based on a current allocation control. Voltage imbalance is a common
problem for ESS with series-connected cells and the MLIs with a series voltage source
string. General sorting control methods for cascaded H-bridge inverter (CHBI) and
other types of conventional MLIs are reviewed and investigated. The modulation limit
for attaining charge balance is overcome by cooperating the switched-ladder structure
with a series-parallel SC cell.
In chapter 6, a series of SCMLI topologies is presented which eliminates the
need of a high voltage H-bridge as the output stage and enables modularity in design.
Instead of employing a high voltage unfolding H-bridge, bipolar output voltage is
produced by a two-phase configuration of series-parallel SC cells. This configuration
allows modular approach by limiting the voltage stress of components to identical
levels. The main drawback of this configuration is the high component count. The
redundant SC cells can be eliminated via bipolar series-parallel technique. The
number of switches can be further reduced by a cross-switched structure. Depending
on the requirements of redundancy and system simplicity, each of the SCMLI
configurations provides unique pros and cons for the specific applications.
Chapter 7 proposes a soft-charging technique for the SCMLI. By adopting the
idea of quasi-resonant ZCS, the soft-charging operation significantly reduces the
power loss caused by the voltage ripples of the SC units. This dramatically improves
the energy efficiency and power rating of the inverter. The characteristics of the soft-
charging SCMLI are explained with circuit analysis and mathematical modeling.
14
Finally, the last chapter concludes the thesis by highlighting the major
contributions of this research. Besides, the remaining areas and some inspirations for
future study are also suggested.
SC Cell Based
Power Conversion
SC DC-AC Conversion SC DC-DC Conversion
Soft-Charging Soft-Switching
Technique SC Technique
(Chapter 7)
Unfolding
H-Bridge Elimination Parallel-Mode
(Chapter 6) SC Converter
(Chapter 2)
Voltage Splitting
Current Splitting
Hybrid SCMLI
(Chapter 4)
Current Multi-Port
Allocation Method SC Equalizer
(Chapter 5) (Chapter 3)
Cell Equalization
Fig. 1.7. Outline of the topics included in this thesis.
15
Chapter 2 Centralized Regulation Control
Chapter 2
Centralized Regulation Control for Parallel-mode SC
DC-DC Converter
The voltage conversion ratios of switched-capacitor (SC) DC-DC converters are
primarily determined by the circuit topologies. In other words, the desired output
voltage can be obtained by an open-loop control with complementary pulse signals.
This feature simplifies the circuit design and increases the system robustness.
However, due to the characteristic of internal resistance, the open-loop SC DC-DC
converters suffer from the problem of inevitable voltage drop at loaded condition. The
traditional closed-loop SC DC-DC converters control the output voltage using pulse-
width modulation (PWM) or frequency adjustment so that the output voltage can be
regulated at lower value under light load condition. These traditional methods
generally provide a limited range of voltage regulation and deteriorate the voltage
ripples.
Instead of controlling the individual pulse-width or switching frequency of the
SC cells, a series of centralized regulation methods is proposed for the parallel-mode
SC converters. The output voltage is controlled by adjusting the number of active SC
cells. In the proposed system, each open-loop zero-current switching (ZCS) SC
16
converter unit operates at its resonant frequency and is supervised by a central controller.
In addition to the typical discrete number of active units, the intermediate
number is realized by employing pulse-dropping PWM (PD-PWM). In the following,
the background of the parallel-mode SC technology for DC-DC power conversion is
reviewed. Based on the double-mode ZCS SC converter, the analysis and design of
the centralized control methods for a system of parallel-model SC DC-DC converters
are presented.
2.1. Review on the Parallel-Mode SC Technology for DC-DC
Conversion Applications
Literature survey found several studies on parallel operation of SC converters aiming
at enhancing the power capability of the converters. Eguchi et al. [83] and
Kiratipongvoot et al. [84] demonstrated the efficiency improvement by parallel
connection of unregulated SC converters in open-loop systems whereas the
interleaving techniques adopted in [85-87] improved the output voltage ripples in the
closed-loop systems of regulated SC converters. The dual-branch voltage doubler and
the interleaved SC converter systems proposed in [85-87] were implemented with
duty cycle and switching frequency controls to regulate the system output voltage.
One advantage of SC converter is that the no-load voltage conversion ratio is
primarily determined by the topology. Hence, the converter can easily attain the target
output voltage with complementary pulse signals at a fixed frequency [11, 12]. In
order to attain the highest efficiency, non-regulated ZCS SC converters usually
operate at the damped resonant frequency and fifty-percent duty cycle to minimize
17
the SC equivalent resistance, RSC [11, 12, 26]. In this case, the voltage conversion ratio
becomes a function of Io and RSC, which are essentially constant because of the fixed
system parameters [26]. Development of digitized system offers an alternative of
control technique with discrete parameters. Instead of tuning the individual operating
frequency or duty cycle of the gate signal of an SC converter unit, load regulation of
SC converters can be achieved by employing the concept of unit commitment to a
group of non-regulated SC converters. Given that the equivalent resistance of the
converters can act as an inherent droop control slope, SC converters are excellent
candidates for parallel operation because the load sharing is inherently allocates.
Besides, identical small power units are highly preferable for mass production which
offers the benefits of cost reduction. Furthermore, the modular approach enables
higher power applications with improved scalability and flexibility in system design.
2.2. Analysis of ZCS SC DC-DC Converter
In theory, excluding the gate driver loss, leakage current loss and switching loss, the
conversion efficiency of an SC converter operating in ZCS mode is directly
proportional to the loaded voltage conversion ratio, which can be expressed as (2.1).
In other words, the steady state output voltage drop of SC converters can be modeled
by the equivalent internal resistance, RSC, and the output current, Io, of the converter
[26, 27, 41, 42].
Vo
 (2.1)
mVi
Vo  mVi  RSC I o (2.2)
18
where Vi and Vo are the input and output voltages, respectively; m is the ideal no-load
voltage conversion ratio.
Adopting the circuit topology presented in [26], a ZCS double-mode SC
converter unit is shown in Fig. 2.1. Considering the equivalent series resistance (ESR)
of the components, Fig. 2.2 illustrates the equivalent circuits during charge and
discharge of the switched-capacitor. The ESR of the charging and discharging paths
are defined as Rch and Rdch, respectively. As suggested in [26], the converter is
differentiated between hard-switching and ZCS operation according to the damping
factor of the equivalent RLC oscillation circuits shown in Fig. 2.2.
D2
Co
D1 Lr
Vo
T2 Cs
Vi Ci
T1
Fig. 2.1. A ZCS double-mode switched-capacitor converter.
RD1 RCL RD2

RCL
RCi RCo
Ich Lr Lr Idch
Ci RT1 Co
Cs Cs RT2
(a) (b)
Fig. 2.2. Equivalent circuit during the charging and discharging cycles of an
SC converter; (a) Rch = RCL+ RD1+ RT1+ Rci; (b) Rdch = RCL+ RD2+ RT2+ Rco.
19
Referring to Kesarwani et al. [6] the equivalent resistance of an underdamped
SC converter is estimated by (2.3).
1  1  e ch 1  e dch 
RSC     (2.3)
2 f sCs  1  e ch 1  e dch 
where f s is the switching frequency, along with
 Rch  Rdch
 ch  and  dch 
2 2
1 R  1 R 
2 Lr   ch  2 Lr   dch 
Lr Cs  2 Lr  Lr Cs  2 Lr 
.
Since Rch and Rdch are in the same range, which is determined by the ESR tolerances
of the components, the values of βch and βdch are approximately equal. On the basis of
this approximation, i.e. R=Rch=Rdch, RSC is simplified to (2.4), which has been verified
by Seeman et al. [27] and Ye et al. [42].

  
1  1  e r 
RSC 
f s Cs  
 (2.4)

r 
 1 e 
R
where   is the neper frequency which indicates how fast the resonance is
2 Lr
1
damped; r    2 is the resonant frequency of the RLC oscillation circuit.
Lr Cs
By substituting (2.2) into Vo=IoRo and considering the forward voltage drop of
diodes, the voltage conversion ratio of the SC converters can be expressed as follows:
20
Vo mRo nV
  D (2.5)
Vi RSC  Ro Vi
where Ro is the load resistance, VD and n are the forward voltage drop and the total
number of conducting diodes in the SC conduction paths, respectively.
If multiple SC converter units with the same specification are operating in
parallel, the equivalent resistance of the system consisting k SC converter units, RSC(k),
can be described as (2.6)
R 'SC
RSC  k   (2.6)
k
where R'SC is the average equivalent resistance of an SC unit. Due to the fact that the
input and output filtering capacitors of all SC converter units are physically tied in
parallel, the total capacitance and the overall ESR of the filtering capacitors are
independent of the number of activated SC converter units. The average equivalent
resistance would slightly increase with the number of operating units. The average
equivalent resistance R'SC, in the system is then approximately
 
  
1  1  e r ' 
R 'SC  kRSC  k  
f s Cs  
  (2.7)

r ' 
 1 e 
by substituting the varied ESR of the charging and discharging path, i.e.
R'SC=Rch'=Rdch'=RCL+RD1+RT1+kRCi=RCL+RD2+RT2+kRCo.
Unlike a single converter, in addition to adjusting the switching frequency or
duty cycle, load regulation can also be achieved by controlling the overall equivalent
21
resistance of the SC converter system, RSC  k  , through varying the number of active
units, k, in the parallel-mode ZCS SC converter system.
2.3. Centralized Regulation Control by Varying the Number of
Active Units
The output voltage of a parallel-mode SC converter system is a function of the average
load current of the activated units. This suggests that the output voltage can be
controlled by adjusting the number of activated units. In a centralized controlled
system, a supervisory central control unit (CCU) can be implemented by a digital
controller equipped with analog inputs and digital outputs. The output bus current or
voltage is sensed by the analog input of the CCU. The measurement is then compared
with the predefined limits or reference values. The number of operating units, k, is
updated according to the control output. Each of the SC converter modules is
controlled by a digital signal which turns on or off the corresponding gate driver or
oscillator circuit. The centralized control with a discrete unit number and a hybrid
variation are described in the following context.
2.3.1. Discrete Unit Control with Current Feedback
The voltage drop and power loss of SC converters are highly related to the equivalent
resistance and the load current. If the switching frequency is fixed, the equivalent
resistance of the hard-switched or ZCS SC converter is essentially constant. As a result,
the power loss as well as the output voltage can be estimated based on the load current.
Unit commitment is formulated according to the output current rating, Io,rate, of a
22
single SC unit. Next unit is committed when the load current exceeds the total current
rating of the activated SC units. (Fig. 2.3)
 I 
k o  (2.8)
 I o ,rated 
Current allocation of the parallel operating SC converter units is attained
according to the voltage droop characteristic. The slope is determined by the value of
RSC. Although the same output voltage is shared by all units, current imbalance can
occur due to the engineering tolerances of components. Nevertheless, individual
overcurrent can be avoided by limiting the minimum system output voltage, or the
maximum voltage drop of the converter.
+1
Irated CLK Counter
−1
Io k
Load
Fig. 2.3. Functional block diagram of discrete unit control with current
feedback (DUCC).
As shown in Fig. 2.3, the total output current, Io, is compared with the k times
and k−1 times of the rated unit current. If the output current exceeds the rated current
of k SC units, the counter value will increase by one. On the contrary, if the output
23
current is less than k−1 times the rated unit current, the counter value will decrease
by one. Else, the counter value will remain unchanged.
2.3.2. Discrete Unit with Hysteresis Voltage Control
Although it is the most straightforward way to use current feedback in determining
the number of active units, the voltage regulation of DUCC is ineffective. On the other
hand, a hysteresis voltage controller which compares the sensed output voltage with
the set-point voltage by a hysteresis comparator is used to select the number of active
units. The hysteresis width is adjusted corresponding to the number of active SC units.
If the output voltage is lower than the set-point with the corresponding hysteresis, the
controller will increase the number of active units and, vice versa (Fig. 2.4).
Vo
Hysteresis
Control
Vset
k
Load
V
Fig. 2.4. Functional block diagram of discrete unit control with hysteresis
voltage-band (DUCV).
A. Voltage Hysteresis Width
Assuming that the load current remains constant during the transition of k, the output
voltage will increase from Vo(k) to Vo(k+1) because the system equivalent resistance is
24
reduced from RSC(k) to RSC(k+1). Minimum peak voltage error is attained by letting
Vset – Vo(k) =Vo(k+1) – Vset =Vhk. Substituting (2.2) into this equality, the voltage
hysteresis width, Vhk, can be expressed as follows
   
Vhk  Vset  mVi  RSC  k  I o  mVi  RSC  k 1 I o  Vset (2.9)
Eliminating Io in (2.9) gives:
(mVi  Vset )( RSC  k   RSC  k 1 )

Vhk  (2.10)
RSC  k   RSC  k 1
If the ESRs of the input and output filter capacitors are small comparing to other
lossy components so that the difference between R'SC for successive k is negligible,
the relationship of the system equivalent resistance with successive numbers of
activated units can be approximated by (2.11).
RSC  k  k 1
 (2.11)
RSC  k 1 k
As a result, the voltage hysteresis width can be simplified to (2.12).
mVi  Vset
Vhk  (2.12)
2k  1
which is only subject to the difference between the no-load voltage, mVi, the target
output voltage, Vset, and the number of active SC converter units, k. The counter
controlling the number of active SC converter units is described by the hysteresis
triggering diagram shown in Fig. 2.5. The voltage resolution of the DUCV is
dominated by the hysteresis width, which is determined by the number of active SC
units. In general, a larger k would result in a better voltage resolution.
25
k+1
-Vhk Vhk (Vset–Vo)
Fig. 2.5. Hysteresis triggering of the number of active SC converter units in

DUCV; k=1,2,…,n−1 is the number of active SC converter units, where n is the
total number of SC converter units connected in parallel.
2.3.3. Hybrid Unit Control Using PD-PWM
One major limitation of the aforementioned methods is the poor voltage regulation
when k is small. In extremely case, i.e. k=1, the voltage regulation control is nullified
at very light load. To address this problem, instead of discrete controls, proportional
voltage regulation is accomplished by the commitment of a partial unit. The
intermediate number of active units is realized by the pulse-dropping PWM (PD-
PWM) which is described in Fig. 2.6. The on-off states of the SC converter units are
controlled by the level-shifted PWM signals at a lower frequency. The carrier
amplitude of Vm1 to Vmn is normalized so that the shifted level for the kth SC unit is
k−1. This level-shifted PWM signals are superposed to the complementary gate
driving signals generated at individual SC converter units. When the level-shifted
PWM signals of the units are at logic “LOW”, the corresponding gate-driving signals
will be skipped, and, vice-versa. This results in a smoother voltage control and more
precise voltage regulation. The functional block diagram of the hybrid unit control
(HUC) is depicted in Fig. 2.7.
26
kth SC unit
Gate
Driver
VGk
PWMk Enable
(a)
TS DTS
Vm3 Vref
Vm2
Vm1
PWM3
PWM2
PWM1
Vosc
VG3
VG2
VG1
t
(b)
Fig. 2.6. Implementation of the Level-shifted pulse-dropping PWM
(PD-PWM) signal; (a) the use of level-shifted PWM signal as the enable
control of the gate driver in the kth SC unit; (b) illustration of the PD-PWM
waveforms.
27
Vo Vref Level-shifted
PI PWM
Vset
PWM
Load
V
Fig. 2.7. Functional block diagram of hybrid unit control (HUC).
Furthermore, there is only one PD-PWM signal at any time instant. The
hardware implementation of level-shifted PWM can be therefore simplified by
specifying only one PD-PWM unit in the system whereas the remainders are
controlled by simple digital on-off signals.
A. Small Signal Analysis of the HUC SC converter System
By modeling the HUC SC converter system with RSC(k+D), the equivalent circuit of the
parallel-mode SC converter system can be simplified to Fig. 2.8.
IRsc Io
RSC(k+D)
mVi VC
Co Ro
Fig. 2.8. Equivalent circuit of the SC converter system regulated by the

hybrid unit control.
28
The voltage drop of the SC converter system can be expressed as the following
equation.
mVi  VC  I Rsc RSC k  D (2.13)
Considering the voltage of the output filter capacitor as the system state, which is
dVC I Rsc  I o
 (2.14)
dt Co
the state-space equation during the k+1th unit is activated, k+1(on), can be derived as
 VC  1 1  mVi
VC      (2.15)
Co  RSC  k 1 Ro  RSC  k 1Co
Similarly, during k+1(off), the state-space equation becomes
 VC  1 1  mVi
VC      (2.16)
Co  RSC  k  Ro  RSC  k Co
Using state-space averaging to linearize the above equations and neglecting the high
order small signal variation, the small-signal averaged state-space equation of the SC
converter system with pulse-dropping PWM at duty cycle D at the k+1th unit is
approximately
vc  D 1  D 1  mVi  VC  1 1 

vc         d (2.17)
Co  RSC  k 1 RSC  k  Ro  Co  RSC  k 1 RSC  k  
 
where D and d are the duty cycle and its small-signal perturbation, respectively. This
can be simplified using (2.7), (2.11) and (2.13):
29

vc  k  D 1  mVi d
vc       (2.18)
Co  R 'SC Ro  Co Ro  k  D   R 'SC
The small signal response to duty cycle in s-domain is therefore
vc mVi 1 1
   (2.19)
d Co Ro  k  D   RSC

s
kD

1
R 'SC Co RoCo
As shown in (2.19), the small signal response of the output capacitor voltage to
duty cycle contains only one pole on the left-half plane. This suggests that the SC
converter system under PD-PWM is stable. A PI controller with a fast roll-off
characteristic could be employed to generate the voltage reference, Vref.
B. Analysis of Output Voltage Ripple due to Pulse-dropping
Although the PD-PWM can improve the voltage regulation compared to the discrete
counterparts, it causes extra voltage ripple at the low PWM frequency. The additional
output voltage ripple of the HUC SC converter system due to pulse-dropping can be
evaluated by considering the charge balancing of the output filter capacitor. By
assuming that the ripple is small so that the output voltage and current remain
constants, the amount of charge accumulated and released during the on and off cycle
of the kth unit is derived as (2.20).
 mVi  VC   mV  V 
Q  Ts 1  D   I o    Ts D  i C
 Io  (2.20)
 RSC  k    RSC  k 1 
   
By substituting (2.13) and (2.20) into ∆Q=Co∆Vo, the output voltage ripple due to the
PD-PWM is approximated by (2.21).
30
I o DTs  RSC  k  D  
Vo    1 (2.21)
Co  RSC  k 1 
 
which can be further simplified using (2.11) and becomes (2.22).
I o DTs 1  D 
Vo  (2.22)
Co  k  D 
Therefore, the output voltage ripple of the SC converter system due to PD-PWM can
be evaluated by (2.22) without knowing the SC converter equivalent resistance.
Since the PD-PWM signal is quantized to discrete numbers of pulses, shorter TS
means lower pulse resolution, i.e. higher quantization error of the modulating signal.
Therefore, besides the output voltage ripple, resolution of the PD-PWM signal should
also be considered in selecting the level-shifted PWM frequency. In general, for SC
converters operating at hundreds kilo-hertz, at least ten times of SC converter
switching period are recommended when selecting the TS for HUC.
2.4. Simulation and Experimental Verification
In order to validate the theory and operation of the centralized regulation methods, the
simulation and experiment on each of the control setups were conducted. The results
were in accordance with the theoretical prediction. Different extends of voltage
regulation were achieved by the centralized control methods. The following
subsections present the simulation study with five parallel double-mode ZCS SC
converter units as well as the experimental results on the system prototype consists of
ten SC converter units.
31
2.4.1. Simulation Results
A 5-parallel double-mode ZCS SC converter system employing the proposed
regulation methods was simulated with non-ideal components listed in Table 2.1. A
schematic for the setup is illustrated in Fig. 2.9. The SC unit model attributed RLC
parameters of about 0.15 Ω, 500 nH and 3 μF, respectively. The switching frequency
of the SC converter units was 125 kHz; the outputs were connected together through
wires modeled by 5 mΩ and 50 nH. The forward voltage drop of each diode was
0.25 V and the equivalent resistance, RSC(1) and RSC(5), were approximately 0.68 Ω and
0.16 Ω, respectively. The current setting for DUCC was 2.0 A, whereas the voltage
settings for DUCV and HUC were 28 V. Only the 1st unit was assigned as the PD-
PWM unit for HUC. The modulating signal and the shifted levels of the units for the
PD-PWM were represented by numeric variables in the control program. The
simulated output waveforms under a ramp load were captured.
Table 2.1. Parameters of the simulated SC converter system.

Input Voltage (Vi) 15 VDC
Switched capacitors (Cs) 3 µF, 20 mΩ
Resonant Inductor (Lr) 500 nH, 5 mΩ
RDS(on) of the MOSFETs 50 mΩ
VF of the Diodes 0.25 V, 50 mΩ
Input/output filter capacitors 300 µF, 50 mΩ each
Number of SC converter units 5
Switching frequency 125 kHz
Level-shifted PWM frequency 5 kHz
32
Double-mode SC Units
V
Ro Enabling
Signals
Vi
Io
Microcontroller
Vo Unit
Central Controller
Fig. 2.9. Schematic of the setup for the parallel-mode SC converter.
When a ramp load (Fig. 2.10) was applied, saw-tooth patterns were observed in
the output voltage and the unit current for the cases of discrete unit control as shown
in Fig. 2.11. Under the light load condition, only the HUC was capable of regulating
the output bus voltage at 28 V.
Additional voltage ripples and current fluctuations appeared in the output
waveform (Fig. 2.12). The simulated voltage ripple magnitude was approximately
0.6% of the rated output voltage. This ripple level would be acceptable for general
applications like lighting systems and electric motors. If the output waveforms were
observed carefully, three sources of output ripples could be noted in the HUC
controlled SC converter system. The output voltage ripples with the highest frequency
were mainly formed by the SC discharging current and the ESR of the output filtering
capacitor whereas the voltage ripples at 5 kHz was caused by the PD-PWM which
skipped the output current pulses.
33
Io (A) Load Current

10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (s)
Fig. 2.10. A load current ramp starts from 0.9A to a peak value of 10.9A.
Output Bus Voltage

Vo (V) All Unit
29.5
28.5
27.5
DUCC
29.5
28.5
27.5
DUCV
29.5
28.5
27.5
HUC
29.5
28.5
27.5
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (s)
(a)
Io (1 st Unit) (A) Unit Output Current

All Unit
8.0
4.0
0
DUCC
8.0
4.0
0
DUCV
8.0
4.0
0
HUC
8.0
4.0
0
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (s)
(b)
Fig. 2.11. The simulation results; (a) the output bus voltage; (b) the output current
of the 1st unit under different regulation methods.
34
Vo (V) Bus Output Voltage

28.1
28.0
27.9
D Duty Ratio
0.405
0.400
0.395
Io (1 st Unit) (A) Unit Output Current (HUC)
4.0
2.0
0
0.0490 0.0495 0.0500 0.0505 0.0510
Time (s)
Fig. 2.12. The output voltage and unit current ripples of HUC at light load.
Moreover, the control signal of HUC was quantized to the pulse number in PD-
PWM. This induced low frequency fluctuations in the output voltage and the duty
cycle. The reference signal generated by the PI controller was alternating between two
quantized pulse numbers, chasing the desired output voltage. This fluctuation is
insignificant compared to other two sources of voltage ripples.
The current rating of the parallel-mode SC converter system can be determined
by the voltage droop represented by the overall equivalent resistance, RSC(n). If the
steady state DC voltage deviation limits of ±10% set by IEC60092-101 is adopted,
the maximum output current, Io,max, can be derived as Io,max=0.2Vnom/RSC, given that
the upper voltage limit is reached at no-load condition and Vnom is the nominal output
voltage. The problem of current circulation was prevented by the diodes in the double-
mode ZCS SC converter topology. Furthermore, this problem is also eliminated by
the inherent RSC characteristic. In the simulation model, the current allocation of SC
converters was determined by the unit voltage droop characteristic, which was a
35
function of the unit RSC. The SC converter unit with higher internal resistance showed
a steeper voltage droop and vice versa. Considering ±20% ESR tolerances of the
components, the RSC would vary between approximately ±7% of the nominal value.
The voltage droop and current allocation of the SC converter system are illustrated in
Fig. 2.13. The inaccuracy due to the resistance variation can be significant when the
number of active units is small. The peak output under the maximum voltage droop
should be considered when sizing the current of SC units. Especially in the case of
DUCV, the hysteresis control allows a lower voltage compared to the nominal voltage
setting. As a result, the peak unit current can be significantly higher than the nominal
average unit current. Overcurrent of individual unit can be avoided by sizing the unit
according to the maximum voltage droop and minimum RSC.
Voltage Droop and Current Allocation

Vo (V) Load current (A)
0.0 2.5 5.0 7.5 10.0 12.5
29.5
+20% ESR
29.0 Typical
-20% ESR
28.5
Bus
28.0
27.5
0.0 0.5 1.0 1.5 2.0 2.5
Unit current (A)
Fig. 2.13. Simulated voltage droop characteristic and current allocation.
36
Open Loop Response of HUC

0 20
0
-10 -20
Phase (deg)
Gain (dB)
-40
-20 -60
-80
-30 from Eq. (19)
(2.19) -100
Simulation -120
-40 -140
20 50 100 fB 500 1000 4000
Frequency (Hz)
Fig. 2.14. Open-loop response of the simulated SC converter system under HUC.
The level-shifted PWM frequency was fixed at 5 kHz. In order to investigate
the stability of the PD-PWM controlled SC converter system, the frequency response
of the system at k=2 and D=0.2 under the HUC was analyzed. The open-loop response
of the parallel SC converter system is plotted in Fig. 2.14.
As predicted in (2.19), there was a 90° phase-shift at high frequency due to the
pole on the left-side plane. The break frequency, fB, is dependent on the load current
and the number of active units. Besides, due to the quantization error of the small-
signal perturbation in PD-PWM, a small amount of extra attenuation could be
observed in the simulation model. In general, a PI controller with moderate gain and
fast roll-off can provide stable operation of the converter. In real implementation, the
quantization error could be considered as a gain deviation of the control signal.
2.4.2. Prototype of the Parallel SC converter System
In order to verify the proposed voltage regulation methods a system prototype (Fig.
2.15) consisting ten double-mode SC converter units was built and tested under
different load conditions. Each SC converter unit was implemented with a 3 µF
37
polypropylene switched-capacitor and a 390 nH inductor to ensure ZCS operation at
about 100 kHz. MOSFETs and Schottky diodes with low RDS(on) and forward voltage
drop were selected to moderate the conduction loss. After fine tuning, the SC
converter units operated at a damped resonant frequency of around 128 kHz, driven
by self-oscillating half-bridge gate drivers which shared the same voltage supply with
the SC converter power circuit. The SC converter units could be turned OFF by
disabling the oscillating signal through the corresponding logic-level MOSFETs.
These logic-level MOSFETs were controlled by an STM32F446 microcontroller. The
measured equivalent resistances of the SC converter system with one unit enabled,
RSC(1), and all units enabled, RSC(10), were 1.218 Ω and 0.139 Ω, respectively.
Table 2.2. Specification of the SC converter system prototype.

Parameters Values
Input Voltage (Vi) 15 VDC
Polypropylene 3 µF
Switched capacitors (Cs)
(ESR = 17.8 mΩ; ESL = 22 nH)
Resonant Inductor (Lr) 390 nH (ESR = 1.3 mΩ)
MOSFETs IRF540N 100 V, 33 A, 44 mΩ
Diodes SL44-E3 40V, 4 A
Number of SC converter units 10
Input/output filter capacitors Electrolytic ~3000 µF in total
Switching frequency 128 kHz
Level-shifted PWM frequency 5 kHz
RSC(1) 1.218 Ω
RSC(10) 0.139 Ω
38
2
4 5
Fig. 2.15. Experimental setup of the parallel double-mode SC converter system;

(1) DC power supply; (2) DC electronic load; (3) 10-unit double-mode SC
converter system; (4) STM32F446 microcontroller board;
(5) instrumentation circuit.
2.4.3. Results of the Unit Control Schemes
A load current ramp of 1.5 A/s from 0.9 A to 10.9 A and a load current step from
0.9 A to 5.9 A were applied to the parallel-mode SC converter system. The system
was controlled by the aforementioned voltage regulation schemes. Considering a total
current rating of 10 A, the dynamic range for the experiment setting was 9%-to-109%
of the rated load. The system output voltage and current, along with the output current
of the first SC converter unit, were measured under different load conditions and
control methods. The system with all units activated was also tested for comparing
the effectiveness of the centralized voltage regulation methods.
Since the equivalent resistance of SC converters remained constant at a fixed
switching frequency, a linear voltage change was observed when a load current ramp
was applied while the number of activated units was fixed. The voltage droop rate of
all units activated was about -0.139 V/A. According to the voltage droop rate, the
39
rated current of a single SC converter unit was defined as 1 A so that including the
forward voltage drop of the diodes, the output voltage at rated load was about 28 V.
The set-point voltage of the DUCV and HUC was also defined as 28 V. The voltage
hysteresis width of the DUCV was computed by the controller using (2.12) based on
the number of active units, k, in real time.
The output voltage drop was dominated by the magnitude of the average load
current. Hence, a higher voltage drop can be observed in Fig. 2.16a compared to 2.16b
when the magnitude of the current ramp was larger than that of the current step.
Moreover, saw-tooth patterns scanning through the relative maxima and minima of
the output voltage and unit output current appeared when the voltage was regulated
by DUCC and DUCV (Fig. 2.17 and 2.18). This was owing to the changes in the
discrete number of operating units along with the voltage and current hysteresis. When
the number of activated units was altered, there would be a step change in the output
voltage and average unit output current.
On the other hand, the output voltage of the HUC SC converter system was
steadily regulated at 28 V regardless of applying a load current ramp or a load current
step (Fig. 2.19). However, when the load current was too high, the output voltage
dropped beyond 28 V after all units were enabled. Besides, in comparison with the
high frequency voltage ripples formed by the current ripples and the impedance of the
output filter capacitor, the voltage ripples due to pulse-dropping and duty-ratio
fluctuation were hardly seen in the measured output voltage waveforms.
40
Time base: 2s/div

Vo: 2V/div
Io: 5A/div 28V
Io(1st unit): 2A/div
(a)
Vo: 2V/div Time base: 0.5s/div
Io: 2A/div 28V
(b)
Fig. 2.16. Output response of the SC converter system with all units
enabled; (a) load current ramp; (b) load current step.
41
Time base: 2s/div

Vo: 2V/div
28V
Io: 5A/div
(a)
Time base: 0.5s/div

Vo: 2V/div
Io: 2A/div 28V

(b)
Fig. 2.17. Output response of the SC converter system with DUCC;
(a) load current ramp; (b) load current step.
42
Time base: 2s/div

Vo: 2V/div
Io: 5A/div 28V

(a)
Time base: 0.5s/div

Vo: 2V/div
Io: 2A/div 28V

(b)
Fig. 2.18. Output response of the SC converter system with DUCV;
43
Time base: 2s/div Time base: 100µs/div
Vo: 2V/div
Zoom in
Io: 5A/div
28V
(a)
Time base: 0.5s/div
Vo: 2V/div
Io: 2A/div 28V

(b)
Fig. 2.19. Output response of the SC converter system with HUC;
44
(a)
10
8 All Units
DUCC
6 DUCV
HUC
k
0
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
(b)
Fig. 2.20. Output characteristic of the SC converter system with different
centralized regulation schemes; (a) output bus voltage;
(b) number of active units, k.
45
As observed in the experiment of applying a current step, the response of the
parallel-mode SC converter system was fast and the output voltage became steady
quickly. The response speeds of the DUCC and DUCV were affected by the sampling
rate of the controller while that of the HUC was mainly determined by the PI time
constant. The output voltage characteristic and the measured efficiency of the parallel
double-mode SC converter system are plotted in Fig. 2.20 and Fig. 2.21, respectively.
The theoretical values were calculated according to the measured equivalent
resistance of the first unit, RSC(1)=1.218 Ω, and all units, RSC(10)=0.139 Ω, and (2.7) to
(2.13) for finding the theoretical output V-I characteristic of different numbers of
operating units. Although the theoretical efficiency of the parallel-mode ZCS SC
converter should follow (2.1). Compared to the unregulated system (i.e. the all units
case), the experimental efficiency of the controlled system at light load was slightly
improved by saving the gate-driving and switching losses.
0.95
0.9
Efficiency
0.85
All units
0.8 DUCC
DUCV
HUC
0.75
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Fig. 2.21. Measured efficiency of the SC converter system prototype.
46
2.5. Summary
This chapter demonstrates a series of centralized control techniques for a parallel-
mode SC converter system aiming at achieving load regulation. The voltage droop
characteristic brought by the equivalent resistance of SC converters eliminates the
current allocation and circulation issues suffered by many other power converters.
The RSC modeling of SC converters also simplifies the analysis and allows intuitive
prediction of operation. The theory and operation of the centralized voltage regulation
controls with discrete and hybrid unit numbers are verified by the simulation and
experimental studies. Voltage regulation throughout the range of 9% to 109% load
condition was attained. With the voltage set-point of 28 V, the measured efficiency of
the double-mode SC converter with 15 V input voltage was approximately 93%. Since
the start-up and shut-down costs of the parallel connected switched-mode power
converters are negligible; also, the current ramp-up speed of SC converters is very
fast, the unit commitment for the parallel-mode SC converter system is very simple
but effective. With a simple centralized control of parallel-mode SC converter system,
the modular design of SC converter units offers an alternative scalable solution for
DC-DC power conversion.
In double-mode SC converter, the switched-capacitor is charged by parallel
connection with a voltage source; double voltage is produced by series connection.
Cascading the SC units is a technique to attain higher voltage step-up ratio. Besides,
it is possible to transport energy between arbitrary potential levels with this SC
technique. The next chapter explores an alternative design of SC based equalization
circuit with centralized control to improve the balancing speed.
47
Chapter 3 Multi-port SC Converter
Chapter 3
Development of Multi-port SC Converters for Energy Storage
Equalization Applications
A novel implementation of multi-port zero-current switching (ZCS) switched-
capacitor (SC) converters for energy storage equalization applications is presented. In
addition to the auto-balancing feature offered by the SC technique, the multi-port SC
converter permits individual control of the charging or discharging current of the
series-connected energy storage elements such as the battery or supercapacitor cells.
This approach enables advanced state control and accelerates the equalizing process
by coordinately operating with the battery management system (BMS) and an
adjustable voltage source which can be implemented by a DC-DC converter
interfacing with the energy storage string. Different configurations, including the
single-input multi-output (SIMO), multi-input single-output (MISO) SC converters
and the corresponding altered circuits for string-to-cells, cells-to-string, as well as
cells-to-cells equalizers are presented with circuit analysis and derivation of the
associated mathematical representation. The simulation study and experimental
results indicated a significant increase in the balancing speed with the centralized
control of SC current by the BMS.
48
3.1. Background of Power Electronics for Energy Storage
Management and SC Equalization Technology
Energy storage devices enable the functioning of electrical systems and modern utility
configured with renewable energy sources. The electro-chemical battery and
supercapacitor are two major technologies nowadays for energy storage systems
(ESSs). In many applications of battery or supercapacitor based ESSs including
electric vehicles (EVs), stationary storage in backup systems such as uninterruptible
power supplies (UPSs) and online systems interfacing renewable generation or
electrical grids, a huge number of energy storage cells are connected in series to
achieve adequate voltage and power ratings. Due to the manufacturing tolerance and
variations of the environmental conditions, the charge-discharge operation of the
battery or supercapacitor strings induces state-of-charge (SOC) inequality among
individual cells. The SOC imbalance can push specific cells beyond the normal
operating condition, degrade the lifespan of the energy storage devices, and eventually
accelerate the failure of the system [88-91]. Therefore, charge equalization plays an
important role in ESS management [89-92].
The techniques for charge equalization can be categorized into passive and
active methods. Passive charge equalizers [46, 93] employ passive shunt elements like
Zener diodes, resistors or even the self-discharge leakage current to attain cell balance.
These passive methods are featuring low cost and easy to implement but the use of
dissipative elements means inefficient. Also, the balancing progress is usually limited
by the thermal condition. In contrast, the active methods utilize SMPCs to transfer
charge and energy among energy storage cells. These equalizers include classical
49
isolated topologies like the fly-back or forward converters and the non-isolated boost,
buck-boost and SC converters [21, 46, 88, 94-97]. Along with the increasing
penetration of battery and supercapacitor based ESSs, the development of advanced
cell balancing technologies has become a significant research area. Numerous novel
ideas, including coupled inductors [95, 98-102], time-shared control [103-106],
multistage structures [91, 107] and resonant converters [24, 108, 109] have been
reported for reducing the implementation cost and improving the performance of
active equalizers for series-connected cells. Due to the simple working principle and
control with a configurable current setting, the fly-back topology remains successful
in commercialized active battery equalizers. Still, the sizable footprint of the coupled
inductors as well as the issues of additional loss and voltage spikes caused by the
leakage inductance [99] increase the design difficulty and implementation cost of fly-
back based active cell equalizers.
On the other hand, varieties of multi-port SC converters [23, 50, 51, 110, 111]
have been developed to realize auto-voltage-equalizers with inherent zero balancing
voltage-gap. By utilizing capacitors as the major medium for charge transfer, it is
possible to achieve compact and low-cost implementation of cell equalizers with the
SC technique. The auto-balancing feature allows open-loop operation with simple
complementary gating signals for the active switches. This principally enables the
possibility of an autonomous onboard equalizer without any complicated voltage
sensing circuits. However, this feature can be a double-edged sword because the
magnitude of the balancing current is determined by the voltage differences, aka
voltage-gaps, among the cells. For the majority of electrochemical systems, the typical
50
cell voltage variations over the whole range are bound to be less than one-third of the
rated voltage. The exiguous voltage differences of unequal cells can limit the speed
performance of SC based equalizers. Furthermore, this confines the applications of
SC equalizer to voltage balancing. Without the interface and collaboration with any
control from a centralized control such as a battery management system (BMS), it is
difficult to achieve advanced state control accounting for the thermal [112], position
[113] and dynamic [107, 114] parameters of specific cells in the string; especially for
the applications of second-life batteries and hybrid energy storage packs [97, 115,
116].
The single-input multi-output (SIMO) and multi-input single-output (MISO)
configurations have been employed to string-to-cells, cells-to-string, source-to-cells
and cells-to-load equalizers [94, 96, 107, 114, 117]. By adopting these configurations,
it is possible to actively control the balancing current. Instead of the voltage-gap
among the cells, the cell current in the SIMO and MISO SC converters is determined
by the voltage difference between the cells and the source, as well as the equivalent
resistances of the SC units. Therefore, the current magnitude can be controlled by
adjusting the source voltage or the resistances with discrete or pulse-dropping gating
control [118]. In this chapter, the working principle of the SIMO and MISO SC
converters is explained with the modeling and mathematical analysis on the SC
equivalent resistance and balancing current. The source-to-cells and cells-to-load
configurations can be altered into string-to-cells, cells-to-string and cells-to-cells
equalizers with a non-isolated DC-DC converter. Design consideration for the altered
implementations is also discussed.
51
3.2. Overview of the SIMO and MISO SC Converters
Bn Bn
B2 B2
T0 T1
Vi B1 Vo B1
T0 T1
SC Unit SC Unit
(a) (b)
Fig. 3.1. Generalized topology of the multi-port SC converter;
(a) SIMO configuration; (b) MISO configuration.
The SIMO and MISO configurations of zero-current switching (ZCS) SC converter
are illustrated in Fig. 3.1. An n cells source-to-cells SC charger consists of n SC units
and an active switch, T0, at the low side of the source. Likewise, an n cells cells-to-
load converter consists of n SC units and an active switch at the high side of the load.
An SC unit is constituted by a capacitor, an active switch, three diodes and a resonant
inductor. The switches T0 and T1 operate in a complementary manner. For the SIMO
configuration, the switched-capacitors are charged by the input voltage source when
T0 is conducting, discharge to the specific battery or supercapacitor cell when the
corresponding T1 is conducting, and vice versa for the MISO configuration. By
inserting a resonant inductor in series with the switched-capacitor, ZCS is achieved.
This dramatically reduces the equivalent resistance of the SC unit and improves the
conversion efficiency and current carrying capability of the converter.
52
To realize individual charge control of the series-connected cells, the gating
signals of the corresponding T1 is enabled or disabled with discrete logic or PWM
signal. This topology is beneficial from the small number of active components. For
n series cells, the number of MOSFETs would be only n+1. However, the topology is
only capable of handling unidirectional current. The proposed SIMO SC converter
allows only charging current to the cells; whereas the MISO SC converter permits
only discharging current from the cells. This eases the soft-switching circuit design
by eliminating the requirement of precise component matching. With this
unidirectional implementation, ZCS can be attained as long as the switching
frequency is lower than the resonant frequency.
3.3. SC Modeling and Analysis
S1 S2 Sn S1 S2 Sn
Vi RSC RSC RSC Vo RSC RSC RSC

Ich,1 Ich,2 Ich,n Idch,1 Idch,2 Idch,n
B1 B2 Bn B1 B2 Bn
(a) (b)
Fig. 3.2. Behavioral model of the SC converter; (a) SIMO configuration;
(b) MISO configuration.
The voltage conversion ratio of an SC converter is determined by the circuit topology.
In the proposed configuration, the ideal voltage conversion ratio of each SC unit at
lossless condition is unity. Taking the lossy components into account, the current
magnitude is determined by the equivalent resistance of the SC unit and the difference
53
between the input and output voltages. The behavioral models [23] of the proposed
SC converters can be described as Fig. 3.2.
The average charging or discharging current for the ith battery, Ich,i or Idch,i, can
be described by the following functions.
Vi  3VD  VBi (3.1)

I ch ,i   Di
RSC
VBi  3VD  Vo (3.2)

I dch,i   Di
RSC
where VBi is the voltage of the ith cell, VD is the forward voltage drop of a diode, Di is
the duty cycle of Si. The equivalent resistance, RSC, of the SC units is determined by
the circuit parameters. Fig. 3.3 illustrates the equivalent circuits of the SC unit during
the conduction period of T0 and T1, respectively. In the SIMO configuration, the
switched-capacitor is charged from the input voltage source through the resonant
inductor, L, two diodes, and the switch, T0, during the conduction period of T0; and
discharged to the battery through the resonant inductor, a diode, and the switch, T1,
when it is conducting. In contrast, the switched-capacitor in the MISO configuration
is charged from the battery during the conduction period of T1 and discharged to the
load during the conduction period of T0. The lossy components include the input
source resistance, Ri, ESR of the capacitor and inductor, RC and RL, diode resistance,
RD, the on-state resistances of the switches, RT0 and RT1, and the series resistance of
the cell, RB, in the charging and discharging paths of the SC unit. The corresponding
SC path resistance can be expressed as R0=kRi+RC+RL+2RD+kRT0 and
R1=RB+RC+RL+RD+RT1. Assuming that the battery voltage connecting to the
activated SC units are close to each other, the charging or discharging current of the
54
SC units would be approximately the same. Therefore, the multiplication factor, k, for
the on-state resistance RT0, of T0 can be substituted by the number of activated SC
units.
2VD VD
ica icb
L L
Vi VBi
R0 vc C vc C R1
(a) (b)
2VD VD
icb ica
L L
Vo VBi
vc C R0 R1 vc C
(c) (d)
Fig. 3.3. Equivalent circuits of the charging/discharging paths of the switched-
capacitor; (a) conduction stage of T0 in SIMO configuration; (b) conduction stage
of T1 in SIMO configuration; (c) conduction stage of T0 in MISO configuration;
(d) conduction stage of T1 in MISO configuration.
In order to attain the underdamped condition for ZCS operation, the RLC
parameters of the SC circuit should fulfill the requirement as stated in [26], i.e.
4L 4L
R0  and R1  (3.3)
C C
By analyzing the underdamped waveforms of the capacitor voltage and current as
suggested in [26, 118], RSC can be derived as (3.4).
tanh  0  tanh 1
RSC  (3.4)
2 fC
55
where f is the switching frequency of the complementary switch pair T0 and T1. β0 and
β1, indicating how much the resonant is damped at ZCS, are associated with the
exponential terms of the resonant circuit.
 R0 C  R1 C
0  and   .
2 4 L  CR0 2 2 4 L  CR12
1
In additional to (3.3), the switching frequency, f, should be lower than the damped-
resonant frequency taking the component tolerances into account.
1 1 R2 1 1 R2
f   0 2 and f   12 (3.5)
2 LC 4 L 2 LC 4 L
Given the condition that (3.3) and (3.5) are fulfilled, according to (3.4), the
equivalent resistance, RSC, of the SC unit is determined by the circuit resistance,
inductance, capacitance, and the switching frequency, which are essentially constant.
Based on (3.1) and (3.2), the currents of the SIMO and MISO SC converters can be
controlled by adjusting the input voltage, Vi, and load voltage, Vo, (or current),
respectively, as well as tuning the duty cycle, D, of the pulse-dropping modulated
signal of T1.
For the unity-mode SC converter, the charge is conserved, i.e., the amount of
charges extracted from the input source is the same of the amount outputted to the
load. In other words, the efficiency is determined by the voltage drop of the SC unit.
By comparing the input and output power, the power loss, PLi, and efficiency, ηi, for
the ith SC unit can be expressed as (3.6) and (3.7) respectively.
 I ch,i (Vi  VBi ) for SIMO configuration

PLi   (3.6)
 I dch,i (VBi  Vo ) for MISO configuration
56
VBi
V for SIMO configuration

i   i (3.7)
 Vo for MISO configuration
VBi
By substituting (3.1) and (3.2) into (3.6) and (3.7), the power losses and efficiencies
can also be expressed as follows.
 I ch ,i 2 RSC
  3I ch ,iVD for SIMO configuration
 Di
PLi   2
(3.8)
 I dch ,i RSC  3I V for MISO configuration
 D dch ,i D
 i
 DVi Bi
 D (V  3V )  I R for SIMO configuration
 i Bi
i  
D ch ,i SC
(3.9)
 Di (VBi  3VD )  I dch ,i RSC for MISO configuration
 DVi Bi
The overall efficiency, η, is simply represented by (3.10).
 n
  I ch ,ii
 i 1n for SIMO configuration

 
I ch ,i
i 1
  n (3.10)
 I
 i 1
dch ,i
 n I for MISO configuration

  dch ,i
 i 1 i
As suggested by (3.8), the power loss of the equalizer increases dramatically
with the charging or discharging current of the SC units; whereas the efficiency can
be affected by the cell voltage. In general, the proposed SC converter is more energy
efficient at a higher cell voltage. Therefore, for ESS with comparatively low cell
57
voltage, the idea of double-tier or multi-tier structures [20] could be adopted to
improve the balancing speed and conversion efficiency.
3.4. Circuit Alteration with Non-Isolated DC-DC Converter
For practical application of charge equalizer with SIMO or MISO DC-DC converters,
the input source or the load are usually implemented by the energy storage string itself.
Unlike the isolated topologies which provide galvanic isolation between the cells and
the input sources or loads; and other non-isolated topologies with large inductive
energy storage devices which allow a wide range of voltage conversion ratio, the SC
converters rely on the floating capacitors to transfer energy between low and high
electric potentials; and the voltage conversion ratio is fundamentally determined by
the circuit topology. A DC-DC converter with a particular voltage conversion ratio
and potential level can be implemented to adapt the SIMO and MISO SC converter to
string-to-cells, cells-to-string equalizers, or combine the SIMO and MISO SC
converters to form a cells-to-cells equalizer.
In the proposed multi-port SC converter, the no-load voltage conversion ratio is
unity if the voltage drop of the lossy components are neglected. Therefore, a DC-DC
converter with voltage conversion ratio of approximately 1/n or n is required to alter
the SIMO or MISO SC converter into string-to-cells or cells-to-string equalizer,
respectively. Taking the voltage drop of the diodes and the equivalent resistances of
the SC units into account, the voltage conversion ratio would be higher for the SIMO
SC converter, while that is lower for the MISO counterpart. Considering the biasing
direction of the diodes, the high-side bus of the input source for the SIMO SC
converter should be lower than that of the positive terminal of B1; while the potential
58
of the low-side loading bus for the MISO SC converter should be lower than that of
the negative terminal of B1.
Q1
Lb Lb
Q1
Vi Vo
(a) (b)
Q1 Lb
Vi Vo
(c)
Fig. 3.4. Circuit alteration of the multi-port SC converters; (a) string-to-cells
implementation with the SIMO configuration and a step-down buck-boost
converter; (b) cells-to-string implementation with the MISO configuration and a
step-up buck-boost converter; (c) cells-to-cells implementation with both SIMO
and MISO SC converters and a step-up boost converter.
59
Based on the aforementioned criteria, the interfacing DC-DC converter between
the SC converter and the energy storage string can be implemented by an inverting
buck-boost converter (Fig. 3.4a and 3.4b). Besides, cells-to-cells equalization can be
achieved by jointing the SIMO and MISO SC converters with a boost converter (Fig.
3.4c). With the boost converter, further design consideration should be taken for
implementing the cells-to-cells equalizer. Assuming that the boost converter operates
at continuous current mode, the current conversion ratio, CCRboost, could be
approximated by (3.11).
CCRboost  1  Dboost (3.11)
where Dboost is the duty cycle of the MOSFET in the boost converter; the current
conversion ratio for the unity-mode SC converter is one. Therefore, when the cells-
to-cells equalizer is operating, the total charging and discharging current of the cells
would follow (3.12).
n I ch ,i
I
i 1
dch ,i  i 1
1  Dboost
(3.12)
3.5. Simulation Study on the Multi-port SC Converters
To investigate the characteristics of the proposed multi-port SC converters, simulation
study on the models with different configurations and parameters listed in Table 3.1
was conducted. The switching frequency of the SC units was fixed at 30 kHz as the
damped resonant frequency calculated from the RLC parameters was approximately
32 kHz. According to (3.4), the equivalent resistance of an SC units would be 0.647 Ω.
This value is satisfactory compared to the conventional hard-switched SC equalizers.
However, the extra diode voltage drop reduced the conversion efficiency, which
60
would be more severe with low-voltage cells. By using the values listed in Table 3.1
the parametric analysis of the conversion efficiency at different cell voltages and
currents are plotted in Fig. 3.5. Referring to (3.9), the multi-port SC converter would
be more efficient with higher cell voltage. For the SIMO configuration, the conversion
efficiency would be about 70% at 1 A and 60% at 2 A for lithium cells with voltages
ranging between 3 V to 4 V. For the 6-cell modules rated at 22 V, the efficiency would
increase to >90%. Although the MISO configuration allows safer operation by
discharging specific cells to effectively prevent cell over-charging, this operation
would result in a reduced energy efficiency.
Table 3.1. Key parameters of the simulation model.
Parameters Values
Switching frequency, f 30 kHz
Diode forward voltage drop, VD 0.25 V
C 22 μF
L 1 μH
R0 0.1+ k×0.029 Ω
R1 0.109 Ω
1A
0.8
Energy efficiency
0.6
2A
0.4
0.2
SIMO
MISO
0
0 5 10 15 20 25
Module voltage, VB, [V]
Fig. 3.5. Efficiency of the SC converter model at different current and voltage.
61
SW
V B4
Voltage
V B3 Multi-port SC Source
CC-CV
Charger Converter
V B2
V B1
VB1, …, VB4 Gating Signals
Central
Control Unit
Fig. 3.6. Schematic of the setup for the multi-port SC balancing circuit.
The operation of the proposed multi-port SC converters was verified by
conducting the simulation study on the models (Fig. 3.6) with four series-connected
350 F electric double-layer capacitors (EDLCs) employed as the supercapacitor string.
The initial voltages of the EDLC cells, B1, B2, B3 and B4 were 2.0 V, 1.9 V, 1.5 V and
1.7 V, respectively. The SIMO configuration permits charging individual cells from
a voltage source. In the first simulation setting, the SIMO SC converter with the
aforementioned parameters, supplied by a voltage source, was implemented to charge
the EDLC string. The maximum operating voltage of a common EDLC cell is rated
at 2.7 V. The total forward voltage drop of the diodes in an SC unit in the simulation
model was 0.75 V. Adding a 50 mV safety margin to the charging voltage, a voltage
source of 3.4 V was used to charge the EDLC cells to the termination voltage of
2.65 V. The gating signals of all switches, T0 and T1 are enabled throughout the
charging period.
By substituting k=4, the average RSC of an SC unit was about 0.85 Ω according
to (3.4). Under open-loop control with the SIMO SC converter, the cell voltages were
62
equally charged to about 2.65 V by the same 3.4 V voltage source. The termination
voltage was determined by the source voltage and the diode voltage drop, whereas the
charging current was determined by the voltage difference between the EDLC cell
and the termination voltage as well as the equivalent resistance, RSC, of the SC unit.
Fig. 3.7 indicates that the balancing progress was 90% (i.e. the cell voltage difference
attained 10% of the initial value) at about 494 s.

VB [V]
B1 B2 B3 B4
Time [s]
Fig. 3.7. EDLC cell voltage, charged by the open-loop SIMO SC converter with
a 3.4 V voltage source.
vc [V]
ic [A]
Time [s]
Fig. 3.8. Zoomed waveforms of the switched-capacitor voltage and current at

about t=0.5s.
63
As shown in Fig. 3.8, the switched-capacitor voltage and current of the SC unit
connecting to B1 oscillated at the switching frequency of 30 kHz. The capacitor
voltage, vc, swung between 1.84 V and 3.19 V at about t=0.5s. Considering that the
maximum and minimum capacitor voltages were larger than Vi−2VD and lower than
VB1+VD, respectively, the SC unit was operated at underdamped condition. Besides,
the capacitor current waveform indicates that ZCS was attain with the parameters
listed in Table 3.1 and designed according to (3.3) and (3.5).
To increase the speed of equalizing charge of the series-connected cells, the
multi-port SC converter was cooperated with a BMS which controlled the charging
current of individual cell. In the second simulation setting, the gating signals of T1 in
the same SIMO SC converter model were controlled by a simple logic (3.13).
1 n
 for VBi  VBj and VBi  2.65V
1
 n j 1
Di   n
(3.13)
0 for V  1 V or V  2.65V
 Bi  Bj Bi
n j 1
The cell voltages were compared with the average voltage of the string with a
hysteresis band of 1 mV. Fig. 3.9a indicates that by allowing the closed-loop control
of the cell current, the duration of attaining 90% balancing progress was shortened to
about 128 s in the closed-loop setting. As indicated in (3.1), the charging current is
dependent on the source voltage, Vi. The charging and balancing speed dramatically
increased by increasing the input voltage to 5 V. As depicted in Fig 3.9b, the duration
of attaining 90% progress was about 44 s and the cell voltages settled at 2.65 V
quickly.
64
VB [V]
B1 B2 B3 B4
Time [s]
(a)
VB [V]
B1 B2 B3 B4
Time [s]
(b)
Fig. 3.9. EDLC cell voltage, charged by the closed-loop SIMO SC converter;
(a) with input source voltage of 3.4 V; (b) with input source voltage of 5 V.
The SIMO SC converter model was altered to a string-to-cell equalizer by
inserting a buck-boost stage with an inductor, Lb=220μH and switching frequency of
50 kHz. The EDLC string was charged by a constant-current-constant-voltage (CC-
CV) charger to compensate the conversion energy loss of the multi-port SC converter.
The CC and CV settings for the charger were 2 A and 10.6 V, respectively. The cell
voltages throughout the charging operation with 0.32 and 0.35 duty cycles for the
switch, Q1, are illustrated in Fig. 3.10.
65
VB [V]
B1 B2 B3 B4
Time [s]
(a)
VB [V]
B1 B2 B3 B4
Time [s]
(b)
Fig. 3.10. EDLC cell voltage, charged by the CC-CV charger with the string-to-
cell balancer altered from the SIMO SC converter; (a) with 0.32 duty cycle
for Q1; (b) with 0.35 duty cycle for Q1.
In the string-to-cell balancer, the input voltage for the SIMO SC converter was
controlled by the duty cycle of the buck-boost stage. Hence, the equalizing current
can be adjusted by varying the duty cycle of Q1. As shown in Fig. 3.10, with other
parameters remaining the same, the durations for attaining 90% of the balancing
progress with 0.32 and 0.35 duty cycles were 129 s and 94 s, respectively.
66
Lb
Q1
Vo
Fig. 3.11. Tapped inductor version for the buck-boost stage to achieve higher
voltage conversion ratio.
Furthermore, the operation of the cells-to-string and cells-to-cells
configurations was compared and investigated with the corresponding altered circuits.
For the cells-to-string equalizer altered from the MISO SC converter, a very high
voltage conversion ratio of the buck-boost stage was required. In this case, the
technique of tapped inductor [119] was required to increase the voltage gain. Fig. 3.11
illustrates the use of a tapped inductor in the altered MISO SC converter. In the
simulation model, the tap position was at the center of Lb. This resulted in a tap ratio
of 1:1 and inductance of about 60 μH in each side. The simulation results of the cells-
to-string equalizer with a tapped inductor is demonstrated in Fig 3.12a. For the cells-
to-cells balancer consisted of the MISO and SIMO SC converters jointed by a boost
converter with an inductor of 220 μH, the duty cycle of Q1 was set to 0.8 to achieve
90% balancing progress with a duration of approximately 109 s (Fig. 3.12b). If the
multi-port SC balancer is applied to battery system instead, it could be expected that
the auto-voltage-balancing would take a longer duration as the voltage sensitivity to
67
the SOC in battery cells is lower. With the feedback control, the dependency of
voltage sensitivity to balancing speed is lesser. The balancing duration would be
mainly determined by the required balancing capacity.

VB [V]
B1 B2 B3 B4
Time [s]
(a)
VB [V]
B1 B2 B3 B4
Time [s]
(b)
Fig. 3.12. EDLC cell voltage, charged by the CC-CV charger with the altered
multi-port SC converters; (a) cells-to-string balancer altered from the MISO SC
converter with tapped inductor; (b) the cells-to-cells balancer combining the
MISO and SIMO SC converters with a boost converter.
68
3.6. Experimental Verification
Table 3.2. Key parameters of the experimental setup.
Parameters Values
Type of cells 350 F EDLC
Number of cells, n 4
Switching frequency of the SC
30 kHz
converter, f
Switching frequency of the buck-boost
50 kHz
stage
Switches, T, Q TK30A06N1 60 V, 43 A, 12.2 mΩ
Diodes SBRT10U50SP5-13 50 V, 10 A
Switched-capacitors, C 22 μF aluminum polymer capacitors
Resonant inductors, L 1 μH SMD inductors
Power inductor, Lb 220 μH through-hole inductor
Filter capacitors 330 μF aluminum polymer capacitors
Buck-boost Stage
B1 B2 B3 B4
4
1
4-channel SIMO SC Converter
Fig. 3.13. Major components in the experiment setup; (1) string-to-cells SC

balancer prototype; (2) microcontroller and gating circuits; (3) LTC6803 based
cell monitoring unit; (4) series-connected EDLC cells with fused terminals.
Taking into the consideration of implementation cost and performance of different
equalization structures, the string-to-cells SC balancer would be more suitable for an
69
EDLC string of four series cells. The operation of the proposed string-to-cells SC
balancer was verified by the experimental measurement of a balancer prototype and
four series-connected EDLC cells. The key parameters are listed in Table 3.2; Fig.
3.13 shows the major components in the experimental setup.
Firstly, the EDLC was charged by an open-loop 4-channel SIMO SC converter
with a 3.4 V input source voltage. The switches, T0 and T1 were driven by a
complementary gating signal at a constant switching frequency of 30 kHz, the initial
voltages of the 350 F EDLC cells, B1, B2, B3 and B4 were set to approximately 2 V,
1.9 V, 1.5 V and 1.7 V respectively. The voltage across each EDLC cell was measured
by a data logger at the rate of 10 samples per second for each channel. The measured
cell voltages throughout the open-loop set-up are plotted in Fig. 3.14a. Similar to the
simulation results, auto-balancing was achieved by the multi-port SC converter with
simple complementary gating signals. In the experimental setup, the time to attain
90% of the balancing progress was around 300 s. To speed-up the balancing process,
the cell voltages were feed-back to the microcontroller by an LTC6803 based cell
monitoring unit, which simulated the presence of BMS; the gating signals of the
output channels of the SC converter were controlled by the discrete function indicated
in (3.13) at an updating rate of 5 Hz; the input source voltage was raised to 5 V. The
measured duration of 40 s for attaining 90% balancing progress indicates that the
equalizing speed was speeded up by more than seven times with the closed-loop
setting cooperating with a BMS.
70
VB [V]
B1 B2 B3 B4
Time [s]
(a)
VB [V]
B1 B2 B3 B4
Time [s]
(b)
Fig. 3.14. Measured EDLC cell voltage, charged by the SIMO SC converter;
(a) with an input voltage of 3.4 V; (b) with an input voltage of 5 V.
Similar to the simulated waveforms, the measured waveforms of the switched-
capacitor (Fig. 3.15) indicated that the SC converter operated at ZCS. With an input
voltage of 3.4 V and an output voltage of about 2 V, the capacitor voltage and current
swung between 1.9 V and 3.1 V and ±2.7 A, respectively. The damped resonant
frequency of the prototype with the same LC parameters was slightly higher than the
30 kHz switching frequency. This coincided with the estimated value of about 32 kHz.
When the input voltage was raised to 5 V, the output current of the SC converter
71
dramatically increased; which was reflected on the amplitude of the capacitor current.
When the input voltage was 3.4 V, the measured output current of the SC channel was
approximately 0.86 A; the current rose to about 3.08 A when the input voltage was
increased to 5 V. This observation fits to the equivalent model in (3.1) by substituting
RSC=0.72Ω and diode forward voltage drop VD=0.26V.
VGS,T0 [10V/div]
vc [2V/div]
ic [5A/div]
Time base: 20μs/div
(a)
VGS,T0 [10V/div]
vc [4V/div]
ic [10A/div]
(b)
Fig. 3.15. Measured voltage and current waveforms of the switch-capacitor and
the gate-source voltage of T0; (a) with an input voltage of 3.4 V; (b) with an input
voltage of 5 V.
Also, the string-to-cells operating was implemented by an additional buck-boost
stage. The EDLC string was charged by a CC-CV power source with voltage and
current settings of 10.6 V and 2 A, respectively. By setting the duty cycle of Q1 to
72
0.35, the output voltage of the buck-boost with 10.6 V input voltage was around 5 V
at the continuous current mode. The voltage and current waveforms of the power
inductor, Lb, in the buck-boost stage during output current of roughly 3.5 A are
illustrated in Fig. 3.16.
VGS,Q1 [10V/div]
vLb [10V/div]
iLb [1A/div]
Fig. 3.16. Voltage and current waveform of the power inductor, Lb.
With the experimental parameters, the current ripple magnitude of the inductor
was below 10%. The cell voltages throughout the charging process were recorded. As
depicted in Fig. 3.17, the cell voltages reached 90% balancing progress at about 55 s
and finally settled at around 2.6 V. As the equalization speed was dependent on the
input voltage of SIMO SC converter, the output voltage of the buck-boost stage varied
from 3.5 V to 5 V during the charging process considering that the initial string
voltage was about 7.5 V in this setting. As a result, the string-to-cells setting required
a slightly longer equalization time compared to the set-up with the 5 V constant
voltage source demonstrated in Fig. 3.14b.
73
VB [V]
B1 B2 B3 B4
Time [s]
Fig. 3.17. Measured EDLC cell voltage, charged by the CC-CV charger with the
string-to-cells balancer prototype.
Both the simulation and experimental results showed that the balancing speed
of the multi-port SC converter could be dramatically increased with the presence of a
BMS which sensed the cell parameters and controlled the SC current accordingly. The
behavior of the SC converter could be accurately described by the equivalent
resistance. ZCS operation can be achieved by selecting the circuit parameters
following (3.3) and (3.5). With an additional step-up or step-down DC-DC converter,
the external voltage source could be eliminated by implementing the controllable
voltage source with the storage string.
3.7. Summary
This chapter presents a series of alternative implementations of multi-port ZCS SC
converters which allow an adjustable current for battery or supercapacitor
management applications. In addition to the auto-voltage-balancing feature offered by
the SC technique, the balancing speed can be dramatically increased by the closed-
loop control cooperating with a BMS and an adjustable voltage source. The SIMO SC
74
converter allows separated control of the current charging to the cells whereas the
MISO SC converter permits separated control of the current discharging from the cells.
In the experimental set-up, the balancing speed with the closed-loop setting with 5 V
input voltage source was more than 7 times faster than the auto-balancing counterpart
with 3.4 V voltage source. Furthermore, the configurations of string-to-cells, cells-to-
string, as well as cells-to-cells equalizers are proposed by adding a buck-boost
converter or boost converter stage. Similar to the conventional SC converters, the cell
charging or discharging current is determined by the SC equivalent resistance and the
voltage differences between the cells and voltage source. The equalizing speed can be
increased by raising the source voltage for the SIMO SC converter and vice versa for
the MISO SC converter. However, increasing the balancing current by raising the
voltage difference implies sacrifice of energy efficiency. Taking the forward voltage
drop of the diodes into account, the proposed multi-port SC converter would be more
efficient with energy storage modules or ESS with higher cell voltage.
Research on the topics of SC DC-DC converters provides the theoretic
foundation of SC power conversion. Attractive features of the modular approach of
SC units are also identified through the investigation on the systems of parallel-mode
or multi-port SC converters. Besides, dynamic reconfiguration of SC units with
centralized coordination enables the feasibility of developing SC multilevel inverters
from specified arrangement of SC units and modulation strategy of switches. In the
following chapters, analysis and design of SC based MLIs are discussed.
75
Chapter 4 Hybrid SCMLI
Chapter 4
Hybrid SC MLI Employing Series-connected Sources
Compared to typical two-level inverters, multilevel inverters (MLIs) offer numerous
advantages such as reducing component stresses, improving output power quality and
cutting down the filter size. With the series-parallel conversion technique, the SC
technology enables a novel approach for the implementation of MLIs. This chapter
presents a general structure of hybrid MLI topologies combining the SC technology
and bidirectional switched converter. Instead of connecting the SC units to
independent voltage sources, the SC units in the proposed MLI are charged from the
entire series-connected voltage source string so that the output voltage magnitude is
effectively boosted. The output power quality is enhanced by the combination of SC
units with a bidirectional switches based multilevel converter which generates the
intermediate output voltage levels from the series-connected sources. Because of the
substantial increase in the number of output levels, the staircase modulation with
nearest-switching technique at the fundamental frequency can be employed to
generate the approximated sinusoidal waveform with multiple output voltage levels.
The generalized topology is capable of arbitrary numbers of voltage sources and
SC units for providing different sets of maximum numbers of output levels and
76
voltage step-up ratios. Furthermore, the numbers of output levels and the step-up ratio
are substantially increased by introducing the asymmetric-mode operation of SC units
with an additional diode between adjunct SC cells. Similar to the existing SC inverters,
the inherent voltage drop across the switched-capacitors would cause ripple loss that
limits the output power level. Therefore, the analysis of SC voltage ripples would be
a major consideration in capacitor sizing and selection of the appropriate operating
frequency and switching scheme.
4.1. Review on the Traditional MLI and SCMLI Topologies
DC-AC inverters are the key components in grid-connected renewable energy (RE)
generation, vehicle electrification, energy storage, and high-frequency AC (HFAC)
distribution systems. Multilevel inverters offer many advantages including reduced
voltage, current and dv/dt stresses of components and better sinusoidal approximation
with staircase switching waveform which improves output power quality with reduced
filter size [55, 75, 76, 120, 121]. These features have attracted extensive research on
the subjects of MLI topology development, control strategy and applications [54, 55,
74, 75, 77, 122-139].
Conventional MLI topologies such as the cascaded H-bridge inverter (CHBI)
[75] and diode-clamped MLI [122] are sophisticated and promising technologies in
medium-to-high voltage and high-power applications. However, there are numerous
challenges to directly adopt these MLI topologies in emerging distributed RE and
vehicle applications: CHBIs require isolated DC voltage sources for real-power
applications, which results in bulky design and complicated system; the versions of
higher than three or five levels diode-clamped MLI are less attractive due to the
77
capacitor voltage imbalance issue along with the dramatic increase in component
count and control complexity [54, 55, 75, 122]. At the same time, researchers have
developed numerous innovative inverter topologies with different techniques. For
instance, the modular multilevel converter (MMC) [70-73] enables high-voltage DC
applications with the modular and multilevel structure which eliminates the
drawbacks of the diode-clamped and CHBI counterparts; Geglia et al. [140] and
Jamaludin et al. [141] developed MLI topologies which employ bidirectional switches
to increase the number of output voltage levels with fewer active components.
In recent years, the switched-capacitor (SC) based MLIs [52, 53, 56-62, 142]
have become a popular solution for smaller scale applications like HFAC power
systems in vehicles and microgrids. The increase in line frequency substantially
reduces the transformer and filter sizes in HFAC power distribution system. Along
with the promoting of vehicular electrification and microgrid concepts, there is
increasing research on the topic of HFAC systems in the ranges of hundreds to kilo-
hertz for vehicles [143, 144] and buildings [145, 146]. Although the current handling
capacity in SC converters is limited by the capacitor size, the substantial increase in
the fundamental frequency and the reduced system scale promotes the practicality of
SC inverters in HFAC systems. The features of self-balancing in capacitor voltage [61]
and voltage step-up capability [53, 57, 61, 62] of particular SCMLI topologies with
series-parallel SC cells have drawn great attention in recent literature. These step-up
inverter topologies eliminate the need of bulky step-up transformers or boost DC-DC
converter stages in systems with low source voltage. Moreover, feasibility of having
asymmetric SC voltages [62] enables a higher number of output voltage levels and
78
conversion ratios. The basic working principles of the existing SCMLI topologies
include utilization of SC units to copy the voltage from DC sources [53, 60-62],
cascade combination of multiple SC converters [58, 62] or voltage sources [59, 142],
and dividing a high voltage DC source into several floating components [147-149].
Compared to isolated DC sources, there is higher availability of the voltage
sources with common-ground or series configuration, for example, battery strings in
ESSs or non-isolated multi-output power converters [150-152]; also, it can be
constituted by isolated sources. Besides, the configuration of series-connected voltage
sources offers many benefits such as easy-to-manage and capability of auxiliary DC
loads sharing the same supply. The increasing penetration of distributed RE
generation and ESSs motivates the development of series-connected sources based
step-up inverters.
4.2. Working Principle of the Hybrid SC MLI Topology
4.2.1. Topology Description
The topology of the proposed hybrid SCMLI is shown in Fig. 4.1. The SCMLI
consists of three parts – 1) a bidirectional switched multilevel converter; 2) series-
parallel SC units; and 3) an H-bridge inverter. The series-parallel operation of the SC
cells is illustrated in Fig. 4.2. The voltage of the kth switched-capacitor, Ck, is refreshed
by conducting Tk1 and Tk3 in the series-parallel units; the capacitor is stacked with
other SC cells in series through Tk2 to step the output voltage up. The intermediate
voltage levels are provided by the bidirectional switches S, which are directly
connected to the terminals of voltage sources and the output DC bus. In the proposed
79
topology, an H-bridge inverter is employed to convert the DC bus voltage into bipolar
output voltage and provide the zero voltage level by controlling the active switches,
Q1 to Q4, accordingly. Since the series-parallel operation repeats and refresh the SC
voltage in every cycle, self-balancing of the capacitor voltage is achieved.
Sn
VSn
Sn-1
VSn-1
T13
S2
VS2
T23 T12
S1 Vs
VS1
T22
C1 Vsc1
T11 Q1 Q3
Tm3 k=1
C2 Vsc2 Vdc Load
T21
Tm2 k=2 Vo
Q2 Q4
Cm Vscm
Tm1
k=m Bidirectional
Series-parallel SC Units Switched Converter H-bridge Inverter
Fig. 4.1. General structure of the proposed hybrid SCMLI topology.
80
(a)
(b)
(c)
Fig. 4.2. Series-parallel conversion; (a) parallel operation for symmetric SC
voltage; (b) parallel operation for asymmetric SC voltage; (c) series operation for
voltage step-up.
81
4.2.2. Symmetric (Equal Voltage) Series-parallel SC Configuration
Corresponding to the charging voltage of the SC units, the configuration of the
proposed SCMLI can be divided between symmetric (equal SC voltage) and
asymmetric (unequal SC voltages) modes of operation. Assuming that the capacitor
sizes are large enough so that the voltage drop are negligible, in the symmetric voltage
configuration, each of the SC units are equally charged to the sum of the voltage
V  
n
source string (i.e. S i 1
VSi ) during parallel operation. Therefore, for the
SCMLI containing n voltage sources and m SC units, the maximum attainable output
voltage would be m times the maximum capacitor charging voltage plus the voltage
sum of the source string (i.e. 2n(m+1)∑VS); the total number of output levels is
2n(m+1)+1.
4.2.3. Asymmetric (Unequal Voltage) Series-parallel SC Configuration
D2 D1 Sn
VSn
Sn-1
VSn-1
T13
S2
VS2
T23 T12
S1
VS1
T22
C1
T11
C2
T21
Fig. 4.3. Enable asymmetric SC voltage by inserting diodes between

SC units.
82
As illustrated in Fig. 4.3, the switched-capacitors can be charged to unequal voltage
levels to provide asymmetric boost voltage to the output by inserting a diode between
the adjacent SC cells. Unlike the symmetric mode, the switched-capacitors are
charged to the summation of the voltage source string and the subordinate SC cells.
Therefore, the maximum charging voltage of the kth SC unit, V(ch)k, under asymmetric
operation would be 2k−1∑VS instead of ∑VS. Due to the substantially increased SC
voltages, the asymmetric mode operation effectively boosts the voltage step-up
capability, along with the increased number of output levels. For the asymmetric mode
SCMLI consisting of a string of n series-connected DC sources and m asymmetric SC
units, the maximum attainable output voltage and the corresponding number of output
levels are 2m∑VS and 2m+1n+1, respectively.
4.2.4. Modulation Technique for the Staircase Output Voltage
A high number of output levels substantially improves the output power quality with
staircase modulation at the fundamental output frequency. By eliminating the need of
high frequency carrier signals, compared to the carrier based pulse-width modulation
(PWM) techniques like sinusoidal PWM or space-vector modulation, staircase
modulation techniques exhibit the advantages of reduced switching loss and improved
EMI performance. The computational-based staircase modulation techniques can be
categorized into frequency domain approaches, such as optimal weighted-THD [153],
selective harmonic elimination (SHE) [154] techniques and time domain approaches
including nearest switching [155] and v-t equaling [156] methods. The former
approaches demand more processing power and the solutions are usually computed
offline [157, 158]. In addition to the dramatic increase in the required memory and
83
computational cost due to the high number of output voltage levels, the voltage
variation in SCMLI introduces challenge in adopting offline frequency domain
approaches. As a result, the nearest switching scheme demanding less computational
burden becomes the most preferred technique for computing the firing angles for the
proposed MLI.
Vo
VM Symmetric Asymmetric
Vp
 cj :  j n 1 2 j1 n 1
...
...
Vbm+Vs1
j
Vcj  2 j 1 Vs
...
...
Vb2+Vs1 Vbj : V
i 1
ci  j Vs
...
...
m m
Vb1+Vs1 Vp : V  V  V (m  1) V  V  2m Vs
VS
s ci s s ci
i 1 i 1
...
...
Vs1+Vs2
Vs1
θ1 θn θ2n θcm θp π/2 π−θp ... π−θ1 3π/2 ωt
θ2 θc1 θc2 π
...
...
...
...
Staircase Voltage
...
...
...
...
Modulation Voltage
Fig. 4.4. Staircase voltage waveform; and the expressions of firing angles θcj, for
jth capacitor and the corresponding output voltage levels, Vbj; and peak output
voltage, Vp, for symmetric and asymmetric configurations.
For an MLI generating staircase output from constant DC sources, the
fundamental amplitude of the output, V1, and the mean-square error, ems, between the
staircase waveform and the reference sine signal of the synthesized 2p+1 levels
staircase waveform (Fig. 4.4) can be expressed as (4.1) and (4.2) respectively.
p
4
V1 
 V
i 1
Si cos i (4.1)

2  1 
ems    VM sin   d   VM sin   Vs1  d   2 VM sin   Vp  d 
2 2 2 2
(4.2)
 0 1  p

84
ems
Minimum mean-square error can be attained by putting  0 for i=1, 2,…,p. The
i
solution is found to be (4.3), which gives the nearest approximation of the modulating
voltage in time domain.

i
V  0.5Vsi
j 1 sj
sin i  (4.3)
VM
The studies by Liu et al. [159, 160] testified that this nearest switching scheme
is also a solution of attaining minimum voltage THD under both constant and varying
DC sources. Furthermore, the error of the fundamental voltage amplitude can be
eliminated by real-time iteration [159, 160] or curve fitting techniques [161]. This
feature is especially useful when real-time response to the varying capacitor voltage
is required. As depicted in Fig. 4.4, θc1 and θc2 are equal to θn+1 and θ2n+1, accordingly.
Given that VCj=∑VS for j=1, 2,…,m, the expressions for the capacitor firing angles,
θcj, the boosting voltage at θcj, Vbj, and the maximum voltage, Vp, for the symmetric
and asymmetric configurations can be derived based on the DC source voltage, VS,
numbers of sources, n, and SC cells, m. To synthesize the desired staircase voltage
waveform across the output terminals, the bidirectional switched converter (BSC), the
SC units, as well as the H-bridge inverter (HBI) are operating at different frequencies.
The states of active switches at different output voltage levels are listed in Tables 4.1
and 4.2 which enumerate the states for the symmetric SC voltage and asymmetric SC
voltage modes, respectively. In the switching tables, the symbol ‘S’ denotes series
operation while ‘P’ denotes parallel operation of the MOSFETs, T1x to Tmx, of the SC
units.
85
Table 4.1. Switching states of the symmetric SC voltage based inverter at

different output voltage levels.
Firing Switching states
Output Level
Angle Q1, …, Q4 S1, …, Sn T1x, …, Tmx
(m  1)Vs  n ( m1) 1 0 0 1 0 … 0 1 S … S S
 Vsi  mVs
n 1
 n ( m 1) 1 1 0 0 1 0 … 1 0 S … S S
i 1
… … 1 0 0 1 0 … 0 0 S … S S
Vs1  mVs  nm 1 1 0 0 1 1 0 … 0 S … S S
mVs  nm 1 0 0 1 0 … 0 1 S … S P
 Vsi  (m  1)Vs
n 1
 nm 1 1 0 0 1 0 … 1 0 S … S P
i 1
… … 1 0 0 1 … … … … S … … …
V s .. 1 0 0 1 0 … 0 1 P … P P
… … 1 0 0 1 0 … … 0 P … P P
Vs1 1 1 0 0 1 1 0 … 0 P … P P
1 0 1 0 1 0 … 0 P … P P
0 0
0 1 0 1 1 0 … 0 P … P P
Vs1   1 0 1 1 0 1 0 … 0 P … P P
… … 0 1 1 0 … … … … … … … …
(m  1)Vs   n ( m 1) 0 1 1 0 0 … 0 1 S … S S
Table 4.2. Switching states of the asymmetric SC voltage based inverter.

Switching states
Output Level Firing Angle
Q1, …, Q4 S1, …, Sn T1x, …, Tmx
2 Vm
s
2 m
n 1 0 0 1 0 … 0 1 S … S S
2 m
V  V s sn
2 m
n 1 1 0 0 1 0 … 1 0 S … S S
… … 1 0 0 1 0 … 0 0 S … S S
(2  1)Vs
m
(2 m
1) n 1 0 0 1 0 … 0 1 P S … S
… … 1 0 0 1 … … … … … … … S
2 m 1
V s
 2m1 n 1 0 0 1 0 … 0 1 S … S P
… … 1 0 0 1 … … … … … … … P
2Vs  2n 1 0 0 1 0 … 0 1 S P … P
… … 1 0 0 1 … … … … … P … P
Vs1 1 1 0 0 1 1 0 … 0 P … P P
1 0 1 0 1 0 … 0 P … P P
0 0
0 1 0 1 1 0 … 0 P … P P
Vs1   1 0 1 1 0 1 0 … 0 P … P P
… … 0 1 1 0 … … … … … … … …
2 m
V s
  2m n 0 1 1 0 0 … 0 1 S … S S
86
Vo
Vdc
Vs
Vsc1
Vsc2
Vsc3
Time (s)
(a)
Vo
Vdc
Vs
Vsc1
Vsc2
Vsc3
Time (s)
(b)
Fig. 4.5. Synthesis of staircase output voltage waveform from voltage
components Vs and Vsc; (a) symmetric SC voltage; (b) asymmetric SC voltage.
87
Table 4.3. Summary of the proposed SCMLI operation for staircase voltage
output.
Pattern repetition count in
Number
Mode of a cycle
operation DC SC Output jth SC
HBI BSC*
sources units levels unit
Symmetric 2n(m+1)+1 1 2 4(m+1)
n m
Asymmetric 2m+1n+1 1 2m−j+2−2 2m+2
*the pattern count for the highest and lowest voltage levels in BSC are 4m+2 for
symmetric mode and 2m+2−2 for asymmetric mode, respectively
The synthesis of voltage waveforms by the symmetric and asymmetric modes
SCMLIs with VS=10V, n=3 and m=3 are illustrated in Fig. 4.5a and Fig. 4.5b,
respectively. Table 4.3 summarizes the repetition counts of the SCMLI components
when the proposed staircase modulation is employed in conjunction with the
corresponding DC sources and SC cells numbers.
4.2.5. Reduction on Active Components for High Power Factor Applications
Sn
VSn
Sn-1D0(n-1)
VSn-1
T13
S2 D02
VS2
T23 T12 D01
VS1
T22
C1
D11
Tm3 Q1 Q3
C2 Load
D21
Tm2
Vo
Q2 Q4
Cm Dm1
Fig. 4.6. Substituting active switches with diodes for high power factor loads.
88
The hybrid SCMLI circuit depicted in Fig. 4.1 allows any phase angle between the
output voltage and current. This enables bidirectional power applications such as
motor drives with regenerative braking and grid-tied energy storage systems.
However, this feature may not be necessary in some other usages like driving high
power factor loads or grid-tied inverters generating only real power in RE farms. In
view of these applications, it is possible to make a trade-off between the capability of
driving inductive load and circuit simplicity by substituting some of the active
switches with diodes. Fig. 4.6 shows a variation which permits an apparent power
phase angle of φ<θ1.
The charging switches of the SC units, Tk1 can be replaced with diodes, while a
bidirectional switch Sk can be substituted with a unidirectional switch, which is
constituted by a MOSFET and a diode. Taking into consideration that if the
MOSFETs in Sk are replaced by diodes, the current should be commutated by the
diodes (D0k) when driving inductive load. Instead of dead-time, overlapping time
between the gating signals of Sk should be provided to assure continuous output
waveform. The idea of replacing active switches with diodes can simplify the control
and gate driving circuits. This makes the design more cost effective for high power
factor applications.
4.3. Capacitor Voltage Ripples & Loss Analysis
Although the series-parallel operation refreshes the SC voltages in every positive and
negative cycles, discharge during series operation of the SC cells results in voltage
drop of the capacitor. This not only distorts the inverter voltage output but also causes
additional power loss. Therefore, the voltage ripples of the capacitors are the key
89
criteria for capacitor sizing and estimating the power rating of the inverter at the
desired operating frequency.
4.3.1. Voltage Ripples of the SC Cells
Since the SC charging path impedance during parallel operation is dominated by the
ESR of the capacitors in the hard-switched SCMLI, the SC units are charged in an
overdamped condition [26]. Hence, the maximum attainable charging voltage for the
jth switched-capacitor is restricted to (m+1)∑VS for symmetric operation and 2m∑VS
for asymmetric operation. In steady-state, the capacitor voltages reach equilibrium
and the net charge received by each of the capacitors in a cycle is zero. Hence, the
capacitor voltage ripple, ∆Vcj, can be derived from the voltage drop throughout the
discharge operation:
Qdch
Vcj  (4.4)
Cj
where Qdch is the amount of discharge during series operation and Cj is the capacitance
of the jth capacitor. For the proposed inverter, the discharging current magnitudes of
the series SC cells are equal to the magnitude of output current. Therefore, Qdch can
be approximated by the output current and the conduction angles of the capacitors:
I o1 ( off ) cj
Vcj 
C j  ( on ) cj
sin( t   )d t (4.5)
where Io1 is the fundamental amplitude of the output current, φ, θ(on)cj and θ(off)cj are
the angle between output voltage and current, the firing angle of Tj2 for series-
connecting Cj, and the firing angle of Tj1 and Tj2 for parallel operation of Cj,
respectively; ω=2𝜋f is the fundamental angular frequency of the output voltage.
90
A. Symmetric SC Voltage Configuration
For the symmetric configuration, the capacitor voltage ripple frequency is double of
the fundamental output voltage frequency. Besides, the associated switching angles,
θ(on)cj and θ(off)cj are θcj and π-θc(m-j+1), respectively. By substituting the corresponding
switching angles in to (4.5), the voltage ripple magnitude of the symmetric SC cells
can be expressed as (4.6).
I o1  c(m  j 1) I o1  (m  j 1)n 1

Vcj 
C j  cj
sin( t   )d t 
C j  jn1
sin( t   )d t
(4.6)
I o1 (cos( jn 1   )  cos( (m  j 1)n 1   ))

C j
B. Asymmetric SC Voltage Configuration
For the asymmetric configuration, additional series and parallel operations of the SC
units are necessary for offering extra output levels. As a result, the voltage ripples of
the asymmetric SC cells consist of two parts: 1) discharge to the load through the BSC
and HBI, and 2) discharge to the higher order SC cells. As indicated in Table 4.3, the
subordinate SC units have higher repetition counts which lead to higher ripple
frequencies. Owing to the symmetrical geometry of sine function, the switching
patterns produced by the staircase modulation would be symmetrical along π/2. In
every output cycle, there are 2m−j+2−2 voltage ripples across the jth capacitor. The
voltage drop for the 1st to (m−1)th SC cells caused by the output current before π/2,
can be expressed as (4.7).
91
I o1 c(j 1)i I o1 
Vcji   sin( t   )d t   sin( t   )d t
2 j in1
C j cji C j 2 j 1( 2 i 1)n1
(4.7)
I o1 (cos( 2 j1 (2i 1)n 1   )  cos( 2 j in 1   ))

C j
for j=1,2,…,m−1 and i=1,2,…,2m−j−1
while the capacitor voltage ripples crossing π/2 can be expressed as follows.
I o1  
 sin( t   )d t
( 2m 2 j 1 )n1
Vcj p 
C j ( 2m 2 j 1 )n1
for j=1,2,…,m (4.8)

2 I o1 cos  (2m  2 j1 )n 1 cos 

C j
On the other hand, the magnitudes of the voltage ripples caused by the charging
operation of higher order SC cells, Ck, are
Ck Vck
Vcj  (4.9)
Cj
where ∆Vck is the voltage rise of the higher order SC cell during parallel operation.
4.3.2. Power Loss Analysis
A. Charge-up Power Loss Due to SC Voltage Ripple
During parallel operation, the SC cells in the proposed hard-switched SCMLI are
charged with overdamped RLC parameters. The voltage gap [26, 42, 162] between
the charging voltage and the capacitor voltages causes irrecoverable charge-up power
loss, which is dissipated as a combination of switching and conduction losses. The
charge-up energy loss of the capacitor expressed in (4.10) is determined by the voltage
drop and the magnitude of the voltage ripple.
92
Ck (Vck ,min Vck )

Eloss (ch)  Ech  Edch  Ck VckVchk   Vck dQ (4.10)
CkVck ,min
where Eloss(ch), Ech, and Edch denote the energy loss, charging and discharging energy,
respectively; Vchk is the maximum charging voltage, and Vck,min is the terminating
discharging voltage of capacitor Ck. The charging current of the SC cell decays
exponentially. At equilibrium, the charge-up voltage ripple is equal to the discharging
voltage ripple, i.e.
Tch ,k

Vck  (Vchk  Vck ,min )(1  e
Rch ,k Ck
) (4.11)
where Tch,k is the charging duration and Rch,k is the total series resistance of the
charging path for capacitor Ck. The charge-up energy loss can be expressed as (4.12).
Tch ,k

Ck Vck (1  e
2 Rch ,k Ck
)
Eloss (ch)  Tch ,k
(4.12)

2(1  e
Rch ,k Ck
)
For the symmetric SCMLI, each of the SC cells performs a series-parallel
operation in every positive and negative cycles of the fundamental output voltage.
Therefore, the total ripple power loss, Ploss(ch), would become (4.13).
m
Ploss (ch)   C j f Vcj 2 coth  j (4.13)
j 1
ρj=Tch,j/2Rch,jCj is charging duration factor of the jth SC cell. When the capacitor
charging duration is considerably larger than the RC time constant (i.e. ρ>>1),
cothρ≈1, the capacitors discharge from approximately Vch. As a result, Ploss(ch) can be
simplified as the following function.
93
m
I o12
Ploss ( ch )   C j f Vcj 2  (4.14)
j 1 Cf
On the contrary, when the capacitor charging duration is considerably shorter than the
RC time constant (i.e. 1/ρ>>1). This gives cothρ≈1/ρ; the capacitor voltages tend to
static values. As a result, Ploss(ch) would be determined by the output current,
equivalent resistance as well as the duration of charging operation, i.e.
m C j f Vcj 2 Tf
Ploss ( ch )    I o12 Rch  (4.15)
j 1 j Tch
where Tf/Tch is the ratio between the fundamental output period and the SC charging
duration.
For the case of asymmetric configuration, the higher order SC cells are
indirectly charged from the constant voltage sources through the subordinate SC cells.
The capacitors generally cannot attain Vch under loading condition. Therefore, instead
of discharging from Vch to Vch−∆VCi, the capacitors would discharge from
VC,mini+∆VC,mini to VC,mini. As a result, the energy loss caused by the ith ripple of the kth
capacitor, Elosski, and the corresponding charge-up power loss, Ploss(ch), become
functions (4.16) and (4.17), respectively.
Vcki
Eloss (ch)ki  Ck Vcki (Vchk  Vc ,mini  ) (4.16)
2
m 2m j 1 1
Ploss ( ch )    C j f Vcji 2 coth  ji (4.17)
j 1 i 1
94
By combining (4.6) to (4.8) and (4.13), (4.17), the charge-up power loss is determined
by the voltage drop of the capacitors, which is dependent on the output current io,
capacitance Ci, and the operation frequency, f.
B. Conduction Power Loss
kRC mRT(on)
RS(on) 2RQ(on)
k×SCs
Load
2RQ(on) io
Load
j×Vs io
(a) (b)
Fig. 4.7. Equivalent circuits of the SCMLI; (a) during zero output voltage;
(b) during non-zero output voltage.
The conduction power loss due the parasitic resistances of components, including the
on-state resistance of MOSFETs and ESR of capacitors, can be derived based on the
equivalent circuits of the proposed SCMLI during different output states (Fig. 4.7).
During zero output voltage, the bidirectional switched converter and the SC units are
bypassed so that only two switches (i.e. Q1 and Q3, or Q2 and Q4) in the H-bridge are
conducting. For the remaining duration, the output current from the voltage sources
passes through a switch, Sj, in the bidirectional converter, k capacitors and m switches
in the SC units as well as two switches in the H-bridge inverter. Since the conduction
loss for the SC cells during parallel operation is covered by the charge-up power loss,
the output current, io, in this analysis is dissociated from the capacitor charging current.
95
Considering the conduction angles of each of the inverter components, the output
conduction loss, Ploss(con), of the inverter can be calculated by the following:
m
Ploss ( con )  2 I o,rms 2 RQ ( on )  I o ( S ),rms 2 ( RS ( on )  mRT ( on ) )  RC  I o ( Cj ),rms 2 (4.18)
j 1
1 

where I o,rms 2  io 2 dt (4.19)
0
1  1
 
I o ( S ),rms 2  io 2 dt (4.20)
1
1  (m  j 1)n 1
 
I o (Cj ),rms 2  io 2 dt (4.21)
jn1
for symmetric mode operation, and
1    m j1 
m j
2 1    j 1
   ( 2 2 )n1 io 2 dt    2 in1 io 2 dt   2 ( 2 i1)n1 io 2 dt  (4.22)
2 j
I o (Cj ),rms
  ( 2m 2 j1 )n1 i 1
 j 1
2 ( 2 i 1)n1
  j
2 in1

for asymmetric mode operation; RQ(on), RS(on), RT(on) are the respective on-state
resistance of the MOSFETs denoted by Q, S and T; RC is the ESR of the capacitors C;
Io,rms is the RMS value of the output current; Io(S),rms is the output current passing
through switches S and T with conduction angle θ1; and Io(Cj),rms is the output current
passing through each of the capacitor, Cj.
C. Switching Power Loss
During the ON and OFF transitions of the switches, the overlapping of the switch
voltage, vsw, and current, isw, causes undesired energy dissipation. The amount of the
dissipated energy, Eloss(sw), throughout the switching duration, Tsw, can be estimated
by v-i integral:
96
Tsw
Eloss ( sw)   vswisw dt (4.23)
0
which can be approximated by linear voltage and current waveforms [163] and
calculated as follows.
  t    t 
vsw (t )  Vsw 1    vsw (t )  Vsw  
  Tsw    Tsw 
on :  off :  (4.24)
 i (t )  I  t  i (t )  I 1  t 
 sw sw    sw sw  
  Tsw    Tsw 
Tsw  t  t  V I T
Eloss ( sw)   Vsw I sw   1  dt  sw sw sw (4.25)
 Tsw  Tsw  6
0
where Vsw and Isw are the maximum voltage and current during the switching operation,
which depend on the voltage and current values before or after the switching
transitions.
The switching loss, Ploss(sw), of the proposed SCMLI can be estimated by the
switching frequencies, the numbers of firing angles as well as the associated
instantaneous voltage and current stresses of the switches. Given that the switching
pattern of the staircase modulation repeats every positive and negative cycles, Ploss(sw)
can be represented as (4.26).
Ploss ( sw)  2 f  E loss ( sw,Q )   Eloss ( sw,S)   Eloss ( sw,T)  (4.26)
where ∑Eloss(sw,Q), ∑Eloss(sw,S) and ∑Eloss(sw,T) are the energy loss in a half cycle which
can be expressed as the following:
Tsw,QVs1I o1  sin(1   )  sin(  1   ) 

E loss ( sw,Q ) 
3
(4.27)
97
 k 
T I n    sin( jn i   )  sin(   jn i   )  
E  sw, S o1  Vsi  k 
j 0
(4.28)
3 i 2  
loss ( sw,S)
    sin( jn 1   )  sin(   jn 1   )  

 j 1 
where k=m for symmetric mode and k=2m−1 for asymmetric mode, respectively;
followed by:
Tsw,T I o1 Vs
 sin(   )  sin(   jn1   ) 
m
 Eloss ( sw,T)  3 j 1
j n 1 (4.29)
for symmetric configuration; and
Tsw,T I o1 Vs m 2m j 1 1
E loss ( sw,T) 
3

j 1 i 1
 
2 j 1 sin( 2 j1 in1   )  sin(   2 j1 in1   ) (4.30)
for asymmetric configuration.
Referring to (4.26)-(4.30), with regardless of the operation mode, the switching
loss of the SCMLI employing staircase modulation would be directly proportional to
the operating frequency, switching durations, as well as the magnitudes of the output
current and source voltage.
4.4. Simulation and Experimental Verification
In order to verify the operation of the proposed SCMLI topology, simulation and
experiment on a 19-level MLI with the symmetric configuration and a 25-level MLI
with the asymmetric configuration were conducted. As shown in Fig. 4.8, the
simulation model and prototype of the SCMLI consisted of three series-connected DC
voltage sources of 24 V and two SC units. The inverter was defined to be capable of
98
driving inductive load with phase lag angle of φ<θ2: a hybrid setting that the switch,
T11, was replaced with a diode, D11; the bidirectional switch, S2, was substituted by an
anti-series MOSFET-diode pair. The AC output of the inverter was not galvanically
isolated from the DC power supplies. If the proposed SCMLI is employed to grid-
connected system only the AC output terminals can be the common electrical
connection between the grid and the inverter. Galvanic isolation is necessary for other
electrical connections from the inverter circuit to the grid.
19-level 25-level
D1
S3
VS3
T13 S2 D02
VS2
T23 T12
VS1 S1 Q1 Q3
VC1
T22 C1 Io
D11 Load
VC2
Vo
C2 T21 Q2 Q4
Fig. 4.8. Circuit configuration of the SCMLI prototype and simulation model.
The specification and component values of the SCMLI prototype are listed in
Table 4.4; the experimental setup for the hybrid SCMLI is depicted in Fig. 4.9.
Capacitance of 1000 μF was selected to achieve a maximum voltage ripple of 2.5% at
400 Hz operation. Taking the forward voltage drop of diodes into account, the SC
units were charged to about 70 V in symmetric SC configuration. By inserting a diode,
99
D1, between T13 and T23, the maximum charging voltage of the SC units in the
asymmetric SC configuration were about 70 V to 140 V.
Table 4.4. Specification and components of the SCMLI prototype.

Components Values
Input Voltage (VS1, VS2, VS3) 24 VDC
Electrolytic 1000 μF
Switched-Capacitors (C1, C2)
(loss tanδ≤0.15 @ 120 Hz)
N-Channel MOSFETs (S, T) FDP52N20 200 V, 52 A, 49 mΩ
N-Channel MOSFETs (Q) IRFPS37N50A 500 V, 36 A, 0.13 mΩ
Ultrafast Rectifier Diodes (D1, D11) MUR820 200 V, 8 A
Ultrafast Rectifier Diode (D02) MUR420 200 V, 4 A
Operating Frequency 50 Hz to 1000 Hz
3 2
1
4
Fig. 4.9. Experimental setup; (1) the hybrid SCMLI prototype; (2) input filter
capacitors; (3) DC power supplies; (4) load resistors and a 1 mH inductor.
100
Vo [V]
Vo [V]
Io [A]
Io [A]
VC [V]
VC [V]
VC1 VC2 VC1 VC2
t [s] t [s]
200 Vo: THD = 4.235% 4 200 Vo: THD = 6.244% 4

Io: THD = 0.983% Io: THD = 0.786%
FFT
FFT
100 2 100 2
0 0 0 0
f [ 104Hz] f [ 104Hz]
(a) (b)
Vo [V]
Vo [V]
Io [A]
Io [A]
VC2 VC2
VC [V]
VC [V]
VC1 VC1
t [s] t [s]
300 Vo: THD = 3.369% 6 300 Vo: THD = 4.691% 6
200 Io: THD = 0.805% 4 200 Io: THD = 0.949% 4
FFT
FFT
100 2 100 2
0 0 0 0
f [ 104Hz] f [ 104Hz]
(c) (d)
Fig. 4.10. Simulated voltage and current waveforms of the SCMLI; symmetric
configuration with (a) staircase modulation; (b) SPWM; asymmetric
configuration with (c) staircase modulation; (d) SPWM.
The simulated waveforms are plotted in Fig. 4.10, which depicts the AC outputs,
the SC voltages along with the associated gate signals of the SCMLI at 400 Hz
operation. For the case of symmetric SC voltage, the peak output voltage was about
210 V; the ripple voltages of the SC units were approximately 1.52 V to 1.56 V at the
101
output power of around 220 W. The peak output voltage for asymmetric SC voltage
configuration was about 280 V; the SC ripple magnitudes were approximately 1.48 V
to 1.74 V at the output power of around 330 W. Although the capacitor voltage ripples
were not compensated in the modulation signal, the fast Fourier transform (FFT)
analyses showed that the nearest switching staircase modulation has satisfactory
harmonic performance. The THD of the unfiltered 19-level and 25-level output
voltage were 4.26% and 3.37%, respectively; while the current THD was below 1%.
For comparison, the output waveforms under SPWM with 30 kHz triangular carrier
were also simulated. In this case, the voltage THD was contributed by the 30 kHz
carrier whereas the current THD was mainly brought by the uncompensated SC
voltage ripples. The overall THD magnitude was similar to the staircase modulation.
However, considering the additional switching loss and EMI, staircase modulation at
the fundamental frequency would be more preferable for the SCMLI.
1
Rch,1=0.3Ω; C1=1000μF Rch,1=0.15Ω; C1=500μF
0.95 Rch,1=0.3Ω; C1=500μF

Efficiency
0.9
0.85
19-level symmetric
25-level asymmetric
0.8
0 500 1000 1500
f [Hz]
Fig. 4.11. Effect of the fundamental output frequency on the energy efficiency
of the SCMLI with different RC parameters.
102
1
1 kHz
400Hz
0.95
Efficiency
0.9
50Hz
0.85
Simulation
Theoretical
0.8
50 150 250 350
Po [W]
(a)
1
1 kHz
0.95
400Hz
Efficiency
0.9 50Hz
0.85
Simulation
Theoretical
0.8
100 200 300 400
Po [W]
(b)
Fig. 4.12. Simulated and theoretical efficiencies of the SCMLI at different
operating condition; (a) 19-level symmetric configuration; (b) 25-level
asymmetric configuration.
103
In addition, the effects of the operating frequency and the RC parameters of the
SC units on the conversion efficiency were investigated with the simulation model.
The efficiency curves of the SCMLI models at about 300 W output are shown in Fig.
4.11. As predicted by (4.14)-(4.15), the efficiency increased with the operating
frequency and capacitance at low frequency (ρ>>1). At high frequency (1/ρ>>1), the
energy loss could not be reduced by further increasing the capacitance or frequency
but by lowering the ESR of the capacitor. Besides, due to the fact that the average
charging duration for the asymmetric inverter was slightly shorter than that of the
symmetric version, the frequency-efficiency curve for the 25-level asymmetric
SCMLI model was shifted to the lower-left side. Furthermore, simulated efficiency of
the SCMLI at 50 Hz, 400 Hz and 1 kHz was compared with the theoretical values. As
shown in Fig. 4.12, with the known parameters of switch resistance, capacitance and
ESR, the energy losses calculated from (4.12)-(4.30) conformed to the simulation
results.
The inverter prototype with the specification listed in Table 4.4 was built to
examine the feasibility and evaluate the performance of the proposed SCMLI
topology. The SCMLIs with the 19-level symmetric and 25-level asymmetric
configurations were tested with inductive loads varied from 660Ω-1mH to 110Ω-1mH;
the operating frequency was altered from 50 Hz to 1000 Hz. The measured waveforms
are illustrated in Fig. 4.13.
104
Time base: 10ms/div Vo: 200V/div
Io: 1A/div
∆VC2 ≈ 3.5V VC2: 10V/div

VC1: 10V/div
∆VC1 ≈ 3.5V
(a)
Io: 2A/div
∆VC2 ≈ 6.5V VC2: 10V/div VC1: 10V/div
∆VC1 ≈ 6.5V
(b)
Io: 1A/div
∆VC2 ≈ 4.5V VC2: 20V/div

VC1: 20V/div
∆VC1 ≈ 3.5V
(c)
105
Io: 2A/div
∆VC2 ≈ 9V VC2: 20V/div VC1: 20V/div
∆VC1 ≈ 7V
(d)
Io: 2A/div
∆VC1 ≈ 1V
(e)
Io: 2A/div
∆VC2 ≈ 1.5V VC2: 20V/div VC1: 20V/div
∆VC1 ≈ 1V
(f)
Fig. 4.13. Measured voltage and current waveforms of the SCMLI prototype;
19-level symmetric configuration driving (a) 330Ω-1mH and (b) 165Ω-1mH
loads at 50 Hz; 25-level asymmetric configuration driving (c) 330Ω-1mH and
(d) 165Ω-1mH load at 50 Hz; driving 165Ω-1mH loads at 1000Hz with (e) 19-
level configuration; and (f) 25-level configuration.
106
The measured amplitudes of the capacitor voltage ripples conformed to the
theoretical values estimated by (4.6) to (4.8). At 50 Hz operation, the measured ripple
amplitudes of the symmetric mode inverter were about 3.5 V to 6.5 V at the loads of
330Ω-1mH to 165Ω-1mH; the measurements for the asymmetric counterpart were
approximately 3.5 V and 4.5 V to 7 V and 9 V. The measured ripple voltages were
close to the prediction of (4.6) to (4.8) with less than 10% error. The major sources of
errors would be the capacitance tolerance and the voltage drop caused by the ESR of
the capacitors. This could cause output voltage sag and extra distortion as the voltage
ripples were not compensated by the modulation technique.

Io: 2A/div
∆VC2 ≈ 1.5V VC2: 10V/div
∆VC1 ≈ 1.5V VC1: 10V/div
(a)
Time base: 1ms/div THD ≈ 4.42%
Vo: 100V/div
FFT: Vo
10Vrms/div; 5kHz/div
(b)
at 400 Hz; (a) the waveforms of output voltage, current and capacitor voltages;
(b) the FFT of output voltage.
107
Besides, the observed waveforms at higher output frequencies and the
corresponding FFTs of the output voltages for the 400 Hz operation at rated load are
depicted in Fig. 4.14 and 4.15. By increasing the operating frequency, the voltage
ripples were mitigated even at heavier load compared to the 50 Hz condition. The FFT
of the recorded output voltage waveforms verified the functionality of the staircase
modulation strategy at high fundamental frequency up to 1000 Hz; the computed THD
values counting the first thousand harmonic orders also conformed to the simulation
results. During the light load conditions of ≤330Ω-1mH, the ripple loss was not a
dominating factor.
Time base: 1ms/div

Vo: 100V/div
Io: 2A/div
∆VC1 ≈ 1.5V
(a)
Time base: 1ms/div THD ≈ 3.45%
Vo: 100V/div
FFT: Vo
10Vrms/div; 5kHz/div
(b)
Fig. 4.15. Measured waveforms of the 25-level SCMLI driving 110Ω-1mH
load at 400 Hz; (a) the waveforms of output voltage, current and capacitor
voltages; (b) the FFT of output voltage.
108
1 kHz
Measured efficiency
0.95
400Hz
0.9 50Hz
0.85
50 100 150 200 250
Po [W]
(a)
1
Measured efficiency
1 kHz
0.95
400Hz
0.9
50Hz
0.85
100 150 200 250 300
Po [W]
(b)
Fig. 4.16. Measured efficiency of the SCMLI; (a) 19-level symmetric
configuration; (b) 25-level asymmetric configuration.
As plotted in Fig. 4.16, the measured efficiency was generally lower than the
theoretical and simulated values due to the additional parasitic components, including
the wire resistance and the additional ranging loss at the switching transient. Also, the
measurement error at the light current would be one reason for the deviation between
109
the simulated and measured efficiencies. Overall, the observed effects of output
current and frequency on the conversion efficiency coincided with the theoretical
analysis. At light load (i.e. 330 Ω), the ripple loss was not a dominating factor, the
measured efficiencies at different operating frequencies were close to each other; the
measured efficiencies for the 19-level symmetric and 25-level asymmetric
configurations were about 97% and 96%, respectively. When the load power was
gradually increased, the efficiency improvement at 400 Hz over 50 Hz became
significant along with the reduction in the capacitor voltage ripples. By increasing the
operating frequency at 110Ω load, the efficiency rose from 93.5% to 96.1% and 90.5%
to 94.5%, respectively. However, the discrepancy between the efficiencies measured
at the 400 Hz and 1 kHz settings were exiguous due to the large RC time constant of
the 1000 µF electrolytic capacitors used in the prototype. This observation also
corresponds with the prediction in section 4.3. As suggested by (4.11) to (4.13), the
ripple loss could be mitigated by increasing the output frequency when the operating
frequency was low compared to the cut-off frequency of the SC parameters. When the
output power was higher than 100 W, the efficiency was dramatically improved by
raising the frequency from 50 Hz to 400 Hz. On the other hand, as indicated by the
curves plotted in Fig. 4.11, the efficiency improvement between 400 Hz and 1 kHz
was insignificant.
4.5. Summary
This chapter presents a series of hybrid SCMLI cooperating with series-connected DC
voltage sources. By employing the series-parallel conversion technique, the proposed
SCMLI is capable of voltage step-up and attaining self-balancing of the capacitor
110
voltages. In comparison with the conventional SCMLI topologies, the proposed
inverter offers an option of generating staircase voltage waveform from a string of
series-connected DC voltage sources. The output power quality is improved by the
intermediate voltage levels provided by the bidirectional switched converter stage.
This greatly increases the available number of output levels without dramatic growth
in the component count. By applying minor modifications to the topology, the
presented SCMLI can be altered between symmetric and asymmetric SC voltage
configurations attributing different features in the voltage step-up capability and
component stresses. The mathematical analyses on the capacitor voltage ripples and
power loss provide necessary information for capacitor sizing and estimation of the
inverter performance at different operating conditions.
In addition, investigation has been conducted on reducing the number of active
components through replacing specified transistors with diodes for the applications
demanding less reactive power. The substantial increase in output levels enables the
possibility of employing simple staircase modulation which reduces the switching
frequency and allows higher output frequency. The nearest switching scheme has be
employed to this SCMLI; the operation and performance of the proposed topology
were studied with the simulation models and prototypes with the 19-level symmetric
and 25-level asymmetric configurations. Peak voltage of about 210 V and voltage
THD of about 4.42% were achieved by the 19-level symmetric configuration with
three 24 V sources whereas the peak voltage and THD for the 25-level asymmetric
configuration were more than 280 V and approximately 3.45%, respectively. Similar
to existing SCMLIs, the driving capability of the inverter is restricted by the capacitor
111
sizes. Taking into account that the ripple power loss can be mitigated by increasing
the fundamental output frequency, the proposed topology is highly preferable for
HFAC applications.
For the energy storage applications with batteries or supercapacitors strings, this
hybrid SCMLI may suffer from the issue of cell imbalance. Unlike in CHBI that each
of the independent voltage sources can be bypassed easily, series sources based
inverters like the diode-clamped inverters tend to coexist with voltage imbalance issue
because the output voltage steps are formed by adjacent cells or capacitors in the string.
This issue would be exacerbated when limited redundant switching states are provided.
Next chapter focuses on the source balancing techniques in multilevel inverters, the
limitations of series voltage sources based single-phase inverters are identified; the
source imbalance issue is addressed by the current allocation method with a variant
of the proposed hybrid SCMLI.
112
Chapter 5 MLI Cell Balancing
Chapter 5
Cell Voltage Balancing with Conventional and SC MLIs
Without proper management on the input current, multi-source based converters like
the MLIs directly attached to battery cells or modules can cause cell imbalance due to
the unequal magnitudes of input current. For this reason, the control techniques for
achieving cell balance have become an interesting research topic. However, the
existing research of MLI based cell balancing control mainly focuses on balancing
independent sources. Charge imbalance in battery or supercapacitor stacks consisting
series-connected cells is a more practical but challenging issue. Yet there is a lack of
exploration of this issue.
This chapter presents a charge balancing method for series-connected energy
storage devices based on the current allocation control with MLIs. Unlike the
independent cells in other MLIs with isolated DC sources, the series-connected cells
in a battery or supercapacitor string cannot be bypassed individually. This leads to the
issue of charge imbalance in many series sources based MLIs. In the following section,
the analysis and design of the current allocation method for charge balancing in
different single-phase MLI topologies are discussed. The analysis of the current
allocation method is elucidated with the mathematical representation of cell
113
discharging current based on the staircase modulation. In order to overcome the limit
of the modulation index for attaining charge balance, a hybrid SCMLI topology is
developed by cooperation an SC cell with the switch-ladder technique. The control
algorithm and the operation for the well-known switch-ladder MLI and the proposed
hybrid SCMLI were testified by the simulation study and experimental results.
5.1. Review on the MLI Cell Balancing Methods
Along with the increased penetration of RE and ESS applications, the ideas of state-
of-charge (SOC) balancing in multi-source power converters through charge
allocation techniques have been reported in recent years. The techniques include
sorting [164-168], droop control [169, 170] and special modulation [127] methods
cooperating with a cascaded H-bridge inverter (CHBI) or modular multilevel
converter (MMC) [127, 167]. Since the average current drawn from the independent
voltage sources in CHBI is determined by the conduction angles of the H-bridge units,
charge equalization can be achieved by simply sorting the conduction angle regarding
the source voltage or SOC such that the input source with the highest SOC will
discharge at the highest rate and vice versa [164, 166]. Given that the current of any
independent input sources can be selected or bypassed in the multi-source power
converters, the charge allocation techniques not only exhibit very effective balancing
capability during the charge or discharge processes but also eliminate the need of
additional on-board or off-board balancing circuitries.
Owing to the high degree of freedom and redundant switching states, the
existing research on the current allocation based SOC balancing are mostly confined
to the independent sources based converters like the CHBI and MMC. However, the
114
configuration of independent voltage sources is not directly compatible with auxiliary
loads having a common ground or other DC loads requiring the string voltage. At the
same time, independent sources requires galvanic isolated management circuitries
which increase system complexity. In many energy storage applications such as the
EVs and buildings integrated with distributed generation, an ESS compatible with
several loads and renewable energy sources is more preferable as it is easier to manage.
Therefore, the series voltage sources based counterparts such as the diode-clamped
[171], bidirectional switched [123, 141], switch-ladder [172, 173], or the switched-
capacitor inverters [53, 59, 61, 142, 174] would be more preferable for these
applications. In addition to preserving the advantages offered by the ESS with a single
string of cells, these MLI topologies are also beneficial from component reduction
which improves the system simplicity.
However, there are certain restrictions on implementing the charge balancing
control with the MLI powered by a voltage source string. Since the input sources are
connected in series, the sources cannot be bypassed individually. As a result, the series
sources based MLI exhibits limited performance in attaining charge balance because
of the limited redundant switching states. In the following, the constraints and
effectiveness of current allocation in various single-phase MLI topologies are
investigated. A variation of hybrid SCMLI is also developed to tackle this weakness.
5.2. MLI Topologies Employing Series Voltage Sources
There are numerous MLI topologies which are capable of producing multilevel AC
output from a DC voltage source string. Fig. 5.1 illustrates four distinct series voltage
sources based single-phase MLI topologies.
115
Bn Bn
Bn-1 Bn-1
vo vo
B2 B2
B1 B1
(a) (b)
vo
Bn
Bn
Bn-1
Bn-1
B2
B2
B1
B1 vo
(c) (d)
Fig. 5.1. Multilevel inverter topologies cooperating with series string of voltage
sources; (a) single phase structure of diode-clamped inverter; (b) bidirectional
switched inverter; (c) switch-ladder inverter; (d) a hybrid SCMLI employing
switched-capacitor unit and bidirectional switches.
The diode-clamped, as known as neutral-point-clamped inverter, is one of the
most widely used MLI topologies in three-phase medium to high voltage systems
since it effectively reduces the voltage stress of components. The single-phase
116
structure of the diode-clamped inverter [171] is illustrated in Fig. 5.1a. In the
conventional configuration, the diode-clamped inverters are supplied by a DC source
while the cells, B1,…,Bn, are implemented by capacitors. The major shortcomings of
this type of inverter are the capacitor voltage imbalance issue [175] and the dramatic
increase in the number of diodes along with growing number of output levels. As a
result, the industrial applications of diode-clamped inverters are usually limited to the
three-level, or five-level configurations with additional balancing circuitries [176-
178]. In order to reduce the component count, the bidirectional switched inverter (Fig.
5.1b) [123, 141] and switch-ladder inverter (Fig. 5.1c) [172, 173] were developed by
employing bidirectional switches and eliminating the need of dc-link capacitors.
Furthermore, by combining a switched-capacitor unit [53] with the bidirectional
switched inverter, a hybrid SC DC-AC inverter (Fig. 5.1d) producing a higher number
of levels and enabling voltage step-up has been developed.
Although the bidirectional switched inverter has an optimal number of switches,
the drawback is the lack of redundant switching states for implementing current
allocation control. This brings up the issue of current imbalance and declines the
practicability of operating with battery or supercapacitor cells. As a result, among the
topologies shown in Fig. 5.1, the current allocation based cell balancing can only be
effectively implemented in the single-phase diode-clamped inverter (Fig. 5.1a) and
switch-ladder inverter (Fig. 5.1c). Based on this principle, by replacing the
bidirectional switched converter in Fig. 5.1d with a switch-ladder, a variation of the
hybrid SCMLI (Fig. 5.2a), offering redundant states, can be derived.
117
T1n T2n
Bn
T1(n-1) T2(n-1)
Bn-1
T1(n-2) T2(n-2)
T12 B2 T22
T11 B1 T21
Q12 Q22
T10 T20 vo
C
T00 Q11 Q21
(a)
T1n
Bn
Bn-1 T1(n-1) Bn-1 Bn-1 T2(n-1)
B2 B2 B2
B1 T21 T11
C T00 C C
(b) (c) (d)

Fig. 5.2. The modified hybrid SC DC-AC inverter; (a) general representation of
the topology; (b) charging of the switched-capacitor; the switching states for: (c)
output V2 at mode-2; (d) output V(2n-2).
In this modified topology, the switched-capacitor, C, is charged from the
voltage source string by conducting the switches T00 and T1n (Fig. 5.2b) during the
zero and nth levels. For low output voltage levels (i.e. when vo is less than the total
string voltage), there are two modes of operation: Mode 1) The switched-capacitor is
118
bypassed; output voltage is supplied through switches T00 and T2x, where x=1,…,n.
Mode 2) Output voltage is supplied through the switched-capacitor and switches T1x
and T2y, where x>y (Fig. 5.2c). On the other hand, for high output voltage levels, there
is only one operating mode: The output voltage is supplied by the switched-capacitor
and voltage source string together through conducting T1x and T2y, where x<y (Fig.
5.2d). As a result, comparing to the hybrid SCMLI discussed in the previous chapter,
the additional switching states offered by this variety can mitigate the current
imbalance issue. Furthermore, it is possible to enable the current allocation control for
charge balancing among the series-connected sources.
Table 5.1. Properties of different MLI topologies with n

series-connected voltage sources.
Previous Modified
Diode- Bidirectional Switch-
Number of hybrid hybrid
clamped Switched ladder
SCMLI SCMLI
MOSFETs, nT 4n 2n+2 4n+4 2n+6 4n+5
Diodes, nD 2n(n−1) 0 0 0 0
Capacitors, nC 0 0 0 1 1
Levels, nL 2n+1 2n+1 2n+1 4n+1 4n+1
States, nSS n(n+1)+1 2n+1 n(n+1)+1 4n+1 2n(n+2)+1
Table 5.1 summarizes the properties including the numbers of components, nT,
nD and nC, output voltage levels, nL, as well as the effective switching states, nSS, of
different topologies with n sources. The series sources based MLIs with optimal
numbers of components such as the bidirectional switched inverter and the hybrid
SCMLI suggested in the previous chapter offer no effective redundant states for
allocation control. This implies that these topologies may suffer from charge
119
imbalance issue when the series voltage source is formed form a string of energy
storage devices. Besides, the modified hybrid SCMLI, diode-clamped and switch-
ladder inverters provide additional switching states for some extent of charge
allocation control. This aids to prevent serious imbalance and help achieve cell
balancing. Although the diode-clamped inverter has the same redundancy states as the
switch-ladder inverter, the forward voltage drop caused by the diodes in the former
topology would deteriorate the conduction loss for low-voltage applications. In the
following sections, the analysis and design of current allocation control will be
focusing on the switch-ladder MLI and the modified SCMLI.
5.3. Current Allocation and Analysis of Series Sources Based MLIs
under Staircase Modulation
Fig. 5.3. The stepped output voltage waveform produced by an MLI with
staircase modulation.
120
The nearest switching scheme at fundamental frequency [159, 160] provides a simple
method for calculating the required firing angles for the single phase AC output with
the minimum voltage THD. The staircase output voltage waveform of the MLI is
illustrated in Fig. 5.3. The firing angles, θ1,…,θk, can be computed by (5.1).
 V V 
i  sin 1  i 1 i  (5.1)
 2 VM 
where VM is the amplitude of the modulating signal, Vi is the output voltage magnitude
at the ith voltage step and ρ is the modulation correction factor which is generally
ranged from about 0.8 to 1.2 and can be obtained iteratively as suggested in [159].
Unlike the isolated sources based MLIs like the CHBI and MMC in which the
current of each cell can be allocated individually, the output current in MLI
cooperating with series voltage sources must be allocated by adjacent cells.
5.3.1. Current Allocation in Diode-clamped Inverter or Switch-ladder Inverter
For diode-clamped inverter or switch-ladder inverter with n series-connected energy
storage devices, B1,…,Bn, offering n(n+1)+1 switching states, the average output
current, IB,avg, of the battery or supercapacitor string can be expressed as (5.2),
n  i
1
I B ,avg 
n
 
i 1 i
io dt (5.2)
which can be simplified to (5.3) by approximating the output voltage and current with
the corresponding fundamental components,
2MI o cos 
I B ,avg  (5.3)

121
where io is the output current with fundamental amplitude Io; M=𝜋VM/4Vk is the
modulation index; and φ is the phase lag angle between the output current and voltage.
Start
Measure SOCB1 to SOCBn
kmax = Bmax
kmin = Bmin
L[1] = kmax
i=2
flag = 0
No No No
L[i−1] = 1 L[i−1] = n−i+2 SOCBL[i-1]-1 > SOCBL[i-1]+i-1
Yes Yes
No No Yes
i = kmin n−i+1 = kmin
i = i+1 Yes Yes
No No
flag = 0 flag = 0
Yes Yes L[i] = L[i−1]
No No
i ≤ n−kmin i < kmin
Yes Yes
flag = 1 flag = 1
L[i] = n−i+1 L[i] = 1 L[i] = L[i−1]−1
Yes
i<n
No
End
with single-phase switch-ladder inverter; for positive output levels, i, switches
T1L[i]−1 and T2L[i]−1+i are switched on; while the switches T1L[i]−1+i and T2L[i]−1 are
switched on for the corresponding negative output levels.
122
Regarding the charge allocation control, the equivalent balancing current could
be considered as the difference between the current, IBmax, of the maximum voltage
(or SOC) cell, Bmax, and the current, IBmin, of the minimum voltage (or SOC) cell, Bmin.
Therefore, the fundamental of the current allocation control is finding the
corresponding switching patterns in fulfillment of: Criterion 1) Minimize IBmin; and
Criterion 2) Maximize IBmax. With the aim of accomplishing these criteria, the current
allocation strategy for charge balancing, as descripted in Fig. 5.4, can be adopted. If
all series-connected cells share the same voltage characteristic and capacity, cell
voltages can be employed in the sorting function. For source string with unequal cell
parameters, it is required to estimate the SOC of each cell in order to perform proper
sorting for charge balancing. Based on the assumption that the switching pattern along
ωt=π/2 is symmetrical, the maximum and minimum attainable current, IBi,max and
IBi,min, of a specific cell, Bi, can be expressed as follows by evaluating the available
switching states provided by the diode-clamped or switch-ladder inverter.
2 I o cos 1 cos 
I Bi ,max  (5.4)

n
 2 I o cos  k i 1 cos  for i 
 2
I Bi ,min 

(5.5)
 o2 I cos  i cos 
n
  for i 
2
while the number of firing angles k=n. By comparing (5.4) and (5.5), the maximum
equivalent balancing current, IBeq, for the optimal case, i.e. Bmin=B1 or Bn, and the
worst case, i.e. Bmax=B1 and Bmin=B2; or Bmax=Bn and Bmin=Bn-1, can be expressed as
(5.6) and (5.7), respectively.
123
 2 I o cos   cos 1  cos  n 



for the optimal case (5.6)
I Beq 

 2 I o cos   cos 1  cos  2  for the worst case (5.7)

 
Besides, in order to reach overall charge balance of the entire source string, two
additional criteria, 3) IBmax>IB,avg and 4) IBmin<IB,avg, have to be satisfied. Since
cosθ1>M for the staircase modulation, criterion 3) is essentially fulfilled. According
to the functions (5.1) and (5.3) to (5.5), criterion 4) suggest that the diode-clamped
inverter or the switch-ladder inverter can achieve charge balance under nearest
switching staircase modulation only if the following condition is fulfilled.
4  16   2  2
M 2
(5.8)
8
In other words, charge balance in this type of single-phase MLIs can only be
achieved at low output voltage given that the nearest switching staircase modulation
is employed. The condition in (5.8) would ensure that the center cells will not
discharge at the highest rate throughout the discharging operation. Otherwise, the
SOC of the center cells will always drop quicker than other cells and deviate from the
balance state.
5.3.2. Current Allocation in the Altered Hybrid SCMLI
By combining the switch-ladder with an SC unit, it is possible to form a higher number
of switching states comparing to the bidirectional switched counterpart. By
substituting Vk=2Vn into (5.3), the average current of the battery or supercapacitor
string in the modified hybrid SCMLI is approximated by (5.9).
124
4MI o cos 
I B ,avg  (5.9)

In order to attain criterion 1), the charging current of Bmin during low output levels
should be maximized. The maximum charging current, Ich,max, for Bmin, is derived as
(5.10).
2 I o cos  (cos 1  cos  n )

I ch,max  (5.10)

The minimum discharging current for Bi during high output voltage levels can be
derived from (5.5) by substituting k=2n. Therefore, the minimum discharging current,
IBi,min, for Bi in one cycle can be approximated by the following expression.
 2 I o cos  (cos  n  cos  2 n i 1 ) for i 

n
  2
I Bi ,min  (5.11)
 2 I o cos  (cos  n  cos  n i ) for i 
n
  2
Similarly, overall charge balance of the string is attainable only if the criteria 3) and
4) are fulfilled. By substitution of (5.1) into (5.9) and (5.11), and considering the case
that Bmin has a center position which a minimum number of voltage levels can be
skipped, the criterion 4) is equivalent to the following inequality.
 2 2
 1      1   3n  2  for even number n

  8M    16Mn 
2M   (5.12)
   
2
 3n   
2
for odd number n
 1     1   

  8M    16Mn 
Expression (5.12) suggests that overall charge balance can be achieved by the
modified hybrid SCMLI within a wide range of modulation indices except under the
125
situation of serious over-modulation when the correction factor, ρ, is too large. Based
on the aforementioned criteria, the current allocation strategy for the proposed hybrid
SCMLI described in Fig. 5.5 is constructed.
Start
Measure SOCB1 to SOCBn
kmax = Bmax
kmin = Bmin
L[1] = kmin
L[n+1] = kmax
i=2
flag = 0
No
i<n
Yes No
i=n
No
Yes Yes i = n+1
L[i−1] = 1
Yes No No No
No L[i−1] = 1 L[i−1] = 2n−i+2 SOCBL[i-1]-1 > SOCBL[i-1]+i-1
Yes
L[i−1] = n−i+2 Yes Yes
No No Yes
No i−n = kmin 2n−i+1 = kmin
Yes
SOCBL[i-1]-1 < SOCBL[i-1]+i-1 Yes Yes
No No
No flag = 0 flag = 0
Yes Yes
i = i+1
No No
i−n ≤ n−kmin i−n < kmin
Yes Yes
flag = 1 flag = 1
L[i] = 1
L[i] = L[i−1] L[i] = L[i−1]−1 L[i] = 2n−i+1
Yes
i < 2n
No
End
with the proposed hybrid MLI; for output levels, i > n, switches T1L[i]−1 and
T2L[i]−1+i−n are switched on; while the switches T1L[i]−1+i and T2L[i]−1 are switched
on for i < n.
126
5.3.3. Ripple Analysis and Capacitor Sizing
As discussed in chapter 4, one major drawback of series-parallel SC inverters is the
voltage ripple issue. The SC voltage decreases during discharge to the load whereas
the SC voltage is refreshed by the parallel operation. Although this operation attains
self-balance of the switched-capacitor, it may bring about the issues of unwanted
output voltage distortion and reduced conversion efficiency. With the staircase
modulation, the SC unit discharges three times in every positive or negative cycles.
By using the same approach as the previous chapter, the magnitudes of these three
voltage ripples can be derived as follows.
 I o (cos(1   )  cos( n   ))
VC ,1  C

 2 I o cos  n 1 cos 
VC ,2  (5.13)
 C
 I (cos(1   )  cos( n   ))
VC ,3 
o
 C
When the output current is dominated by the real power (i.e. φ<<π/2), the voltage
ripple magnitude is determined by ∆VC,2. In order to ensure proper operation with the
proposed staircase modulation (i.e. same number of rising and falling edges in the
unfiltered output voltage waveform), the minimum capacitance, Cmin, can be
determined by (5.14).
2
2Io   
Cmin   1   (5.14)
 fVB  8M max 
where VB, f and Mmax are the cell voltage, output frequency and the maximum
allowable modulation index, respectively.
127
Besides, the voltage ripples of the switched-capacitor bring energy loss which
is dissipated during charge-up of the capacitor at the parallel operation. Assuming that
the charging duration of the switched-capacitor is much longer than the RC time
constant, the capacitor is fully charged by the voltage source string. The ripple energy
loss, Eloss.rip, dissipated in each ripple cycle can be expressed as (5.15)
1
Eloss ,rip  C VC 2 (5.15)
2
By adopting the same procedure of the hybrid SCMLI presented in chapter 4, the
ripple power loss, Ploss,rip, of the modified hybrid SCMLI under staircase modulation
can be expressed as follows:
Io2 3
Ploss ,rip 
4 2Cf

i 1
i
2
(5.16)
where
1  cos(1   )  cos( n   )


 2  2 cos  n 1 cos  (5.17)
  cos(   )  cos(   )
 3 1 n
Similar to other SC inverters, the ripple power loss is inversely proportional to the
capacitance, C, and the fundamental output frequency, f. Therefore, as suggested in
[57, 61, 62], this modified version is also more preferable for HFAC applications.
Comparing to the original topology, there is a trade-off between the charge balance
and energy efficiency in view of the extra ripple loss from the terms α1 and α3 induced
by additional series-parallel operations. Fortunately, as defined by the staircase
128
modulation, the values of α1 and α3 is generally much lower than the value of α2. Hence,
the additional ripple loss for charge balance is insignificant.
Taking the energy efficiency of the inverter into consideration, the capacitor can
also be sized based on the target factor, β, of ripple loss to the output power.
Ploss ,rip
 (5.18)
Po
By substituting (5.16) and Po=Io2Ro/2 into (5.18), the size of the capacitor can be
chosen based on (5.19).
 i
2
Cmin  i 1
(5.19)
2 2 fRo 
  i 2 is generally ≤4 considering the ranges of

3
where Ro is the load resistance and i 1
the cosine terms.
5.4. Simulation and Experimental Verifications
With the purpose of investigating the effectiveness of the current allocation method,
simulation models of a switch-ladder inverter and the modified hybrid SCMLI
constituted with a voltage source string formed by 4 batteries were studied. As
depicted in Fig. 5.6, the AC outputs of the inverters were connected to an inductive
load; the batteries, B1,…,B4, were simulated based on the series modules of a modified
2200 mAh Li-ion battery cell suggested in [179]. The improved open-circuit voltage
(OCV) to SOC function and curve of which are depicted in (5.20) and Fig. 5.7,
respectively. All control blocks are implemented in C program; the modulator and
129
gate control blocks were updated at every simulation cycle (a fixed time-step of 5 μs),
while the sorting was performed every 0.1 s. During the first setting (Setting-1 and
Setting-4), the current source, IS, was disabled; during the second setting (Setting-2
and Setting-5), IS was set to around 120% of IB, avg to simulate the situation that the
battery undergo string charging during loaded condition; the third setting (Setting-3
and Setting-6) simulated the situation of varied modulation index with a fixed load
and charging current. The parameters of the simulation models are listed in Table 5.2.
SW
V B4 io
V B3 DC/AC
Is vo
V B2 MLI
V B1
VB1, …, VB4
Gating signals
Sorting
Function
L[1], …, L[4]
Tc = 0.1s Gate
i Control
m Staircase Tc = 5μs
f Modulation
Tc = 5μs
Fig. 5.6. Configuration of the simulation model.
0.629  SOCB 2  0.889  SOCB  3.387 for SOCB < 0.35

OCVB  
0.556  SOCB  0.178  SOCB  3.491 for SOCB ≥ 0.35
2
(5.20)
and
VB  OCVB  0.1014  I B
130
4.2
OCV [V] 3.8
3.6
3.4
3.2
0.0 0.2 0.4 0.6 0.8 1.0
SOC
Fig. 5.7. The OCV-SOC curve of the Li-ion battery model.
Table 5.2. Parameters of different simulation settings.

Settings
Parameters
1 2 3 4 5 6
MLI topology Switch-ladder MLI Proposed hybrid MLI
Number of Modules 4
Battery Modules 3×2200 mAh Li-ion battery in series
Frequency, f 400 Hz
Switches Ideal MOSFETs
Capacitance N/A 1000 µF
Load 3Ω-1.08mH 18Ω-6mH 10Ω-3.6mH
The criteria for charge balance were fulfilled by fixing the modulation index at
0.35 in simulation settings 1, 2 and 3 with the switch-ladder inverter. This gave a five-
level staircase voltage output from the four series-connected sources. The output
voltage and current waveforms, as well as the cell current, iB, in setting-1 are depicted
in Fig. 5.8. The peak voltage and current were approximately 24.2 V and 6 A,
respectively. In this setting, the Li-ion batteries were discharged to a fixed 3Ω-
131
1.08mH load through the single-phase switch-ladder inverter with the current
allocation control. The power factor of the load at 400 Hz was approximately 0.74
lagging. In setting-2, a constant charging current of 1.6 A was applied to the battery
string. The SOC and the battery terminal voltages are shown in Fig. 5.9. As the cells
B1 and B4 had lower initial SOC, the current allocation function performed charge
balancing through bypassing these two modules with the switch-ladder. After
reaching balance state at about 800 s, the positions of the bypassed modules were
shifting alternatively at an interval of 0.1 s following the sorting control. Overall, the
Li-ion batteries reached and maintained balance state with the single-phase switch-
ladder at low modulation index. In setting-3, the load and charging current were fixed
at 3Ω-1.08mH and 1.6 A, respectively. The initial modulation index was set at 0.6,
then, the modulation index was reduced by a 0.1 step for every 1000 s. As illustrated
in Fig. 5.9c, the balancing performance of the switch-ladder inverter was poor before
t=2000s when the modulation index was ≥0.5. The SOC converged after 2000 s when
the modulation index was ≥0.4.
THD ≈ 21.47%
vo [V]
THD ≈ 4.50%
io [A]
Time [s]
Fig. 5.8. Simulated output voltage and current waveforms of the switch-ladder
inverter.
132
B1 B2 B3 B4
SOC
B1 B2 B3 B4
VB [V]
Time [s]
(a)
SOC
B1 B2 B3 B4
VB [V]
B1 B2 B3 B4
Time [s]
(b)
133
B1 B2 B3 B4
SOC
B1 B2 B3 B4
VB [V]
Time [s]
(c)
Fig. 5.9. The battery SOC and voltages throughout the discharge process; in (a)
simulation setting-1; and (b) setting-2 with charging current and (c) setting-3
with varying modulation index.
For the implementation of the modified hybrid SCMLI in settings 4, 5 and 6,
the operating frequency and modulation index were set to 400 Hz and 0.65,
respectively. Because of the step-up feature provided by the switch-capacitor unit and
the increase in allowable modulation index fulfilling the balancing criteria, the output
voltage became a 15-level staircase waveform with the peak voltage of about 82.7 V.
Also, the THD was substantially improved. The output waveforms of the SCMLI
model are illustrated in Fig. 5.10. The voltage ripple magnitudes ∆VC1, ∆VC2 and ∆VC2
of the simulated waveform were about 0.44 V, 2.51 V and 0.93 V, respectively. These
were very close to the approximation with (5.13). No charging current was applied in
setting-4. Due to the substantial increase in output voltage, the load value was set to
18Ω-6mH to moderate the battery discharge current. In setting-5, charging current
was present. The load was altered to 10Ω-3.6mH so that the magnitude of the AC
134
output current was similar to that in setting-2. As the load power rose, the charging
current was set to 3.9 A, which was approximately 120% of the average load current
to the batteries. In simulation setting-6, the load value and string charging current
were set to 10Ω-3.6mH and 1.6 A, respectively. The initial modulation index was 0.6,
which was then altered to 0.5, 0.4, 0.3 at t=1000s, t=2000s, t=3000s, respectively. The
SOC and cell voltages are shown in Fig. 5.11. In setting-4, the battery string reached
balance state at about 1250 s. In setting-5, since the magnitude of balancing current
was proportional to the output current, the balancing duration was shorten to around
1000 s by increasing the load power. Fig. 5.11c indicates that balance state was
attained throughout the modulation index range simulated in setting-6. The behavior
of the current allocation in switch-ladder inverter and the SCMLI conformed to the
analytical prediction.
THD ≈ 6.61%
vo [V]
THD ≈ 0.80%
io [A]
∆VC1
VC [V]
∆VC3
∆VC2
Time [s]
Fig. 5.10. Simulated output voltage, current and switched-capacitor voltage

waveforms of the modified hybrid MLI.
135
B1 B2 B3 B4
SOC
B1 B2 B3 B4
VB [V]
Time [s]
(a)
SOC
B1 B2 B3 B4
VB [V]
B1 B2 B3 B4
Time [s]
(b)
136
B1 B2 B3 B4
SOC
B1 B2 B3 B4
VB [V]
Time [s]
(c)
Fig. 5.11. The battery SOC and voltages throughout the discharge process; in (a)
simulation setting-4; (b) setting-5 and (c) setting-6.
In order to validate the operation of the modified hybrid SCMLI topology and
the current allocation technique, the experimental study on the SCMLI prototype with
four 350 F electric double-layer capacitor (EDLC) cells was conducted. The current
allocation function was implemented into an STM32F446 microcontroller. The EDLC
cell voltages were acquired by the STM32F446 board through the CAN-bus interface
with an LTC6803 based battery monitoring unit (BMU). The voltage data acquisition
and sorting function were performed with an interval of about 0.1 s, while the output
voltage frequency and modulation index were fixed at 400 Hz and 0.65, respectively.
The major components of the experimental set-up are shown in Fig. 5.12; the
parameters of the prototype are listed in Table 5.3.
137
5
4
3
Not connected
1 2
B4 B3 B2 B1
Fig. 5.12. Major components of the experimental set-up; (1) 350 F EDLC cells
and fused terminals; (2) hybrid SCMLI prototype; (3) gate driver boards; (4)
LTC6803 based cell monitoring circuit; (5) STM32F446 microcontroller board
and CAN-bus module.
Table 5.3. Parameters of the experimental MLI prototype.

Parameter Value
MLI topology Modified hybrid SCMLI (Fig. 5.2)
Number of cells 4
Type of cells 350 F 2.7 V EDLC
Switched-capacitor, C 2×470 μF aluminium electrolytic
Input filter capacitors 100 μF aluminium electrolytic and 10 μF MLCC
n-channel MOSFETs:
Switches T00, ..., T24: NTD5867NL 60 V, 20 A, 39 mΩ
Q11, ..., Q22: IRF540N 100 V, 33 A, 44 mΩ
The EDLC cells, B1, B2, B3 and B4, were charged to the initial voltages of about
2.3 V, 2.4 V, 2.7 V and 2.6 V, respective; and subsequently discharged to an inductive
load of 10Ω-1mH through the MLI prototype with current allocation control. The
output voltage, current and switched-capacitor voltage waveforms were captured.
138
vo: 10V/div
io: 2A/div
vc: 4V/div
Time base: 1ms/div
Fig. 5.13. Output voltage, current and capacitor voltage waveforms of the MLI
prototype at 400 Hz operation.
As illustrated in Fig. 5.13, a 15-level staircase voltage waveform with peak
voltage of 16.2 V was produced by the hybrid SCMLI prototype. The voltage of the
SC unit was maintained by the parallel operation at the zeroth and fourth levels. Due
to the ESR voltage drop across the capacitor, the measured peak ripple was about
0.95 V which was a bit larger than the theoretical value. The cell voltages during the
discharge process were measured and plotted in Fig. 5.14a. Then, the cells were
charged to the aforementioned initial voltage and the EDLC string was connected to
a power source with constant voltage and current settings of 10 V and 1 A.
Simultaneously, the MLI was connected to the load and activated. The cell voltages
were recorded and plotted in Fig. 5.14b. With the current allocation control, the cell
voltages converged at both set-ups within 300 s. Fig. 5.15 shows the measured cell
voltages at a dynamic condition of varied load and charging current. At the beginning,
the EDLC cells were discharged through the SCMLI prototype to a 20Ω-1mH load,
which was then switched to 10Ω-1mH at t1=120s. The charging power source was
applied to the EDLC string at t2=240s; and the load was switched to 20Ω-1mH at
t3=360s.
139
B1 B2 B3 B4
Cell Voltage, VB [V]
Time [s]
(a)
B1 B2 B3 B4
Time [s]
(b)
Fig. 5.14. Measured voltages of the EDLC cells throughout the discharge
process with current allocation control; (a) without charging current; (b) with a
charging source connecting to the EDLC string.
140
t1 t2 t3
B1 B2 B3 B4
Time [s]
Fig. 5.15. Measured voltages of the EDLC cells under a dynamic
loading condition.
With the current allocation technique, the SCMLI prototype was able to balance
the voltages of EDLC cells and maintain a balance state throughout the varied load
condition. Since the balancing current was dependent on the load current, comparing
to the constant load condition in Fig. 5.14a, slightly longer duration was required in
the varied load condition, as the load during the first 120 s was lighter. Besides,
fluctuation of cell voltages were measured due to the 800 Hz ripple current produced
at the positive and negative cycles of the 400 Hz single phase setting. The voltage
sensing error could affect the balancing precision. In practical implementation with
large cells, this issue would be improved by the reduced cell internal resistances and
increasing the sizes of the input filter capacitors.
5.5. Summary
This chapter presents a current allocation method for charge balancing in the
multilevel inverter working with series-connected source string. The analysis and
design of the current allocation with different types of MLI topologies are elucidated
141
by the switching states and mathematical representation of the cell current under the
nearest switching staircase modulation. In order to achieve charge balance at a wide
range of modulation indices, the bidirectional switched converter in the hybrid
SCMLI is substituted by the switch-ladder so that a higher number of redundant
switching states is allowed. The effectiveness of the current allocation control and the
operation of the modified topology are studied with the simulation models of a switch-
ladder MLI and a hybrid SCMLI with four battery cells as well as the experiment on
the SCMLI prototype with four EDLC cells.
Balance state of four cells with the switched-ladder at the modulation index of
0.35 was attained in the simulation setting; cell balance for the SCMLI at 0.65
modulation index was demonstrated in both simulation and experimental setups. By
implementing a sorting function to activate the corresponding switch legs at different
output levels according to the measured cell voltages or SOC, the charges of the cells
in a series-connected energy source string can be balanced during discharging to AC
loads.
In the next chapter, development of various SCMLI topologies aiming at
reducing the voltage rating of components and increasing the feasibility of modular
design will be discussed.
142
Chapter 6 Modular SCMLI
Chapter 6
Development of SC MLIs Offering Modularity in Design
The series-parallel SC technique offers an innovative approach to develop MLIs with
voltage step-up and capacitor self-balance features. However, typical series-parallel
SC cells are only capable of providing DC voltage steps. As a result, most of the
existing SCMLIs produce an AC output with an H-bridge inverter having the same
voltage stress as the peak output voltage. This declines one major benefit of voltage
stress reduction offered by many other MLI topologies.
In this chapter, various approaches to eliminate the high voltage H-bridge in
SCMLI are investigated. The SCMLI topologies with the two-phase structure, bi-
polar series-parallel H-bridge cells, and cross-switched structure with respective
features in circuit simplicity and redundancy are developed. Circuit description and
the working principles of the proposed SC inverter topologies are discussed. Also, the
pros and cons of these inverters are compared. By limiting the voltage stress of
components to an identical level, the derived modular approaches offer increased
feasibility and scalability of SC power conversion. Along with the development of
wide-bandgap semiconductor technology, the modular SCMLI provides a promising
alternative for eliminating the step-up transformer in higher voltage AC system.
143
6.1. Configuration of Typical SC MLIs
The switched-capacitor (SC) inverters boost the output voltage levels by employing
the SC technique which is very similar to the charge-pump circuits or SC DC-DC
converters. The early development of this type of multilevel inverter (MLIs) was
demonstrated by Mak et al. [52]. In recent year, the generalized series-parallel SC
conversion technique for generating multilevel voltage steps was formulated by
Hinago et al. [53] that an extra DC voltage step can be produced by a series-parallel
SC cell as shown in Fig. 6.1.
S3
S2 C
Vo
VS
S1
(a) (b) (c)

Fig. 6.1. A series-parallel SC cell; (a) a basic SC cell; (b) series operation to
produce approximately 2VS at Vo; (c) parallel operation to charge the capacitor
and output approximately VS.
As the series-parallel SC conversion technique is directly derived from the
configuration of the double-mode SC cell in SC DC-DC converters. A typical series-
parallel SC cell is only capable of providing unipolar voltage at a fixed step-up ratio.
As a result, the existing series-parallel conversion based step-up SCMLIs [52, 56, 59,
61, 142, 148, 174] are generally composed of an SC DC-DC multilevel converter and
an H-bridge inverter (Fig. 6.2). However, these SCMLI topologies have limited
system modularity due to the dramatic increase in voltage stress of the H-bridge
144
inverter with the growing numbers of SC units and output voltage levels. Although
employing a single inverter back-end for generating bipolar output voltage can
substantially save the component count, this would negate the benefit of voltage rating
reduction offered by the multilevel setting.
SC Q12 Q22
Multilevel
VS Converter Vo
Q11 Q21
Fig. 6.2. A typical SCMLI employing an SC multilevel converter and

an H-bridge inverter.
VSn
SC
Multilevel
VSn Converter SC
Multilevel
Converter
VS2
SC Vo
Multilevel
Vo SC
VS2 Multilevel
Converter
Converter
VS1
SC
SC Multilevel
Multilevel Converter
VS1 Converter
(a) (b)
Fig. 6.3. The SCMLIs with hybrid configurations; (a) employing CHBI;
(b) employing cross-switched inverter.
145
Besides, there are a number of hybrid configurations [56-58, 62] which combine
the ideas of cascaded H-bridge inverter (CHBI) [75] or cross-switched inverter [128,
180-182] with SC converters (Fig. 6.3). By employing hybrid configurations, these
SCMLIs offer high degree of modularity and enable the ideas of asymmetric input
voltages [57, 62] that dramatically increase the number of output levels and improve
the power quality. Although these configurations offer additional benefits and
effectively reduce the maximum voltage stress of components, similar to the
traditional CHBI or cross-switched inverter, independent DC voltage sources are
required. For this reason, the hybrid configurations weaken the main advantage of the
single source step-up feature offered by SCMLI.
6.2. Elimination of the High Voltage H-bridge
In order to eliminate the need of high voltage H-bridge, at the same time, preserve the
advantages of single source voltage step-up and self-balancing. A number of
approaches are developed to produce bipolar output without a high voltage inverter as
the output stage.
6.2.1. Two-phase Structure
Wen et al. [77] investigated the synthesis of multilevel inverters with typical converter
building blocks. Similar idea can also be adopted to form SCMLIs with basic SC cells.
Fig. 6.4a shows a generalized SC multilevel converter based on the series-parallel
conversion technique presented in [53]. Instead of employing a high voltage H-bridge
across the output of the SC multilevel converter, bipolar output voltage can be
implemented by using a two-phase structure showing in Fig. 6.4b.
146
S(n+1)2
Sn3
Sn2 Cn S(n+1)1
S23
Sn1
S22 C2 Vo
S13
S12 C1 S21
VS
S11
(a)
Vo
S(n+1)2a S(n+1)2b
Sn3a Sn3b
S(n+1)1a Cna Sn2a Sn2b Cnb S(n+1)1b
S23a S23b
Sn1a Sn1b
C2a S22a S22b C2b
S13a S13b
S21a C1a S12a S12b C1b S21b
S11a
VS S11b
(b)
Fig. 6.4. A generalized SCMLI with a two-phase configuration; (a) an SC phase
leg formed by n SC cells; (b) a single-phase (2n+1)-level SCMLI formed by
two SC phase legs.
In a phase leg shown in Fig. 6.4a, the switched-capacitors, Ck, are charged when
the switches, Sk1 and Sk3, conducted. The voltage ratings of the capacitors and each of
the switches are limited to the same level as the source voltage. Fig. 6.4b illustrates a
single-phase SCMLI formed by two SC phase legs; the phase leg shown on the left is
defined as “phase-a” whereas the right SC leg is defined as “phase-b”. When positive
147
voltage is produced at phase-b while the voltage across phase-a is zero, positive output
voltage across Vo is generated, and vice versa. An SCMLI with 2n SC units is capable
of generating 2n+3 output levels with a maximum voltage range of ±(n+1)VS. Table
6.1 lists the working states of the SC cells and switches for a (2n+3)-level
configuration; Fig. 6.5 elucidates the working principle of a two-phase structured
SCMLI for the synthesis of specific output levels.
Table 6.1. Working states of a (2n+3)-level SCMLI with a two-phase structure.*
S(n+1)1a, S(n+1)2a, S(n+1)1b,

Vo C1a, C2a, …, Cna C1b, C2b, …, Cnb
S(n+1)2b
1, 0, 1, 0
0 P, P, …, P
0, 1, 0, 1
VS P, P, …, P
S, P, …, P
2VS
P, P, …, P P, …, P, S
1, 0, 0, 1
S, S, P, …, P
3VS
P, …, P, S, S
⋮ ⋮
(n+1)VS S, S, …, S
− VS P, P, …, P
S, P, …, P
−2VS
P, P, …, S
S, S, …, P P, P, …, P 0, 1, 1, 0
−3VS
P, P, …, S
⋮ ⋮
−(n+1)VS S, S, …, S
*S: series; P: parallel; 1: on; 0: off
148
(a)
(b)
(c)
149
(d)
Fig. 6.5. Working principle of the SCMLI with a two-phase structure; (a) zero
output voltage; (b) attaining output Vo=VS; (c) attaining output Vo=(n+1)VS;
(d) attaining output Vo=−(n+1)VS;
6.2.2. Cascaded Structure with Bipolar Series-parallel Conversion
S3 S3
C
VS S2
Vo Vo
S2
VS C
S1
S1
(a) (b)
Fig. 6.6. Varieties of a series-parallel SC cell; (a) positive stacking during series
operation; (b) negative stacking during series operation.
S2 S4 S6
VS C
S1 S3 S5
Fig. 6.7. A bipolar series-parallel SC cell combing positive and negative

stack operations.
150
Although the high voltage H-bridge can be eliminated by the two-phase structure,
comparing to the conventional SCMLIs, the number of SC cells in the two-phase
structure is doubled. In fact, depending on the position of the capacitor and switches,
the series-parallel SC cell can be differentiated between “positive stacking”, that the
series voltage shares the same negative terminal as the source voltage (Fig. 6.6a), and
“negative stacking” that the series voltage shares the same positive terminal as the
source voltage (Fig. 6.6b). By combining these two series-parallel conversion
techniques, a bipolar series-parallel SC cell (Fig. 6.7) is derived. With the bipolar
series-parallel SC cell shown in Fig. 6.7, VS and its double level can be produced from
the negative terminal of the voltage source to the positive terminal of the capacitor;
also, −VS and −2VS can be produced from the positive terminal of the voltage source
to the negative terminal of the capacitor. The working principle of a bipolar series-
parallel SC cell is illustrated in Fig. 6.8.
(a) (b) (c)

Fig. 6.8. Working principle of the bipolar series-parallel SC cell; (a) parallel
operation for ±VS output; (b) positive stacking for 2VS output; (c) negative
stacking for −2VS output
By cascading the bipolar SC cells and adding a half-bridge at both ends, a new
cascaded SCMLI topology (Fig. 6.9) is derived. With this configuration, the voltage
151
ratings of the capacitors and switches can also be limited to VS. The working states of
a (2n+3)-level cascaded SCMLI are listed in Table 6.2.
A bipolar SC cell
S02 S12 S14 S16 S22 S24 S26 Sn2 Sn4 Sn6 S(n+1)2
VS C1 C2 Cn
S01 S11 S13 S15 S21 S23 S25 Sn1 Sn3 Sn5 S(n+1)1
Vo
Fig. 6.9. A cascaded SCMLI topology constituted of bipolar SC cells and

half-bridges.
Table 6.2. Working states of the cascaded SCMLI.*
Vo C1, C2, …, Cn S01, S02, S(n+1)1, S(n+1)2

1, 0, 1, 0
0 P, P, …, P
0, 1, 0, 1
VS P, P, …, P
S+, P, …, P
2VS
P, …, P, S+
S+, S+, P, …, P 1, 0, 0, 1
3VS
P, …, P, S , S + +
⋮ ⋮
(n+1)VS S+, S+, …, S+
−VS P, P, …, P
S−, P, …, P
−2VS
P, …, P, S−
S−, S−, P, …, P 0, 1, 1, 0
−3VS
P, …, P, S−, S−
⋮ ⋮
−(n+1)VS S−, S−, …, S−
*S+: positive stacking; S−: negative stacking; P: parallel; 1: on; 0: off
152
6.2.3. Cross-switched Structure
Comparing to the two-phase structure, the number of capacitors can be reduced by
employing the bipolar series-parallel SC cells. However, similar to the
implementation of a CHBI, the individual bipolar operation of cells requires a high
number of active switches. In recent year, the cross-switched technique was developed
by Kangarlu et al. [181, 182] and Gupta et al. [128] which has dramatically reduced
the component count in cascaded MLIs. By eliminating the redundant switching states,
the active switches in adjacent cells in CHBI can be combined together to form the
cross-switched structure. The major drawbacks of the cross-switched inverter are the
doubled voltage rating of switches and reduced number of redundancy.
Based on the cross-switched technique, a new cascaded SCMLI is developed to
reduce the number of active components compared to the aforementioned varieties.
As depicted in Fig. 6.10, the cross-switched SCMLI consists of three parts: 1) a triple-
half-bridge front-end connecting to the DC voltage source, 2) SC units, and 3) a half-
bridge back-end connecting to the last SC unit and the AC output terminals.
Triple-half-bridge SC Unit Half-bridge

Front-end Back-end
S12 S22 S(n-1)2 Sn2
S02 S04 S06 S(n+1)2

C1 C2 C(n-1) Cn
VS
S01 S03 S05 S11 S13 S21 S23 S(n-1)1 S(n-1)3 Sn1 Sn3 S(n+1)1
Vo
Fig. 6.10. Generalized topology of the cross-switched SCMLI.
153
(a)
(b)
(c)
(d)
(e)
(f)
Fig. 6.11. Working principle of the cross-switched SCMLI; (a) charging odd SC
units; (b) charging even SC units; (c) positive stacking; (d) negative stacking;
(e) and (f) bypassing the SC units.
154
Table 6.3. Working states of the cross-switched SCMLI.
Vo ‘ON’ Switches C1, C2, …, Cn*

S01, S04, S11, S13, S21, S23, ..., S(n−1)1, S(n−1)3,
(n+1)VS D, D, ..., D, D
Sn1, Sn3,S(n+1)2
S01, S03, S06, S11, S12, S13, S21, S23, ..., S(n−1)1,
C, D, ..., D, D
S(n−1)3, Sn1, Sn3,S(n+1)2
nVS
S01, S04, S11, S13, S21, S23, ..., S(n−1)1, S(n−1)3,
D, D, ..., D, B
Sn1, Sn3,S(n+1)1
S01, S04, S05, S11, S12, S21, S22, S23, ..., S(n−1)1,
B, C, ..., D, D
(n−1)VS S(n−1)3, Sn1, Sn3,S(n+1)2
S01, S04, S11, S13, S21, S23, ..., S(n−1)1, Sn2,S(n+1)2 D, D, ..., B, B
⋮ ⋮ ⋮
S01, S03, S06, S11, S12, S13, S21, S22, ..., S(n−1)1,
C, B, ..., C, D
2VS S(n−1)2, S(n−1)3, Sn1, Sn3,S(n+1)2
S01, S04, S11, S13, S21, ..., S(n−1)2, Sn1,S(n+1)1 D, B, ..., B, B
S01, S04, S05, S11, S12, S21, S22, S23, ..., S(n−1)1,
B, C, ..., B, C
S(n−1)2, Sn1, Sn2, Sn3,S(n+1)2
VS
S01, S03, S06, S11, S12, S13, S21, S22, ..., S(n−1)1,
C, B, ..., C, B
S(n−1)2, S(n−1)3, Sn1, S(n+1)1
S01, S04, S05, S11, S12, S21, S22, S23, ..., S(n−1)1,
B, C, ..., B, C
S(n−1)2, Sn1, Sn2, Sn3,S(n+1)1
0
S01, S03, S06, S11, S12, S13, S21, S22, ..., S(n−1)1,
C, B, ..., C, B
S(n−1)2, S(n−1)3, Sn2, S(n+1)2
S02, S04, S05, S11, S12, S21, S22, S23, ..., S(n−1)1,
B, C, ..., B, C
S(n−1)2, Sn1, Sn2, Sn3,S(n+1)2
−VS
S02, S03, S06, S11, S12, S13, S21, S22, ..., S(n−1)1,
C, B, ..., C, B
S(n−1)2, S(n−1)3, Sn2, S(n+1)2
S02, S03, S06, S11, S12, S13, S21, S22, ..., S(n−1)1,
C, B, ..., C, D
−2VS S(n−1)2, S(n−1)3, Sn2, Sn3, S(n+1)1
S02, S05, S12, S13, S22, ..., S(n−1)1, Sn2,S(n+1)2 D, B, ..., B, B
⋮ ⋮ ⋮
S02, S04, S05, S11, S12, S21, S22, S23, ..., S(n−1)2,
B, C, ..., D, D
−(n−1)VS S(n−1)3, Sn2, Sn3, S(n+1)1
S02, S05, S12, S13, S22, S23, ..., S(n−1)2, Sn1,S(n+1)1 D, D, ..., B, B
S02, S03, S06, S11, S12, S13, S22, S23, ..., S(n−1)2,
C, D, ..., D, D
S(n−1)3, Sn2, Sn3, S(n+1)1
−nVS
S02, S05, S12, S13, S22, S23, ..., S(n−1)2, S(n−1)3,
D, D, ..., D, B
Sn2, S(n+1)2
S02, S05, S12, S13, S22, S23, ..., S(n−1)2, S(n−1)3,
−(n+1)VS D, D, ..., D, D
Sn2, Sn3, S(n+1)1
*B: bypass; C: charge; D: discharge
155
The working principle of a cross-switched SCMLI with an even number n is
illustrated in Fig. 6.11. The H-bridge front-end and the SC units form the bipolar
series-parallel circuits for charge refreshing, voltage step-up as well as voltage
inverting. Owing to the cross-switched structure, C(odd) are charged to VS by
conducting the S(odd)3 when forward voltage is applied through S03 and S06; on the
other hand, C(even) are charged by conducting S(even)3 when inverted voltage is applied
through S04 and S05. Positive voltage is produced across the SC units by conducting
Sk1 and Sk3, while negative voltage is produced by conducting Sk2 and Sk3. Besides,
the SC units can be bypassed by turning off Sk3. Table 6.3 lists the corresponding
working states of the capacitors and the switches for a (2n+3)-level cross-switched
SCMLI with even n number SC units.
6.3. Comparative Study
In the above section, three different configurations have been presented to eliminate
the need of a high voltage H-bridge in SCMLI. Although the presented SCMLI
topologies share the main purposes of step-up DC-AC conversion with self-voltage-
balancing, each of the topologies owns varied parametric quantities in terms of the
number of components, redundancy and component stress. This diversified the
inverter performance and the preferences of applications. In the following, the key
features of these three SCMLI variances will be discussed and compared.
The key parameters of the SCMLI varieties are summarized in Table 6.4. By
eliminating the need of a high voltage H-bridge, the maximum voltage stress of the
components in the SCMLI is dramatically reduced. In the two-phase structure, as the
voltage of all active switches are clamped by the DC voltage source or capacitors
156
through the half-bridge setting, the voltage stress of the switches are essentially
limited to the same level as the DC source. However, the main drawback of employing
the two-phase structure is that the numbers of SCs and active switches are doubled
compared to the traditional counterparts. By combining the positive and negative
series operations of SC cells, the cascaded structure with bipolar SC cells preserves
the same number of SCs as the traditional SCMLIs while limits the voltage stress to
the source voltage level. Unlike the two-phase structure, the switches Sk5 and Sk6 in
the bipolar SC cells are clamped neither by a capacitor nor the voltage source. In
contrast, these switches are clamped indirectly between two adjacent capacitors or
voltage sources through the active switches Sk1 and Sk4. As a result, the maximum
voltage stress of switches Sk5 and Sk6 can increase to 2VS during malfunctioned
switching states. For this reason, additional considerations are required in designing
the switches order and voltage limitation to ensure the system robustness. On the other
hand, the number of active switches in a bipolar SC cell is halved in the cross-switched
structure. The maximum voltage across the active switches in the SC cells is indirectly
clamped by two adjutant capacitors through two body-diodes of the MOSFETs. This
results a voltage stress of 2VS for the switches in the SC cells whereas the maximum
voltage of the half-bridge switches are clamped by the voltage source or the last
capacitor, which is essentially the same level as VS.
The total voltage stress of all switches indicates the efficiency of utilizing the
semiconductor materials in constructing the inverter; whereas the total voltage stress
of the conducting switches specifies the conduction loss due to the non-ideality of
semiconductor devices. Although the proposed topologies requires a higher number
157
of active switches compared to the typical series-parallel SCMLI topology [53], the
sums of voltage ratings of all semiconductor switches required in the two-phase and
cascaded variations are actually lower because of eliminating the high voltage H-
bridge. The switch voltage in the cross-switched variation are clamped to a maximum
value of 2VS, resulting a lower sum of voltage ratings than the typical SCMLI when
n>4. In general, the conduction loss of semiconductor switches is positively related to
the blocking voltage. Therefore, the total blocking voltage of the conducting switches
can also be a performance indicator of the conversion efficiency. In this point of view,
two-phase and cascaded structured SCMLIs outperform the typical topology, while
the proposed cross-switched SCMLI would suffer from a higher conduction loss.
Another important performance consideration is the availability of redundant
switching states. The switching state redundancy not only improves the fault-tolerant
ability, control flexibility and reduces the number of switching transitions of the
inverter [183, 184], it also potentially increases the allowable charge-up duration of
the SC cells that improves the charge-up efficiency and increases the maximum
operating frequency. The interleaved operation of the phase-legs in the two-phase
structure ensures that the minimum charge-up duration for all the SC cells would be
at least a half of the fundamental period regardless of the modulation index and
number of levels. This feature makes it highly preferable for the applications requiring
a higher fundamental frequency. Along with the reduced redundancy in the number
of SC cells, the cascaded variation has the same capacitor charge-up duration as the
conventional series-parallel SC inverter. On the other hand, the charging operation in
the cross-switched structure would be a bit tricky. The odd SC cells and the even SC
158
cells can only be charged separately. This reduces the average charging duration of
capacitors.
Table 6.4. Key parameters of different SCMLI topologies.
Cross- Typical
Two-phase Cascaded
Parameters switched Series-
(Fig. 6.4) (Fig. 6.9) parallel
(Fig. 6.10)
Number of output
2n+3
levels
Maximum output
(n+1)VS
voltage
Number of switched-
2n n
capacitors
Voltage stress of
VS
switched-capacitors
Number of switches 6n+4 3n+8 3n+4
Maximum voltage
VS 2VS (n+1)VS
stress of switches
Total voltage stress of
(6n+4)VS (6n+8)VS (7n+4)VS
switches
Total voltage stress of
(2n+2)VS (4n+3)VS (3n+2)VS
conducting switches
Number of effective
4n+1 4∙3n 2∙(Kn+Kn−1) 2n+1+2
switching states*
*Kn=2Kn−1+2Kn−2+Kn−3, where K−3=−1; K−2=0; K−1=1; K0=1; K1=4,…,etc.
6.4. Simulation Study and Experimental Results
In order to study the switching state and control implementation for realizing different
output voltages, as well as to compare the performance of the proposed SCMLI
varieties, simulation study on the 9-level SCMLI models based on the proposed
topologies was conducted. The voltage ripples of the SC cells and the efficiency of
the SCMLIs under different operating frequencies and loading conditions were
159
investigated. The parameters of the simulation model are listed in Table 6.5. An ideal
voltage source of 100 V was used to drive the 9-level MLI topologies which produced
the staircase output with a peak voltage of about 400 V. Capacitance of 1000 μF was
decided to achieve about 90% efficiency for 1 kW output at the 50 Hz operation. All
the capacitors had identical constant equivalent series resistance (ESR) of 0.1 Ω; the
on-state resistance, Rds(on), of the MOSFETs was directly proportional to the maximum
blocking voltages; the switching loss was modeled by a parallel capacitance of 0.2 nF.
Table 6.5. Parameters of the 9-level SCMLI simulation models.
Parameters Values
Source voltage (VS) 100 V
C=1000 μF;
Capacitors
ESR=0.1 Ω
Rds(on)=50 mΩ (100 V)
MOSFETs Rds(on)=100 mΩ (200 V)
Coss=0.2 nF
The inverter output was modulated by the nearest switching staircase
modulation [159, 161]; the modulation index was fixed at 0.8. To make up a power
level of about 1 kVA, an inductive load of approximately 80 Ω with a lagging power
factor of 0.8 was connected to the output terminals of the 9-level SCMLI models.
Although all three topologies are fundamentally derived from the series-parallel SC
technique and modulated by an identical method, the performance such as the
conversion efficiency can be unequal because of the dissimilarity in switching state
implementation and the conduction loss of the switches in different SCMLI varieties.
The charge and discharge operation of the SC cells among these topologies can be
160
intuitively observed with the internal voltages of capacitors. The output voltage,
output current, and the capacitor voltage waveforms at different frequency settings
and topologies are depicted in Fig. 6.12.
2P CC CS *
Vo (V)
Io (A)
VC (V)
CS: 22.98V 2P: 23.03V CC: 22.99V

C1 C2 C3
time (s)
(a)
2P CC CS *
Vo (V)
Io (A)
VC (V)
2P: 3.30V
CS: 6.65V CC: 5.50V
C1 C2 C3
time (s)
(b)
161
2P CC CS *
Vo (V)
Io (A)
VC (V)
2P: 1.73V CC: 4.55V

CS: 5.81V
C1 C2 C3
time (s)
(c)
2P CC CS *
Vo (V)
Io (A)
2P: 1.07V
VC (V)
CS: 5.42V CC: 4.18V
C1 C2 C3
time (s)
(d)
Fig. 6.12. Simulated output voltage, output current and switched-capacitor
voltage waveforms with different topologies and operating frequencies; (a)
50 Hz; (b) 400 Hz; (c) 1 kHz; (d) 5 kHz (*2P: two-phase structure;
CC: cascaded structure; CS: cross-switched structure)
162
As shown in Fig. 6.12, the output voltage and current waveforms generated by
different SCMLI topologies were apparently the same. With a modulation index of
0.8, the root-mean-square fundamental output voltage and current were approximately
286 V and 3.57 A, respectively. The internal capacitor voltage waveforms show that
the timings for charging and discharging of the SC in the two-phase and cascaded
SCMLI were similar. But the interleaved operation in the former structure allowed the
SC cells in phase-a only discharging during negative output half-cycle and charging
throughout the positive output half-cycle. On the other hand, with the cross-switched
structure, the odd and even SC cells could only be charged separately. In the 9-level
cross-switched SCMLI model, the charging timing for C1 was at the output falling
edge at ±3VS; this was changed-over to C2 at the falling edge at ±2VS; and then
changed back to C1 and C3 at zero-crossing. As a result, although the cross-switched
structure reduced the component count, it had the shortest SC charging among the
presented SCMLI topologies; while the two-phase structure provided the longest
charging duration. As indicated in Fig. 6.12, this resulted in different minimum SC
voltages, which affected the SC conversion efficiency.
At low frequency operation (50 Hz), the three topologies exhibited almost the
same voltage ripple magnitudes. The simulated voltage ripples of the capacitors, C 1,
C2 and C3 were about 14.2 V, 19.2 V and 23 V, respectively. The severe voltage
ripples distorted the output waveform and reduced the output voltage magnitude. The
charging termination voltage of the SC cells in all three configurations was very close
to VS. However, when the operating frequency increased to a higher value, the
distinction in charging durations were reflected by the voltage retaining capability of
163
the SC cells. At high frequency operation (5 kHz), although the ripple magnitudes
were approximately the same, which were about 0.2 V for different SCMLI
configurations, the discrimination in the charging termination voltage was significant.
In the two-phase structure, the maximum internal voltage for all the SC cells were
>99.16 V when driving the 1 kVA load at 5 kHz; while the maximum internal
voltages for C3 in the cascaded variant and C2 in the cross-switched variant were only
96.05 V and 94.78 V, respectively. This implied that the cross-switched SCMLI
would have the highest ripple loss at high frequency operation whereas the two-phase
SCMLI would have the lowest ripple loss.
The simulated total power loss of the capacitors and the conversion efficiency
of the SCMLIs under different loading conditions are plotted in Fig. 6.13 and 6.14,
respectively. In the simulation model, the skin effect was neglected as the switch
resistances and ESR of the capacitors were constant; the switching loss was
insignificant compared to the ripple loss of the capacitors. As suggested in chapter 4,
the ripple loss would be proportional to the square of the output current and inversely
proportional to the operating frequency. As a result, the power level of the SCMLIs
at low frequency is limited. This relationship could also be observed in this simulation
result. Besides, it can be observed that the proposed SCMLI variants have very similar
performance at low operating frequency. In the simulation models, the ripple power
loss was distributed to the parasitic resistances of the capacitors and the switches
accordingly. Although the capacitor voltage ripple magnitudes for the three topologies
were similar at 50 Hz operation, the simulated total capacitor power loss for the two-
phase structure was higher than that for the cascaded and the cross-switched
164
topologies. It was because the total on-state resistance of the conducting switches in
the charging path of the two-phase structure was lower than that of the two other
counterparts. As a result, more conduction power loss was contributed by the ESR of
the capacitors in the two-phase structure. But for the applications with higher line
frequency, the SCMLI with two-phase structure would have considerably higher
efficiency then the cascaded and cross-switched counterparts due to the dramatic
reduction in the capacitor ripple loss. To attain batter charge-up voltage, the charging
duration, Tch should be considerably larger than the RC time constant. It could be
accounted by the charging duration factor derived as (4.13) in chapter 4.
2P CC CS *
50Hz
capacitor power loss (W)
400 Hz
5 kHz
output power (W)
Fig. 6.13. Simulated total capacitor power loss for the three SCMLI variants at
different loading conditions. (*2P: two-phase structure; CC: cascaded structure;
CS: cross-switched structure)
165
2P CC CS *
5 kHz
efficiency
400 Hz
50Hz
output power (W)
Fig. 6.14. Simulated energy efficiency for the three SCMLI variants at different
loading conditions. (*2P: two-phase structure; CC: cascaded structure;
CS: cross-switched structure)
Furthermore, the operation of the proposed topologies was verified by the
experiment on the 9-level SCMLI prototypes. The SCMLI prototypes consisted of SC
modules with a 1000 μF electrolytic capacitor each. The input DC voltage source was
filtered by an electrolytic capacitor. The half-bridges clamped by the capacitors in the
two-phase structure and the cascaded structure were constituted by IRF540N and
IRF540S n-channel MOSFETs, respectively. The higher voltage switches were
implemented by FDP51N25. A picture of the hardware prototype is depicted in Fig.
6.15; the parameters of the prototype are listed in Table 6.6.
166
Fig. 6.15. Prototype of the 9-level SCMLI; (1) gate driving circuits;
(2) 9-level SCMLI prototype.
Table 6.6. Parameters of the 9-level SCMLI prototype.
Parameters Values
Source voltage (VS) 42 V
Switched-capacitors 1000 μF electrolytic (loss tanδ≤0.2 @ 120 Hz)
Cross-switches (S11 to Sn3): FDP51N25
MOSFETs Half-bridges: IRF540S 100 V, 28 A, 77 mΩ /
IRF540N 100V, 33A, 44 mΩ
Operating frequency 50 Hz to 1000 Hz
The input voltage was fixed at 42 V; the operating frequency was varied by the
modulating period; the output power was altered by changing the values of the load
resistance. The output voltage and current, as well as the capacitor voltages of the 9-
level SCMLI prototypes under different settings were measured and the waveforms
are shown in Fig. 6.16 to 6.18.
167
Timebase:10ms/div
Vo:100V/div
Io:5A/div
VC2:20V/div
VC1:20V/div
(a)
Timebase:1ms/div
Vo:100V/div
Io:5A/div
VC2:20V/div
VC1:20V/div
(b)
Timebase:1ms/div
Vo:100V/div
Io:5A/div
VC2:20V/div
VC1:20V/div
(c)
Timebase:1ms/div
Vo:100V/div
Io:5A/div
VC2:20V/div
VC1:20V/div
(d)
Fig. 6.16. Measured waveforms of the 9-level two-phase SCMLI prototype;
driving (a) 100Ω-1mH load at 50 Hz; (b) 100Ω-1mH load at 400 Hz;
(c) 50Ω-1mH load at 400 Hz; (d) 50Ω-1mH load at 1 kHz
168
Timebase:10ms/div
Vo:100V/div
Io:5A/div
VC2:20V/div
VC1:20V/div
(a)
Timebase:1ms/div
Vo:100V/div
Io:5A/div
VC1:20V/div
VC2:20V/div
(b)
Timebase:1ms/div
Vo:100V/div
Io:5A/div
VC1:20V/div
VC2:20V/div
(c)
Timebase:1ms/div
Vo:100V/div
Io:5A/div
VC1:20V/div
VC2:20V/div
(d)
Fig. 6.17. Measured waveforms of the 9-level cascaded SCMLI prototype;
169
Timebase:10ms/div
Vo:100V/div
Io:2A/div
VC2:20V/div
VC1:20V/div
(a)
Timebase:1ms/div
Vo:100V/div
Io:2A/div
VC2:20V/div
VC1:20V/div
(b)
Timebase:1ms/div
Vo:100V/div
Io:5A/div
VC2:20V/div
VC1:20V/div
(c)
Timebase:0.4ms/div
Vo:100V/div
Io:5A/div
VC2:20V/div
VC1:20V/div
(d)
Fig. 6.18. Measured waveforms of the 9-level cross-switched SCMLI prototype;
170
The measured waveforms show that the prototypes were able to produce 9-level
staircase voltage waveforms with the proposed two-phase, cascaded and cross-
switched structures. As expected, both switched-capacitors, C1 and C2, started
discharging with the two-phase and cascaded structures at the rising edge of about
±80 V, whereas the capacitors discharged sequentially with the cross-switched
structure. The measurement indicated a positive relationship between the charging
duration and the average capacitor voltage. Unlike the simulation model, the measured
voltages, VC1 and VC2, were the external voltages measured across the electric
terminals. The additional parallel operation of C1 and C2 caused charging current spike
from C1 to C2, resulting in measured voltage drop with the ESR. Therefore, the
measured voltage ripple magnitudes were slightly higher than that of the simulation
results.
2P CC CS *
1 kHz
efficiency
400 Hz
50Hz
output power (W)
Fig. 6.19. Measured efficiency of the SCMLI prototypes

(*2P: two-phase structure; CC: cascaded structure; CS: cross-switched structure)
171
Also, the conversion efficiency of the prototypes was investigated by comparing
the measured input and output power values. As shown in Fig. 6.19, because of
reduced capacitor ripple magnitudes, the measured efficiency of the inverter
prototypes was higher at 400 Hz and 1 kHz compared to the 50 Hz operation; yet the
efficiency improvement of increasing the operating frequency beyond 400 Hz was
insignificant with the cascaded and cross-switched structures. Moreover, as predicted
in the simulation study, the two-phase SCMLI generally has lower conversion energy
loss than the other variants at high-frequency operation due to the longer charging
duration. This could also be reflected as the higher measured average capacitor
voltage.
6.5. Summary
In this chapter, three SCMLI variants are presented to eliminate the need of a high
voltage H-bridge for step-up DC-AC power conversion. By decreasing the voltage
stress of the components to an identical low voltage level, high voltage AC output can
be generated with a low voltage DC source and low voltage converter modules. With
the two-phase structure, bipolar output voltage is generated by the differential voltage
between two DC SC phase legs. By combining the positive stacking and negative
stacking of SC series-parallel operation into one SC cell, multilevel AC voltage
waveform can be produced by cascading the bipolar series-parallel SC cells.
Moreover, the presented cross-switched SCMLI variant considerably reduces the
number of active components by employing the cross-switched structured existed in
isolated source based MLI.
172
Although there is an obvious advantage of the cross-switched SCMLI over the
two-phase and cascaded variants in view of component counts, the former structure
inherits the drawbacks of increased component voltage stress and reduced switching
state redundancy from component reduction. By comparing the features of these
SCMLI variants, the discrimination of energy efficiency and performance at high
frequency between the SCMLI structures was investigated; also, the simulation and
experimental outcomes suggest that due to the limitation of RC time constant, the
allowable duration for SC charging can be an important factor in determining the
energy efficiency at high frequency operation.
The analysis on the ripple loss of the SCMLI in previous chapters has indicated
that the charge-up loss of SC cells is inversely proportional to the operating frequency.
On the other hand, the maximum operating frequency of the SCMLI is limited by the
RC time constant for charging operation. Based on the simulation result at 5 kHz, with
an identical capacitor size, the two-phase structure could maintain about 97%
efficiency at 2 kW, while the efficiencies for the cascaded and cross-switched
structures were about 94% and 90%, respectively. This suggests that the two-phase
structure has higher potential in constructing a high power SCMLI at higher operating
frequency beyond several kilo-hertz. In the next chapter, development of a high
frequency SCMLI based on the two-phase structure with soft-charging technique will
be investigated. By further increasing the operating frequency as well as reducing the
SC charge-up loss by the proposing soft-charging technique, implementation of a
modular SCMLI for kilo-watts applications can be realized.
173
Chapter 7 Soft-Charging SCMLI
Chapter 7
Design of a Soft-Charging SC MLI with Reduced Ripple Power Loss
In addition to several attractive features such as voltage step-up and self-balance
offered by the series-parallel SC technique, the two-phase structured SCMLI holds
the benefits of producing high output voltage with low voltage components. However,
the ripple power loss issue could hinder the practicability of the SCMLI for higher
power applications. The ZCS technique has been employed in SC DC-DC converters
which exhibited a significant improvement on the SC conversion efficiency. By
extending the idea of ZCS SC technique, the ripple power loss of the SCMLI can be
dramatically reduced by realization of soft-charging SC units with a small resonant
inductor.
This chapter presents the design of a soft-charging SCMLI based on the two-
phase structured topology with quasi-resonant technique. With the simplified
equivalent series RLC circuit of the SC charging path, the performance of the soft-
charging operation can be predicted with the damping factor easily. The design criteria
for achieving soft-charging with underdamped resonance are discussed; the operation
of the inverter and the efficiency enhancement of the soft-charging technique were
verified by the simulation and experiment on a 9-level SCMLI prototype.
174
7.1. Background of Developing Soft-Charging Technique for
SCMLI
Proliferated research attention has been paid on the SC based MLIs featuring self-
balance of the capacitor voltages [53, 56, 60-62, 148, 174, 185]. By employing the
series-parallel conversion technique, the SCMLIs can provide voltage step-up
capability without bulky transformer. The capacitor voltages are refreshed directly by
the DC source voltage which eliminates the necessity of complicated control of the
capacitor voltage [53, 61]. Although the current handling capability of SCMLIs is
inherently limited by the sizes of the capacitors, the study in [59, 61, 148] has shown
the potential of SCMLIs in high-frequency AC (HFAC) applications. However, the
use of unfolding H-bridge in most existing SCMLIs topologies weakens the benefit
of voltage stress reduction and modularity in MLIs; the huge current spikes during
hard-switched parallel operation lead to additional concern of ripple power loss [59,
62] and EMI issue.
In the previous chapter, a set of SCMLI topologies are proposed which reduced
the component voltage stress by eliminating the high-voltage unfolding H-bridge.
Among the three configurations, the two-phase structured SCMLI shows high
potential in HFAC applications of several kilo-hertz. Although the two-phase
structure results in a higher number of switches and capacitors, the drawback of high
component count is offset by the substantial diminution of voltage and current stresses
as well as the required capacitor sizes. The interleaved operation of two phase-legs
can substantially extend the charging duration of the SC units which improves the
high frequency performance of the inverter. Yet, the ripple loss of the capacitors still
175
contributes to a considerable portion of power loss at high power. The ripple power
loss is the inherent result of paralleling two mismatched voltage sources. Regardless
of the switch resistance or the ESR of the capacitors, the charge-up energy loss would
be determined by the magnitude of the voltage-gap [28, 29, 42]. As a result, the
conversion efficiency of SC circuits declines with output current. This theory also
holds for the series-parallel SC based MLIs. The ZCS SC resonant DC-DC converters
[11, 12, 26, 44, 45] shows a dramatic improvement on the conversion efficiency. In
the traditional hard-switched SC converters, the residue energy brought by the
voltage-gap is fully dissipated by the parasitic resistive elements. On the other hand,
by inserting a small inductive element in the SC circuit, part of the residue energy can
be temporary stored as inductive energy. If underdamped condition is fulfilled [26],
part of the inductive energy can be transferred to the capacitor in the ZCS SC resonant
converter which results in substantially increased efficiency.
To address the issue of ripple power loss, the idea of resonant SC converters can
be extended to the series-parallel SC based MLI. With an additional inductive
component, part of the charge-up energy loss could be remedied by the soft-charging
operation. Similar to the resonant SC DC-DC converter, the soft-charging criteria can
also be represented as the underdamped condition, thus, the performance can be
evaluated with the damping factor for the equivalent RLC circuit of the SC charging
path. By introducing the soft-charging technique, the practicability of SCMLIs would
be strengthen not only by the efficiency improvement, but also the mitigation of EMI
caused by the SC charging current spikes.
176
7.2. Circuit Description and Operating Principles
(a) (b)
Fig. 7.1. A basic series-parallel SC unit; (a) parallel operation for capacitor
charging; (b) series operation for voltage step-up.
A basic series-parallel SC unit and its operation [53] are illustrated in Fig. 7.1. Each
SC unit is constituted by a capacitor, C, a diode, D, and two complementary switches,
S1 and S2. To achieve ZCS without any precise frequency or duty cycle control, one
of the charging switches is substituted by a diode. The capacitor is charged from the
power source through the diode when S1 is conducting; the capacitor is stacked with
the preceding voltage source or capacitors and discharged to the load when S 2 is
conducting.
Fig. 7.2 shows the generalized topology of the proposed soft-charging SCMLI.
The two DC phase legs, phase-A and phase-B operate in an interleaved manner.
Letting k be the output level, positive output voltage +k is produced by conducting the
switches S12a, S22a, …, S(k−1)2a and Sn2a in the phase-A leg while the switches S11b,
S21b, …, S(n+1)1b in the phase-B leg are at on-state; whereas negative output voltage −k
is produced by conducting the switches S12b, S22b, …, S(k−1)2b and Sn2b in the phase-B
leg while the switches S11a, S21a, …, S(n+1)1a are at on-state. The working states of a
(2n+3)-level SCMLI with the proposed two-phase structure are listed in Table 7.1.
177
io
Load
S(n+1)2a S(n+1)2b
Dna Vo Dnb
Sn2a
S(n+1)1a Cna Sn2b Cnb S(n+1)1b
D2a D2b
Sn1a
...
...
Sn1b
Phase-A C2a S22a D1a D1b Phase-B

S22b C2b
Lr
S12a
S21a C1a S12b C1b S21b
S11a VS
S11b
Fig. 7.2. Generalized topology of the proposed soft-charging SCMLI with

a two-phase structure.
Table 7.1. Working States of the (2n+3)-level SCMLI with the

two-phase structure.*
Output level C1a, C2a, …, C1b, C2b, …, S(n+1)1a, S(n+1)2a, S(n+1)1b,
(Vo) Cna Cnb S(n+1)2b
(n+1)VS S, S, …, S
S, S, …, P, S
nVS
S, P, S, …, S
⋮ ⋮
1, 0, 0, 1
S, S, P, …, P
3VS
S, P, …, P, S P, P, …, P
2VS S, P, …, P, P
VS
1, 0, 1, 0
0
0, 1, 0, 1
−VS P, P, …, P
−2VS S, P, …, P, P
0, 1, 1, 0
⋮ ⋮
− (n+1)VS S, S, …, S
*S: Series; P: Parallel
178
The interleaved operation extends the charging duration of SC units by a half of
the fundamental output period. This substantially increases the maximum operating
frequency of the inverter. Besides, the magnitude of the charging current spikes is
reduced by inserting a small resonant inductor, Lr, into the charging path of the SC
units. As a result, the soft-charging operation with a more moderate current waveform
could mitigate the charge-up energy loss of the capacitors. In order to utilize the
resonant inductor, it is preferred to discharge the SC units to similar levels during
series operation. Therefore, as shown in Table 7.1, there gives different working states
for the rising and falling slopes. During the rising slope, the lower order SC units
would be connected in series while the higher order SC units are connected in parallel
so that the capacitor voltages tend to be ascending with the order number, i; on the
other hand, the SC units are connected in parallel from the lower order during the
falling slope which tends to balance the capacitor voltages.
7.3. Voltage Ripples and Analysis
The analysis of the capacitor voltage ripples establishes the foundation for
performance evaluation and understanding the soft-charging behavior of the inverter.
In this section, the representation of the capacitor voltage ripple magnitude is derived
based on the nearest switching staircase modulation stated in the previous chapters
and the switching states suggested in Table 7.1. The soft-charging behavior is
elucidated with the equivalent simplified RLC circuit of the SC network. Along with
the mathematic analysis, the performance and criteria for the soft-charging operation
are also provided.
179
7.3.1. Voltage Ripples of the Capacitors under Staircase Modulation
Under the staircase modulation depicted in previous chapters, the fundamental
amplitude of the output voltage, V1, can be estimated by (7.1).
n 1
4VS
V1 

 cos
i 1
i (7.1)
The firing angles, θ1, θ2, …, θn+1, are computed with the following nearest switching
function:
 2i  1 
i  sin 1   (7.2)
 2  M (n  1) 
where M is the modulation index and ρ is the correction factor for the fundamental
amplitude. Neglecting the effect of the current harmonics to the capacitor voltage
ripples, the voltage ripple magnitude, ∆VC, can be represented by the output current
magnitude, Io1, firing angles, θi, power factor angle, φ, as well as the capacitance, C,
of each SC. Based on the aforementioned working state, the voltage ripple magnitude
can be approximated as follows.
I o1   n1
  
n 1 i  2  i 1
VC 
 nC  n1
n sin   t   d  t  
i 1
i
i1
sin t    dt  
 i2
sin t    dt 

2 I o1 cos  n

 nC i 1
 cosi1
(7.3)
The firing angle terms in Eq. (7.3) can be expressed as a function of modulation index
corresponding to (7.1), (7.2) and V1=4MVS(n+1)/π. If a voltage ripple factor, 𝛿, is
180
defined as the ratio between the capacitor voltage ripple magnitude and the source
voltage, 𝛿 can be evaluated by (7.4).
  
2
I o1 cos    1
 M (n  1)  1    (7.4)
 fnCVS   2  M (n  1)  
 
7.3.2. Soft-Charging Analysis
In the proposed topology, soft-charging operation is achieved with the presence of a
resonant inductor, Lr. The charging behavior of the SC units can be analyzed based
on the theory of underdamped RLC circuit. The equivalent circuit of the charging path
in the proposed SCMLI can be represented by Fig. 7.3.
Rch0 Rch1 Rch1

...
ich ic1 ic2 icn
VS RC RC RC
Lr C C C
...
Fig. 7.3. Equivalent circuit of the SC charging path.
The resistance Rch0=RS+RL+RD+Rsw, Rch1=RD+Rsw and RC are the parasitic
resistances of the components in the charging path, where RS is the internal resistance
of the source, RL and RC are the ESRs of the resonant inductor and switched-capacitor,
RD and Rsw are the on-state resistances of the diode and MOSFET transistor. The key
factor in determining the performance of the soft-charging process is the termination
voltage of the SC units for a step-input response.
181
Rch0 Rch1 Rch1

...
VS RC RC RC
Lr C C C
...
=
Rch1/4
Rch0 Rch1 RC C
...
RC C
RC RC
VS RC
C C
Lr C
...
≈
Rch0 5Rch1/4
...
RC RC/2
VS
Lr C 2C
...
...
Rch,eq
VS nC
Lr
Fig. 7.4. Simplification of the RC network in the SC charging path.
Rch,eq
ich
VS nC VC
Lr
Fig. 7.5. Simplified RLC charging path of the SC units.
182
The equivalent circuit in Fig. 7.3 can be simplified by adopting the well-known
equivalent impedance transformation developed by Zobel [186] as shown in Fig. 7.4.
Neglecting the forward voltage drop of the diodes, the equivalent resistance, Rch,eq, of
the RLC charging path can be approximated by the following expression.
1 n 1 2 1
2 
Rch ,eq  Rch 0  i  Rch1   RC
n i 1 n
(7.5)
R (n  1)(2n  1) RC
 Rch 0  ch1 
6n n
Hence, the charge-up behavior of the SC units in the soft-charging SCMLI can
be analyzed with the simplified equivalent RLC circuit depicted in Fig. 7.5. To
improve the charge-up efficiency, an underdamped condition should be ensured by
the RLC parameters so that the maximum charging voltage, i.e. the termination
voltage, of the capacitor, VC,max, exceeds the source voltage, VS. Underdamped
condition can be achieved by fulfilling the following requirement.
4 Lr
Rch ,eq  (7.6)
nC
Given that the above requirement in (7.6) is fulfilling, the capacitor charging voltage
and current would vary following (7.7).
 VS  VC ,max  VC  t
 V (t )  V  e  sin r t  r cos r t 

C S
r
 (7.7)
i (t )  VS  VC ,max  VC e t sin  t
 ch Lrr
r
183
Rch ,eq 1
where   and r    2 are the neper frequency and the damped
2 Lr nLr C
resonant frequency respectively. The charging current would reach zero while the
capacitor voltage would attain the maximum charging voltage at the half of the
damped resonant period, i.e. ωrt=π, during the ON state of the switch, S1. Considering
the worst case that the available charge-up duration is just slightly larger than a half
of the fundamental output period, the maximum fundamental output frequency, f,
should be at most the same as the damped resonant frequency of the equivalent RLC
charging path, i.e.
1 1 Rch ,eq 2
f   (7.8)
2 nLr C 4 Lr 2
By substituting ωrt=π into (7.7), the maximum charging voltage, VC,max, of the SC unit
is derived as follows.
 Rch ,eq

2r Lr
e
VC ,max  VS   Rch ,eq
 VC  VS  VC (7.9)

2r Lr
1+e
 Rch ,eq  Rch ,eq

 
2r Lr 2r Lr
The exponential term, denoted by   e / (1+e ) , in (7.9) is ranged from 0
Rch,eq nC
to 0.5 depending on the damping factor,   . The relationship between
2 Lr
the damping factor and the soft-charging factor, 2ξ, of the equivalent RLC charging
path is plotted in Fig. 7.6.
184
0.8
Soft-charging factor, 2ξ
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1
Damping factor, ζ
Fig. 7.6. Relationship between the soft-charging factor and the damping factor of
the proposed soft-charging SCMLI.
It can be observed that ξ would be approximately zero when the damping factor
is close to unity. In other words, on top of fulfilling the criterion (7.6), the resonant
inductance should be larger, e.g. ζ<0.5, in order to gain a distinct soft-charging effect
for the SC units.
Similar to the hard-charging counterpart, the charge-up energy loss, Eloss,ch, for
the soft-charging SCMLI can be evaluated by the following equality.
Eloss ,ch  ES ,ch  EC , gain (7.10)
where ES,ch is the amount of charging energy extracted from the voltage source; EC,gain
is the energy gain of the capacitor throughout the charging process. The magnitudes
can be expressed as follows.
ES ,ch  nC  VC VS (7.11)
185
EC , gain   nC  VC ,max 2  VC ,max  VC  

1 2
(7.12)
2  
By substituting (7.9), (7.11) and (7.12) into (7.10), the charge-up energy loss is
derived as (7.13).
1 
Eloss ,ch       nC  VC 2 (7.13)
2 
Also, as the charging processes of the SC units in the two phase legs repeat
every output cycle, the charge-up power loss, Ploss,ch, can be simply calculated by
putting (7.3) and (7.13) into Ploss,ch=2fEloss,ch, i.e.
2
1  2  n

Ploss ,ch  2
 nCf  o1

I cos  
i 1
cos i 1 

(7.14)
Eq. (7.14) suggests that with the presence of a resonant inductor, the charging energy
efficiency of the soft-charging SC units is improved by the 2ξ term comparing to the
hard-charging counterpart; where ξ can be solely determined by the damping factor
of the equivalent RLC parameters in the charging path of the SCMLI.
7.4. Design Consideration
7.4.1. Selection of Resonant Inductance
As illustrated in Fig. 7.6, the soft-charging factor, which is the key indicator for the
charging efficiency of the SCMLI, is dependent on the damping factor of the
equivalent RLC parameters of the SC charging path. Among the RLC parameters, the
number of SC units is decided by the required number of voltage levels and step-up
ratio whereas the capacitance is determined by the target voltage ripple factor under
186
the predefined operating frequency and maximum current. Besides, the equivalent
charging resistance, Rch,eq, is fixed by the parasitic resistances of components. As a
result, the damping factor can only be adjusted by the value of the resonant inductance,
Lr. Corresponding to the predefined parameters and the target damping factor, Lr can
be designed based on the following function.
nRch,eq 2C
Lr  (7.15)
4 2
Furthermore, considering that the output current shares part of the SC charging
path, the additional carrying current would be reflected as a slightly increase in Rch,eq.
Therefore, positive tolerance is preferred to secure the target soft-charging factor. On
the other hand, the resonant inductance would also affect the duration of attaining the
maximum charging voltage, VC,max. Equivalent to the fulfillment of (7.8), the
maximum value of resonant inductance is limited by (7.16).
 2
1  1   2 nCfRch,eq  
1
Lr  (7.16)
8n 2Cf 2
Considering the positive effect of output current to the Rch,eq and the stray inductance
of the circuit layout, positive tolerance of Lr should be used to check the criterion
(7.16). Besides, the working frequency has to be lower than the cut-off frequency of
the equivalent RC parameters in the SC charging path, i.e.
1
f  (7.17)
2 nCRch ,eq
187
7.4.2. Power Supplies for Floating Gates
S32b
S22b S31b
S12b S21b
VS High-side Gate Driver
VSg
S11b
Fig. 7.7. Bootstrap design for the floating gate drivers in the two-phase SCMLI.
The high number of active switches increases the complexity of the gate driving
circuits. The system cost can be considerable if the floating gate driver supplies are
realized by independent voltage sources. If the active switches are implemented by
n-channel MOSFETs, the gate drivers for the two low-side switches, S11a and S11b can
be supplied by the same voltage source having a common ground as the main power
voltage source, VS. Separated floating supplies are required for the gating circuit of
the remaining switches. Owing to the cascaded structure of the half-bridges in the
proposed SCMLI, throughout an operating period, the source terminals of all
MOSFETs shares the same minimum potential, which is the same as the potential of
the negative terminal of the main voltage source. Therefore, the power supplies of all
floating gates can be supplied by a common voltage source with separated bootstrap
diodes and capacitors (Fig. 7.7). The bootstrap capacitors would be charged with the
SC units simultaneously. As a result, the floating gates can be implemented by low-
cost high-side drivers with passive bootstrap supplies.
188
7.5. Simulation Study
As indicated in previous study, the performance of the SC based MLI at low frequency
was limited. However, the maximum operating frequency of the SCMLI was
restricted by the large RC time constant of the electrolytic capacitors. In order to
improve the power output capability, the operating frequency of the SCMLI should
be raised to several kilo-hertz whereas the SC modules can be implemented with
polypropylene film capacitors with lower ESR to reduce the RC time constant. In the
following simulation study, a 9-level SCMLI operating at 10 kHz was designed. The
performance of the conventional hard-charging and the proposed soft-charging
operation was investigated and compared at several loading conditions and RLC
parameters.
For the 9-level configuration, the voltage ripple magnitude should be restricted
to be lower than one-fourth of the source voltage. Considering an input voltage of
60 V and 20% capacitor voltage ripples at 1 kW, according to (7.4), the capacitance
would be about 15 μF. The parameters listed in Table 7.2 were used to build the
simulation model. The 9-level configuration with six SC units could produce an AC
output voltage with a root-mean-square value of around 160 V from the 60 VDC
source. Based on the listed parameters, the equivalent resistance, Rch,eq, of the SC
charging path would be around 0.13 Ω; to fulfill the criterion (7.16) with C=15 μF
and n=3, the maximum resonant inductance, Lr, would be about 5.6 μH. The
modulation index was set to 0.85, the output voltage, output current as well as the
voltage of the capacitors in phase-A leg at 1 kVA load and lagging power factor of
0.7 with different resonant inductance are illustrated in Fig. 7.8.
189
Table 7.2. Parameters of the 9-level SCMLI simulation model with the
two-phase structure.
Parameters Values
Source voltage, VS 60 V
Number of levels 9
Number of Switched-capacitors 6
Input source resistance 20 mΩ
Capacitance, C 15 F (ESR=20 mΩ)
On-state resistance of active 44 mΩ
switches
Forward voltage drop of diodes 0.4V (Diode resistance=20 mΩ)
Vo (V)
Io (A)
C1a C2a C3a

VC (V)
ILr (A)
time (ms)
(a)
190
Vo (V)
Io (A)
C1a C2a C3a

VC (V)
ILr (A)
time (ms)
(b)
Vo (V)
Io (A)
C1a C2a C3a

VC (V)
ILr (A)
time (ms)
(c)
Fig. 7.8. Simulated waveforms of the 9-level SCMLI at 1 kVA load with lagging
power factor of 0.7; (a) hard-charging; (b) soft-charging with Lr=1 μH;
(c) soft-charging with Lr=5 μH
191
The damping factors of the equivalent RLC circuits with 1 μH and 5 μH
resonant inductors were about 0.46 and 0.2, respectively. The simulated efficiencies
for the cases of the hard-charging and soft-charging with 1 μH and 5 μH inductors at
the 1 kVA load were 0.915, 0.937 and 0.946, accordingly. As demonstrated in Fig.
7.8 the resonant inductor prolonged the charging process in the soft-charging cases,
brought about upswing of the capacitor voltages beyond the input voltage and a slight
increase in the peak output voltage from 237.6 V to 246.8 V. Besides, voltage rise of
the third SC unit, C3a, was observed due to the lagging power factor of 0.7. When the
output current and voltage were out of phase beyond θ2, the voltage source would be
temporarily charged through the SC units. Because of the presence of diodes, only the
highest order capacitor could be charged which reversely biased the diode.
The total charge-up power loss of the SC units and the efficiency of the 9-level
SCMLI model were simulated at different values of resonant inductance and loading
conditions (Fig. 7.9). As predicted by (7.14), along with the increment of resonant
inductance, Lr, the suppression of the RLC damping factor gradually reduced the
charge-up power loss of the capacitors. By comparing the ripple power loss with that
in the hard-charging case, the simulated soft-charging factor, 2ξ, with the 5 μH, 2 μH,
1 μH resonant inductances were about 0.70, 0.53 and 0.36, respectively, which
conform to the theoretical values of 0.71, 0.54 and 0.37 estimated with (7.9) to (7.14).
Fig. 7.9 shows that the simulated efficiency was improved by inserting a resonant
inductor between the voltage source and the charging path of the SC units.
192
500
Lr=0μH (hard-charging)
400 Lr=1μH
Charge-up power loss
Lr=2μH
Lr=5μH
Ploss,ch (W)
300
200
100
0
0 500 1000 1500 2000
Output power, Po (W)
(a)
1
Simulated efficiency
0.95
0.9
Lr=5μH
0.85 Lr=2μH
Lr=1μH
0.8
0 500 1000 1500 2000
(b)
Fig. 7.9. Simulated performance of the 9-level SCMLI with different resonant
inductance value and loading conditions; (a) simulated total charge-up
power loss; (b) simulated efficiency.
193
7.6. Experimental Verification
To verify the soft-charging operation with the two-phase structured, experiment was
conducted on the 9-level SCMLI prototype. The components constructing the
prototype are listed in Table 7.3. The switched-capacitors were implemented by three
4.7 μF polypropylene capacitors in parallel, making up equivalent capacitance of
about 14.1 μF and ESR of ≤11.3 mΩ. Taking into account that the maximum charging
voltage of the capacitors could be higher than the input source voltage, a voltage
margin has to be taken in deciding the voltage rating of the components, IRF540N
n-channel MOSFETs and NTSB30120CT Schottky diodes rated at 100 V and 120 V
maximum blocking voltages were employed as the switches. Surface-mounted device
(SMD) type power inductors with 1 μH each were connected in series to form varied
values of resonant inductance. The staircase modulation signal was implemented by
an STM32F446 digital microcontroller connecting to the gate driver circuits. The
experimental setup is illustrated in Fig. 7.10.
Table 7.3. Parameters of the 9-level SCMLI prototype.
Parameters Values
Source voltage, VS 60 VDC
Number of levels 9
Number of Switched-capacitors 6
Input filter capacitor 132 μF aluminum solid capacitor
14.1 μF polypropylene capacitors
Switched-capacitors
(loss tanδ≤0.1% @ 1 kHz)
Active switches IRF540N 100 V, 33 A, 44 mΩ
Didoes NTSB30120CT Schottky rectifier
Resonant inductor 1 μH to 5 μH SMD inductor
194
4
1
3
Fig. 7.10. Experimental setup for the 9-level SCMLI prototype with two-phase
structure; (1) two phase-legs of the 9-level SCMLI prototype; (2) STM32F446
microcontroller and gate driver circuits; (3) DC power supply; (4) load.
Under an inductive load of about 1 kVA with a lagging power factor of 0.7, the
measured output voltage, output current and capacitor voltage waveforms for the
settings of hard-charging without a resonant inductor, as well as the soft-charging
condition with inductance values of 1 μF and 5 μH are shown in Fig. 7.11. Similar to
the simulation result, with the 9-level structure consisting six SC units, the SCMLI
produced a peak output voltage of about 240 V from the 60 V voltage source; the
measured waveforms indicated that the resonant inductor prolonged the charging
process by reducing the resonant frequency of the equivalent RLC circuit of the SC
charging path, which also slightly increased the maximum charging voltage of the
capacitors.
195
Vo:100V/div
Io:10A/div
Vc1a:10V/div
Timebase:40μs/div
(a)
Vo:100V/div
Io:10A/div
Vc1a:10V/div
Timebase:40μs/div
(b)
Vo:100V/div
Io:10A/div
Vc1a:10V/div
Timebase:40μs/div
(c)
Fig. 7.11. Output voltage, output current and the capacitor voltage waveforms of
the 9-level SCMLI prototype at 1 kVA load with lagging power factor of about
0.7; (a) hard-charging setting without the resonant inductor; (b) soft-charging
with a 1 μH resonant inductor; (c) soft-charging with a 5 μH resonant inductor.
196
Measured efficiency 0.95
0.9
Lr=5μH
0.85 Lr=2μH
Lr=1μH
0.8
0 400 800 1200
Fig. 7.12. Measured efficiency of the 9-level SCMLI prototype at different

resonant and load settings.
Also, the efficiency of the inverter prototype at different resonant settings and
load power was measured and plotted in Fig. 7.12. Eq. (7.14) suggests that the ripple
power loss would be proportional to the square of the output current magnitude, which
implies that the series-parallel SC unit can be modeled by a resistive component. As
predicted by the simulation result, the efficiency of the inverter declined with
increasing output power. This implies that the power loss was mainly contributed by
the conduction loss and ripple power loss at high power. Besides, the experimental
result shows that the soft-charging operation was effective in reducing the power loss.
At the load of around 1200 W, the measured efficiency of the 9-level SCMLI
prototype at hard-charging and soft-charging operation with a resonant inductor of
5 μH was approximately 84.1% and 91.1%, respectively. This measurement was close
to the respective simulation results of 85.2% and 92.1%.
197
7.7. Summary
This chapter presents the soft-charging operation for the SCMLI topology with a two-
phase configuration. In this topology, only one resonant inductor, connecting between
the input voltage source and the SC charging path, is required to achieve soft-charging
of all SC units. By employing the equivalent impedance transformation, the charging
path of the SC network with a resonant inductor can be modeled by a simple series
RLC circuit. The analysis predicts that the charge-up power loss of SC units could be
mitigated by reducing the damping factor of the equivalent RLC circuit, which has
been successfully verified by the experimental result. By inserting a 5 μH inductor
into the charging path to attain a damping factor of 0.2, the measured efficiency was
improved from 84.1% to 91.1% at 1200 W output power. As an extension of the
technique of zero-current switching (ZCS) which has been widely employed in SC
DC-DC conversion, the soft-charging technique would be a promising solution for
mitigating the notorious ripple loss issue and improve the power driving capability of
series-parallel SC based MLIs.
198
Chapter 8 Conclusion
Chapter 8
Conclusion
Development of power converters constructed with generalized switched-capacitor
units for DC-DC conversion, energy storage management, as well as DC-AC
inversion applications has been explored in previous chapters. In the following, the
context of this thesis is summarized by highlighting the major achievements and
contributions of the study. Also, the potential research areas and some following up
issues are suggested for future work.
8.1. Contributions of the Thesis
The design of power conversion system formed by clusters of generalized SC
converter units has been explored by this thesis. The study includes the parallel-mode
SC converters for DC-DC power conversion with the centralized load regulation
control technique; multi-port SC DC-DC converters for the charge management in
ESSs; varieties of SCMLIs with voltage step-up and self-voltage-balance features;
enhancement on the modularity of SCMLIs by eliminating the high voltage unfolding
stage; improvement in the conversion efficiency by the adoption of a quasi-resonant
ZCS technique to achieve soft-charging operation. This research has demonstrated a
series of SC based power converters with improved system scalability and
199
performance, which potentially extends the applications of SC technology to higher
power applications.
A. Centralized Control for Parallel-Mode SC Converters
The equivalent resistance model of SC converters serves as an inherent droop
characteristic for current sharing. This characteristic improves the system stability and
simplifies the control for parallel-mode operation. By adjusting the number of active
SC units, voltage regulation can be easily achieved by commanding identical ZCS SC
units with a central controller. Instead of turning the duty cycle or frequency of the
switching PWM signals in each individual unit, the equivalent resistance of a specific
SC unit can be altered by implementing the duty cycle to the activating logic signal
of the converter. Behavior of the hybrid unit control with PD-PWM has been analyzed;
the load regulation under dynamic condition has been verified by the experiment on
an SC converter system constituted by ten double-mode ZCS SC units.
B. Multi-port SC Converters for Energy Storage Management
A configuration of multi-port SC converters has been presented for the coordinated
operation of a BMS and the SC based equalizer. This configuration permits active
current control of the specific output or input channels to the ESS. Also, it mitigates
the voltage dependency appearing in many traditional SC equalizers and improves the
equalizing speed regardless of the voltage difference, position and environment
conditions of the energy storage devices. Moreover, this idea enables the potential
applications of SC based equalizers in hybrid energy storage packages involving
different types of energy storage devices and second-life batteries.
200
C. Hybrid SCMLI Topology with Series-Connected Voltage Sources
Along with the increasing penetration of ESSs and distributed renewable generations,
electric systems with multiple power sources are becoming more popular. Series-
connection of low-voltage power sources is a common configuration for improving
the system power driving capability. By combining a series-connected voltage source
string with SC circuits, a hybrid SCMLI with a higher number of output levels and
the features of voltage step-up and self-voltage-balance is developed. The topology is
proposed for generalized numbers of voltage sources and SC units. In addition to the
realization of voltage step-up, the SC units can also facilitate the charge balancing of
the voltage sources with extended modulation index. This solves the practical problem
taking place in many power converters with series input sources. Also, the circuit
alteration for asymmetric SC voltages and the corresponding SC analyses under the
nearest switching staircase modulation are presented.
D. Elimination of Unfolding H-Bridge stage in SCMLI
Although voltage step-up is realized by the series-parallel SC technique, an unfolding
H-bridge stage is required to stand against the maximum output voltage. This
configuration would deny a key benefit of reduced maximum voltage rating of
components offered by MLI. To overcome this limitation, three novel configurations
of SCMLIs have been proposed. The proposed configurations include the two-phase,
cascaded and cross-switched structures, respectively. With these configurations, the
maximum voltage stress of the active switches is substantially lower to two times or
the same level as the input voltage source.
201
E. Soft-charging SCMLI Based on Resonant Technique
Capacitor ripple power loss is a common problem of SCMLIs which reduces the
conversion efficiency and limits the maximum output power. By adopting the quasi-
resonant ZCS technique to the charging process of the SC units, the ripple power loss
is dramatically reduced. With the two-phase structured SCMLI, the charge-up
duration is at least half of the fundamental output period. Also, only a single, small
resonant inductor is required for achieving soft-charging of all SC units in the two-
phase structure. This eases the selection of the inductance value. The reduction on the
equivalent RLC circuit model of the SC charging path facilitates the performance
perdition of the SCMLI that the soft-charging factor can be simply estimated by the
damping factor of the RLC circuit.
Development of DC and HFAC power conversion and distribution technologies
as well as the ESS involving hybrid storage devices and retired EV batteries is
motivated by the increasing penetration of distributed RE generation and
electrification of mobility. The parallel-mode SC DC-DC conversion system offers a
modular approach of DC power conditioning which enables scalable DC distribution
with the adoption of SC units. The proposed hybrid SCMLI provides an alternative of
producing a step-up HFAC output from multiple DC sources whereas the
development of varieties of SCMLI topologies reduces the maximum voltage stress
of the components and increases the voltage stability of SC based DC-AC conversion.
Besides, the soft-charging technique improves the conversion efficiency of SC DC-
AC conversion by reducing the charge-up power loss of the SC units. Furthermore,
the multi-port SC converter and the current allocation technique enable the charge
202
balancing of voltage sources. In theory, these balancing techniques are voltage
independent and can be employed in hybrid ESSs constituted by storage devices with
unequal parameters. The work presented in this thesis contributes towards the SC
based power conversion in the sub-kilowatt range for small scale power distribution
systems. It makes use of multiple energy storage cells to facilitate the power
processing in mobility or building integrated ESS and RE applications. With the
modular approach, it is feasible to further extend the power level for the future
industrial applications of SC power conversion in RE, transportation electrification
and hybrid ESS.
8.2. Recommendations for Future Work
To further improve the performance and modularity of the SC units based power
conversion system, the recommendations of potential research areas and some
remaining issues for future work are listed below.
A. Advanced Control for Parallel-Mode SC Converters
This study has employed a basic PI controller in the hybrid unit control to attain the
required stable output voltage with low steady-state offset. The design of advanced
control techniques for the parallel-mode SC converter with optimal system response,
as well as the implementation of interleaved operation with phase-shift control would
be a significant future work for this topic.
B. Bidirectional Multi-Port SC Balancer with Active Current Control
The analysis in Chapter 3 suggested that the balancing performance of the multi-port
SC converters has limited by the unidirectional configuration. Extension of the idea
203
of active current control to bidirectional SC configuration would have very high
potential in enhancing the overall performance SC balancing technique.
C. Output Voltage Distortion Due to the Capacitor Voltage Ripples
The effect of the capacitor voltage ripples to the conversion efficiency of SCMLI has
been well investigated in this thesis. Besides, the voltage ripples could also influence
the output voltage waveform. Study on the capacitor voltage ripples to the
fundamental amplitude, as well as the harmonic content of the output voltage
waveform would be an interesting future research area for SCMLIs.
D. Other Modulation Approaches for SCMLIs
The study of SCMLIs in this thesis focused on the nearest switching staircase
modulation technique at the fundamental frequency. On the other hand, numerous
modulation approaches for MLIs such as selective harmonic elimination and varieties
of carrier based PWM can be found in the literature. Each of the modulation
approaches has unique characteristic for specific applications. The SC analysis based
on other modulation approaches could be another future work for SCMLIs.
E. Parallel SC Modules in SCMLIs
In chapter 6, varieties of SCMLI topologies have been proposed for the reduction of
the component voltage stress. To further increase the modularity of the SCMLIs, the
future research can focus on the reduction and normalization of the SC current ratings.
Investigation on the sizing and the characteristic of parallel SC modules could be an
interesting research direction for modular SCMLIs.
204
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FONG YAT CHI

The Hong Kong Polytechnic University

Formation and Analysis of Switched-Capacitor Converter

FONG Yat Chi

A thesis submitted in partial fulfilment of the requirements for

extended to medium power processing. A novel power conversion technique based on

power conversion are identified by an overall review of previous development of the

SC technology and the features of existing SC converters. Control techniques and

circuit configurations are developed to address the limitations and weaknesses of

traditional SC converters. The associated analysis and design of power converters

step-up DC-AC multilevel inverters (MLIs) based on the series-parallel SC technique.

The principle of ZCS SC DC-DC converter is reviewed; the analysis is extended to

on the system modeling, a series of centralized control techniques is developed.

multi-port SC conversion system is presented. On top of the well-known

auto-balancing feature offered by the SC technology, feasibility of improving the

balancing speed by an alternative ZCS SC structure with the presence of supervisory

of the single-input multi-output and multi-input single-output, as well as, the

corresponding mutations of string-to-cells, cells-to-string and cells-to-cells

configurations are developed.

Investigation on the topics of SC DC-DC converters provides the theoretic

foundation and working principle of SC based power processing. Attractive features

of the modular SC approach motivates the development of MLIs based on the SC

based on the ideas of series-parallel SC unit and bidirectional switched MLI is

developed. Compared to independent DC sources, series-connected sources have

ladder structure with an SC unit. Furthermore, the weaknesses of common SCMLIs

such as the requirement of high voltage unfolding H-bridge is mitigated by proposing

a series of modular SCMLI topologies based on the two-phase, cascaded bipolar

series-parallel as well as the cross-switched structures. The charge-up power loss is

applications in mobility as well as small scale power distribution systems integrated

with RE and ESS through the idea of modular circuit configuration.

1. Y.C. Fong, K.W.E. Cheng, Y. Ye and Y.C. Chan, "Centralized Regulation

1. Generalized Topology of a Hybrid Switched-capacitor Multilevel Inverter for

First of all, I would like to express my sincere gratitude to my supervisor, Professor

Moonson Chen and Mr. Jie Mei.

period of my research study.

Chapter 1 Introduction ......................................................................................... 1

3.3. SC Modeling and Analysis ......................................................................... 53

Chapter 6 Development of SC MLIs Offering Modularity in Design ........... 143

Fig. 1.1. A basic SC DC-DC converter

Fig. 2.15. Experimental setup of the parallel double-mode SC converter system

Fig. 6.12. Simulated output voltage, output current and switched-capacitor

Table 2.1. Parameters of the simulated SC converter System

Table 2.2. Specification of the SC converter system prototype

Table 3.1. Key parameters of the simulation model

Table 3.2. Key parameters of the experimental setup

Table 4.1. Switching states of the symmetric SC voltage based inverter at

Table 4.2. Switching states of the asymmetric SC voltage based inverter

Table 4.4. Specification and components of the SCMLI prototype

Table 5.1. Properties of different MLI topologies with n series-connected voltage

Table 5.2. Parameters of different simulation settings

Table 5.3. Parameters of the experimental MLI prototype

Table 6.1. Working states of a (2n+3)-level SCMLI with a two-phase structure

Table 6.2. Working states of the cascaded SCMLI

Table 6.3. Working states of the cross-switched SCMLI

Table 6.4. Key parameters of different SCMLI topologies

Table 6.5. Parameters of the 9-level SCMLI simulation models

Table 6.6. Parameters of the 9-level SCMLI prototype