NCP3163

3.4 A, Step−Up/Down/
Inverting 50−300 kHz
Switching Regulator
The NCP3163 Series is a performance enhancement to the popular
MC33163 and MC34163 monolithic DC−DC converters. These
devices consist of an internal temperature compensated reference, http://onsemi.com
comparator, controlled duty cycle oscillator with an active current
limit circuit, driver and high current output switch. This controller was MARKING
specifically designed to be incorporated in step−down, step−up, or DIAGRAMS
16
voltage−inverting applications with a minimum number of external 16
components. The NCP3163 comes in an exposed pad package which 1
can greatly increase the power dissipation of the built in power switch. NCP3163xPW
SOIC−16W AWLYYWWG
Features EXPOSED PAD
• Output Switch Current in Excess of 3.0 A PW SUFFIX
1
• 3.4 A Peak Switch Current
CASE 751AG

• Frequency is Adjustable from 50 kHz to 300 kHz

• Operation from 2.5 V to 40 V Input 18
1 18
• Externally Adjustable Operating Frequency
• Precision 2% Reference for Accurate Output Voltage Control 18−LEAD DFN NCP3163x
• Driver with Bootstrap Capability for Increased Efficiency 1 MN SUFFIX AWLYYWW G
G
• Cycle−by−Cycle Current Limiting CASE 505
• Internal Thermal Shutdown Protection
• Low Voltage Indicator Output for Direct Microprocessor Interface
NCP3163x = Specific Device Code
• Exposed Pad Power Package A = Assembly Location
• Low Standby Current WL = Wafer Lot
• This is a Pb−Free Device YY = Year
WW = Work Week
G = Pb−Free Package
Current G = Pb−Free Package
8 − Limit 9
(Note: Microdot may be in either location)
+
Vin
7 10
+ ORDERING INFORMATION
Cin VCC See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
6 Oscillator 11

*For additional information on our Pb−Free strategy

5 R 12 and soldering details, please download the
Q ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Thermal S
4 13
VCC

3 14

+
2 + 15
−

+
1 + 16
−
LVI VCC
Vout
(Bottom View) CO +
Figure 1. Typical Buck Application Circuit

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

May, 2006 − Rev. 1 NCP3163/D
 NCP3163

0.25 V Current
IPKsense 8 − Limit 9 Driver Collector
+
RSC
VCC 7 10
VCC
Switch Collector
Timing Capacitor
6 Oscillator Q1 11
CT
Shutdown Q2
5 R 12
RDT
Q 60
Thermal S
Gnd 4 Latch 13
VCC
Voltage Feedback 1 3 14
Switch Emitter
45 k 2.0 mA
+
Voltage Feedback 2 2 + Feedback 15
− Comparator
1.25 V 15 k
+
LVI Output 1 + 7.0 V 16
− Bootstrap Input
LVI 1.125 V
VCC
+
(Bottom View) = Sink Only
−
Positive True Logic
Figure 2. Representative Block Diagram

PIN FUNCTION DESCRIPTION

SOIC16 DFN18 PIN NAME DESCRIPTION
1 15 LVI Output This pin will sink current when FB1 and FB2 are less than the LVI threshold (Vth).
2 16 Voltage Feedback 2 Connecting this pin to a resistor divider off of the output will regulate the application
according to the Vout design equation in Figure 22.

3 17 Voltage Feedback 1 Connecting this pin directly to the output will regulate the device to 5.05 V.
4 18 GND Ground pin for all internal circuits and power switch.
6 1 Timing Capacitor Connect a capacitor to this pin to set the frequency. The addition of a parallel resis-
tor will decrease the maximum duty cycle and increase the frequency.

7 3 VCC Power pin for the IC.

8 4 Ipk Sense When (VCC−VIPKsense) > 250 mV the circuit resets the output driver on a pulse by
pulse basis.
9 5 Drive Collector Voltage driver collector
10,11 6,7,8,9 Switch Collector Internal switch transistor collector
14,15 10,11,12,13 Switch Emitter Internal switch transistor emitter
16 14 Bootstrap Input Connect this pin to VCC for operation at low VCC levels. For some topologies, a
series resistor and capacitor can be utilized to improve the converter efficiency.

5,12,13 2 No Connect These pins have no connection.

Exposed Exposed Exposed Pad The exposed pad beneath the package must be connected to GND (pin 4). Addi-
Pad Pad tionally, using proper layout techniques, the exposed pad can greatly enhance the
power dissipation capabilities of the NCP3163.

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 NCP3163

MAXIMUM RATINGS (Note 1)

Rating Symbol Value Unit
Power Supply Voltage VCC 0 to +40 V
Switch Collector Voltage Range VCSW −1.0 to +40 V
Switch Emitter Voltage Range VESW −2.0 to +40 V
Switch Collector to Emitter Voltage VCESW +40 V
Switch Current ISW 3.4 A
Driver Collector Voltage (Pin 8) VCC −1.0 to +40 V
Driver Collector Current (Pin 8) ICC 150 mA
Bootstrap Input Current Range IBST −100 to +100 mA
Current Sense Input Voltage Range VIPKSNS (VCC − 7.0) to (VCC + 1.0) V
Feedback and Timing Capacitor Input Voltage Range Vin −1.0 to +7.0 V
Low Voltage Indicator Output Voltage Range VCLVI −1.0 to +40 V
Low Voltage Indicator Output Sink Current ICLVI 10 mA
Power Dissipation and Thermal Characteristics
Thermal Characteristics °C/W
Thermal Resistance, Junction−to−Case RqJC 15
Thermal Resistance, Junction−to−Air RqJA 56
Storage Temperature Range Tstg −65 to +150 °C
Maximum Junction Temperature TJmax +150 °C
Operating Ambient Temperature (Note 3) TA °C
NCP3163PW 0 to +70
NCP3163BPW −40 to +85

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 1500 V per MIL−STD−883, Method 3015.
Machine Model Method 150 V.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded.
4. The pins which are not defined may not be loaded by external signals.

PIN CONNECTIONS

1 16
LVI Output Bootstrap Input Timing Capacitor 1 18 GND
2 15
Voltage Feedback 2 N/C 2 GND 17 Voltage Feedback 1
3 Switch
14 3 Voltage Feedback 2
Voltage Feedback 1 Emitter VCC 16
4 13 Ipk Sense 4 15 LVI Output
GND
12 N/C Driver Collector 5 14 Bootstrap Input
N/C 5
Switch Collector 6 13 Switch Emitter
6 11
Timing Capacitor Switch Collector 7 12 Switch Emitter
7 10 Switch Collector Switch Collector 8 EP Flag 11 Switch Emitter
VCC
8 9 Switch Collector 9 10 Switch Emitter
Ipk Sense Driver Collector
(Top View)
Note: Pin 18 must be tied to EP Flag on PCB

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 NCP3163

ELECTRICAL CHARACTERISTICS (VCC = 15 V, Pin 16 = VCC, CT = 270 pF, RT = 15 kW, for typical values TA = 25°C, for min/max
values TA is the operating ambient temperature range that applies (Note 5), unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
OSCILLATOR
Frequency fOSC kHz
TA = 25°C, VCC = 15 V 225 250 275
Total Variation over VCC = 2.5 V to 40 V and Temperature (Note 5) 212 250 288
Charge Current Ichg − 225 − mA
Discharge Current Idischg − 25 − mA
Charge to Discharge Current Ratio Ichg/Idischg 8.0 9.0 10 −
Sawtooth Peak Voltage VOSC(P) − 1.25 − V
Sawtooth Valley Voltage VOSC(V) − 0.55 − V
FEEDBACK COMPARATOR 1
Threshold Voltage Vth(FB1) V
TA = 25°C 4.9 5.05 5.2
Total Variation over VCC = 2.5 V to 40 V and Temperature (Note 5) 4.85 − 5.25
Threshold Voltage REGline(FB1) %/V
Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) − 0.008 0.03
Input Bias Current (VFB1 = 5.05 V) IIB(FB1) − 100 200 mA
FEEDBACK COMPARATOR 2
Threshold Voltage Vth(FB2) V
TA = 25°C, VCC = 15 V 1.225 1.25 1.275
Total Variation over VCC = 2.5 V to 40 V and Temperature (Note 5) 1.213 − 1.287
Threshold Voltage REGline(FB1) %/V
Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) − 0.008 0.03

Input Bias Current (VFB2 = 1.25 V) IIB(FB2) − 0.4 − 0.4 mA

CURRENT LIMIT COMPARATOR
Threshold Voltage Vth(Sense) mV
TA = 25°C − 250 −
Total Variation over VCC = 2.5 V to 40 V, and Temperature (Note 5) 230 − 270
Input Bias Current (VIpk (Sense) = 15 V) IIB(Sense) − 1.0 20 mA
DRIVER AND OUTPUT SWITCH (Note 6)
Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded) VCE(sat) V
Non−Darlington Connection (RPin 9 = 110 W to VCC, ISW/IDRV ≈ 20) − 0.6 1.0
Darlington Connection (Pins 9, 10, 11 connected) (Note 7) − 1.0 1.4
Collector Off−State Leakage Current (VCE = 40 V) IC(off) − 0.02 100 mA
Bootstrap Input Current Source (VBS = VCC + 5.0 V) Isource(DRV) 0.5 2.0 4.0 mA
Bootstrap Input Zener Clamp Voltage (IZ = 25 mA) VZ VCC + 6.0 VCC + 7.0 VCC + 9.0 V
LOW VOLTAGE INDICATOR
Input Threshold (VFB2 Increasing) Vth 1.07 1.125 1.18 V
Input Hysteresis (VFB2 Decreasing) VH − 15 − mV
Output Sink Saturation Voltage (Isink = 2.0 mA) VOL(LVI) − 0.15 0.4 V
Output Off−State Leakage Current (VOH = 15 V) IOH − 0.01 5.0 mA
TOTAL DEVICE
Standby Supply Current (VCC = 2.5 V to 40 V, Pin 8 = VCC, ICC − 6.0 10 mA
Pins 6, 14, 15 = GND, remaining pins open)
5. Maximum package power dissipation limits must be observed.
6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
7. Tlow = 0°C for NCP3163 Thigh = + 70°C for NCP3163
= − 40°C for NCP3163B = + 85°C for NCP3163B

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 NCP3163

300
VCC = 15 V
TA = 25°C
250

FREQUENCY (kHz)
200
Rt = 15 kW

150
Rt = open

100

50
0 100 200 300 400 500 600 700
CT, TIMER CAPACITANCE (pF)

Figure 3. Oscillator Frequency vs. Timer

Capacitance (CT)
Δ f OSC, OSCILLATOR FREQUENCY CHANGE (%)

Δ f OSC, OSCILLATOR FREQUENCY CHANGE (%)

2.0 4.0
VCC = 15 V VCC = 15 V
CT = 620 pF 2.0 CT = 230 pF
RT = 20 kW
0
0

−2.0
−2.0
−4.0

−6.0
−4.0
−8.0

−6.0 −10
−55 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TEMPERATURE (°C)

Figure 4. Oscillator Frequency Change vs. Figure 5. Oscillator Frequency Change vs.
Temperature when only CT is connected to Pin 6 Temperature when CT and RT are connected to Pin 6
V th(FB2), COMPARATOR 2 THRESHOLD VOLTAGE (mV)

140 1300
VCC = 15 V
IIB , INPUT BIAS CURRENT (A)

VFB1 = 5.05 V VCC = 15 V Vth Max = 1275 mV

1280
μ

120

1260
Vth Typ = 1250 mV
100
1240
Vth Min = 1225 mV
80
1220

60 1200
−55 −25 0 25 50 75 100 125 −55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 6. Feedback Comparator 1 Input Bias Figure 7. Feedback Comparator 2 Threshold
Current vs. Temperature Voltage vs. Temperature

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 NCP3163

I source (DRV), BOOTSTRAP INPUT CURRENT SOURCE (mA

V Z, BOOTSTRAP INPUT ZENER CLAMP VOLTAGE (V

2.8 7.6
VCC = 15 V IZ = 25 mA
Pin 16 = VCC + 5.0 V
2.4 7.4

2.0 7.2

1.6 7.0

1.2 6.8
−55 −25 0 25 50 75 100 125 −55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 8. Bootstrap Input Current Figure 9. Bootstrap Input Zener Clamp

Source vs. Temperature Voltage vs. Temperature

0 1.2
Darlington Configuration
VCE (sat), SOURCE SATURATION (V)

VCC
VCE (sat), SINK SATURATION (V)
Emitter Sourcing Current to GND 1.0 Darlington, Pins 9, 10, 11 Connected
−0.4 Pins 7, 8, 10, 11 = VCC
Pins 4, 5, 12, 13 = GND
TA = 25°C, (Note 2) 0.8
−0.8 Grounded Emitter Configuration
0.6 Collector Sinking Current From VCC
Bootstrapped, Pin 16 = VCC + 5.0 V Pins 7, 8 = VCC = 15 V
−1.2 Pins 4, 5, 12, 13, 14, 15 = GND
0.4
TA = 25°C, (Note 2)
−1.6 Saturated Switch, RPin9 = 110 W to VCC
Non−Bootstrapped, Pin 16 = VCC 0.2
GND
−2.0 0
0 0.8 1.6 2.4 3.2 0 0.8 1.6 2.4 3.2
IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A)

Figure 10. Output Switch Source Saturation Figure 11. Output Switch Sink Saturation
vs. Emitter Current vs. Collector Current

0 0.5
V OL (LVI) , OUTPUT SATURATION VOLTAGE (V)

VCC=5 V
GND TA=25°C
IC = 10 mA
V E , EMITTER VOLTAGE (V)

−0.4 0.4

−0.8 0.3

IC = 10 mA
−1.2 0.2

VCC = 15 V
−1.6 Pins 7, 8, 9, 10, 16 = VCC 0.1
Pins 4, 6 = GND
Pin 14 Driven Negative
−2.0 0
−55 −25 0 25 50 75 100 125 0 2.0 4.0 6.0 8.0
TA, AMBIENT TEMPERATURE (°C) Isink, OUTPUT SINK CURRENT (mA)
Figure 12. Output Switch Negative Emitter Figure 13. Low Voltage Indicator Output Sink
Voltage vs. Temperature Saturation Voltage vs. Sink Current

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 NCP3163

V th (Ipk Sense), THRESHOLD VOLTAGE (mV

254 1.6
VCC = 15 V

IIB (Sense), INPUT BIAS CURRENT (μ A)

VCC = 15 V
1.4 VIpk (Sense) = 15 V
252

1.2
250
1.0

248
0.8

246 0.6
−55 −25 0 25 50 75 100 125 −55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 14. Current Limit Comparator Threshold Figure 15. Current Limit Comparator Input Bias
Voltage vs. Temperature Current vs. Temperature

8.0 7.2
VCC = 15 V
Pins 7, 8, 16 = VCC
I CC, SUPPLY CURRENT (mA)

I CC, SUPPLY CURRENT (mA)

6.4 Pins 4, 6, 14 = GND
6.0
Remaining Pins Open

4.0 5.6

Pins 7, 8, 16 = VCC
2.0 Pins 4, 6, 14 = GND 4.8
Remaining Pins Open
TA = 25°C
0 4.0
0 10 20 30 40 −55 −25 0 25 50 75 100 125
VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 16. Standby Supply Current Figure 17. Standby Supply Current
vs. Supply Voltage vs. Temperature
V CC(min) , MINIMUM OPERATING SUPPLY VOLTAGE (V)

3.0
CT = 620 pF
Pins 7,8 = VCC
2.6 Pins 4, 14 = GND
Pin 9 = 1.0 kW to 15 V
Pin 16 Open Pin 10 = 100 W to 15 V
2.2

1.8
Pin 16 = VCC

1.4

1.0
−55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
Figure 18. Minimum Operating Supply
Voltage vs. Temperature

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 NCP3163

INTRODUCTION

The NCP3163 is a monolithic power switching regulator oscillator cycle, a partial cycle plus a complete cycle,
optimized for DC−to−DC converter applications. The multiple cycles, or a partial cycle plus multiple cycles.
combination of its features enables the system designer to
directly implement step−up, step−down, and voltage− Oscillator
inverting converters with a minimum number of external The oscillator frequency and on−time of the output switch
components. Potential applications include cost sensitive are programmed by the value selected for timing capacitor
consumer products as well as equipment for the automotive, CT. Capacitor CT is charged and discharged by a 9 to 1 ratio
computer, and industrial markets. A representative block internal current source and sink, generating a negative going
diagram is shown in Figure 2. sawtooth waveform at Pin 6. As CT charges, an internal
pulse is generated at the oscillator output. This pulse is
OPERATING DESCRIPTION connected to the NOR gate center input, preventing output
switch conduction, and to the AND gate upper input,
The NCP3163 operates as a fixed on−time, variable allowing the latch to be reset if the comparator output is low.
off−time voltage mode ripple regulator. In general, this Thus, the output switch is always disabled during ramp−up
mode of operation is somewhat analogous to a capacitor and can be enabled by the comparator output only at the start
charge pump and does not require dominant pole loop of ramp−down. The oscillator peak and valley thresholds are
compensation for converter stability. The Typical Operating 1.25 V and 0.55 V, respectively, with a charge current of
Waveforms are shown in Figure 19. The output voltage 225 mA and a discharge current of 25 mA, yielding a
waveform shown is for a step−down converter with the maximum on−time duty cycle of 90%. A reduction of the
ripple and phasing exaggerated for clarity. During initial maximum duty cycle may be required for specific converter
converter startup, the feedback comparator senses that the configurations. This can be accomplished with the addition
output voltage level is below nominal. This causes the of an external deadtime resistor (RDT) placed across CT. The
output switch to turn on and off at a frequency and duty cycle resistor increases the discharge current which reduces the
controlled by the oscillator, thus pumping up the output filter on−time of the output switch. The converter output can be
capacitor. When the output voltage level reaches nominal, inhibited by clamping CT to ground with an external NPN
the feedback comparator sets the latch, immediately small−signal transistor. To calculate the frequency when
terminating switch conduction. The feedback comparator only CT is connected to Pin 6, use the equations found in
will inhibit the switch until the load current causes the output Figure 22. When RT is also used, the frequency and
voltage to fall below nominal. Under these conditions, maximum duty cycle can be calculated with the NCP3163
output switch conduction can be inhibited for a partial design tool found at www.onsemi.com.

1
Comparator Output
0
1.25 V
Timing Capacitor CT
0.55 V
t 9t
1
Oscillator Output
0

On
Output Switch
Off
Nominal Output
Voltage Level

Output Voltage
Startup Quiescent Operation

Figure 19. Typical Operating Waveforms

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 NCP3163

Feedback and Low Voltage Indicator Comparators output state is controlled by the highest voltage applied to
Output voltage control is established by the Feedback either of the two noninverting inputs.
comparator. The inverting input is internally biased at 1.25 V The Low Voltage Indicator (LVI) comparator is designed
and is not pinned out. The converter output voltage is for use as a reset controller in microprocessor−based
typically divided down with two external resistors and systems. The inverting input is internally biased at 1.125 V,
monitored by the high impedance noninverting input at Pin 2. which sets the noninverting input thresholds to 90% of
The maximum input bias current is ±0.4 mA, which can cause nominal. The LVI comparator has 15 mV of hysteresis to
an output voltage error that is equal to the product of the input prevent erratic reset operation. The Open Collector output is
bias current and the upper divider resistance value. For capable of sinking in excess of 6.0 mA (see Figure 13). An
applications that require 5.0 V, the converter output can be external resistor (RLVI) and capacitor (CDLY) can be used to
directly connected to the noninverting input at Pin 3. The high program a reset delay time (tDLY) by the formula shown
impedance input, Pin 2, must be grounded to prevent noise below, where Vth(MPU) is the microprocessor reset input
pickup. The internal resistor divider is set for a nominal threshold. Refer to Figure 20.

ǒ Ǔ
voltage of 5.05 V. The additional 50 mV compensates for a
1
1.0% voltage drop in the cable and connector from the
Vth(MPU)
converter output to the load. The Feedback comparator’s tDLY = RLVI ⋅ CDLY ⋅ In 1−
Vout

3 14

2
+ Feedback 15
+
− Comparator
RLVI + 1.25 V
Low Voltage 1 + 16
Indicator Output −
CDLY LVI 1.125 V
L
Vout
(Bottom View) CO

Figure 20. Partial Application Schematic Showing

Implementation of LVI Delay with RLVI and CDLY

Current Limit Comparator, Latch and Thermal 200 ns. The parasitic inductance associated with RSC and the
Shutdown circuit layout should be minimized. This will prevent
With a voltage mode ripple converter operating under unwanted voltage spikes that may falsely trip the Current
normal conditions, output switch conduction is initiated by Limit comparator.
the oscillator and terminated by the Voltage Feedback Internal thermal shutdown circuitry is provided to protect
comparator. Abnormal operating conditions occur when the the IC in the event that the maximum junction temperature
converter output is overloaded or when feedback voltage is exceeded. When activated, typically at 170°C, the Latch
sensing is lost. Under these conditions, the Current Limit is forced into the “Set” state, disabling the Output Switch.
comparator will protect the Output Switch. This feature is provided to prevent catastrophic failures from
The switch current is converted to a voltage by inserting accidental device overheating. It is not intended to be used
a fractional ohm resistor, RSC, in series with VCC and output as a replacement for proper heatsinking.
switch transistor Q2. The voltage drop across RSC is
monitored by the Current Sense comparator. If the voltage Driver and Output Switch
drop exceeds 250 mV with respect to VCC, the comparator To aid in system design flexibility and conversion
will set the latch and terminate output switch conduction on efficiency, the driver current source and collector, and
a cycle−by−cycle basis. This Comparator/Latch output switch collector and emitter are pinned out
configuration ensures that the Output Switch has only a separately. This allows the designer the option of driving the
single on−time during a given oscillator cycle. The output switch into saturation with a selected force gain or
calculation for a value of RSC is: driving it near saturation when connected as a Darlington.
The output switch has a typical current gain of 70 at 2.5 A
RSC + 0.25 V and is designed to switch a maximum of 40 V collector to
Ipk (Switch)
emitter, with up to 3.4 A peak collector current. The
Figures 14 and 15 show that the Current Sense comparator minimum value for RSC is:
threshold is tightly controlled over temperature and has a
typical input bias current of 1.0 mA. The propagation delay RSC(min) + 0.25 V + 0.0735 W
3.4 A
from the comparator input to the Output Switch is typically

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 NCP3163

When configured for step−down or voltage−inverting low ESR capacitors. The equation below is used to calculate
applications (see application notes at the end of this a minimum value bootstrap capacitor based on a minimum
document) the inductor will forward bias the output rectifier zener voltage and an upper limit current source.
when the switch turns off. Rectifiers with a high forward
CB(min) + I Dt + 4.0 mA on + 0.001 ton
t
voltage drop or long turn−on delay time should not be used. DV 4.0 V
If the emitter is allowed to go sufficiently negative, collector Parametric operation of the NCP3163 is guaranteed over
current will flow, causing additional device heating and a supply voltage range of 2.5 V to 40 V. When operating
reduced conversion efficiency. below 3.0 V, the Bootstrap Input should be connected to
Figure 12 shows that by clamping the emitter to 0.5 V, the VCC. Figure 18 shows that functional operation down to
collector current will be in the range 10 mA over 1.7 V at room temperature is possible.
temperature. A 1N5822 or equivalent Schottky barrier
rectifier is recommended to fulfill these requirements. Package
A bootstrap input is provided to reduce the output switch The NCP3163 is contained in a heatsinkable 16−lead
saturation voltage in step−down and voltage−inverting plastic package in which the die is mounted on a special heat
converter applications. This input is connected through a tab copper alloy pad. This pad is designed to be soldered
series resistor and capacitor to the switch emitter and is used directly to a GND connection on the printed circuit board to
to raise the internal 2.0 mA bias current source above VCC. improve thermal conduction. Since this pad directly
An internal zener limits the bootstrap input voltage to VCC contacts the substrate of the die, it is important that this pad
+7.0 V. The capacitor’s equivalent series resistance must be always soldered to GND, even if surface mount heat
limit the zener current to less than 100 mA. An additional sinking is not being used. Figure 21 shows recommended
series resistor may be required when using tantalum or other layout techniques for this package.

Vias to 2nd Layer Metal

for Maximum Heat Sinking

Exposed Pad

0.175

0.188

Minimum
Recommended
Exposed Copper

0.145

Flare Metal for Maximum Heat Sinking

Figure 21. Layout Guidelines to Obtain Maximum

Package Power Dissipation

APPLICATIONS

Figures 23 through 30 show the simplicity and flexibility equations for the key parameters. Additionally, a complete
of the NCP3163. Three main converter topologies are application design aid for the NCP3163 can be found at
demonstrated with actual test data shown below each of the www.onsemi.com.
circuit diagrams. Figure 22 gives the relevant design

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 NCP3163

Calculation Step−Down Step−Up Voltage−Inverting

(See Notes 1,2,3)
ton V out ) V F V out ) V F – V in |V out| ) V F
toff V * V sat * V out V – V sat V * V sat
in in in

t on t on t on
t off t off t off
ton
ƒ ǒ t on
t
off
) 1 Ǔ ƒ ǒ t on
t
off
) 1 Ǔ ƒ ǒ t on
t
off
) 1 Ǔ
CT 32.143 · 10*6 * 20 @ 10 *12 32.143 · 10*6 * 20 @ 10 *12 32.143 · 10*6 * 20 @ 10 *12
f f f

IL(avg) Iout I out ǒ t on

t
off
) 1 Ǔ I out ǒt on
t
off
) 1 Ǔ
DI L DI L DI L
Ipk (Switch) IL(avg) ) IL(avg) ) IL(avg) )
2 2 2
0.25 0.25 0.25
RSC Ipk (Switch) Ipk (Switch) Ipk (Switch)

L ǒ V
in
* V sat * V out
DI L
Ǔ t on ǒ V
in
* V sat
DI L
Ǔ t on ǒV
in
* V sat
DI L
Ǔ t on

ǒ8 ƒ1COǓ
2 t on I out t on I out
Vripple(pp) DIL ) (ESR)2 [ [
C C
O O

Vout V
ref
ǒ R2
R1
) 1 Ǔ V
ref
ǒ R2
R1
) 1 Ǔ V
ref
ǒ R2
R1
) 1 Ǔ
The following Converter Characteristics must be chosen:

Vin − Nominal operating input voltage.

Vout − Desired output voltage.
Iout − Desired output current.
DI L −Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less
than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit
threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will
proportionally reduce converter output current capability.
p − Maximum output switch frequency.
Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value
since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.

NOTES: 1. Vsat − Saturation voltage of the output switch, refer to Figures 10 and 11.
NOTES: 2. VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V.
NOTES: 3. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum
NOTES: 3. operating input voltage.

Figure 22. Design Equations

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 NCP3163

Current
0.25 V
8 − Limit 9
+
RSC
Vin 7 10
Cin VCC

6 Oscillator Q1 11
RT CT
R Q2
5 Q 12
Thermal S 60
Latch
4 13
VCC

3 14
45 k
R1 + Feedback
2 + 15
− Comparator D
+ 1.25 V 15 k 2.0 mA
R2 1 + 16
− 7.0 V
LVI 1.125 V VCC CB RB
L
Vout
(Bottom View) CO

Figure 23. Typical Buck Application Schematic

Value of Components
Name Value Name Value
L 47 mH R1 15 kW
D 2 A, 40 V Schottky Rectifier R2 24.9 kW
Cin 47 mF, 35 V Rsc 80 mW, 1 W
Cout 100 mF, 10 V Cb 4.7 nF
Ct 270 pF ±10% Rb 200 W
Rt 15 kW

Test Results for Vout = 3.3 V

Test Condition Results
Line Regulation Vin = 8.0 V to 24 V, Iout = 2.5 A 13 mV
Load Regulation Vin = 12 V, Iout = 0 to 2.5 A 25 mV
Output Ripple Vin = 12 V, Iout = 0 to 2.5 A 100 mVpp
Efficiency Vin = 12 V, Iout = 2.5 A 70.3%
Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A

Test Results for Vout = 5.05 V

Test Condition Results
Line Regulation Vin = 10.2 V to 24 V, Iout = 2.5 A 54 mV
Load Regulation Vin = 12 V, Iout = 0 to 2.5 A 28 mV
Output Ripple Vin = 12 V, Iout = 0 to 2.5 A 150 mVpp
Efficiency Vin = 12 V, Iout = 2.5 A 75.5%
Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A

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Figure 24. Buck Layout

APPLICATION SPECIFIC CHARACTERISTICS

85
3.3 V Eff
80

75
EFFICIENCY (%)

5.0 V Eff
70

65

60

55

50
0 0.5 1.0 1.5 2.0 2.5
Iout (A)

Figure 25. Efficiency vs. Output Current for the

Buck Demo Board at Vin = 12 V, TA = 255C

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Current L
0.25 V
8 − Limit 9
+
RSC
Vin
Cin + 7 10
VCC

6 Oscillator Q1 11
RT CT Q2
R
5 Q 12
Thermal S 60
Latch
4 13
VCC
D
3 14
45 k
+ Feedback
2 + 15
− Comparator
+ 1.25 V 15 k 2.0 mA
1 + 16
− 7.0 V
LVI 1.125 V VCC

+ Vout
R2 R1 (Bottom View) CO

Figure 26. Typical Boost Application Schematic

Value of Components for Vout = 24 V

Name Value Name Value
L 33 mH R1 42.2 kW
D 2 A, 40 V Schottky Rectifier R2 2.32 kW
Cin 330 mF, 35 V Cout 330 mF, 25 V
Ct 270 pF ±10% Rsc 80 mW, 1 W
Rt 15 kW

Test Results for Vout = 24 V

Test Condition Results
Line Regulation Vin = 10 V to 20 V, Iout = 700 mA 90 mV
Load Regulation Vin = 12 V, Iout = 0 to 700 mA 80 mV
Output Ripple Vin = 12 V, Iout = 0 to 700 mA 300 mVpp
Efficiency Vin = 12 V, Iout = 700 mA 83%
Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A

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Figure 27. Boost Demo Board Layout

86

84
EFFICIENCY (%)

82

80

78

76

74
0.1 0.2 0.3 0.4 0.5 0.6 0.7
Iout (A)

Figure 28. Efficiency vs. Output Current for the

Boost Demo Board at Vin = 12 V, TA = 255C

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Current
0.25 V
8 − Limit 9
RSC +

Vin +
7 10
Cin VCC
6 Oscillator Q1 11
RT CT
R Q2
5 Q 12
Thermal S 60
Latch
4 13
VCC

3 14
L
45 k
+ Feedback
2 + 15
− Comparator RB
+ 1.25 V 15 k 2.0 mA CB
1 + 16
− 7.0 V
LVI 1.125 V VCC D

Vout
R1
R2 (Bottom View) + CO

Figure 29. Typical Voltage Inverting Application Schematic

Value of Components for Vout = −15 V

Name Value Name Value
L 47 mH R1 1.07 kW
D 2 A, 40 V Schottky Rectifier R2 11.8 kW
Cin 270 mF, 16 V Rsc 80 mW, 1 W
Cout 2 X 270 mF, 16 V Cb 4.7 nF
Ct 150 pF ±10% Rb 200 mW

Test Results for Vout = −15 V

Test Condition Results
Line Regulation Vin = 7.0 V to 16 V, Iout = 500 mA 35 mV
Load Regulation Vin = 12 V, Iout = 0 to 500 mA 20 mV
Output Ripple Vin = 12 V, Iout = 0 to 500 mA 100 mVpp
Efficiency Vin = 12 V, Iout = 500 mA 68%
Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A

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 NCP3163

Figure 30. Voltage Inverting Demo Board Layout

70

66
EFFICIENCY (%)

62

58

54

50
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Iout (A)

Figure 31. Efficiency vs. Output Current for the

Voltage Inverting Demo Board at Vin = 12 V, TA = 255C

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 NCP3163

ORDERING INFORMATION
Device Package Shipping †
NCP3163PWG SOIC−16 W Exposed Pad 47 Units / Rail
(Pb−Free)
NCP3163PWR2G SOIC−16 W Exposed Pad 1000 / Tape & Reel
(Pb−Free)
NCP3163BPWG SOIC−16 W Exposed Pad 47 Units / Rail
(Pb−Free)
NCP3163BPWR2G SOIC−16 W Exposed Pad 1000 / Tape & Reel
(Pb−Free)
NCP3163MNR2G DFN18 2500 / Tape & Reel
(Pb−Free)
NCP3163BMNR2G DFN18 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 NCP3163

PACKAGE DIMENSIONS

SOIC 16 LEAD WIDE BODY, EXPOSED PAD

PW SUFFIX
CASE 751AG−01
ISSUE O
−U− NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
16 9 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
P SIDE.
B 5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.25 (0.010) M W M
R x 45_
8 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
−W− 6. 751R−01 OBSOLETE, NEW STANDARD 751R−02.

MILLIMETERS INCHES
G 14 PL
PIN 1 I.D. DIM MIN MAX MIN MAX
DETAIL E A 10.15 10.45 0.400 0.411
TOP SIDE B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
C G 1.27 BSC 0.050 BSC
F H 3.31 3.51 0.130 0.138
−T−
J 0.25 0.32 0.010 0.012
0.10 (0.004) T D 16 PL K SEATING
K 0.00 0.10 0.000 0.004
PLANE
L 4.58 4.78 0.180 0.188
0.25 (0.010) M T U S W S M 0_ 7_ 0_ 7_
J P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
H DETAIL E

EXPOSED PAD
1 8 SOLDERING FOOTPRINT*
L 0.350
Exposed
16 9 0.175 Pad
0.050

BACK SIDE
CL
0.188

0.200 0.376
CL

0.074

0.024 0.145
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NCP3163

PACKAGE DIMENSIONS

18−LEAD DFN, 5 x 6 mm
MN SUFFIX
CASE 505−01
ISSUE B NOTES:
A 1. DIMENSIONS AND TOLERANCING PER
D ASME Y14.5M, 1994.
B 2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PIN 1 LOCATION PAD AS WELL AS THE TERMINALS.
E
2X MILLIMETERS
DIM MIN MAX
0.15 C A 0.80 1.00
2X A1 0.00 0.05
A3 0.20 REF
0.15 C TOP VIEW b 0.18 0.30
D 6.00 BSC
D2 3.98 4.28
E 5.00 BSC
E2 2.98 3.28
(A3)
0.10 C e 0.50 BSC
K 0.20 −−−
18X A L 0.45 0.65
0.08 C
A1
C
SIDE VIEW SEATING
PLANE

D2
18X L e
1 9

E2
18X K

18 10
18X b
0.10 C A B
0.05 C NOTE 3

BOTTOM VIEW

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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