Sourcebook PreCCAT 2023
Sourcebook PreCCAT 2023
Sourcebook PreCCAT 2023
1. Course Objective:
a. To prepare for C-DAC entrance exam (C-CAT).
2. Prerequisite:
Candidates should have knowledge of basics of Computer.
3. Eligibility:
a. Graduate in discipline of Engineering (10+2+4 or 10+3+3 years)
b. Post Graduate Degree in Physics / Mathematics / Statistics, OR
c. MCA, MCM, OR
d. Post Graduate Degree in Management with graduation in IT / Computer Science/Applications.
The candidates must have secured a minimum of 50% marks in their qualifying examination.
o Sorting Algorithms – Selection Sort, Insertion Sort, Bubble Sort, Quick Sort, Merge Sort,
Heap Sort
• Session 13-15:
o Searching Algorithms – Sequential Search, Binary Search, Hashing
• Session 16-18:
o Trees – Binary Trees, Binary Search Trees
• Session 19-20:
o Graphs
• Session 1-4:
o Concept and characteristics of Big Data
o History of Big Data
o Jobs in Big Data
o Types of Big data (structured, semi-structured, unstructured)
• Session 5-9:
o Big Data Frameworks
o Big Data Programming Paradigms
o Big Data Programming Languages
• Session 10-11:
o Introduction to Data Science and Skillset required for working with Big Data
• Session 12-15:
o Simplified Overview of Machine Learning Algorithms and Neural Networks
o Types of Machine Learning (Supervised, Un-Supervised, Reinforcement)
• Session 16-18:
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o Examples of Big Data and Data Science in Practice (Healthcare, Logistics & Transportation,
Manufacturing etc.
• Session 19-20:
o Application Examples and Real –World Use Cases (e.g., Healthcare, finance, marketing, etc.)
• Session 1-5:
o Definition of Artificial Intelligence
o Understanding AI
o Different types of AI and main domains of AI technology
• Session 6-10:
o History of Al
o Al Uses
o Various applications of AI
• Session 11-13:
o Advantages and disadvantages associated with Artificial Intelligence
• Session 14-16:
o Learn about the basics of Neural Networks, Fuzzy Logic and Genetic Algorithms
• Session 17-20:
o Current trends and future directions in AI
▪ Associative Mapping
▪ Block-set-associative mapping
▪ Replacement Algorithms
▪ Least Recent Used (LRU) Replacement Policy
▪ FIFO replacement policy
▪ Random replacement policy
• Session 15-16:
o Memory Banking
▪ Even Bank
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▪ Odd Bank
▪ Lower Bank
▪ Higher Bank
• Session 17-18:
o Introduction to quantum computing
▪ Superposition
▪ Entanglement
• Session 19-20:
o Conventional Computing vs Quantum Computing
• Session 21-22:
o Rethinking binary with Quantum computers
▪ How traditional computers work?
▪ Rethinking binary and transistors
▪ How quantum computing work?
▪ Advantages and Applications
• Session 23-24:
o Flynn’s taxonomy
▪ Parallel Computing
▪ Single-instruction, single-data (SISD) systems
▪ Single-instruction, multiple-data (SIMD) systems
▪ Multiple-instruction, single-data (MISD) systems
▪ Multiple-instruction, multiple-data (MIMD) systems
• Session 25-27:
o Clusters in Computer Organization
▪ Load Balancing Cluster
▪ Fail over Clusters
▪ High Availability Clusters
▪ Advantages
• Session 28-30:
o Parallel processing – systolic arrays
▪ Characteristics
▪ Advantages
▪ Disadvantages
• Session 31-33:
o 8259 PIC Microprocessor
▪ Features
▪ Pin Diagram
▪ Block Diagram
o Block Diagram of 8259 Microprocessor
▪ Registers – ISR, IRR & IMR
▪ Priority Resolver
▪ SP/EN (Low Active Pin)
▪ Cascade Buffer
o Microprocessor | 8251 USART
▪ Block Diagram
• Session 34-35:
o Evolution of Microprocessors
▪ 8, 16, 32, 64-bit microprocessors
▪ Generation of Microprocessors
▪ Types of Microprocessors
▪ Advantages
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▪ Disadvantages
o Human – Computer interaction through the ages
• Session 36-38:
o Computer Ports
▪ Serial Ports
▪ Parallel Ports
▪ PS/2 ports
▪ Universal serial bus port
▪ VGA Ports
▪ HDMI Ports
▪ Modem port
▪ Ethernet Port
▪ Game Port
▪ Sockets
▪ DVI Port
• Session 39-41:
o Introduction to Parallel Computing
▪ Introduction
▪ Types of Parallelism
▪ Bit-level parallelism
▪ Instruction-level parallelism
▪ Task Parallelism
▪ Advantages and Limitations
▪ Future of Parallel Computing
• Session 42-44:
o Hardware architecture (parallel computing)
▪ Computing
▪ Types of Computing
▪ Parallel computing
▪ Hardware architecture of parallel computing
o Computer Architecture | Multiprocessor and Multicomputer
▪ Multiprocessor
▪ Advantages, Benefits
▪ Multicomputer
▪ Difference between Multicomputer and Multiprocessor
• Session 43-46:
o Timing diagram of INR M in 8085
o Priority Interrupts
▪ Software Method – Polling
▪ Hardware Method – Daisy Chaining
o I/O Interface
▪ Modes of transfer
▪ Programmed I/O
▪ Interrupt-initiated I/O
▪ Direct Memory Access
▪ Types of DMA transfer using DMA Controller
▪ Cyclic Stealing
o Direct memory access with DMA controller 8257/8237
▪ Modes of DMAC
o Computer Organization | Asynchronous input output synchronization
▪ Problem faced in asynchronous input output synchronization
▪ Strobe Mechanism
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▪ Handshaking Mechanism
• Session 44-47:
o Programmable peripheral interface 8255
▪ Block Diagram
▪ Pin Diagram
▪ Operating Modes
o Interface 8255 with 8085 microprocessors for 1’s and 2’s complement of a number
o Microprocessor | 8255 (programmable peripheral interface)
▪ 8255
▪ 8255 pin Diagram
▪ Modes of 8255
o Interface 8254 PIT with 8085 microprocessors
▪ 8254 Control Register and Operating modes
o Synchronous Data Transfer in Computer Organization
▪ Advantages and Disadvantages
• Session 48:
o Introduction of Input-Output Processor
▪ The Block Diagram
o MPU Communication in Computer Organization
▪ I/Os with 8-bit addresses
▪ I/Os with 16-bit addresses
• Session 49:
o Memory mapped I/O and Isolated I/O
▪ Isolated I/O
▪ Memory Mapped I/O
▪ Their differences
• Session 50:
o BUS Arbitration in Computer Organization
▪ Centralized bus arbitration
▪ Distributed bus arbitration
▪ Methods of Centralized BUS Arbitration
▪ Logic Gates
• Session 14-16:
o Gate Level Minimization:
▪ K-Map (Karnaugh Map)
▪ Implicants in K-Map
▪ 5 variable K-Map
▪ Variable entrant map (VEM)
▪ Minimization of Boolean Functions
▪ Consensus theorem
• Session 17-20:
o Combinational Logic Circuits:
▪ Half-Adder
▪ Half-Subtractor
▪ Half-Adder and Half-Subtractor using NAND NOR Gates
▪ Full-Adder
▪ Full Subtractor
▪ Code Converters – BCD (8421) to/from Excess-3
▪ Code Converters – Binary to/from Gray Code
▪ Code Converters – BCD to 7 Segment Decoder
▪ Parallel Adder & Parallel Subtractor
▪ Carry Look-Ahead Adder
▪ Magnitude Comparator
▪ BCD Adder
▪ Encoders and Decoders
▪ Encoder
▪ Binary Decoder
▪ Combinational circuits using Decoder
▪ Multiplexers
▪ Static Hazards
• Session 21-22:
o Flip-Flops and Sequential Circuits:
▪ Latches
▪ One-bit memory cell
▪ Flip-Flops (Types and Conversions)
▪ Master Slave JK Flip Flop
▪ Introduction of Sequential Circuits
▪ Synchronous Sequential Circuits
▪ Asynchronous Sequential Circuits
▪ Difference between combinational and sequential circuit
▪ RTL (Register Transfer Level) design vs Sequential logic design
▪ Difference between Synchronous and Asynchronous Sequential Circuits
• Session 23-25:
o Register and Counters:
▪ Counters
▪ Design counter for given sequence
▪ n-bit Johnson Counter
▪ Amortized analysis for increment in counter
▪ Ripple Counter
▪ Digital Logic | Ring Counter
▪ Shift Registers
▪ Design 101 sequence detector
▪ Universal Shift Register
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