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Application Note
I2C Solutions for Hot Swap Applications

Nguyen, Duy (Bobby)

ABSTRACT
This document discusses I 2C
hot insertion/hot swap into live backplanes, the potential problems users could
face, and how some devices can add layers of safety for hot insertion applications.

Table of Contents
1 What is an I2C Hot Swap Device?..........................................................................................................................................2
2 Hot Insertion Concerns.......................................................................................................................................................... 2
3 Discrete Hot-Insertion Implementation on the Backplane..................................................................................................3
4 Designing the External Card for Hot Insertion.....................................................................................................................4
5 Rise Time Accelerator............................................................................................................................................................ 6
6 Conclusion.............................................................................................................................................................................. 7
7 Revision History......................................................................................................................................................................8

List of Figures
Figure 3-1. Descrete Hot Insertion Support on a Back Plane......................................................................................................3
Figure 4-1. Example of External Card Design Without Pull up Resistors on TCA9511A IN-side................................................ 4
Figure 4-2. Example of Staggering Male Connector to Support Hot Insertion on External Card.................................................5
Figure 5-1. 360 pF Loading with an External 10 kΩ Pull up and Rise Time Accelerator Disabled.............................................. 6
Figure 5-2. 360 pF Loading with an External 10 kΩ Pull up With Rise Time Accelerator Enabled..............................................7

Trademarks
All trademarks are the property of their respective owners.

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What is an I2C Hot Swap Device? www.ti.com

1 What is an I2C Hot Swap Device?

A device which is capable of hot insertion/hot swap means it can be plugged into a live backplane from an
external PCB without the need to power down the backplane. This kind of feature is useful in applications where
powering down a system may be undesirable or not possible such as in servers or wireless base stations. Hot
insertion devices help to prevent glitches to the downstream devices while trying to minimize the effect of adding
parasitic capacitance into a live bus.
2 Hot Insertion Concerns
Two potential concerns when a hot insertion event occurs on a live bus are false clock edge generation and a
bad power on reset for the downstream I2C slave. A false clock edge could be created during insertion when
SCL is a logic high due to the initial in rush current from the live backplane going to fill the parasitic capacitance
of the external card. This presents a problem because the I2C slave on the bus may see the additional clock
edge and it becomes out of sync with the master’s actual clock pulses. In the worst case scenario, an I2C stuck
bus occurs where the SDA line becomes stuck because the slave is waiting for the last clock pulse to release the
SDA line. This can cause major problems in a system which relies on I2C to pass information before executing
actions/diagnostics.
If the SCL signal on the backplane is at a logic low, the inrush current would not be a concern and a false
clock edge would not be generated. Relying on this to occur each time a hot insertion event occurs is unlikely to
happen and doomed to an eventual stuck bus event occurring.
The second concern for a bad power on reset is derived from the power supply ramp up requirements of the
downstream I2C device and any parasitic capacitance or inductance on the power trace between the backplane
and the I2C device on the external card. I2C devices typically require the VCC ramp rate to be within a certain
minimum or maximum to power up correctly. Being outside of that range due to a hot insertion event (parasitic
inductance causing ringing on the VCC ramp) could result in the downstream I2C device state machine powering
up in an unknown state. If this occurs, the downstream I2C device may power up thinking it is in a read
transaction and end up holding the SDA line low or even in a clock stretching event and lock up the SCL line.

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www.ti.com Discrete Hot-Insertion Implementation on the Backplane

3 Discrete Hot-Insertion Implementation on the Backplane

A discrete approach to preventing a glitch from occurring during the hot insertion event can be implemented
using an I2C switch or I2C buffer with an enable pin. This can be accomplished by designing the I2C switch or
buffer to sit on the edge of the backplane. For the I2C switch, a presence detect signal should be placed on the
external card and feed into the backplane interrupt detection system. This tells the processor when an external
card has been connected to the backplane and can extract data from the downstream I2C slave. Figure 3-1
shows an example of this being implemented with the presence detection signal feeding into a TCA9555 input.
This set up allows for multiple cards to be inserted by using the spare channels on the TCA954x (I2C switch) and
TCA9555 (I2C I/O Expander) for the interrupt detection. The TCA9555 is not necessary though if the processor
has unused GPIOs available.
In this system, when the external card is inserted, the backplane provides power and a common ground
connection to the I2C slave. The backplane I2C pull up resistors on the secondary channel of the I2C switch
pulls the slave SDA/SCL pins high. The TCA9555 has its GPI logic changed from a digital HIGH (an internal
100k pullup) to a digital LOW from the GND connection when the external card is connected. This generates the
interrupt and signals the processor to check to see which input generated the interrupt and then enable the I2C
switch channel that the external card to which it is connected.
Power from
Back Plane backplane
VCC VCC

VCC

VCC VCC
SDA0 SDA
I2C slave
SCL0 SCL
Main I2C SDA TCA954x
lines to GND
processor SCL Hot Insertion
Common GND from
GND Backplane
VCC

VCC Presence Detection

to generate INT

INT VCC GPIOx

External Card
Main I2C SDA TCA9555
lines to
processor SCL

GND

Figure 3-1. Descrete Hot Insertion Support on a Back Plane

Additional notes:
• The external card should connect GND and then power before SDA/SCL:
– This helps prevent any potential back biasing through the SDA/SCL lines if they connect first.
– Requires a female to male connector which staggers the signals to connect at different times.
• This approach helps to prevent glitches on the main bus but does not protect the I2C slave from a bad POR.
– In the worst case scenario, the processor connects the I2C slave to the main bus while it holding the
SCL/SDA line low..
– An I2C switch with a reset can be used to disable all I2C channels to regain I2C control. This does require
the processor to be programmed to detect the stuck bus and toggle the reset if this occurs.
• The switch in Figure 3-1 can be replaced with an I2C level shifter or I2C buffer with an enable pin.
• TCA9555 can be replaced with any I2C GPIO expander with an interrupt feature.

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4 Designing the External Card for Hot Insertion

The approach mentioned previously may not be possible if the system designer does not have control over the
design of the backplane but instead has control of the external card. In this case, using a hot-insertion buffer
on the external card would be an ideal approach. The TCA9511A is a potential device to fit this application.
This devices features a 1-V pre-charge circuit, slew rate triggered rise time accelerators, and stop/idle condition
detection for ‘smart’ connection.
The 1-V pre-charge feature helps to limit the inrush current when the external card SDA/SCL connection is made
with the backplane. While not foolproof, the 1-V pre-charge can help to mitigate glitches during the hot insertion
event into a live bus. In order for the 1-V pre-charge feature to be used during the hot insertion event, two design
considerations must be ensured.
The first design set up that needs to be done is the ‘IN-side’ of the TCA9511A needs to be designed to make
connection with the backplane from the external card. This is because the ‘IN-side’ of the device does its
bus idle/stop condition detection only on the ‘IN-side’ of the device while the ‘OUT-side’ only looks to see if
the voltage is above VIH (Voltage input High). For this reason, pull up resistors should not be populated on
the ‘IN-side’ of the external card’s I2C bus as it would generate a false idle condition to the TCA9511A and
also turn off the 1-V pre-charge circuit. Figure 4-1 points out which side is the ‘IN-side’ of the TCA9511A and
non-populated pullup resistors on the ‘IN-side’.
External Card

8
VCC

SCLIN 3 2 SCLOUT

IN-side

SDAIN 6 7 SDAOUT

1 5
ENABLE READY
GND

Figure 4-1. Example of External Card Design Without Pull up Resistors on TCA9511A IN-side

The second design set up required is the connection from the external card to the backplane must connect
the ground and power to the external card first before the SDAIN/SCLIN connects to the backplane I2C bus.
The reason for this is the TCA9511A needs to power up and turn on its 1-V pre-charge circuit before the SCLIN/
SDAIN connects to the backplane. If the SDAIN or SCLIN lines connect to the backplane at the same time as
the power and ground, then the 1-V pre-charge circuit do not power up in time and the backplane I2C bus may
dip down towards ground momentarily if the SDA/SCL lines on the backplane are HIGH or transitioning HIGH.
This means the external card needs to have staggered connection points on its male connector. An example of a
staggered male connector is shown in Figure 4-2. In this example, the GND connects first. VCC is next which is
done by making the exposed copper trace for VCC about 25 mils shorter than GND. Afterwards, SDAIN or SCLIN
connects to the backplane because their exposed traces are 50 mils shorter than GND and 25 mils shorter than
VCC.

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www.ti.com Designing the External Card for Hot Insertion

Figure 4-2. Example of Staggering Male Connector to Support Hot Insertion on External Card

Once the connection between the external card and the backplane is made, the TCA9511A checks three
conditions:
1. Is the enable pin high?
2. Are the SCLOUT or SDAOUT pins high?
3. Has a stop condition or bus idle been detected on SCLIN or SDAIN?
If all three conditions are met, then the TCA9511A connects the ‘IN-side’ and the ‘OUT-side’ together and the
READY pin of the device goes HIGH to signal this.
Condition:
1. Allows the processor to have control over whether or not it wants to connect the downstream slaves on the
external card.
2. Check to ensure that the downstream slaves on the external card have powered up correctly, and do not
cause a stuck bus. In some cases, the VCC ramp up on the external card may be not be within the slave’s
data sheet power up specifications when the hot insertion occurs. In these instances, if the slave powers up
and gets the I2C bus stuck on the ‘OUT-side’, then the main I2C bus on the backplane does not also become
stuck.
3. Make sure that the connection between the ‘IN-side’ and ‘OUT-side’ are not made until the communication
on the backplane has stopped. If the two sides connected during communication, the slaves on the ‘OUT-
side’ of the external card may see a false I2C start condition and glitch the state machines of the I2C slaves.
These three conditions are what make the TCA9511A suitable devices for hot insertion applications.

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Rise Time Accelerator www.ti.com

5 Rise Time Accelerator

An additional advantage that the TCA9511A provides is the rise time accelerator (RTA) circuit on both sides of
the device. This is advantageous because in applications where the capacitive loading of the system upstream
from the external card is unknown, the rise time accelerators help to keep the rise time of the bus within I2C
specification when plugged into a heavily loaded system. For reference, version 2.6 of the I2C specification
requires the rise time to be less than 1000 ns for standard mode (100 kHz) and less than 300 ns for fast mode
(400 kHz). Rise time is defined as the time for a signal to go from 30% of VCC to 70% of VCC.
Figure 5-1 shows the rise time of a 360 pF load with an external pull up resistor of 10 kΩ in at VCC of 5 V.
The rise time in this system without the TCA9511A rise time accelerator is 3307 ns which is above the required
1000 ns and 300 ns for both standard mode and fast mode. Note that the time scale in Figure 5-1 is 800 ns per
division.

Figure 5-1. 360 pF Loading with an External 10 kΩ Pull up and Rise Time Accelerator Disabled

Figure 5-2 shows the same bus loading conditions of 360 pF and a 10 kΩ pull up resistor at 5 V VCC but this
time the TCA9511A is enabled and its rise time accelerator is engaged. The rise time in this case is 214.7 ns
which now meets the specification for both standard mode and fast mode. The two slew rates in the figure are
due to the original RC constant and then by the rise time accelerators pull up. The rise time accelerator for the
TCA9511A trigger when two conditions are met on both sides of the device:
1. The rising signal is above 0.6 V.
2. The slew rate of the rising signal is faster than 1.25 V/µs.
Note that the time scale in Figure 5-2 is 200 ns per division versus 800 ns per division in Figure 5-1.

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www.ti.com Conclusion

Figure 5-2. 360 pF Loading with an External 10 kΩ Pull up With Rise Time Accelerator Enabled

6 Conclusion
In systems where hot insertion is required, either the backplane or the external card must be properly designed
in order to minimize the effects of hot insertion. Devices like an I2C switch on the backplane or an I2C hot
insertion buffer on the external card are appropriate devices for such applications. Poor hot insertion designs
may result in a stuck bus and preventing key diagnostic information from being extracted to the processor
through the I2C bus.

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Revision History www.ti.com

7 Revision History
Changes from Revision * (February 2020) to Revision A (January 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1

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