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K Abhinay Kumar

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20 views

K Abhinay Kumar

Uploaded by

abhinay kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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K ABHINAY KUMAR

 abhinaykumar595@gmail.com

 + 91 7702653819

CAREER OBJECTIVE
Intend to build carrier with committed and dedicated people, which will help me to
realize my potential, enhance my skill set in the field of VLSI Physical design and help
the organization grow.
PROFESSIONAL EXPERIENCE
2+ years’ experience as physical design engineer at INCISE Infotech Private
Limited in Bangalore.
SUMMARY
 Experience in Physical Design for 45nm Technologies using Synopsys and
Cadence tools.
 Worked on Physical Design Flows I.e. Floor planning, Placement, CTS,
Routing and STA.
 Good in Scripting Skills (TCL/Tk).
 Always on the look to improve skills and grow with the organization.
SKILL SET
Floor Plan and PNR - ICC2, INNOVUS
Timing - Primetime, Tempus
Scripting - TCL/Tk
PROJECTS
BLOCK 1: PnR Implementation of the Block
Client : Canova Tech
Tool : INNOVUS
Clock Frequency : 416MHZ
Technology Node : 45nm
Instance Count : 84K
Macro Count : 70
Role and description:
 Tasks handled were Floor planning, place & route, Perform STA and bring the
block to timing closure.
 Checked the library consistency and validating SDC constraints.
 The block is timing and congestion critical Floorplan has become major thing
for better Qor. Performed multiple floorplans to get better floorplan.
 Made required changes in Tcl script for design optimization.

BLOCK 2: PnR Implementation of the Block


Client : INCU Solutions
Tool : ICC2
Clock Frequency : 269MHZ
Technology Node : 65nm
Instance Count : 72K
Macro Count : 54
Role and description:
 Netlist to GDSII flow including Place and Route.
 Rectilinear Floorplan with lots of congestion and utilization of around 75%.
 Resolved congestion due to pin density and cell density after placement.
 The block is congestion critical, Criticality faced while meeting the clock
latency.
 Insertion of clock buffers and inverters in CTS stage.

BLOCK 3: PnR Implementation of the Block


Client : INCU Solutions
Tool : ICC2
Clock Frequency : 166MHZ
Technology Node : 90nm
Instance Count : 58K
Macro Count : 24
Role and description:
 Did Floorplan to routing with necessary checks at each stage
 Placed hard macros based on flight line analysis manually.
 Creating power and ground rings and stripes.
 Insertion of placement constraints like guide, region, fence.
 Sufficient halo provided around macro to avoid routability issues.

ACADEMIC QUALIFICATIONS
 B. Tech in Electronics and Communication Engineering from National Institute
of Technology Agartala with 6.84 CGPA in 2017.
 Intermediate in MPC from Narayana Junior College with 95.1% at Nellore in
Andhra Pradesh (2012).
 Xth CBSE from JNV Chittoor Andhra Pradesh in 2010 with 8.2 CGPA.

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