Module - 4 Notes

Download as pdf or txt
Download as pdf or txt
You are on page 1of 20

Module – 4 Notes

Course Title: Microcontrollers Course Code: BEC405A


SEM: IV Credits: 03 L:T:P:S = 3:0:0:x
Prepared By: Dr. Babu N V, Prof. – ECE, Academic Dean

Module – 4: Interrupt Programming


Syllabus:
Interrupt Programming:
Basics of Interrupts, 8051 Interrupts, Programming Timer Interrupts, Programming Serial
Communication Interrupts, Interrupt Priority in 8051(Assembly Language only)
(Textbook 2- 3.6, Textbook 1-11.1,11.2,11.4, 11.5)

4.1 8051 INTERRUPTS:


Interrupts vs. polling:
There are two ways to determine whether the peripheral devices require attention or services of the
microcontroller.
1) Polling:
This method is based on software which requires the microcontroller to continuously monitor the status
of a peripheral device and provides services when the device requires service. This method is useful
when the processor has to do only one task (or a few) and response time is not an issue. The problems
with the polling method are the following:
1. It wastes microcontroller time by monitoring the device continuously.
2. Priorities can’t be assigned to devices because the status can be monitored one by one for all devices
irrespective of their priority and importance.
3. It makes the system slower because high-priority device has to wait for its turn when lower priority
devices are being polled and serviced.
2) Interrupt method:
In this method, whenever any device requires attention or services of the microcontroller, it will send an
interrupt signal to the microcontroller and in response to that, the microcontroller will stop the current
activity and serve the device and thereafter, resume the regular activity. Advantages of this method are:
1. Time of microcontroller is efficiently used as there is no wastage of time in continuous &
unnecessary monitoring.
2. Priorities can be given to different devices as per their importance and the higher priority device may
be programmed to interrupt lower priority devices.
3. It makes the system faster because more important activities are handled immediately.
4. More devices can be served (though, only one device at a time).
5. The system can be programmed to ignore any or all devices while handling critical tasks.
Six interrupts in the 8051:
In reality, only five interrupts are available to the user in the 8051, but many manufacturers' data sheets state
that there are six interrupts since they include reset. The six interrupts in the 8051 are allocated as follows.
1. Reset. When the reset pin is activated, the 8051 jumps to address location 0000. This is the power-up
reset.

Page 1 of 20
2. Two interrupts are set aside for the timers: one for Timer 0 and one for Timer 1. Memory locations
000BH and 001BH in the interrupt vector table belong to Timer 0 and Timer 1, respectively.
3. Two interrupts are set aside for hardware external hardware interrupts. Pin numbers 12 (P3.2) and
13 (P3.3) in port 3 are for the external hardware interrupts INT0 and INT1, respectively. Memory
locations 0003H and 0013H in the interrupt vector table are assigned to INT0 and INT1, respectively.
4. Serial communication has a single interrupt that belongs to both receive and transmit. The interrupt
vector table location 0023H belongs to this interrupt.
Interrupt service routine:
For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an interrupt
is invoked, the microcontroller runs the interrupt service routine. For every interrupt, there is a fixed location
in memory that holds the address of its ISR. The group of memory locations set aside to hold the addresses of
ISRs is called the interrupt vector table, shown in below table.

Table: Interrupt Vector Table for the 8051


Interrupt ROM Location (Hex) Pin Flag Clearing
Reset 0000 9 Auto
External hardware interrupt 0 (INT0) 0003 P3.2(12) Auto
Timer 0 interrupt (TF0) 000B Auto
External hardware interrupt (INT1) 0013 P3.3(13) Auto
Timer 1 interrupt (TF1) 001B Auto
Serial COM interrupt (RI and TI) 0023 Programmer clears it

Note:
If the service routine for a given interrupt is short enough to fit in the memory space allocated to it, it is
placed in the vector table; otherwise, an LJMP instruction is placed in the vector table to point to the address
of the ISR. In that case, the rest of the bytes allocated to that interrupt are unused.

Steps in executing an interrupt:


Upon activation of an interrupt, the microcontroller goes through the following steps.
1. It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e., not on the stack).
3. It jumps to a fixed location in memory called the interrupt vector table that holds the address of the
interrupt service routine.
4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. It starts to
execute the interrupt service subroutine until it reaches the last instruction of the subroutine, which is
RETI (return from interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted.
First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack
into the PC. Then it starts to execute from that address.

Page 2 of 20
Enabling and disabling an interrupt:
Upon reset, all interrupts are disabled (masked), meaning that none will be responded to by the
microcontroller if they are activated. The interrupts must be enabled by software in order for the
microcontroller to respond to them through the IE (Interrupt Enable) register by setting bit D7 which is called
as EA (enable all).
IE Register:
*bit addressable register
D7 D0

EA -- ET2 ES ET1 EX1 ET0 EX0

Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt


EA IE.7
source is individually enabled or disabled by setting or clearing its enable bit.
-- IE.6 Not implemented, reserved for future use *
ET2 IE.5 Enables or disables Timer 2'overflow or capture interrupt (8052 only).
ES IE.4 Enables or disables the serial port interrupt.
ET1 IE.3 Enables or disables Timer 1 overflow interrupt.
EX1 IE.2 Enables or disables external interrupt 1.
ET0 IE.1 Enables or disables Timer 0 overflow interrupt.
EX0 IE.0 Enables or disables external interrupt 0.

Steps in enabling an interrupt:


To enable an interrupt, we take the following steps:
1. Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take effect.
2. If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in IE are high. If
EA=0, no interrupt will be responded to, even if the associated bit in the IE register is high.

Ex: Show the instructions to (a) enable the serial interrupt, Timer 0 interrupt, and external hardware
interrupt 1 (EX1), and (b) disable (mask) the Timer 0 interrupt, then (c) show how to disable all
the interrupts with a single instruction.
Solution:
(a) MOV IE, #10010110B ;enable serial, Timer 0, EX1 {SETB IE.7, SETB IE.4, SETB IE.1 & SETB
IE.2}
(b) CLR IE.1 ;mask (disable) Timer 0 interrupt only
(c) CLR IE.7 ;disable all interrupts

Review questions:
1. Of the interrupt and polling methods, which one avoids tying down the microcontroller?
2. Besides reset, how many interrupts do we have in the 8051?

Page 3 of 20
3. In the 8051, what memory area is assigned to the interrupt vector table? Can the programmer change the
memory space assigned to the table? .
4. What are the contents of register IE upon reset, and what do these contents mean?
5. Show the instruction to enable the EX0 and Timer 0 interrupts.
6. What address in the interrupt vector table is assigned to the INT1 and Timer 1 interrupts?
7. Why is reset considered as an interrupt as well?
8. What is meant by the term ISR?
9. What is meant by the term interrupt vector?
10. What memory address in the interrupt vector table is assigned to INT0?
11. What memory address in the interrupt vector table is assigned to INT1?
12. What memory address in the interrupt vector table is assigned to Timer 0?
13. What memory address in the interrupt vector table is assigned to Timer 1?
14. What memory address in the interrupt vector table is assigned to the serial COM interrupt?
15. Why do we put an LJMP instruction at address 0?
16. What the contents of the IE register upon reset, and what do these values mean?
17. Show the instruction to enable theEX1 and Timer 1, interrupts.
18. Show the instruction to enable every interrupt of the 8051.
19. Which pin of the 8051 is assigned to the external hardware interrupts INT0 and INT1?
20. How many bytes of address space in the interrupt vector table are assigned to the INT0 and INT1
interrupts?
21. How many bytes of address space in the interrupt vector table are assigned to the Timer 0 and Timer 1
interrupts?
22. To put the entire interrupt service routine in the interrupt vector table, it must be no more than _____
bytes in size.
23. When an interrupt is activated, what is the first step taken by the 8051?
24. With a single instruction, show how to disable all the interrupts.
25. With a single instruction, show how to disable the EX1 interrupt.
26. What does the 8051 do on encountering the RETI instruction?
In the 8051, how many bytes of ROM space are assigned to the reset interrupt, and why?

4.2 PROGRAMMING TIMER INTERRUPTS:


Roll-over timer flag and interrupt:
In polling TF, we have to wait until the TF is raised. The problem with this method is that the
microcontroller is tied down while waiting for TF to be raised and cannot do anything else. Using interrupts
solves this problem and avoids tying down the microcontroller.
If the timer interrupt in the IE register is enabled, whenever the timer rolls over, TF is raised, and the
microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the
ISR. In this way, the microcontroller can do other things until it is notified that the timer has rolled over.
Note:
• We must avoid the memory space allocated to the interrupt vector table.
• The ISR for Timer is located starting from memory location 000Bh & 001Bh respectively for T0 & T1.

Page 4 of 20
Ex: Write a program that displays a value of 'Y' at port 0 and 'N' at port 2 and also generates a square
wave of 10kHz, with Timer 0 in mode 2 at port pin P1.2. XTAL = 22 MHz
Solution:
ORG 0000H
LJMP MAIN ;bypass interrupt vector table
; ISR for Timer 0 to generate square wave
ORG 000BH ;Timer 0 interrupt vector
CPL P1.2
RETI
; the main program for initialization
ORG 0030H ; a location after the interrupt vectors
MAIN: MOV TMOD, #02H ; Timer 0, mode 2(auto-reload)
MOV TH0, # 0B6H ; move count value into TH0
MOV IE, #82H ; enable interrupt timer 0
SETB TR0 ; start Timer 0
BACK: MOV P0, #’Y’ ; display ‘Y’ at port P0
MOV P2, #’N’ ; display ‘N’ at port P2
SJMP BACK ; keep doing this until interrupted
END

Ex: write a program to create a square wave that has a high portion of 1085 µs and a low portion of 15
µs. Assume XTAL = 11.0592 MHz. Use Timer 1.
Solution:
Since 1085 µs is 1000x 1.085 we need to use mode 1 of Timer1.
; Upon wake-up go to main, avoid using memory space
; allocated to interrupt vector Table
ORG 0000H
LJMP MAIN ;bypass interrupt vector table
;
; ISR for Timer 1 to generate square wave
ORG 001BH ; Timer 1 interrupt vector table
LJMP ISR -T1 ; jump to ISR
;
; The main program for initialization
ORG 0030H ; after vector table
MAIN: MOV TMOD, #10H ; Timer 1, mode 1
MOV P0, #0FFH ; make P0 an input port
MOV TL1, #018H ; TL1 = 18 the Low byte of -1000
MOV TH1, #0FCH ; TH1 = FC the High byte of -1000

Page 5 of 20
MOV IE, # 88H ; IE = 10001000 enables Timer 1 int.
SETB TR1 ; start Timer 1
BACK: MOV A, P0 ; get data from P0
MOV P1, A ; issue it to P1
SJMP BACK ; keep doing it
; Timer 1 ISR. Must be reloaded since not auto-reload
ISR_ T1: CLR TR1 ; stop Timer 1
CLR P2.1 ;P2.1=0, start of low portion
MOV R2, #4 ; 2MC
HERE: DJNZ R2, HERE ;4x2 machine cycle (MC) 8MC
MOV TL1, #18H ; load T1 Low byte value 2MC
MOV TH1, #OFCH ; load T1 High byte value 2MC
SETB TR1 ; starts Timer 1 1MC
SETB P2.1 ;P2.1 = 1, back to high 1MC
RETI ; return to main
END
Ex-4: Write a program to generate two square waves - one of 5 KHz frequency at pin P1.3, and
another of frequency 25kHz at pin P2.3. Assume XTAL = 22 MHz.
Solution:
ORG 0000H ; avoid using the interrupt vector table
LJMP MAIN
; ISR for Timer 0
ORG 0000B ; Interrupt vector for Timer 0
LJMP MAIN
CPL P1.3
RETI
; ISR for Timer 1
ORG 001BH ; Interrupt vector for Timer 1
CPL P2.3
RETI
;main program for initialization
ORG 0030H
MAIN: MOV TMOD, #22H ;both timers are initialized for Mode 2

MOV IE, #8AH ; enable the Timer 0 and Timer 1 Interrupts


MOV TH0, #048H ; count value for 5 KHz square wave
MOV TH1, #0B6H ; count value for 25 KHz square wave

Page 6 of 20
SETB TR0 ; start Timer 0
SETB TR1 ; start Timer 1

WAIT: SJMP WAIT ; keep waiting for the roll off of either timer

END
Ex: Write a program to toggle pin P1.2 every second.
Solution:
To get a large delay of 1 second, we need to use a register, in addition to a timer.
Here register R0 is used along with Timer 1 to get the large time delay.
; upon wake up, go to main, avoid using memory space allocated to interrupt vector table

ORG 0000H ; bypass interrupt vector table


LJMP MAIN
; -- ISR for Timer 1 to generate square wave
ORG 001BH
DJNZ R0, START
CPL P1.2 ; toggle pin P1.2 every second
MOV R0, #28 ; reload register value
MOV TL1, #00H ; reload counter value
MOV TH1, #00H ; reload counter value
START: RETI
;the main program for initialization
ORG 0030H
MAIN: MOV TMOD, 10H ; Timer 1, mode 1
MOV IE, #88H ; enable Timer 1 Interrupt
MOV R0, #28 ; count for 1 second delay
MOV TL1, #00H ; count value for TL1
MOV TH1, #00H ; count value for TH1
SETB TR1
HERE: SJMP HERE
Review Questions:
1. True or false. There is only a single interrupt in the interrupt vector table assigned to both Timer 0 and
Timer 1.
2. What address in the interrupt vector table is assigned to Timer 0?
3. Which bit of IE belongs to the timer interrupt? Show how both are enabled.
4. Assume that Timer 1 is programmed in mode 2, TH1 = F5H, and the IE bit for Timer 1 is enabled.
Explain how the interrupt for the timer works.
5. True or false. The last two instructions of the ISR for Timer 0 are:
CLR TF0; RETI
6. What is the effect of clearing, the EA bit of the IE register?

Page 7 of 20
7. Can the 8051 generate two square waves simultaneously?
8. Write a program to create a square wave of T = 160ms on pin P2.2 while at the same time the 8051 is
sending out 55H and AAH to P1 continuously.
9. Write a program in which every 2 seconds, the LED connected to P2.7 is turned on and off four times,
while at the same time the 8051 is getting data from P1 and sending it to P0 continuously: Make sure the
on and off states are 50ms in duration.

4.3 PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT:


RI and TI flags and interrupts
TI (transfer interrupt) is raised when the last bit of the framed data, the stop bit, is transferred, indicating that
the SBUF register is ready to transfer the next byte. RI (received interrupt), is raised when the entire frame of
data, including the stop bit, is received. In the polling method, we wait for the flag (TI or RI) to be raised;
while we wait, we cannot do anything else. In the interrupt method, we are notified when the 8051 has
received a byte or is ready to send the next byte; we can do other things while the serial communication
needs are served.
In the 8051 only one interrupt is set aside for serial communication. This interrupt is used to both send and
receive data. If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised the 8051 gets
interrupted and jumps to memory address location 0023H to execute the ISR. In that ISR we must examine
the TI and RI flags to see which one caused the interrupt and respond accordingly.
Clearing RI and TI before the RETI instruction
It is necessary and job of the ISR to clear RI or TI flags before the RETI, since there is only one interrupt for
both receive and transmit and the 8051 does not know who generated it. In serial communication the RI (or
TI) must be cleared by programmer using software instructions such as "CLR TI" and "CLR RI" in the ISR.
Ex: Write a program in which the 8051 reads data from P1 and writes it to P2 continuously while
giving a copy of it to the serial COM port to be transferred serially. Assume that XTAL = 11.0592
MHz. Set the baud rate at 9600.
Solution:
ORG 0
LJMP MAIN
ORG 23H
LJMP SERIAL ;jump to serial interrupt ISR
ORG 30H
MAIN : MOV P1,# 0FFH ;make p1 an input port
MOV TMOD, # 20H ; timer 1, mode 2 (auto- reload)
MOV TH1,# 0FDH ; 9600 baud rate
MOV SCON, #50H ; 8- bit, 1stop, REN enabled
MOV IE, #10010000B ; enable serial interrupt
SETB TR1 ; start timer 1
BACK: MOV A, P1 ; read data for port 1
MOV SBUF, A ; give a copy to SBUF
MOV P2, A ; send it to P2

Page 8 of 20
SJMP BACK ; stay in loop indefinitely
; serial port ISR
ORG 100H
SERIAL: JB TI, TRANS ; jump if TI is high
MOV A, SBUF ; otherwise due to receive
CLR RI ; clear RI since CPU does not
RETI ; return from ISR
CLR TI ; clear TI since CPU does not
RETI ; return from ISR
END

Ex: Write a program in which 10 bytes of data stored in RAM locations starting from 45H are
transferred serially. At the end of data transfer, the value of R0 (i.e., 0) is displayed on P1.
Solution:
ORG 000H
LJMP MAIN
ORG 0023H ; jump to ISR for serial transmission
LJMP SERIAL
ORG 0030H
MAIN: MOV TMOD, # 20H ; timer 1 in mode 2
MOV TH1, # -6 ; set baud rate
MOV SCON, #50H ; 8- bit, 1stop, EN enabled
MOV IE, #90H ; serial port enable interrupt
SETB TR1 ; start timer 1
MOV R0, #10 ; counter for number of bytes
MOV R1, #45H ; R1 is the pointer to RAM
BACK: MOV A, @R1 ; move data from RAM to A
MOV SBUF, A ; data to be transmitted is loaded into SBUF
DJNZ R0, BACK ; repeat till all data is sent
HERE: SJMP HERE
; serial port ISR
SERIAL: JNB TI, RECE ;If TI is not high, it implies reception
MOV A, R0 ; if TI is high, move value of R0 into A
MOV P1, A ; transfer it to P1
CLR TI ; clear TI for next transmission
RETI
RECE: MOV A, SBUF ; If reception, move received data to SBUF
CLR RI ; clear RI to enable next reception
RETI
END

Ex: This example is to show that many jobs can be attended to simultaneously using interrupts. Three
interrupts used here - the serial interrupt, timer 0 interrupt, and the external interrupt INT0.
Timer 1 is used to generate the baud rate for serial communications.
Page 9 of 20
Write a program to
(1) generate a square wave at P1.2 using timer 0 in mode I, interrupt mode
(2) take data from port P2 and send it serially and continuously .
(3) when INT0 is activated, port P0 is made 0 for a short time, t-o switch off the LEDs connected
to it. The LEDs will also remain off if the switch connected to INT0 pin (P3.2) is kept pressed.
Solution:
ORG 0000H
LJMP MAIN
; Timer 0 ISR
ORG 000BH ;ISR for Timer 0
CPL P1.2 ; toggle pin P1.2
MOV TH0, #00H ; Timer is in mode 1 so reload count values
MOV TL0, #0F0H ; reload count value
RETI
; INT 0 interrupt vector
ORG 0003H ; ISR for INT 0
SJMP LED
; serial port interrupt vector
ORG 0023H ; ISR for serial interrupt
LJMP SERIAL
; main program for initialization
ORG 0030H
MAIN: MOV P2, #0FFH ;make P2 an input port
MOV TMOD, #21H ; Timer 0 in mode1, Timer 1, in mode 2
MOV TH1, #-6 ; select baud rate
MOV TH0, #00H ; load count values for Timer 0
MOV TL0, #0F0H ; load count values for Timer 0
MOV SCON, #50H ;8 bit, 1 stop, REN enabled
MOV IE, #93H ; enable Timer 0, serial and EX0 interrupts
SETB TR1 ; start Timer 1
SETB TR0 ; start Timer 0
BACK: MOV A, P2 ; move data in P2 to A
MOV SBUF, A ; move A to SBUF for transmission
SJMP BACK ; continue
; serial port ISR
SERIAL: JNB TI, RECE ;if TI is not high, jump
CLR TI ; if TI = 1, implying transmission, clear TI
RETI
RECE: MOV A, SBUF ; since reception is seen, move received data to A
CLR RI ;clear RI
RETI
;ISR for INT0
LED: MOV P0, #00H ;move 0 to P0 to switch off LEDs
MOV R0, #0FFH

Page 10 of 20
HERE: DJNZ R0, HERE ; for delay
MOV P0, #0FFH ;light up LEDs again
RETI
END
Review questions:
1. True or false. There is a single interrupt in the interrupt vector table assigned to both the TI and RI
interrupts.
2. What address in the interrupt vector table is assigned to the serial interrupt?
3. Which bit of the IE register belongs to the serial interrupt? Show how it is enabled.
4. Assume that the IE bit for the serial interrupt is enabled. Explain how this interrupt gets activated and also
explain its actions upon activation.
5. True or false. Upon reset, the serial interrupt is active and ready to go.
6. True or false. The last two instructions of the ISR for the receive interrupt are:
CLR RI
RETI
7. How many serial interrupts has the 8051?
8. What address in interrupt vector table is assigned to serial interrupt? How many bytes are assigned to it?
9. Which bit of the IE register belongs to the serial interrupt? Show how it is enabled.
10. Assume that the IE bit for the serial interrupt is enabled. Explain how this interrupt gets activated and
also explain its working upon activation.
11. True or False? On making EA = 0 of the IE register, the serial interrupt is still enabled.
12. True or false. The last two instructions of the ISR for the receive interrupt are:
CLR TI
RETI
13. If RI is kept enabled, can data be received on RxD line?
14. Write a program using interrupts to get data serially and send it to P2 while at the same time Timer 0 is
generating a square wave of 5 kHz.
15. Write a program using interrupts to get data serially and send it to P2 while Timer 0 is turning the LED
connected to P1.6 on and off every second.

4.4 INTERRUPT PRIORITY IN THE 8051


What happens if two interrupts are activated at the same time? Which of these two interrupts is responded to
first?
Interrupt priority upon reset
When the 8051 is powered up, the priorities are assigned according to Table below.
Table: 8051 Interrupt Priority upon Reset
Highest to Lowest Priority
External Interrupt 0 (INT0)
Timer Interrupt 0 (TF0)
External Interrupt 1 (INT1)
Timer Interrupt 1 (TF1)
Serial communication (RI+TI)

Page 11 of 20
Ex: Discuss what happens if interrupts INT0, TF0, and INT1 are activated at same time. Assume
priority levels were set by power-up reset and that external hardware interrupts are edge-triggered.
Solution:
If these three interrupts are activated at the same time, they are latched and kept internally. Then the 8051
checks all five interrupts according to the default sequence listed. If any is activated, it services it in
sequence. Therefore, when the above three interrupts are activated, IE0 (external interrupt 0) is serviced first,
then Timer 0(TF0), and finally IE1 (external interrupt 1).
Setting interrupts priority with the IP register:
We can alter the sequence of above table by assigning a higher priority to anyone of the interrupts. This is
done by programming a register called IP (interrupt priority). Figure below shows the bits of the IP register.
Upon power-up reset, the IP register contains all 0s, making the priority sequence based on above table. To
give a higher priority to any of the interrupts, we make the corresponding bit in the IP register high.
D7 D0
-- -- PT2 PS PT1 PX1 PT0 PX0

Priority bit = 1 assigns high priority. Priority bit = 0 assigns low priority.
-- IP.7 Reserved
-- IP.6 Reserved
PT2 IP.5 Timer 2 interrupt priority bit (8052 only)
PS IP.4 Serial port interrupt priority bit
PT1 IP.3 Timer 1 interrupt priority bit
PX1 IP.2 External interrupt 1 priority bit
PT0 IP.1 Timer 0 interrupt priority bit
PX0 IP.0 External interrupt 0 priority bit
Ex: (a)Program the IP register to assign the highest priority to INT1 (external interrupt 1), then (b)
discuss what happens if INT0, INT1, and TF0 are activated at the same time. Assume that the
interrupts are both edge-triggered.
Solution:
(a) MOV IP, #00000100B; IP.2=1 to assign INT1 higher priority the instruction "SETB IP.2" also will
do the same thing as the above line since IP is bit addressable.
(b) The instruction in Step (a) assigned a higher priority to INTI than the others; therefore, when INT0,
INT1, and TF0 interrupts are activated at the same time, the 8051 services INT1 first, then it services
INT0, then TF0. This is due to the fact that INT1 has a higher priority than the other two because of the
instruction in Step (a). The instruction in Step (a) makes both the INT0 and TF0 bits in the IP register 0.
As a result, higher priority is to INT0 over TF0.
Ex: Assume that after reset, the interrupt priority is set by the instruction "MOV IP, #00001100B".
Discuss the sequence in which the interrupts are serviced.
Solution:
The instruction "MOV IP, #00001100B" (B is for binary) sets the external interrupt 1 (INT1) and Timer 1
(TF1) to a higher priority level compared with the rest of the interrupts. They will have the following
priority.

Page 12 of 20
Highest Priority External Interrupt 1 (INT1)
Timer Interrupt 1 (TF1)
External Interrupt 0 (INT0)
Timer Interrupt 0 (TF0)
Lowest Priority Serial communication (RI+TI)
Interrupt inside an interrupt
What happens if the 8051 is executing an ISR belonging to an interrupt and another interrupt is activated? In
such cases, a high-priority interrupt can interrupt a low-priority interrupt. This is an interrupt inside an
interrupt. In the 8051 a low-priority interrupt can be interrupted by a higher-priority interrupt, but not by
another low-priority interrupt. Although all the interrupts are latched and kept internally, no low-priority
interrupt can get the immediate attention of the CPU until the 8051 has finished servicing the high-priority
interrupts.
Triggering the interrupt by software
There are times when we need to test an ISR by way of simulation. This can be done with simple instructions
to set the interrupts high and thereby cause the 8051 to jump to the interrupt vector table. For example, if the
IE bit for Timer 1 is set, an instruction such as "SETB TF1" will interrupt the 8051 in whatever it is doing
and force it to jump to the interrupt vector table. In other words, we do not need to wait for Timer 1 to roll
over to have an interrupt. We can cause an interrupt with an instruction that raises the interrupt flag.
Review Questions
1. True or false. Upon reset, all interrupts have the same priority.
2. What register keeps track of interrupt priority in the 8051? Is it a bit-addressable register?
3. Which bit of IP belongs to the serial interrupt priority? Show how to assign it the highest priority.
4. Explain what happens if a higher-priority interrupt is activated while the 8051 is serving a lower-priority
interrupt (that is, executing a lower-priority ISR).
5. Which is the highest priority interrupt of 8051?
7. Which register caters to the function of changing interrupt priorities?
8. Which bit of IP belongs to the EX2 interrupt priority? Show how to assign it the highest priority.
9. Which bit of IP belongs to the Timer1 interrupt priority? Show how to assign it the highest priority.
10. True or False? Interrupts can be enabled by software.
11. Assume IP register has all 0s. Explain what happens if both INT0 and INT1 are activated at same time.
12. Assume that IP register has all 0s. Explain what happens if both TF0 and TF1 are activated at the same
13. If both TF0 and TF1 in the IP are set to high, what happens if both are activated at the same time?
14. If both INT0 and INT1 in the IP are set to high, what happens if both are activated at the same time?
15. Explain what happens if a low-priority interrupt is activated while the 8051 is serving a higher-priority
interrupt.

Page 13 of 20
Extra-1: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS {Beyond syllabus for extended
learning}

The 8051 has two external hardware interrupts. Pin 12 (P32) and pin 13 (P3.3) of the 8051, designated as
INT0 and INT1, are used as external hardware interrupts. Upon activation of these pins, the 8051 gets
interrupted in whatever it is doing and jumps to the vector table to perform the interrupt service routine.

External Interrupts INT0 and INT1


There are only two external hardware interrupts in the 8051: INT0 and INT1. They are located on pins P3.2
and P3.3 of port 3, respectively. The interrupt vector table locations 0003H and 0013H are set aside for INT0
and INT1, respectively. They are enabled and disabled using the IE register.
There are two types of activation for the external hardware interrupts: (1) level triggered, and (2) edge
triggered.

Level- triggered interrupt


In the level-triggered mode, INT0 and INT1 pins are normally high (just like all I/O port pins) and if a low-
level signal is applied to them, it triggers the interrupt. Then the microcontroller stops whatever it is doing
and jumps to the interrupt vector table to service that interrupt. This is called a level-triggered or level-
activated interrupt and is the default mode upon reset of the 8051. The low-level signal at the INT pin must
be removed before the execution of the last instruction of the interrupt service routine, RETI; otherwise,
another interrupt will be generated.

Ex-1: Two switches are connected to pins P3.2 and P 3.3. When a switch is pressed, the corresponding
line goes low. Write a program to:(a) light all LEDs connected to port 0, if the first switch is
pressed.(b) light all LEDs connected to port 2, if the second switch is pressed.
Solution:

Pin 3.2 is the pin for Interrupt 0, and pin 3.3 is the pin for Interrupt 1.

; upon wake up, go to main


ORG 000H ; bypass interrupt vector table
LJMP MAIN
; -----the ISR for INT0
ORG 0003H ; interrupt vector for Interrupt 0
MOV P0, # 0FFH ; turn on LEDs of port 0
MOV R0, #255
LED1: DJNZ R0, LED1 ; keep the LEDs ON for a short time
RETI
; ------the ISR for INT 1
ORG 0013H ; Interrupt vector for Interrupt 1
MOV P2, # 0FFH ; turn on LEDs of port 2
MOV R0, #255
LED2: DJNZ R0, LED2 ; keep the LEDs ON for a short time
RETI
; ---------------main program for initialization

Page 14 of 20
ORG 0030H
MAIN: MOV IE, #85H ; enable INT0 and INT1
HERE: SJMP HERE
END

Edge-triggered interrupts
Upon reset the 8051 makes INT0 and INT1 low-level triggered interrupts. To make them edge-triggered
interrupts, we must set IT0 and IT1 bits (DO & D2) of the TCON register, respectively by using instructions
such as “SETB TCON.0”&“SETB TCON.2”. Now, when a high-to-low signal is applied to pin P3.3, the
controller will be interrupted and forced to jump to location 0013H in the vector table to service the ISR
(assuming that the interrupt bit is enabled in the IE register).

Ex-2: Generate a square wave on all pins of P0 which is half the frequency of signal applied at INT0
pin (P3.2).
Solution:

Every negative edge at Pin 3.2 will cause the INTO (vectored to location 0003) interrupt to be activated.
ORG 000H
LJMP MAIN
; ---ISR for hardware interrupt INT0
ORG 0003H
CPL P0
RETI
ORG 0030H
;make INT0 an edge-triggered
MAIN: SETB TCON.0
interrupt
MOV IE, #81H ;enable hardware interrupt INT0
HERE: SJMP HERE
END

Ex-3: What is the difference between the RET and RETI instructions? Explain why we cannot use
RET instead of RETI as the last instruction of an ISR.
Solution:

1. Both perform the same actions of popping off the top two bytes of the stack into the program counter,
and making the 8051 return to where it left off. However, RETI also performs an additional task of
clearing the interrupt-in-service flag, indicating that the servicing of the interrupt is over and the 8051
now can accept a new interrupt on that pin. If you use RET instead of RETI as the last instruction of the
interrupt service routine, you simply block any new interrupt on that pin after the first interrupt, since
the pin status would indicate that the interrupt is still being serviced. In the cases of TF0, TF1,
TCON.1, and TCON.3, they are cleared by the execution of RETI.
2. The second point is that while the interrupt service routine is being executed, the INTn pin is ignored,
no matter how many times it makes a high-to-low transition. In reality one of the functions of the RETI
instruction is to clear the corresponding bit in the TCON register (TCON.1 or TCON.3). This informs

Page 15 of 20
us that the service routine is no longer in progress and has finished being serviced. For this reason,
TCON.1 and TCON.3 in the TCON register are called interrupt-in-service flags.

Review Questions
1. True or false. There is a single interrupt in the interrupt vector table assigned to both external hardware
interrupts IT0 and IT1
2. What address in the interrupt vector table is assigned to INT0 and INT1? How about the pin numbers on
post 3?
3. Which bit of IE belongs to the external hardware interrupts? Show how both are enabled.
4. Assume that the IE bit for the external hardware interrupt EX1 is enabled and is active low. Explain how
this interrupt works when it is 'activated.
5. True or false. Upon reset, the external hardware interrupt is low-level triggered.
6. In Question 5, how do we make sure that a single interrupt is not recognized as multiple interrupts?
7. True or false. The last two instructions of the ISR for INT0 are:
CLR TCON.1
RETI
8. Explain the role that each of the two bits TCON.0 and TCON.2 play in execution of external interrupt 0.

PROGRAMMING EXTERNAL HARDWARE INTERRUPTS- more questions


1. How many hardware interrupts has the 8051? How are they activated?
2. What address in the interrupt vector table is assigned to INT0 and INT1? How about the pin numbers
on port 3?
3. Which bits of the IE register are used to set/reset the external hardware interrupts?
4. Write a program to transfer a data FFH through port 1 when EX0 is enabled and to transfer 00H if EX1
is enabled?
5. Assume that the IE bit for external hardware interrupt EX0 is enabled and is low-level triggered.
Explain how this interrupt works when it is activated, How can we make sure that a single interrupt is
not interpreted as multiple interrupts? .
6. True or false. Upon reset, the external hardware interrupt is edge-triggered. .
7. Which bits of TCON belong to EX0 & EX1?
8. What should be the minimum time period of the high-to-low pulse used for an edge-triggered
interrupt?
9. Explain the role of TCON.0 and TCON.2 in the execution of external interrupt 0.
10. Assume that the IE bit for external hardware interrupt EX1 is enabled and is edge-triggered. Explain
how this interrupt works when it is activated. How can we make sure that a single interrupt is not
interpreted as multiple interrupts? .
11. Write a program using interrupts to get data from P1 and send it to P2 while Timer 0 is generating a
square wave of 3 kHz. .
12. Write a program using interrupts-to get data from P1 and send it to P2 while Timer 1 is turning on and
off the LED connected to P0.4 every second.
13. Write a program to generate a rising edge once, when a high-to-low transition is received on INT0.
14. What is the method to disable all interrupts?
15. Which interrupts are latched, low-level or edge-triggered?
16. Which register keeps the latched interrupt for INT0 and INT1?

Page 16 of 20
Extra-2: INTERRUPT PROGRAMMING IN C {Beyond syllabus for extended learning}
8051 C interrupts numbers:
The 8051 C compilers have extensive support for the 8051 interrupts with two major features as follows:
1. They assign a unique number to each of the 8051 interrupts, as shown in below table.
2. It can also assign a register bank to an ISR. This avoids code overhead due to the pushes and pops of the
R0-R7 registers.
Table: 8051 Interrupt Numbers in C
Interrupt Name Numbers used by 8051 C
External Interrupt 0 (INT0) 0
Timer Interrupt 0 (TF0) 1
External Interrupt 1 (INT1) 2
Timer Interrupt 1 (TF1) 3
Serial communication (RI+TI) 4
Ex: Write a C program that continuously gets a single bit of data from P1.7 and sends it to P1.0, while
simultaneously creating a square wave of 200 µs period on pin P2.5. Use timer 0 to create the
square wave. Assume that XT AL= 11.0592MHz.
Solution:
We will use timer 0 in mode 2 (auto-reload). One half of the period is 100 µs,
100/1.085µs = 92, and TH0 = 256 - 92 = 164 or A4H
#include <reg51.h>
sbit SW = P1^7;
sbit IND = P1^0;
sbit WAVE = P2^5;
void timer0(void) interrupt 1
{
WAVE = ~WAVE; //toggle pin
}
void main ( )
{
SW = 1; // make switch input
TMOD = 0x02;
TH0 = 0xA4; //TH0 = -92
IE = 0x82; //enables interrupts for timer 0
while (1)
{
IND = SW; //send switch to LED
}
}
Ex: Write a C program that continuously gets a single bit of data from P1.7 and sends it to P1.0 in the
main, while simultaneously (a) creating a square wave of 200 µs period on pin P2.5, and (b)
sending letter' A' to the serial port. Use Timer 0 to create the square wave. Assume that XTAL =
11.0592 MHz. Use the 9600 baud rate.

Page 17 of 20
Solution:
We will use Timer 0 in mode 2 (auto-reload). TH0 = 100/1.085µs = -92, which is A4H
#include <reg51.h>
sbit SW = P1^7;
sbit IND = P1^0;
sbit WAVE = P2^5;
void timer0(void) interrupt 1
{
WAVE = ~WAVE; //toggle pin
}
void serial0( ) interrupt 4
{
If (TI = = 1)
{
SBUF = ‘A’; //send A to serial port
TI = 0; //clear interrupt
}
else
{
RI =0; //clear interrupt
}
}
void main ( )
{
SW = 1; // make switch input
TH1 = -3; //9600 baud
TMOD = 0x22; //mode 2 for both timers
TH0 = 0xA4; //-92 = A4Hfor timer 0
SCON = 0x50;
TR0 = 1;
TR1=1; //start timer
IE = 0x92; //enables interrupts for T0
while(1) //stay here
{
IND = SW; //send switch to LED
}
}
Ex: Write a C program using interrupts to do the following. Assume that XTAL = 11.0592 MHz. Set
the baud rate at 4800.
(a) Receive data serially and send it to P0,
(b) Read port P1, transmit data serially, and give a copy to P2,
(c) Make timer 0 generate a square wave of 5 KHz frequency on P0.1.
Solution:

Page 18 of 20
#include <reg51.h>
sbit WAVE = P0^1;
void timer0( ) interrupt 1
{
WAVE = ~WAVE; //toggle pin
}
void serial0 ( ) interrupt 4
{
If (TI = = 1)
{
TI = 0; //clear interrupt
}
else
{
P0 = SBUF; //put value on pins
RI = 0; //clear interrupt
}
}
void main ( )
{
unsigned char x;
P1 = 0xFF; // make P1 an input
TMOD = 0x22;
TH1 = 0xF6; //4800 baud rate
SCON = 0x50;
TH0 = 0xA4; //5 kHz has T = 200 µs
IE = 0x92; //enables interrupts
TR1 = 1; //start timer 1
TR0 = 1; // start timer 0
while (1)
{
x = P1; //read value from pins
SBUF = x; //put value in buffer
P2 = x; //write value to pins
}
}
Ex: Write a C program using interrupts to do the following:
(a) Generate a 10000Hz frequency on P2.1 using T0 8-bit auto-reload,
(b) Use timer 1 as an event counter to count up a 1-Hz pulse and display it on P0. The pulse is
connected to EX1.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.
Solution:
#include <reg51.h>

Page 19 of 20
sbit WAVE = P2^1;
unsigned char cnt;
void timer0( ) interrupt 1
{
WAVE = ~WAVE; //toggle pin
}
void timer1 ( ) interrupt 3
{
cnt++ ; //increment counter
P0 = cnt; //display value on pins
}
void main ( )
{
Cnt = 0; //set counter to zero
TMOD = 0x42;
TH0 = 0x-46; //10000Hz
IE = 0x86; //enables interrupts
TR0 = 1; //start timer 1
TR1 = 1; // start timer 1
while (1); //wait until interrupts
}
1 / 10000Hz = 100µs
100µs / 2=50µs
50µs/1.085µs = 46

Page 20 of 20

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy