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    Cia - Ii - QP - 22MT4201 - PC - Set-A

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    R.MADHU SUDHANAN HICET STAFF EIE
    Processor & Controller Question paper

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    Cia - Ii - QP - 22MT4201 - PC - Set-A

    Uploaded by

    R.MADHU SUDHANAN HICET STAFF EIE
    12 views2 pages
    Processor & Controller Question paper

    Original Title

    CIA -II_QP_22MT4201_PC_SET-A (1)

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    Processor & Controller Question paper

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    12 views2 pages

    Cia - Ii - QP - 22MT4201 - PC - Set-A

    Uploaded by

    R.MADHU SUDHANAN HICET STAFF EIE
    Processor & Controller Question paper

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    AUTONOMOUS UG - DEGREE EXAMINATIONS

    CONTINUOUS INTERNAL ASSESSMENT - II


    PROGRAMME & BRANCH: B.E., Mechatronics Engineering SEMESTER: IV
    COURSE CODE & NAME: 22MT4201 – Processor and Controller ACADEMIC YEAR: 2023-2024
    DURATION: 01 HR 30 MINS MAXIMUM MARK: 50 MARKS
    DATE AND SESSION: QP SET: A

    S.NO PART-A (ANSWER ALL QUESTIONS) (6 X 2 = 12) BTL COS MARKS

    1. List the features of an 8051 microcontroller. R CO4 2

    2. What is PSW in an 8051? How is stack implemented in 8051? R CO4 2

    3. What are the addressing modes available in an 8051 controller? R CO4 2


    What is a synchronous data transfer scheme? What is an asynchronous data
    4. transfer scheme? R CO5 2

    5. What is a subroutine? What are the advantages of subroutine? R CO5 2

    6. What is data transfer scheme and what are its types? R CO5 2
    PART-B (ANSWER ALL QUESTIONS) ( 2 X 14 = 28)
    7. Illustrate the types of 8051 addressing modes each with an example. U CO4 14
    OR
    Explain the following type of 8051 instruction each with few examples
    8. i. Logic Instructions. U CO4 14
    ii. Program Branching Instructions.

    Explain the pin description of USART-8251A with neat sketch also elaborate
    9. it with a functional block diagram. U CO5 14

    OR
    i. Explain the pin description of INTEL-8255 Programmable Peripheral
    Interface with neat sketch also elaborate it with internal block
    10. diagram. U CO5 14
    ii. Draw and explain the schematic diagram of interfacing 8255 with
    8085 Processor. Tabulate IO addresses of 8255A

    PART – C (1 X 10 = 10)
    Show and tell about the Little-endian memory organization & Big-endian memory
    11.A. Ap CO3 2
    organization
    i. Explain the 3-stage pipeline ARM organization with neat sketch.
    ii. Enumerate ARM single-cycle instruction 3-stage pipeline operation
    11.B. with neat figure Ap CO3 8
    iii. Enumerate ARM multi-cycle instruction 3-stage pipeline operation
    with neat figure
    OR
    12.A. Tell about the stages of 3-stage & 5-stage pipeline in ARM organization. Ap CO3 2
    Explain the following with reference to ARM instruction set
    i. Software Interrupts
    12.B. Ap CO3 8
    ii. Data processing instructions
    iii. Multiply instructions

    COURSE COORDINATOR HOD

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