R23 - MTech - VLSI&ES - CourseStructure - Syllabus FANAL

NARASARAOPETA ENGINEERING COLLEGE, NARASARAOPET
(AUTONOMOUS)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M.TECH COURSE STRUCTURE

VLSI & Embedded Systems (VLSI&ES)
I M.TECH-I SEMESTER
Internal External Total
Name of Subject L T P Credits
Marks Marks Marks
1 RTL Simulation and Synthesis 4 - - 40 60 100 3
with PLDs
Microcontrollers and
2 Programmable Digital Signal 4 - - 40 60 100 3
Processors
3 VLSI signal processing 4 - - 40 60 100 3
CAD of Digital System
4 4 - - 40 60 100 3
Elective I
i. Digital Signal and Image
Processing
5 ii. Parallel Processing
iii. IOT and Its Applications 4 - - 40 60 100 3
Elective II
i. Programming Languages for

Embedded Systems
6 ii. System Design with Embedded 4 - - 40 60 100 3
Linux
iii. Hardware Software co-design
Laboratory
7 RTL Simulation and - - 3 40 60 100 1.5
Synthesis with PLDs
Lab
8 Laboratory
Microcontrollers and - - 3 40 60 100 1.5
Programmable Digital Signal
Processors Lab
TOTAL 24 - 6 320 480 800 21
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NARASARAOPETA ENGINEERING COLLEGE

(AUTONOMOUS)
I M.TECH-II SEMESTER
Internal External Total
S.No. Name of Subject L T P Credits
Marks Marks Marks
1 Analog and Digital CMOS VLSI 4 - - 40 60 100 3
Design
2 Real Time Operating Systems 4 - - 40 60 100 3
3 SoC Design 4 - - 40 60 100 3
Network Security and
4 4 - - 40 60 100 3
Cryptography
Elective III
i. Memory Architectures
ii. Low power VLSI Design
iii. Artificial Intelligence
5 4 - - 40 60 100 3
Elective IV
i. Algorithms for VLSI
design automation
6 ii. Communication Buses and
Interfaces
iii. Physical design automation 4 - - 40 60 100 3
Laboratory
7 Analog and Digital CMOS VLSI - - 3 40 60 100 1.5
Design Lab
8 Laboratory
Real Time Operating Systems Lab - - 3 40 60 100 1.5
TOTAL 24 - 6 320 480 800 21
II M.TECH-III & IV SEMESTERS

S.No. Name of Subject Total Marks Credits
1 Seminar 100 1
2 Comprehensive Viva-Voce 100 2
3 Project - 35
TOTAL 200 38
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INTERNAL EXTERNAL TOTAL
L T P CREDITS
I M.TECH-I SEMESTER MARKS MARKS MARKS
4 - - 40 60 100 3
RTL SIMULATION AND SYNTHESIS WITH PLDs
Course Objectives:
 To introduce Verilog HDL for the design and functionality verification of a digital circuit.
 To understand the design of data path and control circuits for sequential machines
 To introduce the concept of realizing a digital circuit using PLDs
Course Outcomes:
Upon completion of this course, the student will be able to
 Develop the Verilog HDL to design a digital circuit.
 Appreciate the analysis of finite state machine of a controlling circuit
 Understand the Static Timing Analysis and clock issues in digital circuits
 Verify the functionality of the digital designs using PLDs.
UNIT-I:
Verilog HDL: Importance of HDLs, Lexical Conventions of Verilog HDL Gate level
modelling: Built in primitive gates, switches, gate delays Data flow modeling: Continuous
and implicit continuous assignment, delays Behavioural modeling: Procedural constructs,
Control and repetition Statements,delays, function and tasks.
UNIT-II:
Digital Design: Design of BCD Adder, State graphs for control circuits, shift and add multiplier,
Binary divider.FSM and SM Charts: Finite state diagram, Implementation of sequence detector
using FSM, State machine charts, Derivation of SM Charts, Realization of SM Chart,
Implementation of Binary Multiplier.
UNIT-III:
ASIC Design Flow: Simulation, simulation types, Synthesis, synthesis methodologies,
translation, mapping, optimization, Floor planning, Placement, routing, Clock tree
synthesis, Physical verification.
UNIT-IV:
Static Timing Analysis: Timing paths, Meta-stability, Clock issues, Need and design
strategies for multi- clock domain designs, setup and hold time Violations, steps to remove
Setup and hold time violations.
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UNIT-V:
Digital Design using PLDs: ROM, PLA, PAL- Registered PALs, Configurable PALs,
GAL.CPLDs: Features, programming and applications using complex programmable logic
devices. FPGAs: Field Programmable gate arrays Logic blocks, routing architecture, design
flow.
TEXT BOOKS:
1. Verilog HDL,A Guide to Digital Design and Synthesis Samir Palnitkar, 2nd Edition, 2003
2. Fundamentals of Logic Design, Charles H. Roth, 5th Edition. Cengage Learning, 2010.
3. Verilog HDL Synthesis A Practical Primer by Bhasker J, 1st edition, 1998
4. Modern Digital Electronics P Jain, 3rd Edition, TMH, 2003.
5. Data Sheets for CPLD & FPGA architectures, 1996.
REFERENCES:
2. Donald D Givone, “Digital principles and Design”, TMH, 2016
3. Bob Zeidman, “Designing with FPGAs & CPLDs”, CMP Books, 2002.
4. Richard S. Sandige, “Modern Digital Design”, MGH, International Editions, 1990
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L T P CREDITS
4 - - 40 60 100 3
MICROCONTROLLERS AND PROGRAMMABLE DIGITAL SIGNAL PROCESSORS
Course Objectives:
 To understand, compare and select ARM processor core based
SoC with severalfeatures/peripherals based on requirements of
embedded applications.
 To be able to identify and characterize architecture of Programmable DSP Processors
 To develop small applications by utilizing the ARM processor core and DSP
processor basedplatform.
Course Outcomes:
 Compare and select ARM processor core based SoC with several
features/peripheralsbased on requirements of embedded applications.
 Identify and characterize architecture of Programmable DSP Processors
 Develop small applications by utilizing the ARM processor core and DSP
UNIT-I:
ARM Cortex-M3 processor: Applications, Programming model – Registers,
Operation modes, Exceptions and Interrupts, Reset Sequence Instruction Set,
Unified Assembler Language,Memory Maps, Memory Access Attributes,
Permissions, Bit-Band Operations, Unaligned and Exclusive Transfers. Pipeline,
Bus Interfaces
UNIT-II:
Exceptions, Types, Priority, Vector Tables, Interrupt Inputs and Pending
behavior, Fault Exceptions, Supervisor and Pendable Service Call, Nested
Vectored Interrupt Controller, Basic Configuration.
UNIT-III:
LPC 17xx microcontroller- Internal memory, GPIOs, Timers, ADC, UART and
other serialinterfaces, PWM, RTC, WDT
UNIT-IV:
Programmable DSP (P-DSP) Processors: Harvard architecture, Multi port memory,
architecturalstructure of P-DSP- MAC unit, Barrel shifters, Introduction to TI DSP
processor family
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UNIT-V:
VLIW architecture and TMS320C6000 series, architecture study, data paths, cross
paths, Introduction to Instruction level architecture of C6000 family, Assembly
Instructions memory addressing, for arithmetic, logical operations. Code Composer
Studio for application development fordigital signal processing
TEXT BOOKS:
1. Dr. K.V.K.K. Prasad, “Embedded/Real-Time Systems”, Dream Tech Publications.
2. Rajkamal, “Embedded Systems-Architecture, Programming and Design”, Second Edition,
Tata McGraw Hill Publications, 2008.
REFERENCES:
1. Labrosse, “Embedding system building blocks “, CMP publishers.
2. Rob Williams,” Real time Systems Development”, Butterworth Heinemann Publications.
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(AUTONOMOUS)
I M.TECH-I SEMESTER L T P CREDITS
MARKS MARKS MARKS
4 - - 40 60 100 3
VLSI SIGNAL PROCESSING
Course Objectives:
 Introduce students to the fundamentals of VLSI signal processing and expose them
to examples of applications.
 Design and optimize VLSI architectures for basic DSP algorithms.
 .Design VLSI architectures for DSP algorithms.
Course Outcomes:
 Ability to modify the existing or new DSP architectures suitable for VLSI.
 Understand the concepts of folding and unfolding algorithms and applications.
 Ability to implement fast convolution algorithms.
 Low power design aspects of processors for signal processing and wireless applications.
UNIT- 1
Introduction to DSP: Typical DSP algorithms, DSP algorithms benefits, Representation of DSP
algorithms Pipelining and Parallel Processing
Introduction, Pipelining of FIR Digital filters, Parallel Processing, Pipelining and Parallel Processing for
Low Power Retiming Introduction, Definitions and Properties, Solving System of Inequalities, Retiming
Techniques
UNIT –II
Folding and Unfolding: Folding- Introduction, Folding Transform, Register minimization Techniques,
Register minimization in folded architectures, folding of Multirate systems
Unfolding- Introduction, An Algorithm for Unfolding, Properties of Unfolding, critical Path, Unfolding
and Retiming, Applications of Unfolding
UNIT -III
Systolic Architecture Design: Introduction, Systolic Array Design Methodology, FIR Systolic Arrays,
Selection of Scheduling Vector, Matrix Multiplication and 2D Systolic Array Design, Systolic Design for
Space Representations contain Delays.
UNIT -IV
Fast Convolution: Introduction – Cook-Toom Algorithm – Winogard algorithm – Iterated Convolution –
Cyclic Convolution – Design of Fast Convolution algorithm by Inspection
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UNIT V:
Digital lattice filter structures, bit level arithmetic, architecture, redundant arithmetic.
Numerical strength reduction, synchronous, wave and asynchronous pipe lines, low
power design.
Low Power Design: Scaling Vs Power Consumption, Power Analysis, Power Reduction techniques,
Power Estimation Approaches
Text Books:
1. Keshab K. Parthi[A1] , VLSI Digital signal processing systems, design and implementation[A2] ,
Wiley, Inter Science, 1999.
2. Mohammad Isamail and Terri Fiez, Analog VLSI signal and information processing, McGraw
Hill, 1994
3. S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal Processing, Prentice Hall,
1985.
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(AUTONOMOUS)
I M.TECH-I SEMESTER INTERNAL EXTERNAL TOTAL
L T P CREDITS
MARKS MARKS MARKS
4 - - 40 60 100 3
CAD OF DIGITAL SYSTEM
Course Objectives:
 To understand the fundamentals of CAD tools for modeling, design, test and verification of VLSI
systems.
 To study various phases of CAD, including simulation, physical design, test and
Verification.
 To be able to demonstrate the knowledge of computational algorithms and tools for CAD.
Course Outcomes:
 Fundamentals of CAD tools for modelling, design, test and verification of VLSI systems.
 Understand various phases of CAD, including simulation, physical design, test and
verification.
 Demonstrate knowledge of computational algorithms and tools for CAD.
UNIT- 1:
Introduction to VLSI Methodologies – Design and Fabrication of VLSI Devices, Fabrication Materials,
Transistor Fundamentals, Fabrication of VLSI Circuits, Design Rules Layout of Basic Devices,
Fabrication Process and its Impact on Physical Design, Scaling Methods , Status of Fabrication Process,
Issues related to the Fabrication Process, Future of Fabrication Process , Solutions for Interconnect
Issues, Tools for Process Development
UNIT- II
VLSI design automation tools – Data Structures and Basic Algorithms , Basic Terminology , Complexity
Issues and NP-hardness , Basic Algorithms ,Basic Data Structures, graph theory and Computational
complexity, tractable and intractable problems.
UNIT- III
General purpose methods for combinational optimization – Partitioning- Problem Formulation,
Classification of Partitioning Algorithms, Group Migration Algorithms , Simulated Annealing Simulated
Evolution, Other Partitioning Algorithms Performance Driven Partitioning Floor planning- Chip
planning , Pin Assignment , Integrated Approach, Placement- Problem Formulation , Classification of
Placement Algorithms, Simulation Based Placement Algorithms , Partitioning Based Placement
Algorithms , Performance Driven Placement, Routing -Global Routing, , Problem Formulation ,
Classification of Global Routing Algorithms, Maze Routing Algorithms , Line-Probe Algorithms,
Shortest Path Based Algorithms. Steiner Tree based Algorithms Integer Programming Based Approach ,
Performance Driven Routing
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UNIT- IV
Simulation- Gate-level Modeling and Simulation , Switch-level Modeling and Simulation, LogicSynthesis
and Verification - Introduction to Combinational Logic Synthesis , Binary-decision Diagrams, Two-level
Logic Synthesis, High-level Synthesis- Hardware Models for High level Synthesis , InternalRepresentation of the
Input Algorithm , Allocation, Assignment and Scheduling
UNIT- V
MCMs-VHDL-Verilog-implementation of simple circuits using VHDL
Text Books:
1. N.A. Sherwani, “Algorithms for VLSI Physical Design Automation”.

2. S.H. Gerez, “Algorithms for VLSI Design Automation.
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(AUTONOMOUS)
L T P CREDITS
(ELECTIVE-I) 4 - - 40 60 100 3
DIGITAL SIGNAL AND IMAGE PROCESSING
Course Objectives:
 Students will gain knowledge on fundamental concepts of a digital signal and image processing System.
 Students will develop skill of developing new algorithms in signal and image processing Applications.
 Student will develop skill on MATLAB implementation of different signal and image processing techniques.
Course Outcomes:
 Analyze discrete-time signals and systems in various domains ( i.e Time, Z and Fourier)
 Design the digital filters (both IIR and FIR) from the given specifications
 Analyze the quantization effects in digital filters and understand the basics of image sampling,
quantization and image transforms.
 Understand the concepts of image enhancement, image restoration and image segmentation.
 Know the various methods involved in image compression and fundamentals in color image
processing.
UNIT I
Review of Discrete Time signals and systems, Characterization in time, Z and Fourier domain, Fast
Fourier Transform using Decimation In Time (DIT) and Decimation In Frequency (DIF) Algorithms.
UNIT II
IIR Digital Filters: Introduction, Analog filter approximations – Butter worth and Chebyshev, Design of
IIR Digital filters from analog filters using Impulse Invariance, Bilinear Transformation methods.
FIR Digital Filters: Introduction, Design of FIR Digital Filters using Window Techniques, Frequency
Sampling technique, Comparison of IIR & FIR filters.
UNIT III
Analysis Of Finite Word length Effects: The Quantization Process and Errors, Quantization of Fixed-
Point Numbers, Quantization of Floating-Point Numbers, Analysis of Coefficient Quantization effects.
Introduction To Digital Image Processing: Introduction, components in image processing system,
Applications of Digital image processing, Image sensing and acquisition, Image sampling, Quantization,
Basic Relationships between pixels, Image Transforms: 2D-DFT, DCT, Haar Transform.
UNIT IV
Image Enhancement: Intensity transformation functions, histogram processing, fundamentals of spatial
filtering, smoothing spatial filters, sharpening spatial filters, the basics of filtering in the frequency
domain, image smoothing using frequency domain filters, Image Sharpening using frequency domain
filters, Selective filtering.
Image Restoration: Introduction, restoration in the presence of noise only-Spatial Filtering, Periodic
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Noise Reduction by frequency domain filtering, Linear, Position –Invariant Degradations, Estimating the
degradation function, Inverse filtering, Minimum mean square error (Wiener) filtering.

(AUTONOMOUS)
Image Segmentation: Fundamentals, point, line, edge detection, thresholding, region based
segmentation.
UNIT V
Image Compression: Fundamentals, Basic compression methods: Huffman coding, Arithmetic coding,
Run-Length coding, Block Transform coding, Predictive coding, Wavelet coding.
Color Image Processing: color fundamentals, color models, pseudo color image processing, basics of
full color image processing, color transformations, smoothing and sharpening. Image segmentation based
on color, noise in color images, color image compression.
Text Books:
1. Digital Signal Processing, Principles, Algorithms, and Applications: John G. Proakis, Dimitris
G.Manolakis,PearsonEducation/PHI,2007.
2. S. K. Mitra. “Digital Signal Processing – A Computer based Approach”, TMH, 3rd Edition,2006
3. Rafael C.Gonzalez and Richard E. Woods, “Digital Image Processing”, Pearson Education, 2011.
4. S.Jayaraman, S.Esakkirajan, T.Veerakumar, “Digital Image Processing”, Mc Graw Hill Publishers,
2009
Reference Books:
2. Digital Signal Processing: Andreas Antoniou, TATA McGraw Hill , 2006

3. Digital Signal Processing: MH Hayes, Schaum‟s Outlines, TATA Mc-Graw Hill, 2007.
4. Anil K. Jain, “Fundamentals of Digital Image Processing,” Prentice Hall of India, 2012
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L T P CREDITS
(ELECTIVE-I) MARKS MARKS MARKS
4 - - 40 60 100 3
PARALLEL PROCESSING
Course Objectives:
 To familiarize students with the fundamental concepts, techniques and tools of parallel
computing.
 To better use parallel computing in your application area, and
 To take advanced courses in more specific areas of parallel computing.
Course Outcomes:
At the end of this course, students will be able to
 Identify limitations of different architectures of computer
 Analysis quantitatively the performance parameters for different architectures
 Investigate issues related to compilers and instruction set based on type of architectures.
UNIT I:Overview of Parallel Processing and Pipelining, Performance analysis, Scalability
UNITII:Principles and implementation of Pipelining, Classification of

pipelining processors,Advanced pipelining techniques, Software pipelining
UNITIII:VLIW processors Case study: Superscalar Architecture- Pentium, Intel Itanium

Processor, UltraSPARC,MIPS on FPGA, Vector and Array Processor, FFT Multiprocessor
Architecture
UNIT IV: Multithreaded Architecture, Multithreaded processors, Latency

hiding techniques,Principles of multithreading, Issues and solutions
UNITV:Parallel Programming Techniques: Message passing program development,

Synchronous and asynchronous message passing, Shared Memory Programming, Data
Parallel Programming, Parallel Software Issues. Operating systems for multiprocessors
systems Customizing applications on parallelprocessing platforms
Text Books:
1. Kai Hwang, Faye A. Briggs, “Computer Architecture and Parallel

Processing”, MGH International Edition
2. Kai Hwang, “Advanced Computer Architecture”, TMH
3. V. Rajaraman, L. Sivaram Murthy, “Parallel Computers”, PHI.
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Reference Books:
1. William Stallings, “Computer Organization and Architecture, Designing

for performance“Prentice Hall, Sixth edition
2. Kai Hwang, ZhiweiXu, “Scalable Parallel Computing”, MGH
3. David Harris and Sarah Harris, “Digital Design and Computer Architecture”, Morgan
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L T P CREDITS
(ELECTIVE-I) MARKS MARKS MARKS
4 - - 40 60 100 3
IOT AND ITS APPLICATIONS
Course Objectives
 Understand the definition and significance of the Internet of Things.
 Discuss the architecture, operation, and business benefits of an IoT solution.
 Examine the potential business opportunities that IoT can uncover.
 Explore the relationship between IoT, cloud computing, and big data.
Course Outcomes:
 Apply the Knowledge in IOT Technologies and Data management.
 Determine the values chains Perspective of M2M to IOT.
 Implement the state of the Architecture of an IOT.
 Compare IOT Applications in Industrial & real world.
 Demonstrate knowledge and understanding the security and ethical issues of an IOT.
UNIT I:FUNDAMENTALS OF IoT- Evolution of Internet of Things, Enabling Technologies, IoT

Architectures,oneM2M, IoT World Forum (IoTWF) and Alternative IoT models, Simplified IoT
Architecture and Core IoT Functional Stack, Fog, Edge and Cloud in IoT, Functional blocks of an IoT
ecosystem, Sensors, Actuators, Smart Objects and Connecting Smart Objects.
IoT Platform overview: Overview of IoT supported Hardware platforms such as: Raspberry pi, ARM
Cortex Processors, Arduino and Intel Galileo boards.
UNIT II:IoT PROTOCOLS- IT Access Technologies: Physical and MAC layers, topology and Security
of IEEE 802.15.4, 802.15.4g, 802.15.4e, 1901.2a, 802.11ah and Lora WAN, Network Layer: IP versions,
Constrained Nodes and Constrained Networks, Optimizing IP for IoT: From 6LoWPAN to 6Lo, Routing
over Low Power and Lossy Networks, Application Transport Methods: Supervisory Control and Data
Acquisition, Application Layer Protocols: CoAP and MQTT.
UNIT III: DESIGN AND DEVELOPMENT- Design Methodology, Embedded computing logic,
Microcontroller, System on Chips, IoT system building blocks, Arduino, Board details, IDE
programming, Raspberry Pi, Interfaces and Raspberry Pi with Python Programming.
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UNIT IV: DATA ANALYTICS AND SUPPORTING SERVICES- Structured Vs Unstructured Data
and Data in Motion Vs Data in Rest, Role of Machine Learning – No SQL Databases, Hadoop
Ecosystem, Apache Kafka, Apache Spark, Edge Streaming Analytics and Network Analytics, Xively
Cloud for IoT, Python Web Application Framework, Django, AWS for IoT, System Management with
NETCONF-YANG
UNIT V: CASE STUDIES/INDUSTRIAL APPLICATIONS: IoT applications in home,

infrastructures, buildings, security, Industries, Home appliances, other IoT electronic equipments. Use of
Big Data and Visualization in IoT, Industry 4.0 concepts.
Sensors and sensor Node and interfacing using any Embedded target boards (Raspberry Pi / Intel
Galileo/ARM Cortex/ Arduino)
Text Books:
1.IoT Fundamentals: Networking Technologies, Protocols and Use Cases for Internet of Things, David
Hanes, Gonzalo Salgueiro, Patrick Grossetete, Rob Barton and Jerome Henry, Cisco Press, 2017
Reference Books:
1. Internet of Things – A hands-on approach, ArshdeepBahga, Vijay Madisetti, Universities Press, 2015
2. The Internet of Things – Key applications and Protocols, Olivier Hersent, David Boswarthick, Omar
Elloumi and Wiley, 2012 (for Unit 2).
3. “From Machine-to-Machine to the Internet of Things – Introduction to a New Age of
Intelligence”,Jan Ho¨ ller, VlasiosTsiatsis, Catherine Mulligan, Stamatis, Karnouskos, Stefan
Avesand. David Boyle and Elsevier, 2014.
4. Architecting the Internet of Things,Dieter Uckelmann, Mark Harrison, Michahelles and Florian (Eds),
Springer, 2011.
5. Recipes to Begin, Expand, and Enhance Your Projects, 2nd Edition,Michael Margolis, Arduino
Cookbook and O‟Reilly Media, 2011.
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L T P CREDITS
(ELECTIVE-II) 4 - - 40 60 100 3
PROGRAMMING LANGUAGES FOR EMBEDDED SYSTEMS
Course Objectives:
To introduce the Building Blocks of Embedded System

 To Educate in Various Embedded Development Strategies
 To Introduce Bus Communication in processors, Input/output interfacing.
 To impart knowledge in various processor scheduling algorithms.
 To introduce Basics of Real time operating system and example tutorials to discuss on one real time
operating system tool
Course Outcomes: Upon completion of this course, the student will be able to
 Write an embedded C application of moderate complexity.
 Develop and analyze algorithms in C++.
 Differentiate interpreted languages from compiled languages
UNIT I: Embedded „C‟ Programming Bitwise operations, Dynamic memory allocation, OS services.
Linked stack and queue, Sparse matrices, Binary tree. Interrupt handling in C, Code optimization issues.
Embedded Software Development Cycle and Methods (Waterfall, Agile)
UNITII:Object Oriented Programming Introduction to procedural, modular, object-oriented and

genericprogramming techniques, Limitations of procedural programming, objects, classes, data
members, methods, data encapsulation, data abstraction and information hiding, inheritance,
polymorphism
UNIT III:CPP Programming: „cin‟, „cout‟, formatting and I/O manipulators, new and delete
operators, Defining a class, data members and methods, „this‟ pointer, constructors, destructors, friend
function, dynamic memory allocation
UNIT IV:Overloading and Inheritance: Need of operator overloading, overloading the

assignment,Overloading using friends, type conversions, single inheritance, base and derived
classes, friend Classes, types of inheritance, hybrid inheritance, multiple inheritance, virtual
base class, Polymorphism, virtual functions.
UNIT V:Templates: Function template and class template, member function templates and
templatearguments, Exception Handling: syntax for exception handling code: try-catch- throw,
Overview of Scripting Languages – PERL, CGI, VB Script, Java Script.
PERL: Operators, Statements Pattern Matching etc. Data Structures, Modules, Objects, Tied
Variables, Inter process Communication Threads, Compilation & Line Interfacing.
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Text Books:
1. Michael J. Pont , “Embedded C”, Pearson Education, 2nd Edition, 2008
2. Randal L. Schwartz, “Learning Perl”, O‟Reilly Publications, 6th Edition 2011
Reference Books:
1. A. Michael Berman, “Data structures via C++”, Oxford University Press, 2002
2. Robert Sedgewick, “Algorithms in C++”, Addison Wesley Publishing Company, 1999
3. Abraham Silberschatz, Peter B, Greg Gagne, “Operating System Concepts”, John Willey
& Sons, 2005Kaufmann.
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L T P CREDITS
(ELECTIVE-II) 4 - - 40 60 100 3
SYSTEM DESIGN WITH EMBEDDED LINUX
Course Objectives:
 To understand the embedded Linux development model.
 To be able to write and debug applications and drivers in embedded Linux.
 To be able to understand and create Linux BSP for a hardware platform
Course Outcomes:
 Get the familiarity about embedded Linux development model.
 Write and debug applications and drivers in embedded Linux.
 Understand and create Linux BSP for a hardware platform
UNIT I:
Embedded Linux , Vendor Independence, Time to Market,Varied Hardware Support, Open Source,
Standards (POSIX®) Compliance, Embedded Linux Versus Desktop Linux, Embedded Linux
Distributions, BlueCat Linux, Cadenux , Denx, Embedded Debian (Emdebian),ELinOS (SYSGO),
Metrowerks ,MontaVista Linux, RTLinuxPro, TimeSys Linux.
UNIT II:
Embedded Linux Architecture, Real-Time Executive, Monolithic Kernels, Micro kernel Kernel
Architecture – HAL, Memory manager, Scheduler, File System, I/O and Networking subsystem, IPC,
User space, Start-up sequence, Boot Loader Phase, Kernel Start-Up, User Space Initialization.
UNIT III:
Board Support Package Embedded Storage: MTD, Architecture, Drivers, Embedded File System
Embedded Drivers: Serial, Ethernet, I2C, USB, Timer, Kernel Modules.
UNIT IV:
Porting Applications, Architectural Comparison, Application Porting Roadmap, Programming with P
threads, Operating System Porting Layer (OSPL), Kernel API Driver, Real-Time Linux: Linux andReal
time, Programming, Hard Real-time Linux
UNIT V:
Building and Debugging: Kernel, Building the Kernel, Building Applications, Building the Root File
System, Integrated Development Environment, Debugging Virtual Memory Problems , Kernel
Debuggers, Root file system Embedded Graphics. Graphics System, Linux Desktop Graphics, Embedded
Linux Graphics, Embedded Linux Graphics Driver, Windowing Environments, Toolkits, and
Applications,Case study of uC linux
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Text Books:
1. KarimYaghmour, “Building Embededd Linux Systems”, O'Reilly & Associates

2. P Raghvan, Amol Lad, SriramNeelakandan, “Embedded Linux System Design and
Development”, Auerbach Publications
Reference Books:
1. Christopher Hallinan, “Embedded Linux Primer: A Practical Real World Approach”,Prentice

Hall, 2nd Edition, 2010.
2. Derek Molloy, “Exploring BeagleBone: Tools and Techniques for Building withEmbedded
Linux”, Wiley, 1st Edition, 2014.
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L T P CREDITS
(ELECTIVE-II) 4 - - 40 60 100 3
HARDWARE SOFTWARE CO-DESIGN
Course Objectives:
Practice computer engineering

Define and diagnose problems, and provide and implement computer engineering solutions in an
industrial environment
Collaborate with others as a member or as a leader in an engineering team
Course Outcomes:
 About the Hardware-Software Code sign Methodology.
 How to select a target architecture and how a prototype is built and how emulation of a prototype is
done.
 Brief view about compilation technologies and compiler development environment.
 Understand the importance of system level specification languages and multi-language co-simulation.
UNIT-I:
Co- Design Issues

Co- Design Models, Architectures, Languages, A Generic Co-design Methodology.
Co- Synthesis Algorithms
Hardware software synthesis algorithms: hardware – software partitioning distributed system co-synthesis.
UNIT-II:
Prototyping and Emulation
Prototyping and emulation techniques, prototyping and emulation environments, future developments in emulation
and prototyping architecture specialization techniques, system communication infrastructure
Target Architectures
Architecture Specialization techniques, System Communication infrastructure, Target Architecture and
Application System classes, Architecture for control dominated systems (8051-Architectures for High performance
control), Architecture for Data dominated systems (ADSP21060, TMS320C60), Mixed Systems.
UNIT-III:
Compilation Techniques and Tools for Embedded Processor Architectures
Modern embedded architectures, embedded software development needs, compilation technologies, practical
consideration in a compiler development environment.
UNIT-IV:
Design Specification and Verification
Design, co-design, the co-design computational model, concurrency coordinating concurrent computations,
interfacing components, design verification, implementation verification, verification tools,
Interface verification. Page 21

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UNIT-V:
Languages for System-Level Specification and Design-I
System-level specification, design representation for system level synthesis, system level specification languages.
Languages for System-Level Specification and Design-II
Heterogeneous specifications and multi language co-simulation, the cosyma system and lycos system.
Text Books:
1. Hardware / Software Co- Design Principles and Practice – Jorgen Staunstrup, Wayne Wolf – 2009,
Springer.
2. Hardware / Software Co- Design - Giovanni De Micheli, Mariagiovanna Sami, 2002, Kluwer
Academic Publishers.
Reference Books:
1. A Practical Introduction to Hardware/Software Co-design -Patrick R. Schaumont - 2010 –

SpringerPublications.
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L T P CREDITS
- - 3 40 60 100 1.5
RTL SIMULATION AND SYNTHESIS WITH PLDS LAB
Course Outcomes:
 Identify, formulate, solve and implement problems in signal processing,
communicationSystems etc using RTL design tools.
 Use EDA tools like Cadence, Mentor Graphics and Xilinx
List of Experiments:
1) Verilog implementation of
i) 8:1 Mux/Demux,
ii) Full Adder, 8-bit Magnitude comparator,
iii) 3-bit Synchronous Counters
iv) Parity generator.
2) Sequence generator/detectors, Synchronous FSM – Mealy and Moore machines.
3) Vending machines - Traffic Light controller, ATM, elevator control.
4) PCI Bus & arbiter and downloading on FPGA.
5) UART/ USART implementation in Verilog.
6) Realization of single port SRAM in Verilog.
7) Verilog implementation of Arithmetic circuits like serial adder/
subtractor, paralleladder/subtractor, serial/parallel multiplier.
8) Discrete Fourier transform/Fast Fourier Transform algorithm in Verilog.
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(AUTONOMOUS)
INTERNA EXTERNA TOTAL
L T P CREDI
I M.TECH-I SEMESTER L L MARKS
TS
MARKS MARKS
- - 3 40 60 100 1.5
Microcontrollers and Programmable Digital Signal Processors Lab
Course Objectives:
 To understand, compare and select ARM processor core based
SoC with severalfeatures/peripherals based on requirements of
embedded applications.
 To be able to identify and characterize architecture of Programmable DSP Processors
 To develop small applications by utilizing the ARM processor core and DSP
Course Outcomes:
 Compare and select ARM processor core based SoC with several
features/peripheralsbased on requirements of embedded applications.
 Identify and characterize architecture of Programmable DSP Processors
 Develop small applications by utilizing the ARM processor core and DSP
List of Assignments:
Part A) Experiments to be carried out on Cortex-M3 development boards

and using GNUTool chain
1. Blink an LED with software delay, delay generated using the Sys Tick timer.
2. System clock real time alteration using the PLL modules.
3. Control intensity of an LED using PWM implemented in software and hardware.
4. Control an LED using switch by polling method, by interrupt method and flash
the LED onceevery five switch presses.
5. UART Echo Test.
6. Take analog readings on rotation of rotary potentiometer connected to an ADC channel.
7. Temperature indication on an RGB LED.
8. Mimic light intensity sensed by the light sensor by varying the blinking rate of an LED.
9. Evaluate the various sleep modes by putting core in sleep and deep sleep modes.
10. System reset using watchdog timer in case something goes wrong.
11. Sample sound using a microphone and display sound levels on LEDs.
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(AUTONOMOUS)
Part B) Experiments to be carried out on DSP C6713 evaluation kits and using
Code ComposerStudio (CCS)
1. To develop an assembly code and C code to compute Euclidian distance
between any twopoints
2. To develop assembly code and study the impact of parallel, serial and mixed execution
3. To develop assembly and C code for implementation of convolution operation
4. To design and implement filters in C to enhance the features of given input sequence/signal
Page 25

(AUTONOMOUS)
L T P CREDITS
I M.TECH-II SEMESTER MARKS MARKS MARKS
4 - - 40 60 100 3
ANALOG AND DIGITAL CMOS VLSI DESIGN
Course Objectives:
 To teach fundamentals of CMOS Digital integrated circuit design such as importance of
Combinational MOS logic circuits, and Sequential MOS logic circuits.
 To teach the fundamentals of Dynamic logic circuits and basic semiconductor memories which
are the basics for the design of high performance digital integrated circuits.
 Basic design concepts, issues and tradeoffs involved in analog IC design are explored.
 To learn about Design of CMOS Op Amps, Compensation of Op Amps, Design of Two-Stage Op
Amps, Power Supply Rejection Ratio of Two-Stage Op Amps, Cascade Op Amps, Measurement
Techniques of OP Amp.
Course Outcomes:
 Appreciate the trade-offs involved in analog integrated circuit design.
 Understand and appreciate the importance of noise and distortion in analog circuits.
 Analyze complex engineering problems critically in the domain of analog IC design for
conducting research.
 Demonstrate advanced knowledge in Static and dynamic characteristics of CMOS, Alternative
CMOS Logics, Estimation of Delay and Power, Adders Design.
 Solve engineering problems for feasible and optimal solutions in the core area of digital ICs.
Syllabus Contents:
Technology Scaling and Road map, Scaling issues, Standard 4 mask NMOS Fabrication process
Digital CMOS Design:
UNIT I:
Review: Basic MOS structure and its static behavior, Quality metrics of a digital design: Cost,
Functionality, Robustness, Power, and Delay, Stick diagram and Layout, Wire delay models.
Inverter: Static CMOS inverter, Switching threshold and noise margin concepts and their
Evaluation, Dynamic behavior, Power consumption.
UNIT II:
Physical design flow: Floor planning, Placement, Routing, CTS, Power analysis and IRdrop
estimation-static and dynamic, ESD protection-human body model, Machine model.
Combinational logic: Static CMOS design, Logic effort, Rationed logic, Pass transistor logic,
Dynamic logic, Speed and power dissipation in dynamic logic, Cascading dynamic gates,
CMOS transmission gate logic.
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(AUTONOMOUS)
UNIT III:
Sequential logic: Static latches and registers, Bi-stability principle, MUX based latches,
Static SR flip-flops, Master-slave edge-triggered register, Dynamic latches and registers, Concept of
pipelining, Pulse registers, Non-bistable sequential circuit. Advanced technologies: Giga-scale dilemma,
Short channel effects, High–k, Metal Gate Technology, FinFET, TFET etc.
Analog CMOS Design:

UNIT IV:
Single Stage Amplifier: CS stage with resistance load, Divide connected load, Currentsource
load, Triode load, CS stage with source degeneration, Source follower, Common gate,stage,
Cascade stage, Choice of device models. Differential Amplifiers: Basic difference pair,
Commonmode response, Differential pair with MOS loads, Gilbert cell.
UNIT V:
Passive and active current mirrors: Basic current mirrors, Cascade mirrors, Active current mirrors.
Frequency response of CS stage: Source follower, Common gate stage, Cascade stage and difference
pair, Noise. Operational amplifiers: One stage OPAMP, Two stage OPAMP, Gain boosting,Common
mode feedback, Slew rate, PSRR, Compensation of 2 stage OPAMP
Text Books:
1. J P Rabaey, A P Chandrakasan, B Nikolic, “Digital Integrated circuits: A design perspective”,

Prentice Hall electronics and VLSI series, 2nd Edition.
2. Baker, Li, Boyce, “CMOS Circuit Design, Layout, and Simulation”, Wiley, 2nd Edition.
3. BehzadRazavi , “Design of Analog CMOS Integrated Circuits”, TMH, 2007.
Reference Books:
1. Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design”, Oxford, 3rd Edition.
2. R J Baker, “CMOS circuit Design, Layout and Simulation”, IEEE Inc., 2008.
3. Kang, S. and Leblebici, Y., “CMOS Digital Integrated Circuits, Analysis and Design”,TMH,
3rdEdition.
4. Pucknell, D.A. and Eshraghian, K., “Basic VLSI Design”, PHI, 3rd Edition.
Page 27

(AUTONOMOUS)
L T P CREDITS
4 - - 40 60 100 3
REAL TIME OPERATING SYSTEMS
Course Objectives:
 To Know the Basic Designs using an RTOS.
 To Know the Functions and Types of RTOS for Embedded Systems.
 To Analyze the issues in real time operating systems
 To Study the Programming Concepts of RT Linux.
 To Understand Applications Control by RT Linux System.
 To Analyze the Operating System Software
Course Outcomes:
 Illustrate real time programming concepts.
 Apply RTOS functions to implement embedded applications
 Understand fundamentals of design consideration for embedded applications
UNIT I
Introduction to Real-Time Operating Systems - Defining an RTOS, The scheduler, Kernel Objects and
services, Key characteristics of an RTOS
Task- Defining a Task, Task States and Scheduling, Typical Task Operations, Typical Task Structure,
Synchronization, Communication and Concurrency
UNIT II
Semaphores - Defining Semaphores, Typical Semaphore Operations, Typical Semaphore Use
Message Queues - Defining Message Queues, Message Queue States, Message Queue Content, Message
Queue Storage, Typical Message Queue Operations, Typical Message Queue Use, Pipes, Event
Registers, Signals and condition Variables
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(AUTONOMOUS)
UNIT III
Exceptions and Interrupts - Exceptions and Interrupts, Applications of Exceptions and Interrupts,
Closer look at exceptions and interrupts, processing general Exceptions, Nature of Spurious Interrupts
Timer and Timer Services - Real-Time clocks and System Clocks, Programmable Interval Timers,
Timer Interrupt Service Routines.
I/O Subsystems - I/O concepts, I/O subsystems
UNIT IV
Memory Management - Dynamic Memory Allocation in Embedded Systems, Fixed-Size Memory
management in Embedded Systems, Blocking VS. Non-Blocking Memory Functions, Hardware Memory
Management Units
Modularizing an application for concurrency- An outside-in approach to decompose
Applications, Guidelines and Recommendations for Identifying Concurrency, Schedulability Analysis
UNIT V
Synchronization and Communication - Synchronization, Communication, Resource Synchronization
Methods, Critical section, Common practical design patterns, Specific Solution Design Patterns,
Common Design Problems - Resource Classification, Deadlocks, Priority Inversion.
Text Books
1. Qing Li, Caroline Yao (2003), “Real-Time Concepts for Embedded Systems”, CMP Books.
Page 29

(AUTONOMOUS)
L T P CREDITS
4 - - 40 60 100 3
SOC DESIGN
Course Objectives:
 To understand the concepts of System on Chip Design methodology for Logic and Analog Cores.
 To understand the concepts of System on Chip Design Validation.
 To understand the concepts of SOC Testing
Course Outcomes:
 Identify and formulate a given problem in the framework of SoC based design approaches
DesignSoC based system for engineering applications
 Realize impact of SoC on electronic design philosophy and Macro-electronics thereby
 incline towards entrepreneurship & skill development.
UNIT I:
ASIC: Overview of ASIC types, design strategies, CISC, RISC and NISC approaches for SOC
architectural issues and its impact on SoC design methodologies, Application Specific
Instruction Processor (ASIP) concepts.
UNIT II:
NISC: NISC Control Words methodology, NISC Applications and Advantages, Architecture
Description Languages (ADL) for design and verification of Application Specific Instruction set
Processors (ASIP), No-Instruction-Set-computer (NISC)- design flow, modeling NISC
architectures and systems, use of Generic Netlist Representation - A formal language for
specification, compilation and synthesis of embedded processors.
UNIT III:
Simulation: Different simulation modes, behavioral, functional, static timing, gate level, switch level,
transistor/circuit simulation, design of verification vectors, Low power FPGA, Reconfigurable systems,
SoC related modeling of data path design and control logic, Minimization of interconnects impact, clock
tree design issues.
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(AUTONOMOUS)
UNIT IV:
Low power SoC design / Digital system:

Design synergy, Low power system perspective- power gating, clock gating, adaptive voltage
scaling (AVS), Static voltage scaling, Dynamic clock frequency and voltage scaling (DCFS),
building block optimization, building block memory, power down techniques, power
consumption verification.
UNIT V:
Synthesis
Role and Concept of graph theory and its relevance to synthesizable constructs, Walks, trails
paths, connectivity, components, mapping/visualization, nodal and admittance graph.
Technology independent and technology dependent approaches for synthesis, optimization
constraints, Synthesis report analysis Single core and Multi core systems, dark silicon issues,
HDL coding techniques for minimization of power consumption, Fault tolerant designs.
Text Books:
1. Hubert Kaeslin, “Digital Integrated Circuit Design: From VLSI Architectures to CMOS
Fabrication”, Cambridge University Press, 2008.
2. B. Al Hashimi, “System on chip-Next generation electronics”, The IET, 2006
Reference Books:
1. Rochit Rajsuman, “System-on- a-chip: Design and test”, Advantest America R & D Center,2000
2. P Mishra and N Dutt, “Processor Description Languages”, Morgan Kaufmann, 2008
3. Michael J. Flynn and Wayne Luk, “Computer System Design: System-on-Chip”. Wiley
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(AUTONOMOUS)
I M.TECH-II SEMESTER INTERNAL EXTERNAL TOTAL
L T P CREDITS
MARKS MARKS MARKS
4 - - 40 60 100 3
NETWORK SECURITY AND CRYPTOGRAPHY
Course Objectives:
 To understand basics of Cryptography and Network Security

 To be able to secure a message over insecure channel by various means
 To learn about how to maintain the Confidentiality, Integrity and Availability of a data.
 To understand various protocols for network security to protect against the threats in the networks.
Course Outcomes:
 Identify and utilize different forms of cryptography techniques.
 Incorporate authentication and security in the network applications.
 Distinguish among different types of threats to the system and handle the same.
UNIT 1:
Security & Number Theory
Need, security services, Attacks, OSI Security Architecture, one time passwords, Model for Network
security, Classical Encryption Techniques like substitution ciphers, Transposition ciphers, Cryptanalysis
of Classical Encryption Techniques. Introduction, Fermat‟s and Euler‟s Theorem, The Chinese
Remainder Theorem, Euclidean Algorithm, Extended Euclidean Algorithm, and Modular Arithmetic.
UNIT II:
Private-Key (Symmetric) Cryptography

Block Ciphers, Stream Ciphers, RC4 Stream cipher, Data Encryption Standard (DES),Advanced
Encryption Standard (AES), Triple DES, RC5, IDEA, Linear and Differential Cryptanalysis.
UNIT III:
Public-Key (Asymmetric) Cryptography

RSA, Key Distribution and Management, Diffie-Hellman Key Exchange, Elliptic Curve
Cryptography, Message Authentication Code, hash functions, message digest algorithms:
MD4 MD5, Secure Hash algorithm, RIPEMD-160, HMAC.
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(AUTONOMOUS)
UNIT IV:
Authentication
IP and Web Security Digital Signatures, Digital Signature Standards, Authentication Protocols,
Kerberos, IP security Architecture, Encapsulating Security Payload, Key Management, Web
Security Considerations, Secure Socket Layer and Transport Layer Security, Secure Electronic
Transaction.
UNIT V:
System Security
Intruders, Intrusion Detection, Password Management, Worms, viruses, Trojans, Virus
Countermeasures, Firewalls, Firewall Design Principles, Trusted Systems.
Text Books:
1. William Stallings, “Cryptography and Network Security, Principles and Practices”, Pearson
Education, 3rd Edition.
2. Charlie Kaufman, Radia Perlman and Mike Speciner, “Network Security, Private Communication
in a Public World”, Prentice Hall, 2nd Edition
Reference Books:
1. Christopher M. King, Ertem Osmanoglu, Curtis Dalton, “Security Architecture, Design
Deployment and Operations”, RSA Pres,
2. Stephen Northcutt, LenyZeltser, Scott Winters, Karen Kent, and Ronald W. Ritchey, “Inside
Network Perimeter Security”, Pearson Education, 2nd Edition
3. Richard Bejtlich, “The Practice of Network Security Monitoring: Understanding Incident
Detection and Response”, William Pollock Publisher, 2013.
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(AUTONOMOUS)
L T P CREDITS
(ELECTIVE-III) MARKS MARKS MARKS
4 - - 40 60 100 3
MEMORY ARCHITECTURES
Course objective
to give the students a thorough exposure to ARM architecture and make the students to learn the ARM
programming & Thumb programming models
Course Outcomes:
 Select architecture and design semiconductor memory circuits and subsystems.

 Identify various fault models, modes and mechanisms in semiconductor memories and
their testing procedures.
 Know how the state-of-the-art memory chip design

UNIT 1:Random Access Memory Technologies:
Static Random Access Memories (SRAMs), SRAM Cell Structures, MOS SRAM
Architecture, MOS SRAM Cell and Peripheral Circuit, Bipolar SRAM, Advanced SRAM Architectures,
Application Specific SRAMs.
UNIT II:DRAMs, MOS DRAM Cell, BiCMOS DRAM, Error Failures in DRAM, Advanced
DRAM Design and Architecture, Application Specific DRAMs. SRAM and DRAM Memory controllers.
UNIT III: Non-Volatile Memories: Masked ROMs, PROMs, Bipolar & CMOS PROM,
EEPROMs,Floating Gate EPROM Cell, OTP EPROM, EEPROMs, Non-volatile SRAM, Flash
Memories.
UNIT IV:Semiconductor Memory Reliability and Radiation Effects: General Reliability Issues,
RAM Failure Modes and Mechanism, Nonvolatile Memory, Radiation Effects, SEP, Radiation
Hardening Techniques. Process and Design Issues, Radiation Hardened Memory Characteristics,
Radiation Hardness Assurance and Testing.
UNIT V :Advanced Memory Technologies and High-density Memory Packing Technologies:

Ferroelectric Random Access Memories (FRAMs), Gallium Arsenide (GaAs) FRAMs, Analog
Memories, Magneto Resistive Random Access Memories (MRAMs), Experimental Memory
Devices. Memory Hybrids (2D & 3D), Memory Stacks, Memory Testing and Reliability Issues,
Text Books:
1. Ashok K Sharma, “Advanced Semiconductor Memories: Architectures, Designs and
Applications”, Wiley Inter science
2. KiyooItoh, “VLSI memory chip design”, Springer International Edition
Page 34
Reference Books:
1. Ashok K Sharma,” Semiconductor Memories: Technology, Testing and Reliability , PHI
(AUTONOMOUS)
I M.TECH-II SEMESTER L T P CREDITS
MARKS MARKS MARKS
(ELECTIVE-III)
4 - - 40 60 100 3
LOW POWER VLSI DESIGN
Course Objectives:
Ability to understand Signal processing at Different rates and its applications.
Students able to implement Digital filters and able to estimate non-parametric methods.
Students able to implement filter structures and able to estimate power spectrum of
parametric methods.
Course Outcomes:
 Identify the sources of power dissipation in digital IC systems & understand the
impact of power on system performance and reliability.
 Characterize and model power consumption & understand the basic analysis
methods.
Understand leakage sources and reduction techniques
UNIT 1: Technology & Circuit Design Levels: Sources of power dissipation in digital ICs,
degreeOf freedom, recurring themes in low-power, emerging low power approaches, dynamic
dissipation in CMOS, effects of Vdd& Vt on speed, constraints on Vt reduction, transistor
sizing& optimal gate oxide thickness, impact of technology scaling, technology innovations.
UNIT II:Low Power Circuit Techniques: Power consumption in circuits, flip-flops & latches,
highcapacitance nodes, energy recovery, reversible pipelines, high performance approaches.
UNIT III: Low Power Clock Distribution: Power dissipation in clock distribution, single
driverVersus distributed buffers, buffers & device sizing under process variations, zero
skew Vs. Tolerable skew, chip & package co-design of clock network.
UNIT IV:Logic Synthesis for Low Power estimation techniques: Power minimization
techniques,Low power arithmetic components- circuit design styles, adders, multipliers.
UNIT V: Low Power Memory Design: Sources & reduction of power dissipation in
memory subsystem, sources of power dissipation in DRAM & SRAM, low power DRAM
circuits,
low power SRAM circuits. Low Power Microprocessor Design System: power management support,
architectural trade offs for power, choosing the supply voltage, low-power clocking, implementation
problem for low power.
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(AUTONOMOUS)
Text Books:
1. P. Rashinkar, Paterson and L. Singh, “Low Power Design Methodologies”, Kluwer Academic,
2002
2. Kaushik Roy, Sharat Prasad, “Low power CMOS VLSI circuit design”, John Wiley sons
Inc.,2000.
Reference Books:
1. J.B.Kulo and J.H Lou, “Low voltage CMOS VLSI Circuits”, Wiley, 1999.
2. A.P.Chandrasekaran and R.W.Broadersen, “Low power digital CMOS design”,Kluwer,1995
3. Gary Yeap, “Practical low power digital VLSI design”, Kluwer, 1998.
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(AUTONOMOUS)
L T P CREDITS
(ELECTIVE-III) MARKS MARKS MARKS
4 - - 40 60 100 3
ARTIFICIAL INTELLIGENCE
Course Objectives:
 Explain the basic knowledge representation, problem solving, and learning methods of Artificial Intelligence
 Assess the applicability, strengths, and weaknesses of the basic knowledge representation, problem solving,
and learning methods in solving particular particular engineering problems
 Develop intelligent systems by assembling solutions to concrete computational problems
 Understand the role of knowledge representation, problem solving, and learning in intelligent-system
engineering
Course Outcomes:
 Understand the concept of Artificial Intelligence, search techniques and knowledge

representation issues
 Understanding reasoning and fuzzy logic for artificial intelligence
 Understanding game playing and natural language processing
Syllabus Contents:
UNIT 1
What is AI (Artificial Intelligence)? : The AI Problems, The Underlying Assumption, What are A
Techniques, The Level Of The Model, Criteria For Success, Some General References, One Final Word
Problems, State Space Search & Heuristic Search Techniques: Defining The Problems As A State Space
Search, Production Systems, Production Characteristics, Production System Characteristics, And Issues
In The Design Of Search Programs, Additional Problems. Generate-And-Test, Hill Climbing, Best-First
Search, Problem Reduction, Constraint Satisfaction, Means-Ends Analysis.
UNIT II
Knowledge Representation Issues: Representations And Mappings, Approaches To Knowledge
Representation. Using Predicate Logic: Representation Simple Facts In Logic, Representing
Instance And Isa Relationships, Computable Functions And Predicates, Resolution. Representing
Knowledge Using Rules: Procedural Versus Declarative Knowledge, Logic Programming,
Forward Versus Backward Reasoning.
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(AUTONOMOUS)
UNIT III
Symbolic Reasoning Under Uncertainty: Introduction To No monotonic Reasoning, Logics For
Non-monotonic Reasoning. Statistical Reasoning: Probability And Bays‟ Theorem, Certainty
Factors And Rule-Base Systems, Bayesian Networks, Dempster Shafer Theory.
Fuzzy Logic. Weak Slot-and-Filler Structures: Semantic Nets, Frames. Strong Slot-and-Filler
Structures: Conceptual Dependency, Scripts, CYC
UNIT IV
Game Playing: Overview, And Example Domain: Overview, Mini Max, Alpha-Beta Cut-off,
Refinements, Iterative deepening, The Blocks World, Components Of A Planning System, Goal
Stack Planning, Nonlinear Planning Using Constraint Posting, Hierarchical Planning, Reactive
Systems, Other Planning Techniques. Understanding: What is understanding? What makes it
hard? As constraint satisfaction
UNIT V
Natural Language Processing: Introduction, Syntactic Processing, Semantic Analysis, Semantic
Analysis, Discourse And Pragmatic Processing, Spell Checking Connectionist Models:
Introduction: Hopfield Network, Learning In Neural Network, Application Of Neural Networks,
Recurrent Networks, Distributed Representations, Connectionist AI And Symbolic AI.
Text Books:
1. Elaine Rich and Kevin Knight “Artificial Intelligence”, 2nd Edition, Tata Mcgraw-Hill, 2005.
2. Stuart Russel and Peter Norvig, “Artificial Intelligence: A Modern Approach”, 3rdEdition,
Prentice Hall, 2009.
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(AUTONOMOUS)
L T P CREDITS
(ELECTIVE-IV) MARKS MARKS MARKS
4 - - 40 60 100 3
COMMUNICATION BUSSES AND INTERFACES
Course Objectives:
 Understand Communication Fundamentals
 Familiarize with Bus Architectures
 Study Bus Protocols and Standards
Analyze Interface Components
Course Outcomes: At the end of the course the student will be able to
 Select a particular serial bus suitable for a particular application.

 Develop APIs for configuration, reading and writing data onto serial bus.
 Design and develop peripherals that can be interfaced to desired serial bus.
UNIT I
Serial Busses- Cables, Serial busses, serial versus parallel, Data and Control Signal- data frame, data rate,
features Limitations and applications of RS232, RS485, I2C , SPI
UNIT II
CAN
ARCHITECTURE- ISO 11898-2, ISO 11898-3, Data Transmission- ID allocation, Bit timing, Layers-
Application layers, Object layer, Transfer layer, Physical layer, Frame formats- Data frame, Remote
frame, Error frame, Over load frame, Ack slot, Inter frame spacing, Bit spacing, Applications.
UNIT III
PCIe
Revision, Configuration space- configuration mechanism, Standardized registers, Bus enumeration,
Hardware and Software implementation, Hardware protocols, Applications.
Page 39
.
(AUTONOMOUS)
UNIT IV
USB
Transfer Types- Control transfers, Bulk transfer, Interrupt transfer, Isochronous transfer. Enumeration- Device
detection, Default state, Addressed state, Configured state, enumeration sequencing. Descriptor types and
contents- Device descriptor, configuration descriptor, Interface descriptor, Endpoint descriptor,String
descriptor. Device driver
UNIT V
Data streaming Serial Communication Protocal- Serial Front Panel Data Port(SFPDP) configurations,
Flow control, serial FPDP transmission frames, fiber frames and copper cable.
TEXTBOOKS
1. A Comprehensive Guide to controller Area Network – Wilfried Voss, Copperhill Media

Corporation, 2nd Ed., 2005.
2. Serial Port Complete-COM Ports, USB Virtual Com Portsand Ports for Embedded Systems- Jan
Axelson, Lakeview Research, 2nd Ed.,
REFERENCES
1. USB Complete – Jan Axelson, Penram Publications.

2. PCI Express Technology – Mike Jackson, Ravi Budruk, Mindshare Press.
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(AUTONOMOUS)
L T P CREDITS
(ELECTIVE-IV) MARKS MARKS MARKS
4 - - 40 60 100 3
PHYSICAL DESIGN AUTOMATION
Course Objectives:
 Understand the concepts of Physical Design Process such as partitioning,
Floorplanning, Placement and Routing.
 Discuss the concepts of design optimization algorithms and their application to
physical design automation.
 Understand the concepts of simulation and synthesis in VLSI Design Automation
 Formulate CAD design problems using algorithmic methods
 Understand the relationship between design automation algorithms and Various

constraints posedby VLSI fabrication and design technology.
 Adapt the design algorithms to meet the critical design parameters.
 Identify layout optimization techniques and map them to the algorithms
 Develop proto-type EDA tool and test its efficacy
UNIT -I:
VLSI design Cycle, Physical Design Cycle, Design Rules, Layout of Basic Devices, and
Additional Fabrication, Design styles: full custom, standard cell, gate arrays, field
programmable gate arrays, sea of gates and comparison, system packaging styles, multi-
chip modules. Design rules, layout of basic devices, fabrication process and its impact on
physical design, interconnect delay, noise and cross talk, yield and fabrication cost.
UNIT -II:
Factors, Complexity Issues and NP-hard Problems, Basic Algorithms (Graph and
Computational Geometry): graph search algorithms, spanning tree algorithms, shortest path
algorithms, matching algorithms, min-cut and max-cut algorithms, Steiner tree algorithms
Page 41

(AUTONOMOUS)
UNIT -III:
Basic Data Structures, atomic operations for layout editors, linked list of blocks, bin based
methods, neighbour pointers, corner stitching, multi-layer operations.
UNIT -IV:
Graph algorithms for physical design: classes of graphs, graphs related to a set of lines,
graphs related to set of rectangles, graph problems in physical design, maximum clique and
minimum colouring, maximum k-independent set algorithm, algorithms for circle graphs.
UNIT -V:
Partitioning algorithms: design style specific partitioning problems, group migrated
algorithms, simulatedannealing and evolution, and Floor planning and pin assignment,
Routing and placement algorithms
Text Books:
1. Naveed Shervani, Algorithms for VLSI Physical Design
Automation, 3rd Edition,Kluwer Academic, 1999.
2. Charles J Alpert, Dinesh P Mehta, Sachin S Sapatnekar, Handbook of Algorithms for
Physical DesignAutomation, CRC Press, 2008
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(AUTONOMOUS)
I M.TECH-II INTERNAL EXTERNAL TOTAL
L T P CREDITS
SEMESTER MARKS MARKS MARKS
(ELECTIVE-IV) 4 - - 40 60 100 3
ALGORITHMS FOR VLSI DESIGN AUTOMATION
Course Objectives:
Student will learn the basic concepts of CAD design using algorithms.
Student will impart the knowledge in Modeling and Simulation of Digital Circuits.
Student will understand the different Logic Synthesis and its verification.
Modify the CAD design problems using algorithmic paradigms
Illustrate Backend Design Concepts
Illustrate about Modeling and Simulation of Digital Circuits
Summarize about different Logic Synthesis and its verification
Analyze physical design problems of FPGA,MCM
UNIT-I
PRELIMINARIES& GENERAL PURPOSE METHODS FOR COMBINATIONAL
OPTIMIZATION: Introduction to Design Methodologies, Design Automation tools, Algorithmic Graph
Theory, Computational Complexity, Tractable and Intractable Problems
General Purpose Methods for Combinational Optimization: Backtracking, Branch and Bound, Dynamic
Programming, Integer Linear Programming, Local Search, Simulated Annealing, Tabu search, Genetic
Algorithms.
UNIT- II
LAYOUT COMPACTION: Design Rules, Symbolic Layout, Problem Formulation, Algorithms for
Constraint –graph Compaction.
Placement and Partitioning: Circuit Representation, Wire-length Estimation, Types of Placement Problem,
Placement Algorithms, Partitioning
Floor Planning: Floor Planning Concepts, Shape Functions and Floor plan Sizing
Routing: Types of Local Routing Problems, Area Routing, Channel Routing, Introduction to Global Routing,
Algorithms for Global Routing.
UNIT- III
MODELLING AND SIMULATION: Gate Level Modeling and Simulation, Switch level modeling and
simulation.
UNIT- IV
LOGIC SYNTHESIS AND VERIFICATION: Basic issues and Terminology, Binary –Decision diagram,
Two – Level Logic Synthesis. High Level Synthesis: Hardware Models, Internal representation of the input
algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aspects of
Assignment problem, High – level Transformations.
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(AUTONOMOUS)
UNIT- V
PHYSICAL DESIGN AUTOMATION OF FPGA’S: FPGA technologies, Physical Design cycle for
FPGA‘s partitioning and routing for segmented and staggered models.
Physical Design Automation of MCM’s: MCM technologies, MCM physical design cycle, Partitioning,
Placement – Chip array based and full custom approaches, Routing –Maze routing, Multiple stage routing,
Topologic routing, Integrated Pin –Distribution and routing, routing and programmable MCM‘s.
TEXT BOOKS:
1. S.H.Gerez, ―Algorithms for VLSI Design Automation‖, WILEY student edition, Johnwiley& Sons (Asia)
Pvt.Ltd. 1999.
2. NaveedSherwani, ―Algorithms for VLSI Physical Design Automation‖, Springer International Edition
3rd edition, , 2005
REFERENCES:
1. Hill &Peterson, ―Computer Aided Logical Design with Emphasis on VLSI‖, John Wiley, 1993.
2. Wayne Wolf, ―Modern VLSI Design: Systems on silicon‖, Pearson Education Asia,2ND Edition, 1998.
Page 71

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L T P CREDITS
- - 3 40 60 100 1.5
ANALOG AND DIGITAL CMOS VLSI DESIGN LAB
 The students are required to design and implement the Circuit and
Layout of any TENExperiments using CMOS 130nm Technology with
Mentor Graphics Tool/Cadence/ Synopsys/Industry Equivalent Standard
Software.
1. MOS Device Characterization and parametric analysis

2. Common Source Amplifier
3. Common Source Amplifier with source degeneration
4. Cascode amplifier
5. simple current mirror
6. cascode current mirror.
7. Wilson current mirror.
8. Full Adder
9. RS-Latch
10. Clock Divider
11. JK-Flip Flop
12. Synchronous Counter
13. Asynchronous Counter
14. Static RAM Cell
Page 72

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L T P CREDITS
 T
h - - 3 40 60 100 1.5
e
REAL TIME OPERATING SYSTEMS LAB

 Students are required to write the programs using C-Language according to the
Experimentrequirements using RTOS Library Functions and macros ARM-926
developer kits and ARM- Cortex.
 The following experiments are required to develop the algorithms, flow
diagrams, source codeand perform the compilation, execution and implement the
same using necessary hardware kitsfor verification. The programs developed for
the implementation should be at the level of an embedded system design.
 The students are required to perform at least SIX experiments from Part-I and
TWO experimentsfrom Part-II.
Part-I:Experiments using ARM-926 with PERFECT RTOS
1. Register a new command in CLI.

2. Create a new Task.
3. Interrupt handling.
4. Allocate resource using semaphores.
5. Share resource using MUTEX.
6. Avoid deadlock using BANKER‟S algorithm.
7. Synchronize two identical threads using MONITOR.
8. Reader‟s Writer‟s Problem for concurrent Tasks.
Part-II Experiments on ARM-CORTEX processor using any
open source RTOS.(Coo-Cox-Software-Platform)
1. Implement the interfacing of display with the ARM- CORTEX processor.

2. Interface ADC and DAC ports with the Input and Output sensitive devices.
3. Simulate the temperature DATA Logger with the SERIAL
communicationwith PC.
4. Implement the developer board as a modem for data
communication usingserial port communication between two
PC‟s.
Lab Requirements:
Software:
 Eclipse IDE for C and C++ (YAGARTO Eclipse IDE), Perfect
RTOS Library,COO-COX Software Platform, YAGARTO
TOOLS, and TFTP SERVER.
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 LINUX Environment for the compilation using Eclipse IDE &
Java with latestversion.
Hardware:
 The development kits of ARM-926 Developer Kits and ARM-Cortex Boards.
 Serial Cables, Network Cables and recommended power supply for the board.
Page 74

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