 ARM Design Philosophy Portable Embedded Systems ARM processors are designed with a

focus on physical features tailored to portable embedded systems. Reduce Power

Consumption Emphasizing the reduction of power consumption for extended battery life,
crucial for mobile devices like phones and PDAs. Code Density Essential for embedded
systems with limited memory due to cost and size constraints.

 Key Requirements of ARM Design

1 Price-Sensitive Environment Utilizing slow and low-cost memory devices in price-
sensitive embedded systems.
2 Cost-Effectiveness Aiming to reduce the die area occupied by the processor for cost-
effectiveness.
3 Hardware Debug Technology Inclusion of hardware debug technology for software
engineers to monitor code execution, aiding issue resolution and reducing development
costs.

 ARM Core Adaptations for Embedded Systems Hybrid Architecture ARM core not a pure
RISC architecture due to the constraints of embedded systems. Performance & Power
Consumption Focusing on total effective system performance and power consumption
over raw processor speed. Code Optimization Introduction of Thumb 16-bit instruction
set for improved code density.

 ARM Instruction Set for Embedded Systems Variable Cycle Execution Enhances
performance and code density for specific instructions like load-store-multiple
instructions. Code Density Enhancement Inline barrel shifter adds complexity but
enhances core performance and code density. Thumb 16-bit instruction set Support fast
operations, including DSP instructions for 16×16- bit multiplier operations. Conditional
execution This feature improves performance and code density by reducing Branch
instructions Enhanced Instructions These instructions allow a faster-performing ARM
processor in some cases to replace the traditional combinations of a processor plus a
DSP.

 ARM's Popularity in Embedded Systems 1 Global Adoption ARM processor's additional

features make it widely used in 32-bit embedded systems. 2 Global Production Many top
semiconductor companies globally produce products based on the ARM processor. 3
Diverse Applications ARM's adaptability and features contribute to its popularity in
diverse embedded.
Overview of ARM architecture

Features of ARM Processor

 Multiprocessing System
 Tightly Coupled Memory
 Memory Management
 Thumb-2 Technology
 One-Cycle Execution Time
 Pipelining
 A large number of Registers
1. Multiprocessing Systems: ARM processors are designed to be used in cases of
multiprocessing systems where more than one processor is used to process information. The
First AMP processor introduced by the name of ARMv6K could support 4 CPUs along with its
hardware.
2. Tightly Coupled Memory: The memory of ARM processors is tightly coupled. This has a
very fast response time. It has low latency (quick response) that can also be used in cases of
cache memory being unpredictable.
3. Memory Management: ARM processor has a management section. This includes Memory
Management Unit and Memory Protection Unit. These management systems become very
important in managing memory efficiently.
4. Thumb-2 Technology: Thumb-2 Technology was introduced in 2003 and was used to
create variable-length instruction sets. It extends the 16-bit instructions of initial Thumb
technology to 32-bit instructions. It has better performance than previously used Thumb
technology.
5. One-Cycle Execution Time: ARM processor is optimized for each instruction on the CPU.
Each instruction is of a fixed length that allows time for fetching future instructions before
executing the present instructions. ARM has CPI (Clock Per Instruction) of one cycle.
6. Pipelining: Processing of instructions is done in parallel using pipelines. Instructions are
broken down and decoded in one pipeline stage. The channel advances one step at a time to
increase throughput (rate of processing).
7. A large number of Registers: A large number of registers are used in ARM processors to
prevent large amounts of memory interactions. Records contain data and addresses. These act
as a local memory store for all operations.

ARM Processor Registers

Basically, there are two types of registers – General purpose registers and Special purpose
registers. General-purpose registers hold either data or an address. The letter r is prefixed to the
register number to identify them. For example, the label r4 is assigned to register 4. Figure
depicts the active registers that are available in user mode, which is a protected state that is often
utilized for running programs. There are seven various modes that the CPU may work in, which
we shall go through momentarily. The registers in this example are all 32 bits in size. Up to 18
active registers are available: 16 data registers and 2 processor status registers. The data registers
are labeled r0 through r15 by the programmer. The ARM processor contains three registers: r13,
r14, and r15, each of which is allocated to a specific duty or unique function. To distinguish them
from the other registers, they are typically given separate labels. The colored registers indicate
which special-purpose registers have been allocated.
 Register 13 is traditionally used as the stack pointer (SP) and stores the head of
the stack in the current processor mode.
 Register r14 is called the link register (LR) and is where the core puts the return
address whenever it calls a subroutine.
 Register 15 is the program counter (PC) and contains the address of the next
instruction to be fetched by the processor.
ARM Operating Modes

SVR Operating Mode in ARM

In this Operating modes in ARM, On reset, the ARM7 enters this mode. Its purpose is to run the
BIOS software (Booting program). SWI can also be used by the programmer to activate this
mode (Software Interrupt). For example, there are two distinct privileges on our phone or
computer. The supervisor mode is one, while the user mode is the other. These two modes are
separated by the amount of protection they provide. When you’re in supervisor mode, you have
access to both system and user data. When in user mode, however, you can only access user data.
Because of the system’s security level, you do not have authorization to view the data.

User Mode in ARM

This is the default mode, which runs all user programmes. It’s the only mode that isn’t
privileged. Memory, I/O components, and flags are all restricted. All of the other modes can be
accessed via a variety of exceptions (interrupts). After leaving supervisor mode, the
microcontroller enters user mode and remains there until you turn it off. Remember This does
not go straight to user mode when you start it. It is first handled by the supervisor mode, after
which the supervisor mode switches to user mode. The ARM processor spends more than 95% of
its time in user mode over its lifespan. You may access all other modes from this mode.

System Mode in ARM

In this Operating modes in ARM, Its a privileged version of user mode. This mode may be used
by the User application to get complete control over CPSR and Memory. Needless to say, the
programmer should utilise this mode with extreme caution, otherwise the entire protective
mechanism may be jeopardised.

When you make a system call, you automatically enter system mode. For example, on our phone,
if we wish to modify certain settings or adjust the brightness of our phone. We know that all we
have to do is move the cursor left and right. However, it then sends a system call to alter the
brightness of your phone before returning to normal user mode.

FRQ Operating Mode in ARM

In this Operating modes in ARM, Fast Interrupt Request ModeWhen a high priority interrupt is
received through the nFIQ pin, this mode is activated. Because this mode is used for high-
priority interruptions, the ISR should run as quickly as possible (delay). Normally, when we start
an ISR, the original values of all GPRs in the parent programme must be preserved, and these
values must be restored into the GPRS before the ISR is completed so that the main programme
may continue properly. This consumes a lot of time, which causes Interrupt Latency to rise. A
fresh copy of R8-R14 is utilised when a fast Interrupt request is sent. This eliminates the need to
save and restore these registers, making the ISR significantly quicker to perform. As a result, it’s
known as Fast Interrupt Mode.

Abort Mode in ARM

In this Operating modes in ARM , When an attempt to access a memory location fails, this mode
is activated. Specific areas are inaccessible in some settings due to the protection system. When
an attempt is made to access one of these locations, the CPU enters Abort mode, and the
programme that attempted to access it is terminated. When we go from user to supervisor mode
and try to access system data or a system application that the user does not have the authorization
to access, it goes into abort mode, kills the operation, and returns to user mode.

Undefined Operating Mode in ARM

Undefined instructions are entered in this mode. When a co-processor instruction is encountered
but no co-processor is available in the system, this happens. The CPU then enters Undefined
mode, terminating the programme that was attempting that instruction.

CONDITIONAL EXECUTION
Conditional execution controls whether or not the core will execute an instruction. Most
instructions have a condition attribute that determines if the core will execute it based on the
setting of the condition flags. Prior to execution, the processor compares the condition attribute
with the condition flags in the cpsr. If they match, then the instruction is executed; otherwise the
instruction is ignored.
The condition attribute is postfixed to the instruction mnemonic, which is encoded into the
instruction. Table 2.5 lists the conditional execution code mnemonics. When a condition
mnemonic is not present, the default behavior is to set it to always (AL) execute.
ARM Pipelining :
 A Pipelining is the mechanism used by RISC(Reduced instruction set
computer) processors to execute instructions,
 by speeding up the execution by fetching the instruction, while other instructions
are being decoded and executed simultaneously.
 Which in turn allows the memory system and processor to work continuously.
 The pipeline design for each ARM family is different.
Pipelining is a design technique or a process which plays an important role in increasing the
efficiency of data processing in the processor of a computer and microcontroller. By keeping
the processor in a continuous process of fetching, decoding and executing called (F&E cycle).
ARM devices need pipelining because of RISC as it emphasizes on compiler complexity. Each
stage is equivalent to 1 cycle, that is n stages = n cycles.
Pipeline

 Fetch loads an instruction from memory.

 Decode identifies the instruction to be executed.
 Execute processes the instruction and writes the result back to the register.
 By over lapping the above stages of execution of different instructions, the speed of
execution is increased.
 The pipelining allows the core to execute an instruction every cycle, which results
in increased throughput.

Exception handling
What is a vector table in ARM?
The vector table is an array of addresses. The very first entry is the initial stack pointer
after reset, all others are addresses of exception / interrupt handlers (functions). The
first handler (Reset_Handler) address is loaded by the MCU as initial program counter
after reset.

What is the purpose of a vector table?

A vector table consists of a set of assembler (or machine) instructions, which cause the
controller or computer to jump to a specific location that can handle a specific exception
or interrupt. A vector uses a special assembler instruction to load the address of the
handler.