Chapter 5:

Memory Hierarchy

[with materials from Computer Organization and Design, 4th Edition,

Patterson & Hennessy, © 2008, MK]

1
5.1. Introduction: Memory Technology
❑ Static RAM (SRAM)
l 0.5ns – 2.5ns, $2000 – $5000 per GB

❑ Dynamic RAM (DRAM)

l 50ns – 70ns, $20 – $75 per GB

❑ Magnetic disk
l 5ms – 20ms, $0.20 – $2 per GB

❑ Ideal memory
l Access time of SRAM
l Capacity and cost/GB of disk

2
Principle of Locality

❑ Programs access a small proportion

of their address space at any time
❑ Temporal locality /'tempərəl/ thời gian
now maybe
l Items accessed recently are likely to be
accessed again soon
l e.g., instructions in a loop, induction
variables

❑ Spatial locality /'speiʃəl/ không gian

l Items near those accessed recently are maybe

likely to be accessed soon now

l E.g., sequential instruction access,

array data
3
Taking Advantage of Locality
❑ Memory hierarchy
❑ Store everything on disk
❑ Copy recently accessed (and nearby) items from disk to
smaller DRAM memory
l Main memory

❑ Copy more recently accessed (and nearby) items from

DRAM to smaller SRAM memory
l Cache memory attached to CPU

4
Memory Hierarchy Levels

❑ Block (aka line): unit of copying

l May be multiple words

❑ If accessed data is present in upper

level
l Hit: access satisfied by upper level
- Hit ratio: hits/accesses

❑ If accessed data is absent

l Miss: block copied from lower level
- Time taken: miss penalty
- Miss ratio: misses/accesses
= 1 – hit ratio
l Then accessed data supplied from
upper level

5
5.2. Cache Memory

❑ Cache memory
l The level of the memory hierarchy closest to the CPU

❑ Given accesses X1, …, Xn–1, Xn

◼ How do we know if
the data is present?
◼ Where do we look?

6
Direct Mapped Cache

❑ Location determined by address

❑ Direct mapped: only one choice
l (Block address) modulo (#Blocks in cache)

◼ #Blocks is a
power of 2
◼ Use low-order
address bits

Block Number 11
7
Tags and Valid Bits
❑ How do we know which particular block is stored in a
cache location?
l Store block address as well as the data
l Actually, only need the high-order bits
l Called the tag

❑ What if there is no data in a location?

l Valid bit: 1 = present, 0 = not present
l Initially 0

Hit Block address (n bit)

(V=1)

Tag Index
Initial Miss
(stored in cache) (in cache)
(V=0) (V=1)

8
 Cache Example

❑ 8-blocks, 1 word/block, direct mapped

❑ Initial state
High Address Bits of Mem,
Address Bits
but stored in Cache
of Cache

Index V Tag Data

000 N
001 N
010 N
011 N
100 N
101 N
110 N
111 N

9
Cache Example

Word addr Binary addr Hit/miss Cache block

22 10 110 Miss 110

Index V Tag Data

000 N
001 N
010 N
011 N
100 N
101 N
110 Y 10 Mem[10110]
111 N

10
Cache Example

Word addr Binary addr Hit/miss Cache block

26 11 010 Miss 010

Index V Tag Data

000 N
001 N
010 Y 11 Mem[11010]
011 N
100 N
101 N
110 Y 10 Mem[10110]
111 N

11
Cache Example

Word addr Binary addr Hit/miss Cache block

22 10 110 Hit 110
26 11 010 Hit 010

Index V Tag Data

000 N
001 N
010 Y 11 Mem[11010]
011 N
100 N
101 N
110 Y 10 Mem[10110]
111 N

12
Cache Example

Word addr Binary addr Hit/miss Cache block

16 10 000 Miss 000
3 00 011 Miss 011
16 10 000 Hit 000

Index V Tag Data

000 Y 10 Mem[10000]
001 N
010 Y 11 Mem[11010]
011 Y 00 Mem[00011]
100 N
101 N
110 Y 10 Mem[10110]
111 N

13
Cache Example

Word addr Binary addr Hit/miss Cache block

18 10 010 Miss 010

Index V Tag Data

000 Y 10 Mem[10000]
001 N
010 Y 10 Mem[10010]
011 Y 00 Mem[00011]
100 N
101 N
110 Y 10 Mem[10110]
111 N

14
Address Subdivision

15
Example: Larger Block Size

❑ Cache has 64 blocks, 16 bytes/block

l To what block number does address 1200 map?

❑ Block address = 1200/16 = 75

❑ Block number = 75 modulo 64 = 11

Block
31 10 9 4 3 0 Address
0
Tag Index Offset Block
22 bits 6 bits 4 bits Address
1

Block
Address
11
Block Address No.75 in MEM, mapped to Block number 11 in Cache
16
Block Size Considerations

❑ Larger blocks should reduce miss rate

l Due to spatial locality

❑ But in a fixed-sized cache

l Larger blocks  fewer of them
- More competition  increased miss rate
l Larger blocks  pollution

❑ Larger miss penalty

l Can override benefit of reduced miss rate
l Early restart and critical-word-first can help
read it first if MISS
CPU CPU Mem
send it now
if HIT

17
Cache Misses

❑ On cache hit, CPU proceeds normally

❑ On cache miss
l Stall the CPU pipeline
l Fetch block from next level of hierarchy
l Instruction cache miss
- Restart instruction fetch
l Data cache miss
- Complete data access

18
Write-Through
❑ On data-write hit, could just update the
block in cache fast
CPU Cache
l But then cache and memory would be
slow
inconsistent
Mem
❑ Write through: also update memory
❑ But makes writes take longer
l e.g., if base CPI = 1, 10% of instructions
are stores, write to memory takes 100
cycles
- Effective CPI = 1 + 10% × 100 = 11 CPU Cache
Buffer
❑ Solution: write buffer
l Holds data waiting to be written to memory
l CPU continues immediately Mem
- Only stalls on write if write buffer is already
full 19
Write-Back

hit
❑ Alternative: On data-write hit, just
update the block in cache CPU Cache

l Keep track of whether each block is block … in

mem is dirty
dirty

Mem

hit
❑ When a dirty block is replaced CPU Cache
l Write it back to memory Buffer

l Can use a write buffer to allow

replacing block to be read first
Mem

20
Write Allocation
❑ What should happen on a write miss?
❑ Alternatives for write-through
l Allocate on miss: fetch the block
l No write allocate (aka. Write around): don’t fetch the block
- Since programs often write a whole block before reading it (e.g.,
initialization)

❑ For write-back
l Usually fetch the block miss

CPU Cache

Mem

21
Example: Intrinsity FastMATH
❑ Embedded MIPS processor
l 12-stage pipeline
l Instruction and data access on each cycle

❑ Split cache: separate I-cache and D-cache

l Each 16KB: 256 blocks × 16 words/block
l D-cache: write-through or write-back

❑ SPEC2000 miss rates

l I-cache: 0.4%
l D-cache: 11.4%
l Weighted average: 3.2%

22
Example: Intrinsity FastMATH

23
Example: Asus K43SJ

❑ Notebook: Asus K43SJ

l Intel(R) Core(TM) i5-2410M CPU @ 2.30GHz

l Cache hit: Access time = 1/5.37297~ 0.18ns

l Cache miss: Access time = 1/0.07375 ~13.56ns
(75 times bigger)

24
Main Memory Supporting Caches
❑ Use DRAMs for main memory
l Fixed width (e.g., 1 word)
l Connected by fixed-width clocked bus
- Bus clock is typically slower than CPU clock

❑ Example cache block read

l 1 bus cycle for address transfer
l 15 bus cycles per DRAM access
l 1 bus cycle per data transfer

❑ For 4-word block, 1-word-wide DRAM

l Miss penalty = 1 + 4×15 + 4×1 = 65 bus cycles
l Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle
25
Increasing Memory Bandwidth

◼ 4-word wide memory

◼ Miss penalty = 1 + 1×15 + 1×1 = 17 bus cycles
◼ Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle
◼ 4-bank interleaved memory
◼ Miss penalty = 1 + 1×15 + 4×1 = 20 bus cycles
◼ Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle

26
4-word block, 1-word wide memory (a)

Address 1bc (bus cycle)

4-word block
Get Data 15bc W1
Word 1

W2 4-word block
Get Data 15bc
Word 2
4-word block
Get Data 15bc RAM
Word 3
1-
Cache word 4-word block
Get Data 15bc
wide Word 4

Data (1-word wide) 1bc

Data (1-word wide) 4-word 1bc
Data (1-word wide) block 1bc
Data (1-word wide) 1bc

27
4-word block, 4-word wide memory (b)

Address 1bc
4-word block
Get Data 15bc W W W W
Word 1,2,3,4

Data (4-word wide) 1bc

4-word
block

RAM
Cache 4-word wide

28
4-word block, 4 bank 1-word memory (c)

Address 1bc
4-word block
Get Data 15bc W W W W
Word 1,2,3,4

Data (1-word wide) 1bc

Data (1-word wide) 4-word 1bc RAM
Cache Data (1-word wide) 1bc 1-word wide
block
Data (1-word wide) 1bc

29
Advanced DRAM Organization

❑ Bitsin a DRAM are organized as a

rectangular array
l DRAM accesses an entire row
l Burst mode: supply successive words
from a row with reduced latency

❑ Double data rate (DDR) DRAM

l Transfer on rising and falling clock
edges

❑ Quad data rate (QDR) DRAM

l Separate DDR inputs and outputs
CPU

30
DRAM Generations

Year Capacity $/GB 300

1980 64Kbit $1500000

250
1983 256Kbit $500000
1985 1Mbit $200000 200
1989 4Mbit $50000 Trac
150
1992 16Mbit $15000 Tcac

1996 64Mbit $10000 100

1998 128Mbit $4000
50
2000 256Mbit $1000
2004 512Mbit $250 0
2007 1Gbit $50 '80 '83 '85 '89 '92 '96 '98 '00 '04 '07

31
Measuring Cache Performance

❑ Components of CPU time

l Program execution cycles
- Includes cache hit time
l Memory stall cycles
- Mainly from cache misses

❑ With simplifying assumptions:

Memory stall cycles

Memory accesses
=  Miss rate  Miss penalty
Program
Instructions Misses
=   Miss penalty
Program Instructions

32
Cache Performance Example
❑ Given
l I-cache miss rate = 2% Tỷ lệ miss với cache dữ liệu
Số chu kì truy cập bộ nhớ
4%
100

l D-cache miss rate = 4% Số chu kì/lệnh (hit 100%)

Tỷ lệ lệnh truy cập bộ nhớ 36%
2

Số chu kì đợi lệnh t.bình 2

l Miss penalty = 100 cycles Số chu kì đợi dữ liệu t.bình
CPI thực tế có trễ bộ nhớ
1.44
5.44

l Base CPI (ideal cache) = 2

l Load & stores are 36% of instructions
❑ Miss cycles per instruction
l I-cache: 0.02 × 100 x 1 = 2
l D-cache: 0.04 × 100 × 0.36 = 1.44
❑ Actual CPI = 2 + 2 + 1.44 = 5.44
l Ideal CPU is 5.44/2 =2.72 times faster

33
Average Access Time
❑ Hit time is also important for performance
❑ Average memory access time (AMAT)
l AMAT = Hit time + Miss rate × Miss penalty

❑ Example
l CPU with 1ns clock, hit time = 1 cycle, miss penalty = 20 cycles,
I-cache miss rate = 5%
l AMAT = (1 + 5% × 20)x1 = 2ns
- 2 cycles per instruction

34
Performance Summary
❑ When CPU performance increased
l Miss penalty becomes more significant

❑ Decreasing base CPI

l Greater proportion of time spent on memory stalls

❑ Increasing clock rate

l Memory stalls account for more CPU cycles

❑ Can’t neglect cache behavior when evaluating system

performance

35
Associative Caches
❑ Fully associative
l Allow a given block to go in any cache entry
l Requires all entries to be searched at once
l Comparator per entry (expensive)

❑ n-way set associative

l Each set contains n entries
l Block number determines which set
- (Block number) modulo (#Sets in cache)
l Search all entries in a given set at once
l n comparators (less expensive)

36
Associative Cache Example

Main memory

Block# 0 1 2 3 4 5 6 7 Set# 0 1 2 3

Data
Data Data

Tag 1 1 Tag 1
Tag
2 2 2

Search Search Search

37
Spectrum of Associativity
❑ For a cache with 8 entries

38
Associativity Example

❑ Compare 4-block caches

l Direct mapped, 2-way set associative,
fully associative
l Block access sequence: 0, 8, 0, 6, 8
❑ Direct mapped

Access Block Cache Hit/miss Cache content after access

sequence address index 0 1 2 3
1 0 0 miss Mem[0]
2 8 0 miss Mem[8]
3 0 0 miss Mem[0]
4 6 2 miss Mem[0] Mem[6]
5 8 0 miss Mem[8] Mem[6]
%4

39
Associativity Example

❑ 2-way set associative

Access Block Cache Hit/miss Cache content after access
sequence address index Set 0 Set 1
1 0 0 miss Mem[0]
2 8 0 miss Mem[0] Mem[8]
3 0 0 hit Mem[0] Mem[8]
4 6 0 miss Mem[0] Mem[6]
5 8 0 miss Mem[8] Mem[6]
%2

◼ Fully associative
Access Block Hit/miss Cache content after access
sequence address
1 0 miss Mem[0]
2 8 miss Mem[0] Mem[8]
3 0 hit Mem[0] Mem[8]
4 6 miss Mem[0] Mem[8] Mem[6]
5 8 hit Mem[0] Mem[8] Mem[6]

%1
40
How Much Associativity
❑ Increased associativity decreases miss rate
l But with diminishing returns

❑ Simulation of a system with 64KB

D-cache, 16-word blocks, SPEC2000
l 1-way: 10.3%
l 2-way: 8.6%
l 4-way: 8.3%
l 8-way: 8.1%

[di'mini∫ip] (adj) hạ bớt, giảm bớt

41
Set Associative Cache Organization

42
Replacement Policy
❑ Direct mapped: no choice
❑ Set associative prefer
l Prefer non-valid entry, if there is one
V=0 V=1
l Otherwise, choose among entries in the set

❑ Least-recently used (LRU)

l Choose the one unused for the longest time
- Simple for 2-way, manageable for 4-way, too hard beyond that

❑ Random
l Gives approximately the same performance as LRU for high
associativity

43
Multilevel Caches

❑ Primary cache attached to CPU

l Small, but fast

❑ Level-2 cache services misses from primary

cache
l Larger, slower, but still faster than main memory

❑ Main memory services L-2 cache misses

❑ Some high-end systems include L-3 cache

44
Multilevel Cache Example
❑ Given
l CPU base CPI = 1, clock rate = 4GHz
l Miss rate/instruction = 2%
l Main memory access time = 100ns

❑ With just primary cache

l Miss penalty = 100ns/0.25ns = 400 cycles
l Effective CPI = 1 + 0.02 × 400 = 9

45
Example (cont.)
❑ Now add L-2 cache
l Access time = 5ns
l Global miss rate to main memory = 0.5%

❑ Primary miss with L-2 hit (Miss L1, hit L2)

l Penalty = 5ns/0.25ns = 20 cycles

❑ Primary miss with L-2 miss (Miss L1 & L2)

l Extra penalty = 400 cycles

❑ CPI = 1 + 0.02 × 20 + 0.005 × 400 = 3.4

❑ Performance ratio = 9/3.4 = 2.6

46
Multilevel Cache Considerations
❑ Primary cache
l Focus on minimal hit time

❑ L-2 cache
l Focus on low miss rate to avoid main memory access
l Hit time has less overall impact

❑ Results
l L-1 cache usually smaller than a single cache
l L-1 block size smaller than L-2 block size

47
 Interactions with Advanced CPUs
❑ Out-of-order
CPUs can execute instructions
during cache miss
l Pending store stays in load/store unit
l Dependent instructions wait in reservation stations
- Independent instructions continue
L/S ..pending..
depend L/S L/S depend
depend
depend Independent
Independent
Reservation
depend Stations
❑ Effect of miss depends on program data flow
l Much harder to analyse
l Use system simulation

48
Interactions with Software

❑Misses depend on
memory access
patterns
l Algorithm behavior
l Compiler
optimization for
memory access

49
5.3. Virtual Memory
❑ Use main memory as a “cache” for secondary
(disk) storage
l Managed jointly by CPU hardware and the
operating system (OS)

❑ Programs share main memory Main Memory

l Each gets a private virtual address space code code

holding its frequently used code and data data data

l Protected from other programs

❑ CPU and OS translate virtual addresses to

physical addresses
l VM “block” is called a page
l VM translation “miss” is called a page fault 50
Address Translation
❑ Fixed-size pages (e.g., 4K)
Virtual Address
31 30 29 …. 15 14 13 12 11 10 …… 3 2 1 0
Virtual Page Number Page Offset

Physical Page Number Page Offset

Physical Address

51
Page Fault Penalty
❑ On page fault, the page must be fetched from disk
l Takes millions of clock cycles
l Handled by OS code

❑ Try to minimize page fault rate

l Fully associative placement
l Smart replacement algorithms

52
Page Tables
❑ Stores placement information
l Array of Page Table Entries, indexed by virtual page number
l Page table register in CPU points to page table in physical
memory

❑ If page is present in memory

l PTE stores the physical page number
l Plus other status bits (referenced, dirty, …)

❑ If page is not present

l PTE can refer to location in swap space on disk

53
Translation Using a Page Table

54
Mapping Pages to Storage

55
Replacement and Writes
❑ To reduce page fault rate, prefer least-recently used
(LRU) replacement
l Reference bit (aka use bit) in PTE set to 1 on access to page
l Periodically cleared to 0 by OS
l A page with reference bit = 0 has not been used recently

❑ Disk writes take millions of cycles

l Block at once, not individual locations
l Write through is impractical
l Use write-back
l Dirty bit in PTE set when page is written

56
Fast Translation Using a TLB

❑ Addresstranslation would appear to require

extra memory references
l One to access the PTE
l Then the actual memory access

❑ But access to page tables has good locality

l So use a fast cache of PTEs within the CPU
l Called a Translation Look-aside Buffer (TLB)
l Typical: 16–512 PTEs, 0.5–1 cycle for hit, 10–100
cycles for miss, 0.01%–1% miss rate
l Misses could be handled by hardware or software

57
Fast Translation Using a TLB

58
TLB Misses
❑ If page is in memory
l Load the PTE from memory and retry
l Could be handled in hardware
- Can get complex for more complicated page table structures
l Or in software
- Raise a special exception, with optimized handler

❑ If page is not in memory (page fault)

l OS handles fetching the page and updating the page table
l Then restart the faulting instruction

59
TLB Miss Handler
❑ TLB miss indicates
l Page present, but PTE not in TLB
l Page not present

❑ Must recognize TLB miss before destination register

overwritten
l Raise exception

❑ Handler copies PTE from memory to TLB

l Then restarts instruction
l If page not present, page fault will occur

60
Page Fault Handler
❑ Use faulting virtual address to find PTE
❑ Locate page on disk
❑ Choose page to replace
l If dirty, write to disk first (reread write back)

❑ Read page into memory and update page table

❑ Make process runnable again
l Restart from faulting instruction

61
 TLB and Cache Interaction

Virtual Memory ❑ If cache tag uses

physical address
1 l Need to translate before
2 cache lookup

3
❑ Alternative: use virtual
address tag
Physical Memory l Complications due to
aliasing
- Different virtual
addresses for shared
physical address

physical
or virtual?
62
Memory Protection
❑ Different tasks can share parts of their virtual address
spaces
l But need to protect against errant access
l Requires OS assistance

❑ Hardware support for OS protection

l Privileged supervisor mode (aka kernel mode)
l Privileged instructions
l Page tables and other state information only accessible in
supervisor mode
l System call exception (e.g., syscall in MIPS)

63
The Memory Hierarchy

The BIG Picture

❑ Common principles apply at all levels of the memory
hierarchy
l Based on notions of caching

❑ At each level in the hierarchy

l Block placement
l Finding a block where to be placed?
and replaced?
l Replacement on a miss
l Write policy where are you?

write back/through?

64
Block Placement
❑ Determined by associativity
l Direct mapped (1-way associative)
- One choice for placement
l n-way set associative
- n choices within a set
l Fully associative
- Any location

❑ Higher associativity reduces miss rate

l Increases complexity, cost, and access time

65
Finding a Block

Associativity Location method Tag comparisons

Direct mapped Index 1
n-way set Set index, then search n
associative entries within the set
Fully associative Search all entries #entries
Full lookup table 0

❑ Hardware caches
l Reduce comparisons to reduce cost

❑ Virtual memory
l Full table lookup makes full associativity feasible
l Benefit in reduced miss rate
66
Replacement
❑ Choice of entry to replace on a miss
l Least recently used (LRU)
- Complex and costly hardware for high associativity
l Random
- Close to LRU, easier to implement

❑ Virtual memory
l LRU approximation with hardware support

67
Write Policy
❑ Write-through
l Update both upper and lower levels
l Simplifies replacement, but may require write buffer

❑ Write-back
l Update upper level only
l Update lower level when block is replaced
l Need to keep more state

❑ Virtual memory
l Only write-back is feasible, given disk write latency

68
Sources of Misses

❑ Compulsory misses (aka cold start misses)

l First access to a block

❑ Capacity misses
l Due to finite cache size
l A replaced block is later accessed again

❑ Conflict misses (aka collision misses)

l In a non-fully associative cache
l Due to competition for entries in a set
l Would not occur in a fully associative cache of the same total size

69
 Cache Design Trade-offs

Design change Effect on miss rate Possible Negative

performance effect
Increase cache size Decrease capacity May increase access
misses time
Increase associativity Decrease conflict May increase access
misses time
Increase block size Decrease compulsory Increases miss
misses penalty. For very large
block size, may
increase miss rate
due to pollution.

70
5.4. Virtual Machines
❑ Host
computer emulates guest operating system
and machine resources
l Improved isolation of multiple guests
l Avoids security and reliability problems
l Aids sharing of resources

❑ Virtualization has some performance impact

l Feasible with modern high-performance computers

❑ Examples
l IBM VM/370 (1970s technology!)
l VMWare
l Microsoft Virtual PC (Hyper-V)
71
Virtual Machine Monitor
❑ Maps virtual resources to physical resources
l Memory, I/O devices, CPUs

❑ Guest code runs on native machine in user mode

l Traps to VMM on privileged instructions and access to protected
resources

❑ Guest OS may be different from host OS

❑ VMM handles real I/O devices
l Emulates generic virtual I/O devices for guest

72
Example: Timer Virtualization

❑ In native machine, on timer interrupt

l OS suspends current process, handles interrupt,
selects and resumes next process

❑ With Virtual Machine Monitor

l VMM suspends current VM, handles interrupt, selects
and resumes next VM

❑ If a VM requires timer interrupts VM1

l VMM emulates a virtual timer

l Emulates interrupt for VM when VM4 Host VM2

physical timer interrupt occurs

VM3

73
Instruction Set Support

❑ User and System modes

❑ Privileged instructions only available in system
mode
l Trap to system if executed in user mode

❑ All physical resources only accessible using

privileged instructions
l Including page tables, interrupt controls, I/O registers

❑ Renaissance of virtualization support

l Current ISAs (e.g., x86) adapting
IBM 370, June 30, 1970

74
Cache Control

❑ Example cache characteristics

l Direct-mapped, write-back, write allocate
l Block size: 4 words (16 bytes)
l Cache size: 16 KB (1024 blocks)
l 32-bit byte addresses
l Valid bit and dirty bit per block
l Blocking cache
- CPU waits until access is complete

31 10 9 4 3 0
Tag Index Offset
18 bits 10 bits 4 bits

75
Interface Signals

Read/Write Read/Write
Valid Valid
32 32
Address Address
32 Cache 128 Memory
CPU Write Data Write Data
32 128
Read Data Read Data
Ready Ready

Hit rate Miss rate Multiple cycles

Ideal CPI Miss penalty per access

76
Finite State Machines

❑ Usean FSM to
sequence control steps
❑ Setof states, transition
on each clock edge
l State values are binary
encoded
l Current state stored in a
register
l Next state
= fn (current state,
current inputs)

❑ Control output signals

= fo (current state) 77
Cache Controller FSM

Could
partition into
separate
states to
reduce clock
cycle time

78
Cache Coherence Problem

❑ Suppose two CPU cores share a physical

address space
l Write-through caches
Time Event CPU A’s CPU B’s Memory
step cache cache
0 0
1 CPU A reads X 0 0
2 CPU B reads X 0 0 0

3 CPU A writes 1 to X 1 0 1

79
Coherence Defined
❑ Informally: Reads return most recently written value
❑ Formally:
l P writes X; P reads X (no intervening writes)
 read returns written value
l P1 writes X; P2 reads X (sufficiently later)
 read returns written value
- c.f. CPU B reading X after step 3 in example
l P1 writes X, P2 writes X
 all processors see writes in the same order
- End up with the same final value for X

80
Cache Coherence Protocols
❑ Operations performed by caches in multiprocessors to
ensure coherence
l Migration of data to local caches
- Reduces bandwidth for shared memory
l Replication of read-shared data
- Reduces contention for access

❑ Snooping protocols
l Each cache monitors bus reads/writes

❑ Directory-based protocols
l Caches and memory record sharing status of blocks in a
directory

81
Invalidating Snooping Protocols
❑ Cache gets exclusive access to a block when it is to be
written
l Broadcasts an invalidate message on the bus
l Subsequent read in another cache misses
- Owning cache supplies updated value

CPU activity Bus activity CPU A’s CPU B’s Memory

cache cache
0
CPU A reads X Cache miss for X 0 0
CPU B reads X Cache miss for X 0 0 0
CPU A writes 1 to X Invalidate for X 1 0
CPU B read X Cache miss for X 1 1 1

82
Memory Consistency

❑ When are writes seen by other processors

l “Seen” means a read returns the written value
l Can’t be instantaneously

❑ Assumptions
l A write completes only when all processors have
seen it
l A processor does not reorder writes with other
accesses

❑ Consequence
l P writes X then writes Y
 all processors that see new Y also see new X
l Processors can reorder reads, but not writes
83
Multilevel On-Chip Caches

Intel Nehalem 4-core processor

Per core: 32KB L1 I-cache, 32KB L1 D-cache, 512KB L2 cache

84
2-Level TLB Organization

Intel Nehalem AMD Opteron X4

Virtual addr 48 bits 48 bits
Physical addr 44 bits 48 bits
Page size 4KB, 2/4MB 4KB, 2/4MB
L1 TLB L1 I-TLB: 128 entries for small L1 I-TLB: 48 entries
(per core) pages, 7 per thread (2×) for L1 D-TLB: 48 entries
large pages Both fully associative, LRU
L1 D-TLB: 64 entries for small replacement
pages, 32 for large pages
Both 4-way, LRU replacement
L2 TLB Single L2 TLB: 512 entries L2 I-TLB: 512 entries
(per core) 4-way, LRU replacement L2 D-TLB: 512 entries
Both 4-way, round-robin LRU
TLB misses Handled in hardware Handled in hardware

85
3-Level Cache Organization

Intel Nehalem AMD Opteron X4

L1 caches L1 I-cache: 32KB, 64-byte L1 I-cache: 32KB, 64-byte
(per core) blocks, 4-way, approx LRU blocks, 2-way, LRU
replacement, hit time n/a replacement, hit time 3 cycles
L1 D-cache: 32KB, 64-byte L1 D-cache: 32KB, 64-byte
blocks, 8-way, approx LRU blocks, 2-way, LRU
replacement, write- replacement, write-
back/allocate, hit time n/a back/allocate, hit time 9 cycles
L2 unified 256KB, 64-byte blocks, 8-way, 512KB, 64-byte blocks, 16-way,
cache approx LRU replacement, write- approx LRU replacement, write-
(per core) back/allocate, hit time n/a back/allocate, hit time n/a
L3 unified 8MB, 64-byte blocks, 16-way, 2MB, 64-byte blocks, 32-way,
cache replacement n/a, write- replace block shared by fewest
(shared) back/allocate, hit time n/a cores, write-back/allocate, hit
time 32 cycles
n/a: data not available

86
Miss Penalty Reduction
❑ Return requested word first
l Then back-fill rest of block

❑ Non-blocking miss processing

l Hit under miss: allow hits to proceed
l Mis under miss: allow multiple outstanding misses

❑ Hardware prefetch: instructions and data

❑ Opteron X4: bank interleaved L1 D-cache
l Two concurrent accesses per cycle

87
Pitfalls
❑ Byte vs. word addressing
l Example: 32-byte direct-mapped cache,
4-byte blocks
- Byte 36 maps to block 1
- Word 36 maps to block 4

❑ Ignoring memory system effects when writing or

generating code
l Example: iterating over rows vs. columns of arrays
l Large strides result in poor locality

88
Pitfalls
❑ In multiprocessor with shared L2 or L3 cache
l Less associativity than cores results in conflict misses
l More cores  need to increase associativity

❑ Using AMAT to evaluate performance of out-of-order

processors
l Ignores effect of non-blocked accesses
l Instead, evaluate performance by simulation

89
Pitfalls
❑ Extending address range using segments
l E.g., Intel 80286
l But a segment is not always big enough
l Makes address arithmetic complicated

❑ Implementing a VMM on an ISA not designed for

virtualization
l E.g., non-privileged instructions accessing hardware resources
l Either extend ISA, or require guest OS not to use problematic
instructions

90
Concluding Remarks

❑ Fast memories are small, large memories are

slow
l We really want fast, large memories 
l Caching gives this illusion ☺

❑ Principle of locality
l Programs use a small part of their memory space
frequently

❑ Memory hierarchy
l L1 cache  L2 cache  …  DRAM memory
 disk

❑ Memory system design is critical for

multiprocessors 91