UNIT V

Memory & Programmable Logic Devices: Digital Logic Families: DTL, DCTL, TTL, ECL & CMOS
etc., Fan Out, Fan in, Noise Margin; RAM, ROM, PLA, PAL; Circuits of Logic Families, Interfacing of
Digital Logic Families, Circuit Implementation using ROM, PLA and PAL; CPLD and FPGA.

The basic building blocks of logic circuits are logic gates. And logic gates themselves are
simple electronic circuits comprising of diodes, transistors and resistors.
The characteristics which are bound to be identical and used to compare performance are:
1. Supply voltage range 4. Input and output logic levels 7. Flexibility
2. Speed of response 5. Current sinking capability 8. Noise immunity
3. Dissipation of power 6. Current sourcing capability 9. Fan-out
Propagation Delay: - Time required for a pulse to propagate from input to output.
Fan in: - no: of inputs that the gate is designed to handle
Fan out: - no; of std. loads that the output of a gate can drive without impairing its normal
operation.
Noise margin: - Noise immunity is the ability of a circuit to tolerate noise voltages at its inputs.
Quantitative measure of noise immunity is Noise margin.
Or
The maximum noise voltage that can be tolerated by a circuit is termed its noise immunity
Speed Power Product: - for measuring the overall performance of an IC family. (Propagation
delay * gate power dissipation)(Figure of merit of an IC family)
Integration Levels:
SSI: Small scale integration 12 gates/chip
MSI: Medium scale integration 100 gates/chip
LSI: Large scale integration 1K gates/chip
VLSI: Very large scale integration 10K gates/chip
ULSI: Ultra large scale integration 100K gates/chip
TYPES OF LOGIC FAMILY
There are two kinds of semiconductor devices. The logic family which falls under the first
kind Bipolar logic family and the other is Unipolar logic family.
BIPOLAR LOGIC FAMILY
It mainly uses bipolar devices like diodes, transistors in addition to passive elements like
resistors and capacitors. There are two kinds of operations in bipolar integrated circuits:
 (a) Saturated Bipolar Logic family and
(b) Non-saturated Bipolar Logic family.

(a) Saturated Bipolar Logic Families: In this family the transistors used in ICs are driven into
saturation. These are
1. Diode logic (DL) 5. Transistor Transistor Logic (TTL)
2. Resistor Transistor Logic (RTL) 6. Direct Coupled Transistor Logic (DCTL)
3. Diode Transistor Logic (DTL) 7. High Threshold Logic(HTL)
4. Integrated Injection Logic (IIL or I2L)
(b) Non-saturated Bipolar Logic Families: In this family the transistors used in IC is not driven
into saturation. These are
1. Schottky TTL
2. Emitter Coupled Logic (ECL)
UNIPOLAR LOGIC FAMILY
Unipolar logic family consists of Metal Oxide Semiconductor (MOS) logic families. It mainly
uses unipolar devices like MOSFETs in addition to passive elements like resistors and capacitors.
These logic families have the advantages of high speed and lower power consumption than bipolar
families. These are classified as:
1. P-type MOS (PMOS) Logic 4. Bipolar MOS (BiMOS) logic
2. N-type MOS (NMOS) logic 5. Bipolar CMOS (BiCMOS) logic
3. Complementary MOS (CMOS) logic
DIODE LOGIC GATES
Diode logic is implemented by diodes which exhibit low impedance when forward biased
and a very high impedance when reverse biased. There are two kinds of diode logic gates - OR
and AND. It is not possible to construct NOT (invert) diode gates because the invert function
requires an active component such as a transistor.
OR logic gate

All diodes have inputs on their anodes and their cathodes are connected together to drive the
output. R is connected from the output to some negative voltage (-6 volts) to provide bias current
for the diodes.
AND logic gate

The diode AND is basically the same as the OR except it is turned upside down. The diodes
are reversed so that the cathodes are connected to the inputs and the anodes are connected together
to provide the output. R is connected to +12 volts to provide the forward bias current for the diodes
and current for output drive.
RTL AND DTL CIRCUITS
RTL Basic Gate
Each input is associated with one resistor and one transistor. The collectors of the transistors
are tied together at the output.
The voltage levels for the circuit are 0.2 V for the low level and from 1 to 3.6 V for the high
level. The working of npn transistor is as follows:
(1) Input = High, Transistor goes into saturation region (ON switch).
(2) Input = Low, Transistor goes into cutoff region (OFF switch).
The RTL basic NOR gate is shown in figure below:

Basic RTL NOR Gate

Note:
• The noise margin for low signal input is 0.6 - 0.2 = 0.4 V.
• The power dissipation of the RTL gate is about 12 mW and the propagation delay averages
25 ns.
DTL Basic Gates
The basic circuit in the DTL digital logic family is the NAND gate shown in figure below.
 The two voltage levels are 0.2 V for the low level and between 4 and 5 V for the high level.
The voltage at point P is equal to the input voltage of 0.2 V plus a diode drop of 0.7 V, for a total
of 0.9 V. In order for the transistor to start conducting, the voltage at point P must overcome a 1-
VBE drop in Q1 plus two diode drops across D1 and D2, or 3 X 0.6 = 1.8 V. Since the voltage at P
is maintained at 0.9 V by the input conducting diode, the transistor is cut off with no drop across
the 2-kO resistor and the output voltage is high at 5 V.
If all inputs of the gate are high, the transistor is driven into the saturation region. The voltage
at P now is equal to VBE plus the two diode drops across D1 and D2, or 0.7 X 3 = 2.1 V. Since all
inputs are high at 5 V and since Vp = 2.1 V, the input diodes are reverse biased and off. With the
transistor saturated, the output drops to Va = 0.2 V, which is the low level for the gate
The fan-out of a DTL gate may be increased by replacing one of the diodes in the base circuit
with a transistor, as shown in figure shown below

Modified DTL gate

Direct-Coupled Transistor Logic
Direct-coupled transistor logic (DCTL) is similar to resistor–transistor logic (RTL) but the
input transistor bases are connected directly to the collector outputs without any base resistors.
 DCTL gates have fewer components, are more economical, and are simpler to fabricate onto
integrated circuits than RTL gates. Unfortunately, DCTL has much smaller signal levels, has more
susceptibility to ground noise, and requires matched transistor characteristics.
Emitter-Coupled Logic (ECL)
The logic diagram of ECL is shown in figure below:

Basic ECL gate

• ECL is a non-saturated digital logic family. Since transistors do not saturate.
• It is possible to achieve propagation delays as low as 1-2 ns.
• This logic family has the lowest propagation delay of any family and is used mostly in
systems requiring very high speed operation.
• Its noise immunity and power dissipation, however, are the worst of all the logic families
available
• The outputs provide both the OR and NOR functions.
• The two voltage levels are about -0.8 V for the high state and about -1.8 V for the low state.
Integrated Injection Logic
Integrated injection logic (IIL, I2L, o I2L) is a class of digital circuits built with multiple
collector bipolar junction transistors (BJT). When introduced it had speed comparable to TTL yet
was almost as low power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits.
• I2L has high noise immunity because it operates by current instead of voltage.
• The basic IIL gate, when connected to other gates perform NOR logic function.
Metal -Oxide Semiconductor
The n-channel gates usually employ positive logic. The p-channel MOS circuit uses a
negative voltage for VDD to allow positive current flow from source to drain.
AND operation is implemented by the series connections of the n-MOS whereas OR is
implemented by the parallel connections.
The output is complemented of the input combination.
The active load a gate to drain connected MOS is used in place of resistive load.
Basic MOS gates of NOT, NAND and OR are shown in the figures given below:

Complementary MOS
Complementary MOS (CMOS) circuits take advantage of the fact that both n-channel and
p-channel devices can be fabricated on the same substrate.
To understand the operation of the inverter, we must review the behavior of the MOS transistor
from the previous section:
1. The n-channel MOS conducts when its gate-to-source voltage is positive.
2. The p-channel MOS conducts when its gale-to-source voltage is negative.
3. Either type of device is turned off if its gate-to-source voltage is zero.
Implementation of the logic gates using CMOS:
1. Implement the AND or OR combination of the Boolean expression with n-channel.
2. Make the opposite configuration of n-channel with p-channel MOS (change AND into OR
and vice versa).
3. Connect both the configuration.
4. The output will be complement of the configuration.
Basic NOT, NAND and NOR gates implementation by CMOS is shown in the figure given below:

Transistor-Transistor Logic (TTL)

The original basic transistor- transistor logic (TIL) gate was a slight improvement over the
DTL gate.
Commercial TIL ICs have a number designation that starts with 74 and follows with a suffix
that identifies the series. Examples are 7404, 74S86 and 74ALS161.
TTL gates in all the available series come in three different types of output configuration:
(1) Open -collector output
(2) Totem-pole output
(3) Three-state output
Open-Collector Output Gate
• The multiple emitters in transistor Q1 are connected to the inputs.
 • The two voltage levels of the TTL gate are 0.2 V for the low level and from 2.4 to 5 V for
the high level.
• The basic circuit is a NAND gate.
If any input is low, the corresponding base-emitter junction in Q1 is forward biased. The
voltage at the base of Q1 is equal to the input voltage of 0.2 V plus a VBE drop of 0.7. or 0.9 V. In
order for Q3 to start conducting, the path from Q1 to Q3 must overcome a potential of one diode
drop in the base-collector pn junction of Q1 and two VBE drops in Q2 and Q3, or 3 x 0.6 = 1.8 V.
Since the base of QI is maintained at 0.9 V by the input signal, the output transistor cannot conduct
and is cut off. The output level will be high if an external resistor is connected between the output
and VCC (or an open circuit if a resistor is not used)

Open-collector TTL NAND gate

Totem-Pole Output
For a typical operating value of C = 15 pF and RL = 4 kΩ, the propagation delay of a TTL
open-collector gate during the turnoff time is 35 ns. With an active pull-up circuit replacing the
passive pull-up resistor RL, the propagation delay is reduced to 10 ns. This configuration shown in
figure below is called a totem-pole output because transistor Q4 sits upon Q3.
The TTL gate with the totem-pole output is the same as the open-collector gate, except for the
output transistor Q4 and the diode D1.
 TTL gate with totem-pole output
Schottky TTL Gate
A reduction in storage time results in a reduction in propagation delay. This is because the time
needed for a transistor to come out of saturation delays the switching of the transistor from the on
condition to off condition.
Saturation can be eliminated by placing a Schottky diode between the base and collector of
each saturated transistor in the circuit.
The voltage across a conducting Schottky diode is only 0.4 V, compared with 0.7 V in a
conventional diode. The presence of a Schottky diode between the base and collector prevents the
transistor from going into saturation. The resulting transistor is called a Schottky transistor.

Schottky TTL gate

S. Parameters DTL RTL HTL TTL ECL IIL MOS CMOS
No.
1 Basic Gates NAND NOR NAND NAND OR, NOR NAND NOR
NOR or
NAND
2 Fan in 8 5 5 10
3 Fan out 8 5 10 10 24 8 20 >50
(minimum)
4 Noise Good Medium Excellent 0.4 0.25 0.35 1.5 5
margin (V)
5 Propagation 30 12 90 9 1 1 50 < 50
delay time
(nsec)
6 Power 8-12 12 55 10 50 0.1 0.1 0.01
dissipation
/gate (mW)
7 Clock rate 12-30 8 4 15-60 60- -- 2 5
400
8 Number of Fairy High Medium Very High Low Low
functions high high
9 Cost Low High Very Low Low
low
Memory and Programmable Logic
A memory unit stores binary information in groups of bits called words.
1 byte = 8 bits
1 word = 2 bytes
2 The communication between a memory and its environment is achieved through data input and
output lines, address selection lines, and control lines that specify the direction of transfer.

Content of a memory
Each word in memory is assigned an identification number, called an address, starting from 0 up
to 2k-1, where k is the number of address lines.
The number of words in a memory with one of the letters K=210, M=220, or G=230.
64K = 216 ; 2M = 221; 4G = 232
Types of memories:
In random-access memory, the word locations may be thought of as being separated in space,
with each word occupying one particular location.
In sequential-access memory, the information stored in some medium is not immediately
accessible, but is available only certain intervals of time. A magnetic disk or tape unit is of this
type.
There are two basic types of RAM:
1. Dynamic Ram
2. Static RAM
Dynamic RAM: loses its stored information in a very short time (for millisecond.) even when
power supply is on. D-RAM’s are cheaper.
READ ONLY MEMORY
It’s non-volatile memory, i.e., the information stored in it, is not lost even if the power supply
goes off. It’s used for the permanent storage of information. It also possess random access property.
Information cannot be written into a ROM by the users/programmers. In other words the contents
of ROMs are decided by the manufactures.
A ROM is essentially a memory device in which permanent binary information is stored. Once
the pattern is established it stays within the unit even when power is turned off and on again.
A block diagram of ROM is shown in the figure below. ROM is characterized by the number
of words 2n and number of bits/word n.
The number of words in a ROM is determined from the fact that k address input lines are
needed to specify 2k words.

Consider for example a 32 x 8 ROM. The unit consists of 32 words of 8 bits each. There are
five input lines that form the binary numbers from 0 through 31 for the address. The Figure shows
the internal logic construction of the ROM.

The five inputs are decoded into 32 distinct outputs by means of a 5 x 32 decoder. Each output
of the decoder represents a memory address. The 32 outputs of the decoder are connected to each
of the eight OR gates.
Types of ROMs:
The following types of ROMs are listed below:
(i) PROM: It’s programmable ROM. Its contents are decided by the user. The user can
store permanent programs, data etc. in a PROM. The data is fed into it using a PROM
programs.
 (ii) EPROM: An EPROM is an erasable PROM. The stored data in EPROM’s can be
erased by exposing it to UV light for about 20 min. It’s not easy to erase it because the
EPROM IC has to be removed from the computer and exposed to UV light. The entire
data is erased and not selected portions by the user. EPROM’s are cheap and reliable.
(iii) EEPROM (Electrically Erasable PROM): The chip can be erased & reprogrammed on
the board easily byte by byte. It can be erased within a few milliseconds. There is a
limit on the number of times the EEPROM’s can be reprogrammed, i.e.; usually around
10,000 times.
(iv) CPLD: A combinational PLD is an integrated circuit with programmable gates divided
into an AND array and an OR array to provide an AND-OR sum of product
implementation.
(a) PROM: fixed AND array constructed as a decoder and programmable OR array.
(b) PAL: programmable AND array and fixed OR array.
(c) PLA: both the AND and OR arrays can be programmed.
COMBINATIONAL PLDs
The PROM is a combinational programmable logic device (PLD). A combinational PLD is an
integrated circuit with programmable gates divided into an AND array and an OR array to provide
an AND-OR sum of product implementation. There are three major types of combinational PLDs
and they differ in the placement of the programmable connections in the AND-OR array. The
Figure 3 shows the configuration of three PLDs.

Basic configuration of PLD

Programmable Logic Array (PLA)
The PLA is similar to PROM in concept except that PLA does not provide full decoding of the
variable and does not generate all the minterms. The decoder is replaced by an array of AND gates
that can be programmed to generate any product term of the input variables. The product terms are
then connected to OR gates to provide the sum of products for the required Boolean functions
nxk m links
links
k product m sum
terms terms
n input (AND) kxm (OR) m
nxk links outputs
links

• PLA consists of n inputs, m outputs, k product terms and m sum terms.

• The number of program links is 2n x k + k x m + m.
• The size of PLA is specified by the number of inputs, the number of product terms and the
number of outputs
Programmable Array Logic (PAL)
The programmable array logic (PAL) is a programmable logic device with a fixed OR array and a
programmable AND array. Because only the AND gates are programmable the PAL is easier to
program, but is not as flexible as the PLA.

PAL with Four Inputs, Four Outputs and Three Wide AND-OR Structure