Bidirectional DC-DC Converter Modeling and Unified Controller with Digital Implementation

Junhong Zhang, Jih-Sheng Lai and Wensong Yu

Virginia Polytechnic Institute and State University Future Energy Electronics Center Blacksburg, VA 24061-0111, USA jhzhang@vt.edu, laijs@vt.edu and wensong@vt.edu

Abstract In this paper, a unified current controller is introduced for a bidirectional dc-dc converter which employs complementary switching between upper and lower switches. The unified current controller is to use one controller for both buck and boost modes. Such a controller may be designed with analog implementation that adopts current injection control method, which is difficult to be implemented in high power applications due to parasitic noises. The averaged current mode is thus proposed in this paper to avoid the current sensing related issues. Additional advantage with the unified digital controller is also found in smooth mode transition between battery charging and discharging modes where conventional analog controller tends to saturate and take a long delay to get out of saturation. The unified controller has been designed based on a proposed novel thirdorder bidirectional charging/discharging model and implemented with a TMS320F2808 based digital controller. The complete system has been simulated and verified with a high-power hardware prototype testing. Index Terms Bidirectional dc-dc converter, high-power density, digital controller, converter modeling and control

I.

INTRODUCTION

The high power bidirectional dc-dc power converter has been widely used in hybrid electric vehicle and fuel cell applications [1-8]. To increase its power density, the design can adopt small inductor with multiphase interleaving to operate in discontinuous conduction mode (DCM) while reducing the ripples [9]. The problem with DCM operation is the related parasitic ringing caused by the inductor and the device output capacitance during current turn-off condition [9], resulting poor efficiency and significant EMI noises. A gate signal complementary control scheme was thus introduced to allow the inductor current continuously flow through the opposite direction such that the parasitic ringing is avoided, and the zero voltage soft switching (ZVS) is achieved [10] [12]. This complementary switching scheme is also defined as synchronous conduction mode and is adopted here for a high-power bidirectional charger application. There are two operating modes for a bidirectional converter: (1) buck charging mode and (2) boost discharging mode. In order to share the current between the modules and to improve the dynamic performance, a bus voltage regulator with peak current injection control (CIC) was proposed in [3] for both charging and discharging modes. In high power applications, the CIC control which requires current sensors for individual phase switches will introduce parasitic inductance and pose

significant noise problem. The cost for sensors is another concern. A unified controller was proposed in [13] to use analog controller and digital power management to control bus voltage and charging current. One of the main switches takes care of both charging and discharging. This analog implementation relies on the competition of three error amplifiers, which tend to have difficulties in mode transition, because the error amplifier of the preferred mode is saturated during the transition [14]. The analog implementation is also difficult to synchronize multiple phases. Digital controller is preferred to generate multiphase interleaved gate signals. It has good noise immunization, which is important in high power application. Digital controller can be easily set to reduce or avoid the delay out of the saturation in the transition. With accurate digital control and relatively high parasitic resistance in high power application, current in each phase can be easily balanced. In this paper, a power stage averaged model is established based on the gate signal complementary control scheme. A unified digital controller, which essentially has the advantage of smooth mode transition capability due to the adoption of one main switch control and one common controller, both for battery charging and discharging thus is designed and implemented. A series experiments are conducted to verify this concept. II. UNIFIED CONTROLLER FOR BUCK AND BOOST CONVERTER A. Circuit Topology Fig. 1 shows the circuit diagram of a multiphase softswitching bidirectional dc-dc converter, which is adopted for the controller implementation. A battery pack or other energy source such as ultra-capacitor is placed on the low-voltage side, and a primary energy source such as fuel cell or generator-set is placed on the high-voltage dc bus, which also contains a high-frequency capacitor as the energy buffer. The highvoltage dc bus VH also serves as the main power bus that provides power output to the main load. The bidirectional dcdc converter is placed in between low-voltage and high-voltage sources to allow energy transfer. B. Gate Signal Complementary Control for ZVRT Soft Switching Fig. 2 shows the complementary gating control for one phase-leg operation. Fig.2 (a) is the circuit diagram and Fig.2 (b) is the control scheme. The inductor current, rather than

978-1-4244-1874-9/08/$25.00 2008 IEEE

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operating in a traditional DCM condition, goes from positive to negative direction and then swings back to positive. Using the upper switch Q1 as the main switch for buck mode operation, lower switch Q2 becomes the auxiliary switch.
+ Q1 Q3 Q5 Q7 L1 R1 v1 VH CH Q2 Q4 Q6 Q8 L2 L3 L4 CL VL R2 v2 iL +

inductor current iL will increase until it passes through zero and changes into positive direction, and the main switch Q1 naturally takes over the positive current. The main switch Q1 is turned on at zero-voltage condition. The benefits of complementary control ZVRT is less heat sinking requirement and reduction of the inductor size [12]. C. Unified Controller Concept In order to simplify the controller and at the same time stabilize the system during the mode transition, a unified controller is proposed. A current mode controller is cited as an example. Fig. 3 (a) shows that traditional way of two separate controllers: buck and boost controllers. The switch between the two different modes is manipulated by a power management command. With complementary switching, these two controllers can be merged into one, as shown in Fig. 3(b). Instead of individual controllers for each mode shown in Fig. 4(a), a unified controller can be realized. Different current flow directions represent different modes. The control signal in Fig. 4(b) shows that if the buck mode charging current is set to be positive, boost mode discharging current is negative. In this way, the charging and discharging is controlled only by reference current iL* setting in positive and negative values, respectively.
Q1 + R1 v1 VH CH Q2 RLP iL2 L iL1 R2 CL VL v2 +

Fig.1. Circuit diagram of zero-voltage switching four phases interleaved bidirectional dc-dc

Gate1

Gate2

(a) Circuit diagram of bidirectional dc-dc single phase

td1 ton td2 Gate1 Gate2 iL Ipeak IO 0 D1 Q1 D2

td1 ton td2

Buck Controller iL1*

Mode Switch Logic

Boost Controller iL2*

Power Management

Q2 D1 Q1

D2

Q2
+ R1 v1 VH

(a) Separate controllers controlled power stage

Q1

RLP

iL L + R2 CL VL v2

(b) Gate signal complementary control Fig.2. System control scheme

During the dead time period td1 as shown in Fig.2(b), a negative current formerly created by the auxiliary switch Q2 helps charge MOSFET Q2 output capacitance C2, and discharge MOSFET Q1 output capacitance C1. After C1 is fully discharged, the voltage across the main switch VQ1 becomes zero. MOSFET body diode D1 will carry the inductor negative current. After MOSFET Q1 turns on, it will conduct the current in reverse direction and go into synchronous rectification mode. The voltage difference between dc bus voltage VH and battery voltage VL will apply across the inductor L and the

CH

Q2

Charging and discharging Controller

Power iL* Management

(b) Unified controller controlled power stage Fig.3. Separate controller and unified controller

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On Stage

IL1

Charging IL2

Discharging

IL

Charging

Rdson

RLP

iL L + R2 CL VL

+ R1 CH VH

iL1

iL2

0 Discharging

iL*

v1

v2

(a) Separate controllers (b) Unified controller Fig.4. Separate controller and unified controller

(a) First subinterval

III. SYSTEM MODELING State-space averaging method is employed for the modeling of the bidirectional dc-dc converter with the following assumptions. 1. Current is relatively balanced among different phases. Thus simplified single phase is used for modeling. 2. Neglect dead time effect, since dead-time td is less than ten percent of switching period Tsw. 3. MOSFET turn-on resistance Rdson in both conduction directions is same. 4. The soft-switching period is neglected. The simplified multiphase bidirectional dc-dc converter is shown in Fig. 5. The two power sources imitate bus voltage side with high side voltage VH and the battery side with low side voltage VL. R1 is the internal resistance of the high side voltage source. R2 is the internal resistance of the low side battery. There are three energy storage components: input capacitor CH, output capacitor CL and inductor L. For phase number n, the equivalent inductance L is each phase inductance L1 divided by n. The upper switch Q1 is the control switch. Inductor parasitic resistance RlP and MOSFET turn-on resistance Rdson are also included in the model. From the above discussion, it can be seen that no matter which operating mode there are only two subintervals. In the first subinterval, when the switch Q1 is on, and the Q2 is off, the converter equivalent circuit is as shown in Fig. 6(a). In the second subinterval, when the switch Q1 is off, and Q2 is on, the converter equivalent circuit is as shown in Fig. 6(b).
Q1 + R1 v1 VH CH Q2 CL VL RLP iL L R2 v2 +

Off Stage + R1 v1 VH

RLP

iL L R2 + CL VL

CH

Rdson

v2

(b) Second subinterval Fig.6. Bidirectional converter circuit with two subintervals

The state-space averaged dc model is shown in (1).

IL V 0 = A V1 + B L VH V2

where
RP L D A= CH

0 1 R2 CL

1 CL

and Rp=RlP+Rdson. Solving (1), we can get expressions (2)-(4).

IL = D VH VL R1 D 2 + R2 + RP

V1 =

VH ( R2 + RP ) + D R1 VL R1 D 2 + R2 + RP

V2 =

D (VH R2 + D R1 VL ) + RP VL R1 D 2 + R2 + RP

Fig.5. Simplified bidirectional dc-dc converter

where

C = 1 CH 0

0 0

0 0

Solving (5), the following (6)-(8) are obtained.

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1L

The state-space averaged ac model is shown in (5). iL iL IL d v1 = A v1 + C V1 d dt v2 v2 V2

D L 1 R1 CH

1 L

0 0 1 R2 CL

0 1 R1 CH 0

B=

(2) (3) (4)

(5)

(1)

 v1 = d

1 D iL IL CH d CH 1 s+ CH R1

(6)

v2 = d

IL

Charging

The buck and boost test conditions are shown in Table 2 and Table 3 respectively. Their test conditions include input voltage V1, inductor reference current IL*, output voltage V2, resistor load R1 or R2 and output Po. It is noticed that a positive current setting is offered for charging mode and negative current setting is offered for discharging mode.
TABLE 2 BUCK TEST CONDITIONS

DO

1 D
No. VH=V1 VL (V) (V) 1 250 0 2 250 0

Fig.7. Duty cycle D versus inductor averaged current IL

Do = VL / VH

(9)
No. 3 4 VH (V) 0 0

TABLE 3 BOOST TEST CONDITIONS

IL =

(10) (11)

Gid =

iL VH = L s + R p + R2 d

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D VH VL RP + R2

B. Filter Design RC(s) and BF(s) Design Considerations The entire controller is implemented with DSP TI2808 code, so half of PWM switching cycle delay e(-0.5 Tsw s) is included. Here Tsw means 50 s switching period. The inductor current iL has relatively large ripple, even though interleaving technique help eliminate it. A 2nd order hardware RC filter and software Butterworth filter BF are needed to get an averaged current with smaller ripple. Since the switching ripple at 20 kHz is unavoidable, a relatively high

When the low-side voltage VL is zero, and R2 is treated as a resistive load, the model derived in (8) becomes a standard second-order buck converter model. When the high-side voltage VH is zero, and R1 is treated as a resistive load, the above equation becomes a standard second-order boost converter model. For a two-voltage sources system, where CH, CL, R1 and R2 are neglected, equation (8) can be simplified into (10) and (11), which are a first order system.

VL=V2 (V) 60 60

V1 (V) 114 81

IL* (A) -12 -12

R2 ( ) 0 0

R1 ( ) 18 9

Discharging

V2 (V) 150 75

IL* (A) 50 50

R2 ( ) 3 1.5

R1 ( ) 0 0

Po (kW) 7.5 3.75

Po (W) 720 720

Equation (8) shows that this is a third order system, since there are three energy storage components. With this ac model, the relationships between high side bus voltage v1, low side battery voltage v2, inductor current iL and duty cycle d are obtained. Since the buck charging and boost discharging current modes share the same power plant transfer function, they can share a unified controller. The defined inductor averaged current iL reference flow direction is the same as the battery charging power flow direction. In Fig.7, it can be found that the current flow direction of IL only depends on the relationship between control duty cycle D and zero current duty cycle Do, which is defined in (9). To charge the battery, inductor averaged current IL should be greater than 0. According to (2), correspondingly duty cycle D should be adjusted to be greater than Do.

A. Design and Test Conditions In order to verify the unified controller concept and the modeling results, we design an average current model controller and made a preliminary test with this controller. The design conditions are shown in Table 1.
TABLE 1 TEST CONDITIONS n L ( H) 25/4 CH (mF) 7.2 CL (mF) 7.2 fsw (Hz) 20k Rdson (m ) 35 RlP (m ) 36

Where a = CL R2 , b = C H R1 , c = D I L R1 .

IV. CONTROLLER DESIGN AND IMPLEMENTATION

Gid =

iL (a s + 1)[(b s + 1) V1 c] (8) = d ( Ls + R p )(a s + 1)(b s + 1) + D 2 R1 (a s + 1) + R2 (bs + 1)

1 CL i L 1 d s+ C L R2

(7)

Equation (11) shows that inductor steady-state averaged current IL is affected only by system parameters RP, R2, VH, VL and the control variable D. In real application, RP and R2 are very small, so IL will be very sensitive to the control signal D. From (10), it is noticed that control to inductor current transfer function Gid is not only related with VH and battery internal resistance R2, but also with system parasitic resistance RP. In high power application, RP is not negligible. For example, inductor parasitic resistance RlP is as high as 36m and MOSFET APTM50AM17F turn-on resistance Rdson is as high as 35m at high temperature condition. For four phases, the RP is 18m (=(35+36)m /4). This value is comparable with the battery resistance R2, which varies from several to several m . Neglecting RP will affect controller stability.

sampling frequency is necessary. Here a 200 kHz sampling frequency is applied. Their transfer functions are shown in (12) and (13).
RC ( s ) = 1+

s=
Ci ( z ) =

2 z 1 Tsa z + 1

(15) (16)

s 2 f RC

(12)

a2 z 2 a1 z 1 + 1

b2 z 2 + b1 z 1 + b0

BF ( s ) =

1 s s 1 + 1.414 )2 +( 2 f BC 2 f BC

(13)

With the switching frequency of 20 kHz, the filter cutoff frequency is set as fRC = 5.3 kHz, fBC = 8 kHz. C. Controller Ci(s) Structure The controller has two poles and two zeroes compensator shown in (14).
Ci ( s ) = C0 (1 + s

Where b0 = 0.0000656, b1 = 0.0001104, b2 = 0.0000464, a1 = 1.9906194, a2 = 0.9906194. With the same procedure, the filter BF(s) in (13) is discretized into BF(z). Control block diagram is shown in Fig. 9. Gain Hi is the multiplication of Hall sensor current conversion ratio and the conditioning circuit gain.
iL* + if Ci(z) d

e-0.5T

sw

*s

Gid(s)

z1

) (1 + s

Ti(s)
BF(z) RC Filter Gain Hi

z2

(14)

DSP

s (1 +

p1

)
Fig.9. Control block diagram

where z1=400 2 , z2=700 2 , p1=30 2 , C0=3.276. One pole is integrator, and the other pole is to cancel the plant zero. Two zeros help increase the phase margin. The Bode plots of four cases power plant Gid(s) and the designed loop gain Ti(s) are shown in Fig. 8.
150 100 0 -50 90 Gid(s) 45 0 -45 Ti(s) -90 -135 -180 1 fc=300Hz Phase (degree) case1 case2 case3 case4 PM=60degree 10 100 1000 10000 Magnitude (dB) Gid(s) Ti(s) case1 case2 case3 case4 GM=15dB

z = exp( j Tsa )

Ci(z)

Ci(s) Ci(s)

Ci(z)

Fig.8. Bode plot for bidirectional converter

Buck and boost averaged current modes share the same transfer functions. The controller design can be based on the worst case (case 3 in the plot). In this case, the crossover frequency is 300 Hz, phase margin is 20 dB and gain margin is 60 degree. D. Controller Ci(s) and Filter BF(s) Discretization Replacing s in (14) with Tustin bilinear transformation (15) and sampling time Tsa of 50 s, a discretized model (16) is derived.

Fig.10. Controller quantization effect

F. Software Programming The program flow chart is shown in Fig. 11. The main program is to calculate the controller output upper switch duty cycle with the past and present input current error signal and output information. The interrupt routine is to respond to the AD sampling and BF filter process. It takes half of switching

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E. Quantization Effect Normally, for a certain word length digital controller, a quantization effect, which can move the pole and zero positions, needs to be considered. To check the resolution of the quantized coefficients, (17) is substituted for z in (16) and coefficients are replaced by its corresponding quantized value, therefore z domain frequency response is mapped to domain. This transfer function is compared with the transfer function in (14). Fig.10 shows the comparison result. The two curves agree with each other, which mean the quantized coefficient has enough resolution to provide expected frequency response. (17)

period from the sampling point to the final execution of output PWM signal.
Main
Main routine Interrupt Routine ADC Sampling Filter out unexpected value
N

The controller regulates the inductor averaged current back to 50A.

vo =150V vo (100V/div) iL(20A/div)

i=0;Flag=0 For
i 10?

iL =50A

Butterworth

2nd

order filter
N

i=0
N

i++; i=5?
Y

(a) Buck load step-up simulation result

Flag=1? Y

Flag=1
Return

vo =150V

Flag=0 2nd order controller Update Duty

End

iL =50A

Fig.11. DSP program flow chart

(b) Buck load step-up experimental result

V. EXPERIMENT AND SIMULATION RESULTS Fig. 12 shows the hardware test setup. MOSFET modules are sitting on the heat sink. Gate drive board is on the top of power modules, and DSP controller board sits on top of gate drive board. The total current is sensed and fed back to the DSP board. Four Finemet-based inductors are connected to each respective module.
Gate Drive Board MOSFET Bus Bar Heat Sink Inductor 1 2 3 4 Current Sensor DSP Board

vo =75V

iL =50A A

(c) Buck load step-down simulation result

vo =75V

iL =50A A

Fig.12. Test setup for 4-phase bidirectional dc-dc converter

(d) Buck load step-down experimental result Fig.13. Buck load step-up and dump-down simulation and test results

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Fig. 13(a) and 13(b) show the buck constant current mode load step-up simulation and experimental results, respectively. Before point A, an averaged current of 50A is regulated. At point A, load resistance changes from 3 into 1.5 . The inductor current increases immediately and is fed back to controller. Finally, before the current increases further, the controller regulates the inductor averaged current back to 50A. Fig.13(c) and 13(d) show the buck constant current mode load step-down simulation and experimental results, respectively. The averaged current is 50A. Contrary to the load step-up, at point A, load resistance changes from 1.5 to 3 . The current decreases immediately and is fed back to controller.

Boost constant current mode load step-up simulation and experimental results are shown in Figs. 14(a) and 14(b), respectively. Due to the opposite current reference direction, for load step-up the current goes to more negative value instead of going to positive value. Before point A, an averaged current of 12A is regulated. At point A, the load resistance changes from 18 into 9 . The current increases immediately and is fed back to controller. Finally, before the current increases further, the controller regulates the inductor averaged current back to 12A. Fig. 14(c) and 14(d) show the boost constant current mode load step-down simulation and experimental

R=1.5

R=3

R=1.5

R=3

R=3

R=1.5

R=3

R=1.5

t(1ms/div)

vo =100V iL =20A

t(1ms/div)

vo (100V/div) iL (20A/div)

t(1ms/div)

vo (100V/div) iL (20A/div)

iL =50A t(1ms/div)

results, respectively. The averaged current is 12A. Contrary to the load step-up, at point A, load resistance changes from 9 to 18 . Current decreases immediately and is fed back to controller. The controller regulated the inductor averaged current back to 12A. A significant current ripple presents due to inconsistent inductor values among 4 phases. However experimental results match with simulation results very well.
vo (50V/div) vo=114V iL=-12A iL=-12A

(a) Boost load step-up simulation test result

vo=114V iL=-12A

(b) Boost load step-up experimental result

vo=83V

iL=-12A

(c) Boost load step-down simulation result

vo=83V

iL =-12A

(d) Boost load step-down experimental result Fig.14. Boost load step-up and step-down simulation and test results [12] [13] [14]

VI. CONCLUSIONS A third-order average model for the bidirectional dc-dc converter is developed. The model contains voltage sources on both high- and low-sides and passive components. It is considered as a general-purposed model. If both ends are constant voltage source, the complete model becomes a firstorder system. If one of the voltage sources is replaced with a

R=9

R=18

R=9

A R=18

R=18

R=9

R=18

R=9

iL (5A/div)

t(5ms/div)

resistive load, the transfer function becomes a second-order system. A unified averaged current mode controller, which controls only one duty cycle for both buck and boost modes, is designed based on the derived general-purposed model. The proposed controller is implemented with a digital signal processor to avoid mode transition discontinuity. The complete system has been simulated with a circuit simulator and verified with hardware experiments. Both simulation and experimental results show that the proposed unified controller performs well in a high power bidirectional dc-dc converter. Stable operation is verified with load step up and down tests under both buck charging and boost discharging modes. The results indicate that the derived model is valid and can be used to for the unified controller design to achieve constant current charging and discharging. REFERENCES
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vo (50V/div) iL (5A/div) iL=-12A

Trigger(10V/div)

t(5ms/div)

vo (50V/div)
[5] [6]

iL (5A/div) t(5ms/div)

vo (50V/div) iL(5A/div)

t(5ms/div)
[11]

[3] [4]

[7] [8] [9]

[10]

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