Analog DPP

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TARGET : GATE 2025/26

Analog Electronics
Topic : Diode Family (Clipper Circuit) DPP - 01

Question 1
Consider the circuit shown in below figure, assume diode is ideal (V  0) . The output waveform of the
circuit is
Vi
5V Ideal
20 V    

t Vi 6.8 kΩ V0
0
 20 V  

(A) V0 (B) V0

19.3 V
T
2 T
0 t 0 t
T T
2
19.3 V

(C) V0 (D) V0

15
T T
2 T 2 T
0 t 0 t

15 15V
Question 2
Consider the circuit shown in below figure, assume diode is practical (V  0.7) . The output waveform of
the circuit is
Vi
Si 2.2 k
10 V Vi V0

t 1.2 k

10 V
TARGET : GATE 2025/26, DPP-01 2 GATE ACADEMY®

(A) V0 (B) V0

T
3.28 2 T
t

t
T T  3.28
2

(C) V0 (D) V0

6.56 T
2 T
t

t
T T
2  6.56

Question 3
Consider the circuit shown in below figure, assume diode is practical (V  0.7) . The output waveform of
the circuit is
Vi
Si 5V
10 V Vi V0
 

t 4.7 k

10 V

(A) V0 (B) V0

14.3
8.5

t t
T T T T
2 2

(C) V0 (D) V0

T
T
2 T
t 2 T
t

14.3  8.5

Question 4
Consider the circuit shown in below figure, assume diode is ideal (V  0) . The output waveform of the
circuit is
Vi
2V Ideal
20V    

Vi 1 k V0
0
t
 
5V
GATE ACADEMY® 3 TARGET : GATE 2025/26, DDP-01

(A) V0 (B) V0

T
3
2 T
t
t
T T
3
2

(C) V0 (D) V0

T
3
2 T
t
t
T T
3
2

Question 5

Consider the circuit shown in below figure, assume diode is ideal (V  0) . The output waveform of the
circuit is

Vi
Ideal
Vi V0
20V

22 k
0
t
5V 5V

(A) V0 (B) V0

20
20

5
t t
0 T T 0 T T
2 2

(C) V0 (D) V0
T T
2 T 2 T
t t
5

 20
20
TARGET : GATE 2025/26, DPP-01 4 GATE ACADEMY®
Question 6
Consider the circuit shown in below figure, assume diode is practical (V  0.7) . The output waveform of
the circuit is
Vi

8V  2.2 kΩ 
Si
Vi V0
t 
0 4V

 
 8V

(A) V0 (B) V0

8
4.7 T
T t 2 t
T T
2  4.7
8

(C) V0 (D) V0

4.7 T 4.7
2 T t t
T T
 4.7  4.7 2

Question 7
Consider the circuit shown in below figure, assume diode is practical (V  0.7) . The output waveform of
the circuit is
Vi
4V
8V Vi   V0
 2.2 kΩ

t Si

 8V

(A) V0 (B) V0

12 V
0.7
t 4

4 t
 0.7
12 V
GATE ACADEMY® 5 TARGET : GATE 2025/26, DDP-01
(C) V0 (D) V0

4.7 T 4.7
2 T t t
T T
 4.7  4.7 2

Question 8
Consider the circuit shown in below figure, assume diode is practical (V  0.7) . The output waveform of
the circuit is
Vi
10 kΩ
10 V
 
Si Si
t Vi V0
0
 
5.3 V 7.3 V
 
10 V  

(A) V0 (B) V0

8 6
T
0 0 2 T
t t
T T
6 2
8

(C) V0 (D) V0

8 8
T
0 2 T 0
t t
T T
6 2
8

Question 9
Consider the circuit shown in below figure, assume diode is ideal (V  0) . The output waveform of the
circuit is, when input Vi  10sin t V is
1 k
Vi V0

1 k 2 k
15 V
TARGET : GATE 2025/26, DPP-01 6 GATE ACADEMY®
(A) V0

7
5
0 t
–5
–7

– 10

(B) V0

10

7
5
0 t
–5
–7

(C) V0

7
5
0 t
–5
–7

(D) V0

7
5
0 t
–5
–7
GATE ACADEMY® 7 TARGET : GATE 2025/26, DDP-01
Question 10
Consider the circuit shown in below figure, assume diode is ideal (V  0) . The output waveform of the
circuit is
vi R  100 
Vi V0
30 V

t +
0 10 V

30 V

(A) V0 (t )

10 V

– 30 V

(B) V0 (t )

30 V

– 10 V

(C) V0 (t )

10 V

– 10 V

(D) V0 (t )

10 V

– 10 V
TARGET : GATE 2025/26, DPP-01 8 GATE ACADEMY®
Question 11
Consider the circuit shown in below figure, assume diode is ideal (V  0) . The output waveform of the circuit is
Vi 2V
+ –
20 V + +

Vi 10 k V0
0 t
5 V – –

(A) (B)
V0 (t ) V0 (t )

7V

t
0 t
0

– 7V

(C) (D)
V0 (t ) V0 (t )

4V 4V
t t
0 0
– 4V – 4V

Question 12
Consider the circuit shown in below figure, assume diode is ideal (V  0) . The output waveform of the circuit is
Vi Vi V0

20 V 2.2 k

+
0 t 5V

5 V

(A) (B)
V0 (t ) V0 (t )

20 V 20 V

5V
t
t 0
0

(C) (D)
V0 (t ) V0 (t )

20 V
20 V

5V t
0
t
0
GATE ACADEMY® 9 TARGET : GATE 2025/26, DDP-01
Question 13
Consider the circuit shown in in below figure, the value of V1 and V2 are needed (in V) respectively to
produce the output waveform shown in below figure
Vi V0
10 k
10 V
+ +
6V
T D1 D2 T
2 T Vi V0 2 T
t – t
+
V1 V2
– +
– – 8 V
10 V

(A) 6, 8 (B) – 6, 8
(C) 6, – 8 (D) – 6, – 8
Question 14
A triangular wave form Vi (t ) shown in figure (a), is applied as input to the circuit shown figure (b).
Assume the diode to be ideal (V  0)
Vi (t )

D1
0.5 k
+ +
12 V
D2 1k
Vi (t) 1.5 k V0 (t )
+ +
7V 5V
– –
0
t (ms) – –
1 2 3 4
Fig. (a) Fig.(b)
The minimum and maximum levels V0min and V0 max in output wave form V0 (t ) are respectively.
(A) 5 V and 7 V (B) 3 V and 5 V
(C) 2 V and 3 V (D) 3 V and 7 V
Question 15
Consider the circuit shown in below figure, output waveform of the circuit is
Vi
2 k
16
+
+
0 t Vi V0
T T –
2 4V +


– 16
TARGET : GATE 2025/26, DPP-01 10 GATE ACADEMY®
(A) V0 (B) V0

16
12

4 4
t t
T T T T
2 2
(C) V0 (D) V0

16
12
T
2 T 4
t t
–4 T T
2

Question 16
Consider the circuit shown in below figure, assume diode is practical (V  0.7 V) .

+
20 k 10k
+
Vi V0

10 V +
– 10V

The plot of V0 verses Vi for 10  Vi  10 V is


V0
(A) V0 (B)

9.3 9.3

3.33 3.33
Vi Vi
– 10 3.33 10 – 10 4.03 10
V0 V0
(C) (D)
10 10

3.33 3.33
Vi Vi
– 10 3.3 10 – 10 4.03 10
GATE ACADEMY® 11 TARGET : GATE 2025/26, DDP-01
Question 17
Consider the circuit shown in below figure, assume diode is practical (V  0.7 V) .

2 k 1k
1k V0
+
15 V + Vi
– –

The plot of V0 verses Vi is

(A) V0 (B) V0

19.6 19.6

5.7 4.3
Vi Vi
5.7 15 4.3 15
(C) V0 (D) V0

9.42 9.42
5.7 4.3
Vi Vi
5.7 15 4.3 15
Question 18
Consider the circuit shown in figure (a). If the diode used here has the V-I characteristics as shown in
figure (b), then the output waveform V0 is

(A) (B)

(C) (D)
TARGET : GATE 2025/26, DPP-01 12 GATE ACADEMY®
Question 19
In the circuit shown in below figure Vi is 4 V. Assuming the diodes to be ideal, V0 is

(A) 3 V (B) 4 V
(C) 4.5 V (D) 6 V
Question 20
In the circuit shown, assume that the diodes D1 and D2 are ideal. The average value of voltage Vab (in
Volts), across terminals ‘a’ and ‘b’ is ______. (rounded upto one decimal places)

Question 21
In the circuit shown, Vs is a square wave of period T with maximum and minimum values of 8 V and
– 10 V, respectively. Assume that the diode is ideal and R1  R2  50  . The average value of VL
is_______ volts (rounded off to one decimal place).
R1
Vs
8 

0 t Vs RL VL
T T
2

10

Question 22
In figure the input Vi is a 100 Hz triangular wave having a peak to peak amplifier of 2 V and on average
value of 0 volts. Given that the diode is ideal the average value of the output V0 (in V) is _____. (rounded
upto one decimal place)
GATE ACADEMY® 13 TARGET : GATE 2025/26, DDP-01
Question 23
Draw the transfer characteristics for the given circuit, assume ideal diodes.

(A) (B)

(C) (D)

Question 24
The input voltage Vi to a two level clipper shown below varies from 0 to 150 V. Assume diodes to be
ideal. The transfer characteristics of the circuit is

(A) (B)

(C) (D)

25 V

25 V 100 V 100 V
TARGET : GATE 2025/26, DPP-01 14 GATE ACADEMY®
Question 25
The input voltage Vi varies linearly from 0 to 150 V.

The transfer characteristics for the figure shown below is


(A) (B)

(C) (D)

Question 26
The transfer curve for the given below figure :

(A) (B)
2/3

(C) (D)

Question 27
For the circuit in figure the cut-in voltage of diode is V  0.7 V. The plot of v0 verses vi is

2 k 1 k
1 k V0
15V Vi
GATE ACADEMY® 15 TARGET : GATE 2025/26, DDP-01
(A) V0 (B) V0

19.6 19.6

5.7 4.3

Vi Vi
5.7 15 V 4.3 15 V
(C) V0 (D) V0

9.42 9.42

5.7 4.3

Vi Vi
5.7 15 V 4.3 15 V
Question 28
The transfer characteristics for given circuit is

(A) (B)

(C) (D) V0

19.6

4.3

Vi
4.3 15 V
Question 29
Consider the circuit shown in below figure assume diode is ideal ( v  0 ), the output waveform of the
circuit is
vi
+ D1 D4
100 V
T  v0 
2 vi
T t R

100 V D2 D3

TARGET : GATE 2025/26, DPP-01 16 GATE ACADEMY®
v0 v0
(A) (B)

100 V 100 V
T
t 2 T
t
T T
2
–100 V

v0 v0
(C) (D)

100 V
T T
2 2 T
t t
T

–100 V –100 V

Question 30
In the circuit shown below, the three signals of fig are impressed on the input terminals. If diode are ideal
( v  0 ). The output waveform of the circuit is
v
v3 D1

+ D2
v2
v1 + D3
t v1 v0
+
v2
v3 10 k
– – –

(A) (B)

(C) (D)


TARGET : GATE 2025/26
Analog Electronics
Topic : Diode Family (Equivalent Circuit) DPP - 02

..Common Data for Q.1 to Q.8..


In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.

0.5k D1
V1
I D1

0.5 k D2
V2 V0
I D2
9.5 k

Question 1
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  10 V and V2  0 V are respectively
is ______. (rounded upto two decimal places)
Question 2
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  10 V and V2  0 V are
respectively is ______. (rounded upto two decimal places)
Question 3
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  5 V and V2  0 V are respectively
is ______. (rounded upto two decimal places)
Question 4
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  5 V and V2  0 V are
respectively is ______. (rounded upto two decimal places)
Question 5
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  10 V and V2  5 V are respectively
is ______. (rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-02 2 GATE ACADEMY®
Question 6
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  10 V and V2  5 V are
respectively is ______. (rounded upto two decimal places)
Question 7
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  V2  10 V is ______. (rounded upto
two decimal places)
Question 8
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  V2  10 V is ______.
(rounded upto two decimal places)
..Common Data for Q.9 to Q.16..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
10V
I
9.5 k
0.5k D1
V1 V0
I D1

D2
0.5k
V2
I D2

Question 9
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  V2  10 V is ______. (rounded upto
two decimal places)
Question 10
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  V2  10 V is ______.
(rounded upto two decimal places)
Question 11
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  10 V and V2  0 V are respectively
is ______. (rounded upto two decimal places)
Question 12
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  10 V and V2  0 V are
respectively is ______. (rounded upto two decimal places)
Question 13
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  10 V and V2  5 V are respectively
is ______. (rounded upto two decimal places)
Question 14
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  10 V and V2  5 V are
respectively is ______. (rounded upto two decimal places)
GATE ACADEMY® 3 TARGET : GATE 2025/26, DDP-02
Question 15
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  V2  0 V is ______. (rounded upto
two decimal places)
Question 16
The value of sum of diode current ( I D1  I D2 ) in mA, when input voltage V1  V2  0 V is ______. (rounded
upto two decimal places)
..Common Data for Q.17 to Q.24..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
10 V
D1
0.5k I
V1
ID 9.5k
1

V0
D2
0.5k D3
V2
ID 2 ID 3

5 V
Question 17
The value of diode current ( I D1  I D2  I D3  I ) in mA, when input voltage V1  V2  0 V is ______.
(rounded upto two decimal places)
Question 18
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  V2  0 V is ______. (rounded upto
two decimal places)
Question 19
The value of diode current ( I D1  I D2  I D3  I ) in mA, when input voltage V1  V2  5V is ______.
(rounded upto two decimal places)
Question 20
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  V2  5V is ______. (rounded upto
two decimal places)
Question 21
The value of diode current ( I D1  I D2  I D3  I ) in mA, when input voltage V1  5 V and V2  0 V are
respective is ______. (rounded upto two decimal places)
Question 22
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  5 V and V2  0 V are respective is
______. (rounded upto two decimal places)
Question 23
The value of diode current ( I D1  I D2  I D3  I ) in mA, when input voltage V1  5 V and V2  2 V are
respective is ______. (rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-02 4 GATE ACADEMY®
Question 24
The output voltage 'V0 ' (in V) of the circuit, when input voltage V1  5 V and V2  2 V are respective is
______. (rounded upto two decimal places)
..Common Data for Q.25 to Q.27..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
10 V

ID 1

5V
D1
ID
2

D2 R1

V1
ID
3

R2
D3
V2

R3

5 V

Question 25
The value of sum of resistance ( R1  R2  R3 ) in k such that diode current I D1  0.2 mA , I D2  0.3 mA
and I D3  0.5 mA are respectively is ______. (rounded upto two decimal places)
Question 26
The value of sum of voltage (V1  V2 ) in V such that R1  10 k , R2  4 k and R3  2.2 k are
respectively is _______. (rounded upto two decimal places)
Question 27
The value of current ( I D1  I D2  I D3 ) in mA such that R1  6 k , R2  3 k and R3  6 k are respective
is _______. (rounded upto two decimal places)
..Common Data for Q.28 to Q.30..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
5V

I  5 mA

I D1 I D2

D1 D2

2 V
GATE ACADEMY® 5 TARGET : GATE 2025/26, DDP-02
Question 28
The value of resistance ' R ' (in kΩ ) such that, diode current ( I D1  I D2 ) is ______. (rounded upto two
decimal places)
Question 29
The value of resistance ' R ' (in kΩ ) such that, diode current ( I D1  0.2 I D2 ) is ______. (rounded upto two
decimal places)
Question 30
The value of resistance ' R ' (in kΩ ) such that, diode current ( I D1  5 I D2 ) is ______. (rounded upto two
decimal places)
..Common Data for Q.31 to Q.34..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
5V
ID1
D1

R1  2k
10V VA
I D2
I  5 mA
D2

R2

5V
Question 31
The value of the current ( I D1  I D2 ) in mA such that, R2  1.1 k is ______. (rounded upto two decimal
places)
Question 32
The value of the voltage 'VA ' (in V) such that R2  1.1 k is ______. (rounded upto two decimal places)
Question 33
The value of resistance ' R2 ' (in k ) such that voltage VA  0 V is ______. (rounded upto two decimal
places)
Question 34
The value of the current ( I D1  I D2 ) in mA such that, VA  0 V is ______. (rounded upto two decimal
places)
TARGET : GATE 2025/26, DPP-02 6 GATE ACADEMY®
..Common Data for Q.35 to Q.38..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
D1
5k

I D1
5k
V0
I D2
D2
V1 +
– 500
500

Question 35
The value of output voltage 'V0 ' (in V), such that V1  5 V is _______. (rounded upto two decimal places)
Question 36
The value of output voltage 'V0 ' (in V), such that V1   5 V is _______. (rounded upto two decimal
places)
Question 37
The value of diode current ( I D1  I D2 ) in mA, such that V1  5 V is _______. (rounded upto two decimal
places)
Question 38
The value of diode current ( I D1  I D2 ) in mA, such that V1   5 V is _______. (rounded upto two decimal
places)
..Common Data for Q.39 & Q.40..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
15 V

R1  6.15 k 
I D1
V0
I D3 ID 2 D1
D3 D2 R2  2 k

R4 R3

10 V 5 V
GATE ACADEMY® 7 TARGET : GATE 2025/26, DDP-02
Question 39
The value of diode current ( I D1  I D2  I D3 ) in mA, such that R3  14 k , R4  24 k are respectively is
_______. (rounded upto two decimal places)
Question 40
The value of output voltage 'V0 ' (in V), such that R3  14 k , R4  24 k are respectively is _______.
(rounded upto two decimal places)
..Common Data for Q.41 to Q.44..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.

I D2 D2
R1
10 V V0
I D1

D1 R1

10 V

Question 41
The value of diode current ' I D1 ' (in mA), such that R1  5 k , R2  10 k are respectively is _______.
(rounded upto two decimal places)
Question 42
The value of output voltage 'V0 ' (in V), such that R1  5 k , R2  10 k are respectively is _______.
(rounded upto two decimal places)
Question 43
The value of diode current ' I D2 ' (in mA), such that R1  10 k , R2  5 k are respectively is _______.
(rounded upto two decimal places)
Question 44
The value of output voltage 'V0 ' (in V), such that R1  10 k , R2  5 k are respectively is _______.
(rounded upto two decimal places)
..Common Data for Q.45 to Q.48..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.
D2
R1 ID
2
10 V V0

D1 R2
ID
1

15 V
TARGET : GATE 2025/26, DPP-02 8 GATE ACADEMY®
Question 45
The value of diode current ' I D1 ' (in mA), such that R1  5 k , R2  10 k are respectively is _______.
(rounded upto two decimal places)
Question 46
The value of output voltage 'V0 ' (in V), such that R1  5 k , R2  10 k are respectively is _______.
(rounded upto two decimal places)
Question 47
The value of diode current ' I D2 ' (in mA), such that R1  10 k , R2  5 k are respectively is _______.
(rounded upto two decimal places)
Question 48
The value of output voltage 'V0 ' (in V), such that R1  10 k , R2  5 k are respectively is _______.
(rounded upto two decimal places)
..Common Data for Q.49 to Q.52..
In the circuit shown in below figure, the diode have piecewise linear parameters, with cut in voltage of diode is
V  0.6 V and forward resistance of diode is rf  0 , otherwise ideal.

D2
R1
10 V V0
ID1 I D2

D1 R2

15 V
Question 49
The value of diode current ' I D1 ' (in mA), such that R1  5 k , R2  10 k are respectively is _______.
(rounded upto two decimal places)
Question 50
The value of output voltage 'V0 ' (in V), such that R1  5 k , R2  10 k are respectively is _______.
(rounded upto two decimal places)
Question 51
The value of diode current ' I D2 ' (in mA), such that R1  10 k , R2  5 k are respectively is _______.
(rounded upto two decimal places)
Question 52
The value of output voltage 'V0 ' (in V), such that R1  10 k , R2  5 k are respectively is _______.
(rounded upto two decimal places)
GATE ACADEMY® 9 TARGET : GATE 2025/26, DDP-02
Question 53
Consider the circuit shown in below figure, the cut-in voltage of silicon diode is 0.7 V, otherwise diode is
ideal. The value of output voltage 'V0 ' (in V) of the circuit is ______. (rounded upto two decimal places)
1.2k Si
10 V V0

4.7 k

2V
Question 54
Consider the circuit shown in below figure, the cut-in voltage of silicon diode is 0.7 V, otherwise diode is
ideal. The value of diode current ' I D ' (in mA) is ______. (rounded upto two decimal places)
1.2k Si
10 V V0

4.7 k

2V
Question 55
Consider the circuit shown in below figure, the cut-in voltage of silicon diode is 0.7 V, otherwise diode is
ideal. The value of diode current ' I D1 ' (in mA) is ______. (rounded upto two decimal places)
15 V

ID1
D2 Si Si D1
I D2

Vin
2.2 k

Question 56
Consider the circuit shown in below figure, the cut-in voltage of silicon diode is 0.7 V, otherwise diode is
ideal. The value of output voltage 'V0 ' (in V) of the circuit is ______. (rounded upto two decimal places)
16 V

Si

Si Si

Vin

4.7 k

12V
TARGET : GATE 2025/26, DPP-02 10 GATE ACADEMY®
Question 57
Consider the circuit shown in below figure, the cut-in voltage of silicon diode is 0.7 V and cut-in voltage
of germanium diode is 0.3 V, otherwise both diode are ideal. The value of the current ‘I ’ (in mA) is
______. (rounded upto two decimal places)
1 k 0.47k

I

20 V Si Ge

Question 58
Consider the circuit shown in below figure, the cut-in voltage of silicon diode is 0.7 V, otherwise diode is
ideal. The value of output voltage 'V0 ' (in V) of the circuit is ______. (rounded upto two decimal places)
10 V
Si

10 V V0
Si
1kΩ

10 V


TARGET : GATE 2025/26
Analog Electronics
Topic : Diode Family (Zener Regulator) DPP - 03

..Common Data for Q.1 to Q.4..


The voltage regulator is to power a car radio at VL  9 V from an automobile battery whose voltage may vary
between 11 and 13.6 V. The current in the radio will vary between 0 (off) to 100 mA (full volume).
Ii Ri IL

IZ
+ +
V ps VZ  9 V Radio
– –

Question 1
The value of maximum power dissipated (in W) by the Zener diode is _______. (rounded upto one decimal
place)
Question 2
The value of the current limiting resistor Ri (in ) is ______. (rounded upto one decimal place)
Question 3
The value of maximum power dissipated (in W) by the resistance ' Ri ' is _______. (rounded upto one
decimal place)
Question 4
The value of minimum current (in mA) flow through the Zener diode is ______. (rounded upto one
decimal place)
..Common Data for Q.5 & Q.6..
The Zener diode regulator circuit shown in below figure has an input voltage that varies between 10 to 14 V, and
a load resistance that varies between RL  20 to 100 . The breakdown voltage of Zener diode is 5.6 V and
assume I L (min)  0.1I Z (max) .
I in Ri

IZ IL +
+ +
Vin VZ RL VL



TARGET : GATE 2025/26, DPP-03 2 GATE ACADEMY®
Question 5
The value of the resistance Ri (in  ) is _______. (rounded upto one decimal place)
Question 6
The minimum power rating (in W) of the Zener diode is _______. (rounded upto two decimal places)
..Common Data for Q.7 & Q.9..
Consider the circuit shown in below figure. The breakdown voltage of Zener diode is VZ  3.9 V , otherwise diode
is ideal.
12 k

IZ IL +
+ +
20 V VZ 4 k VL



Question 7
The value of the Zener current I Z (in mA) is ________. (rounded upto two decimal places)
Question 8
The value of the load current I L (in mA) is ________. (rounded upto two decimal places)
Question 9
The value of the power dissipated (in mW) by the Zener diode is ________. (rounded upto two decimal
places)
..Common Data for Q.10 & Q.13..
Consider the Zener diode circuit shown in below figure. The breakdown voltage of Zener diode VZ  12 V ,
otherwise diode is ideal.
Iin 120 

IZ IL +
+ +
40 V VZ RL VL


Question 10
The value of the Zener current I Z (in A), when RL   is ________. (rounded upto two decimal places)
Question 11
The value of the power dissipated (in W) by the Zener diode, when RL   is ________. (rounded upto
two decimal places)
Question 12
The value of RL (in  ) such that the current in Zener diode is one-tenth of the current supplied by the 40
V source is ______. (rounded upto two decimal places)
Question 13
The value of the power dissipated (in W) by the Zener diode, when RL  40  is ________. (rounded
upto two decimal places)
GATE ACADEMY® 3 TARGET : GATE 2025/26, DDP-03
..Common Data for Q.14 & Q.18..
In the voltage regulator circuit in below figure, given that : VI  20 V , VZ  10 V , Ri  222  and
PZ (max)  400 mW .
I in Ri

IZ IL +
+ +
Vin VZ RL VL


Question 14
The value of the load current I L (in mA), when load resistance RL  380  , is ________. (rounded upto
two decimal places)
Question 15
The value of the Zener current I Z (in mA), when load resistance RL  380  , is ________. (rounded upto
two decimal places)
Question 16
The value of the input current Iin (in mA), when load resistance RL  380  , is ________. (rounded upto
two decimal places)
Question 17
The value of the load resistance RL (in k ) that will stablish maximum power in the Zener diode is
______. (rounded upto two decimal places)
Question 18
The value of the load resistance RL (in k ) that will stablish maximum power in the Zener diode is
______. (assume Ri  175  ) (rounded upto two decimal places)

..Common Data for Q.19 & Q.34..


Consider the circuit shown in below figure, given that : VZ0  5.6 V (diode voltage when I Z  0 ) and incremental
diode resistance rz  3  , otherwise diode is ideal and input resistance Ri  50 .
I in Ri

IZ IL +
+ +
Vin VZ RL VL


Question 19
The value of load voltage VL (in V) such that input voltage Vin  10 V and load resistance RL   is
______. (rounded upto two decimal places)
Question 20
The value of Zener current I Z (in mA) such that input voltage Vin  10 V and load resistance RL   is
______. (rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-03 4 GATE ACADEMY®
Question 21
The value of load current I L (in mA) such that input voltage Vin  10 V and load resistance RL   is
______. (rounded upto two decimal places)
Question 22
The value of power dissipated (in W) by the Zener diode, such that input voltage Vin  10 V and load
resistance RL   is ______. (rounded upto two decimal places)
Question 23
The value of load voltage VL (in V) such that input voltage Vin  10 V and load resistance RL  200  is
______. (rounded upto two decimal places)
Question 24
The value of Zener current I Z (in mA) such that input voltage Vin  10 V and load resistance RL  200 
is ______. (rounded upto two decimal places)
Question 25
The value of load current I L (in mA) such that input voltage Vin  10 V and load resistance RL  200 
is ______. (rounded upto two decimal places)
Question 26
The value of power dissipated (in W) by the Zener diode, such that input voltage Vin  10 V and load
resistance RL  200  is ______. (rounded upto two decimal places)
Question 27
The value of load voltage VL (in V) such that input voltage Vin  12 V and load resistance RL   is
______. (rounded upto two decimal places)
Question 28
The value of Zener current I Z (in mA) such that input voltage Vin  12 V and load resistance RL   is
______. (rounded upto two decimal places)
Question 29
The value of load current I L (in mA) such that input voltage Vin  12 V and load resistance RL   is
______. (rounded upto two decimal places)
Question 30
The value of power dissipated (in W) by the Zener diode, such that input voltage Vin  12 V and load
resistance RL   is ______. (rounded upto two decimal places)
Question 31
The value of load voltage VL (in V) such that input voltage Vin  12 V and load resistance RL  200  is
______. (rounded upto two decimal places)
Question 32
The value of Zener current I Z (in mA) such that input voltage Vin  12 V and load resistance RL  200 
is ______. (rounded upto two decimal places)
Question 33
The value of load current I L (in mA) such that input voltage Vin  12 V and load resistance RL  200 
is ______. (rounded upto two decimal places)
GATE ACADEMY® 5 TARGET : GATE 2025/26, DDP-03
Question 34
The value of power dissipated (in W) by the Zener diode, such that input voltage Vin  12 V and load
resistance RL  200  is ______. (rounded upto two decimal places)

..Common Data for Q.35 & Q.38..


Consider the circuit shown in below figure, given that : VL  7.5V . The Zener diode voltage is VZ  7.5V at
I Z  10 mA . The incremental diode resistance is rz  12  . The nominal supply voltage is Vin  12 V and the
nominal load resistance is RL  1k .
I in Ri

IZ IL +
+ +
Vin VZ RL VL



Question 35
The value of input resistance Ri (in  ) is _______. (rounded upto two decimal places)
Question 36
If input voltage 'Vin ' varies by 10% of its nominal value, what is the variation in output voltage (in V)
is _______. (rounded upto one decimal place)
Question 37
If input voltage 'Vin ' varies by 10% of its nominal value, then the value of source regulation (in %) is
_______. (rounded upto one decimal place)
Question 38
If load resistance RL varies over the range of 1 k  RL   , what is the variation in output voltage (in
V) is _______. (rounded upto one decimal place)
Question 39
The percent regulation of the Zener diode regulator shown in below figure is 5%. The Zener voltage is
VZ 0  6 V and the Zener resistance rZ  3  . Also the load resistance varies between 500  to 1000  ,
the input resistance Ri  280  and the minimum power supply by voltage is Vin (min)  15 V . The value
of maximum power (in mW) supply voltage allowed is _______. (rounded upto two decimal places)
I in Ri

IZ IL +
+ +
Vin VZ RL VL



TARGET : GATE 2025/26
Analog Electronics
Topic : BJT-Biasing & Region of BJT DPP : 04

..Common Data for Q.1 to Q.4..


For the circuit shown in below figure the parameters are : VBB  1.5 V , VEB (on)  0.6 V,   100 .
5V

RB  580 k +
1.5 V VEC

RC

Question 1
The value of based current I B (in A ) such that VEC  2.5 V is _________. (Rounded upto two decimal
places)
Question 2
The value of collector current I C (in mA ) such that VEC  2.5V is _________. (Rounded upto two
decimal places)
Question 3
The value of emitter current I E (in mA) such that VEC  2.5 V is_________. (Rounded upto two decimal
places)
Question 4
The value of the resistance RC (in k ) such that VEC  2.5 V is_________. (Rounded upto two decimal
places)
Question 5
For the circuit shown in below figure, the transistor parameters are :   100, and VBE (on)  0.7 V . If the
transistor is biased in saturation, then assume VCE (sat)  0.2 V , the value of sum of current ( I B  I C  I E )
(in mA) is________. (Rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-04 2 GATE ACADEMY®

Question 6
Consider the circuit shown in below figure, the transistor parameters are VBE (on)  0.7 V and
VCE (sat)  0.2 V ,   50 . The value of power dissipated by the transistor (in mW) such that VI  3.6 V is

(A) 0 (B) 4.53


(C) 5.35 (D) 10.9
Question 7
Consider the circuit shown in below figure, the transistor parameters are VBE (on)  0.7 V and   50 , the
value of input voltage VI (in V) such that VBC  0 V is
GATE ACADEMY® 3 TARGET : GATE 2025/26, DPP-04
..Common Data for Q.8 to Q.12..
Consider the circuit shown in below figure, measured value of the collector voltage is VC  2.27 and base to
emitter voltage is 0.7 V.

Question 8
The value of based current I B (in A ) is _________. (Rounded upto two decimal places)
Question 9
The value of collector current I C (in mA ) is _________. (Rounded upto two decimal places)
Question 10
The value of emitter current I E (in mA) is_________. (Rounded upto two decimal places)
Question 11
The value of common emitter current gain  is________. (Rounded upto two decimal places)
Question 12
The value of common base current gain  is________. (Rounded upto five decimal places)

..Common Data for Q.13 to Q.17..


Consider the circuit shown in below figure, the common-emitter current gain  is 150 and base to emitter voltage
of the transistor is 0.7 V, let RE  500 , RC  4 k, R1  85 k, R2  35 k .

Question 13
The value of Thevenin’s voltage ‘ Vth ’ (in V) across the base terminal of the transistor is_________.
(Rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-04 4 GATE ACADEMY®
Question 14
The value of Thevenin’s resistance ‘ Rth ’ (in k ) across the base terminal of the transistor is_________.
(Rounded upto two decimal places)
Question 15
The value of based current I B (in A ) is _________. (Rounded upto two decimal places)
Question 16
The value of collector current I C (in mA ) is _________. (Rounded upto two decimal places)
Question 17
The value of collector to emitter voltage VCE of the transistor (in V) is_________. (Rounded upto two
decimal places)

..Common Data for Q.18 to Q.21..


Consider the circuit shown in below figure, the common-emitter current gain  is 75 and base to emitter voltage
of the transistor is 0.7 V.

Question 18
The value of the resistance RE (in k ) is_________. (Rounded upto two decimal places)
Question 19
The value of the collector current I E (in mA) is_________. (Rounded upto two decimal places)
Question 20
Consider the circuit shown in below figure, the emitter to base voltage of the transistor is 0.7 V and   1
. The value of ‘ RE  RC ’ (in k ) such that collector current of 1 mA and reverse bias on the collector
based junction of 4 V is_________. (Rounded upto two decimal places)
GATE ACADEMY® 5 TARGET : GATE 2025/26, DPP-04
Question 21
Consider the circuit shown in below figure, the magnitude of base to emitter voltage of the transistor is
0.7 V and   100. The value of output voltage ‘ V0 ’ (in V) is_________. (Rounded upto one decimal
place)

..Common Data for Q.22 to Q.27..


Consider the circuit shown in below figure, the emitter to base voltage of the transistor is 0.7 V.

Question 22
The value of the base current I B (in A ) is_________. (Rounded upto two decimal places)
Question 23
The value of the collector current I C (in mA) is_________. (Rounded upto two decimal places)
Question 24
The value of the emitter current I E (in mA) is_________. (Rounded upto two decimal places)
Question 25
The value of the emitter to collector voltage VEC (in V) is_________. (Rounded upto two decimal places)
Question 26
The value of power dissipated by transistor (in mW) is_________. (Rounded upto two decimal places)
Question 27
The value of common emitter current gain  is_________. (Rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-04 6 GATE ACADEMY®
..Common Data for Q.28 to Q.34..
Consider the circuit shown in below figure, the emitter to base voltage of the transistor is 0.7 V.

Question 28
The value of the base current I B (in A ) is_________. (Rounded upto two decimal places)
Question 29
The value of the collector current I C (in mA) is_________. (Rounded upto two decimal places)
Question 30
The value of the emitter current I E (in mA) is_________. (Rounded upto two decimal places)
Question 31
The value of the emitter to collector voltage VEC (in V) is_________. (Rounded upto two decimal places)
Question 32
The value of power dissipated by transistor (in mW) is_________. (Rounded upto two decimal places)
Question 33
The value of common emitter current gain  is_________. (Rounded upto two decimal places)
Question 34
For the circuit shown in below figure the value of RE (in k ) so that the transistor saturates with a forced
 of 10. Assume VEB = 0.7V and VECsat  0.2V _________. (Rounded upto two decimal places)
GATE ACADEMY® 7 TARGET : GATE 2025/26, DPP-04
..Common Data for Q.35 to Q.38..
For of the saturated circuit in below figure, assume VBE  0.7V and VCEsat  0.2V .

Question 35
The value of the base current I B (in A ) is_________. (Rounded upto two decimal places)
Question 36
The value of the collector current I C (in mA) is_________. (Rounded upto two decimal places)
Question 37
The value of the emitter current I E (in mA) is_________. (Rounded upto two decimal places)
Question 38
The value of power dissipated by transistor (in mW) is_________. (Rounded upto two decimal places)

..Common Data for Q.39 to Q.46..


Consider the circuit shown in below figure, the emitter to base voltage of the transistor is 0.7 V and common
emitter current gain  to be very high.

Question 39
The value of the base current I B (in A ) is_________. (Rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-04 8 GATE ACADEMY®
Question 40
The value of the collector current I C (in mA) is_________. (Rounded upto two decimal places)
Question 41
The value of the emitter current I E (in mA) is_________. (Rounded upto two decimal places)
Question 42
The value of the emitter to collector voltage VEC (in V) is_________. (Rounded upto two decimal places)
Question 43
The value of power dissipated by transistor (in mW) is_________. (Rounded upto two decimal places)
Question 44
The value of the collector voltage VC (in V) is_________. (Rounded upto two decimal places)
Question 45
The value of the emitter voltage VE (in V) is_________. (Rounded upto two decimal places)
Question 46
The value of the base voltage VB (in V) is_________. (Rounded upto two decimal places)
Question 47
Consider the circuit shown in below figure, the emitter to base voltage of the transistor is 0.7 V and
common emitter current gain  is 50 , the value of RC (in k ) such that VC  5 V is_________. (Rounded
upto two decimal places)

Question 48
The DC load line and Q-point of the circuit in figure (a) are shown in figure (b) the transistor parameters
are the base to emitter voltage of the transistor is 0.7 V and common emitter current gain  is 90. The
value of the sum of the resistance ‘ R1  R2  RE (in k ) such that the circuit is bias stable is_________.
(Rounded upto two decimal places)

Fig. (a) Fig. (b)


GATE ACADEMY® 9 TARGET : GATE 2025/26, DPP-04
Question 49
The range of  for the transistor in the circuit shown in below figure is 80    120 the value of sum
resistance ‘ R1  R2  RE ’ (in k ) such that the normal Q point value I CQ  0.2 mA and VCEQ  1.6 V the
value of I CQ must be fall in the range 0.19  I CQ  0.21mA is__________. (Rounded upto two decimal
places)

Question 50
The transistor in the circuit shown below figure is biased with a constant current in the emitter. The emitter
to base voltage of the transistor is 0.7 V and common emitter current gain  is 50. The value sum of the
voltage ‘ VC  VE ’ (in V) such that I Q  1mA is__________. (Rounded upto two decimal places)

Question 51
Consider the circuit shown in below figure, the emitter to base voltage of the transistor is 0.7 V and
common emitter current gain  is 60. The value of RB (in k ) such that V0  8.8V and I C  25 I B
when VI  5V is_________. (Rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-04 10 GATE ACADEMY®
..Common Data for Q.52 to Q.60..
Consider the circuit shown in below figure, the base to emitter voltage of the transistor is 0.7 V and common
emitter current gain  is 80.

Question 52
The value of the base current I B (in A ) is_________. (Rounded upto two decimal places)
Question 53
The value of the collector current I C (in mA) is_________. (Rounded upto two decimal places)
Question 54
The value of the emitter current I E (in mA) is_________. (Rounded upto two decimal places)
Question 55
The value of the emitter to collector voltage VEC (in V) is_________. (Rounded upto two decimal places)
Question 56
The value of power dissipated by transistor (in mW) is_________. (Rounded upto two decimal places)
Question 57
The value of the collector voltage VC (in V) is_________. (Rounded upto two decimal places)
Question 58
The value of the common base current gain  is_________. (Rounded upto two decimal places)
Question 59
The value of percentage change of collector current I C if  is change to 120 is_________. (Rounded
upto two decimal places)
Question 60
The value of percentage change of collector to emitter voltage VCE if  is change to 120 is_________.
(Rounded upto two decimal places)

..Common Data for Q.61 to Q.72..


Consider the circuit shown in below figure, the base to emitter voltage of the transistor is 0.7 V and common
emitter current gain  is 80.
GATE ACADEMY® 11 TARGET : GATE 2025/26, DPP-04

Question 61
The value of the Thevenin resistance Rth (in k ) across the base terminal of the transistor is_________.
(Rounded upto two decimal places)
Question 62
The value of the Thevenin voltage Vth (in V) across the base terminal of the transistor is_________.
(Rounded upto two decimal places)
Question 63
The value of the base current I B (in A ) is_________. (Rounded upto two decimal places)
Question 64
The value of the collector current I C (in mA) is_________. (Rounded upto two decimal places)
Question 65
The value of the emitter current I E (in mA) is_________. (Rounded upto two decimal places)
Question 66
The value of the emitter to collector voltage VEC (in V) is_________. (Rounded upto two decimal places)
Question 67
The value of power dissipated by transistor (in mW) is_________. (Rounded upto two decimal places)
Question 68
The value of the collector voltage VC (in V) is_________. (Rounded upto two decimal places)
Question 69
The value of the common base current gain  is_________. (Rounded upto two decimal places)
Question 70
The value of percentage change of collector current I C if  is change to 120 is_________. (Rounded
upto two decimal places)
Question 71
The value of percentage change of collector to emitter voltage VCE if  is change to 120 is_________.
(Rounded upto two decimal places)
Question 72
The value of the sum of resistance ‘ RC1  RC2  RE1  RE2 ’ (in k ) such that I C1  I C2  0.8 mA ,
VECQ1  3.5 V and VCEQ2  4.0 V is________. (Rounded upto two decimal places)
TARGET : GATE 2025/26, DPP-04 12 GATE ACADEMY®
Question 73
Consider the circuit shown in below figure, the base to emitter voltage of the transistor is 0.7 V and
common emitter current gain  is 110. The value of sum of the resistance ' RC  RB  RE ' (in k ) such
1
that I C  I C ( sat ) , I C ( sat )  8 mA, VC  18 V.
2

Question 74
Consider the circuit shown in below figure, the base to emitter voltage of the transistor is 0.7 V and
common emitter current gain  is 250. The value of sum of the resistance ' RC  RB ' (in k ) such that
I C ( sat )  8 mA.

Question 75
Consider the circuit shown in below figure, the transistor parameters are VBE (on)  0.7 V,   120,
VCE (sat)  0.2 . The transfer characteristics of the transistor is
GATE ACADEMY® 13 TARGET : GATE 2025/26, DPP-04
(A) V0 (V) (B) V0 (V)

5 5

0.2 0.2
VI (V) VI (V)
0 0.7 1.9 5 0 0.7 2.5 5

(C) V0 (V) (D) V0 (V)

5 5

0.2 0.2
VI (V) VI (V)
0 1.9 5 0 0.7 2.5 5


TARGET : GATE 2025/26
Analog Electronics
Topic : Operational Amplifier DPP : 05

..Common Data for Q.1 & Q.2..


The Op-Amp in the circuit shown in below figure is ideal.

Question 1
The value of input resistance Ri (in k ) is_________. (Rounded upto one decimal place)
Question 2
 V 
The value of voltage gain  AV  0  is_________. (Rounded upto one decimal place)
 Vi 

..Common Data for Q.3 & Q.4..


The Op-Amp in the circuit shown in below figure are ideal.

Question 3
The value of input resistance Ri (in k ) is_________. (Rounded upto one decimal place)
Question 4
 V 
The value of voltage gain  AV  0  is_________. (Rounded upto one decimal place)
 Vi 
TARGET : GATE 2025/26, DPP-05 2 GATE ACADEMY®
..Common Data for Q.5 & Q.6..
The parameters of the two inverting Op-Amp circuits connected in cascade shown in below figure are R1  10 k
, R2  80 k , R3  20 k and R4  100 k . Assume Op-Amp are ideal
R2
R4
i2
R1 i4

R3
Vi   0.15 i1 –
+ V01 i3 V02
+

Question 5
The value of the current (i1  i2  i3  i4 ) (in A ) is_________. (Rounded upto one decimal place)
Question 6
The value of voltage (V0  V0 ) (in volt) is_________. (Rounded upto one decimal place)
1 2

..Common Data for Q.7 & Q.8..


The Op-Amp in the circuit shown in below figure is ideal except it has a finite open loop gain.

Question 7
The value of input voltage ‘ Vi ’ (in V) such that open loop gain AOL  104 and output voltage is 2 V
is________. (Rounded upto two decimal place)
Question 8
The value of open loop gain such that input voltage is 2 V and output voltage is 1V are respectively
is________. (Rounded upto two decimal place)

..Common Data for Q.9 & Q.10..


Consider the circuit shown in below figure
GATE ACADEMY® 3 TARGET : GATE 2025/26, DPP-05
Question 9
The value of output voltage ‘ V0 ’ (in V) such that input voltage is  0.40V (assume Op-Amp is ideal)
is_________. (Rounded upto one decimal place)
Question 10
The value of output voltage ‘ V0 ’ (in V) such that input voltage is  0.40V and open loop gain of Op-Amp
is 5 103 , otherwise Op-Amp is ideal is_________. (Rounded upto three decimal place)
Question 11
 V 
Consider the Op-Amp circuit shown in below figure is ideal, the value of the voltage gain  AV  0  of
 Vi 
the circuit is________. (Rounded upto one decimal place)

Question 12
Consider the Op-Amp circuit shown in below figure. The open loop gain the Op-Amp is 2.5 103
otherwise Op-Amp is ideal. The value of output voltage ‘ V0 ’ (in V) such that input voltage is  0.80V is
_________. (Rounded upto three decimal place)

..Common Data for Q.13 & Q.14..


For the circuit shown in below figure, the input voltage is Vi  5 V .
TARGET : GATE 2025/26, DPP-05 4 GATE ACADEMY®
Question 13
If output voltage is 2.5 V, the value of finite open-loop differential gain of the Op-Amp is_________.
(Rounded upto one decimal place)
Question 14
If the open-loop differential gain of the Op-Amp is 5000, the value of output voltage V0 (in V)
is_________. (Rounded upto one decimal place)
Question 15
Consider the ideal non-inverting Op-Amp circuit shown in below figure. The value of the output voltage
V0 (in V) such that VI  0.2 V and VI  0.3V are respectively is_________. (Rounded upto one decimal
1 2

place)

..Common Data for Q.16 & Q.17..


Consider the circuit shown in below figure the Op-Amp is ideal.

Question 16
 V 
The value of closed loop voltage gain  AV  0  of the circuit is________. (Rounded upto one decimal
 Vi 
place)
Question 17
The value of output voltage ‘ V0 ’ (in V) such that input voltage is 0.25 V is________. (Rounded upto one
decimal place)
GATE ACADEMY® 5 TARGET : GATE 2025/26, DPP-05
..Common Data for Q.18 & Q.19..
Consider the circuit shown in below figure the Op-Amp is ideal.

Question 18
 V 
The value of closed loop voltage gain  AV  0  of the circuit is________. (Rounded upto one decimal
 Vi 
place)
Question 19
The value of output voltage ‘ V0 ’ (in V) such that input voltage is 0.25 V is________. (Rounded upto one
decimal place)

..Common Data for Q.20 & Q.21..


Consider the circuit shown in below figure the Op-Amp is ideal.

RL  1 k
V0
Vi iL
R1  9 k

Question 20
If the Op-Amp saturates at 10 V , the maximum value of ‘ Vi ’ (in V) before the Op-Amp saturates
is________. (Rounded upto one decimal place)
Question 21
If the Op-Amp saturates at 10 V , the maximum value of ‘ iL ’ (in mA) before the Op-Amp saturates
is________. (Rounded upto one decimal place)

..Common Data for Q.22 & Q.23..


Consider the circuit shown in below figure the Op-Amp is ideal.
TARGET : GATE 2025/26, DPP-05 6 GATE ACADEMY®
Question 22
The value of output voltage ‘ V0 ’ (in V) such that input voltage is –5 V is________. (Rounded upto one
decimal place)
Question 23
The value of output voltage ‘ V0 ’ (in V) such that input voltage is 3 V is________. (Rounded upto one
decimal place)
Question 24
Consider the ideal Op-Amp circuit shown in below figure, the value of (V0  V0 ) (in V) such that input
1 2

voltage is 0.8 V is_________. (Rounded upto one decimal place)

Question 25
V0 ( s)
For an ideal operational amplifier in the circuit shown in figure, the transfer function is
Vi ( s)

1 1  sRC
(A) (B)
sRC sRC
sRC sRC
(B) (D)
1  sRC 1  2 sRC
GATE ACADEMY® 7 TARGET : GATE 2025/26, DPP-05
Question 26
In the circuit shown in below figure, if Vi  sin t , the voltage V0 is

  1  
(A) 2 sin  t   (B) sin  t  
 4 2  4
1    
(C) sin  t   (D) 2 sin  t  
2  4  4
Question 27
A source is characterized by VS  2 V in series with RS  1 k is connected to the terminal V of the
circuit shown in figure. Value of iL in mA considering Op-Amp as an ideal device is ________.

Question 28
Pick up the correct relationship for the circuit shown in figure.

R2
(A) e0  e1 (B) e0  e1
R1
e1 e
(C) I (D) I 1
R2 R1
Question 29
For the Op-Amp shown in figure input resistance is
TARGET : GATE 2025/26, DPP-05 8 GATE ACADEMY®
(A) R || Z (B) – Z
(C) Z (D)  ( R || Z )
Question 30
Neglecting the Op-Amp circuit errors, output voltage of the amplifier shown is

(A) 2 V (B) 3 V
(C) 1 V (D) 4 V
Question 31
When the switch S2 is closed, the gain of the programmable gain amplifier shown in the following figure
is

(A) 0.5 (B) 2


(C) 4 (D) 8
Question 32
If the value of the resistance R in the following figure is increased by 50 %, then voltage gain of the
amplifier shown in the figure will change by

(A) 50 % (B) 5 %
(C) – 50 % (D) negligible amount
GATE ACADEMY® 9 TARGET : GATE 2025/26, DPP-05
Question 33
In the circuit given below, the Op-Amp is ideal. The input vx is a sinusoid. To ensure v y  vx , the value
of C N in picofarad is ________.

Question 34
Consider the circuit shown in below figure, the value of input resistance ' Rin ' (in k ) is ______.
(Rounded upto one decimal place)
Vs
V0

7.5 k

120 k
15 k
Rin


TARGET : GATE 2025/26
Analog Electronics
Topic : Operational Amplifier DPP : 06

..Common Data for Q.1 & Q.2..


Three inverting amplifiers, each with R2  150 k and R1  15k are connected in cascade. Each op-amp has a
low-frequency gain of A0  5 104 and a unity-gain bandwidth of fT  1.5 MHz . Where resistance R2 is used as
a feedback resistor.
Question 1
The value of low-frequency closed-loop gain of the overall system is _________(rounded upto two
decimal places).
Question 2
The value of the -3 dB frequency (in Hz) overall system is_________(rounded upto two decimal places).

..Common Data for Q.3 to Q.5..


An inverting amplifier circuit has a voltage gain of -25. The op-amp used in the circuit has a low-frequency
voltage gain of 5 104 and a unity-gam bandwidth of 1 MHz.
Question 3
The value of dominant pole frequency (in Hz) of the op-amp is_________(rounded upto two decimal
places).
Question 4
The value of small-signal bandwidth. f 3 dB (in kHz) of the inverting amplifier is_________(rounded upto
two decimal places).
Question 5
The value of magnitude of the closed-loop voltage gain at 0.5 f 3 dB is_________(rounded upto two
decimal places).
Question 6
An audio amplifier system, using a non-inverting op-amp circuit, needs to have a small-signal bandwidth
of 20 kHz. The open-loop low-frequency voltage gain of the op-amp is 105 and the unity-gain bandwidth
is 1 MHz. The value of maximum closed-loop voltage gain that can be obtained for these specifications
is_________(rounded upto two decimal places).
TARGET : GATE 2025/26, DPP-06 2 GATE ACADEMY®
Question 7
If an op-amp has a slew-rate of 5 V/s is. The value of full-power bandwidth (in kHz) for a peak output
voltage of 5 V is_________(rounded upto two decimal places).
Question 8
An op-amp with a slew rate of 8 V/s is driven by a 250 kHz sine wave. The value of maximum output
amplitude (in volt) at which slew-rate limiting is reached is_________(rounded upto two decimal places).
Question 9
An amplifier system is to be designed to provide an undistorted 10 V peak sinusoidal signal at a frequency
of f  12 kHz . The value of minimum slew rate (in V/s) required for the amplifier is
_________(rounded upto two decimal places).
Question 10
Consider the circuit shown in below, the value of common mode rejection ratio of the circuit
is_________(rounded upto two decimal places).
+ +
Vd V0  8 V V0  12 mV
– –
Vi1  0.5 mV Vi1  1 mV
Vi 2   0.5 mV Vi2  1 mV

Fig. Differential mode operation Fig. Common mode operation

Question 11
Consider the circuit shown in below figure. The value of ratio of resistance ( R2 /R1 ) is required for
oscillation of the circuit is ________ (rounded upto one decimal place).
R2

R1

v0

R L
L R

Question 12
The value of output voltage (in mV) of an op-amp for input voltages of Vi1  150 V and Vi 2  140 V .
The amplifier has a differential gain of Ad = 4000 and value of CMRR is 100_________(rounded upto
two decimal places).
GATE ACADEMY® 3 TARGET : GATE 2025/26, DPP-06
Question 13
Consider a non-inverting amplifier shown in below figure, the value of output voltage (in volt) of the
circuit is_________(rounded upto two decimal places).
33k R f  330 k
V1  0.2 V

22k
V2   0.5 V
V0
12k
V3  0.8 V

Question 14
Consider a circuit shown in below figure, the value of voltage 'V2  V3 ' (in volt) of the circuit
is_________(rounded upto two decimal places).
200k

20k

V2

V1  0.2 V V3

200k

10 k

Question 15
Consider a circuit shown in below figure, the value of output voltage (in volt) of the circuit
is_________(rounded upto two decimal places).
100k
V1  0.1V 20k

10k V0
400 k
20k
TARGET : GATE 2025/26, DPP-06 4 GATE ACADEMY®
Question 16
Consider a circuit shown in below figure, the value of output voltage (in volt) of the circuit
is_________(rounded upto two decimal places).
600 k
300 k
15k
25 mV

30 k
30 k
20 mV + V0
+

15 k

Question 17
The value of total offset voltage (in mV) for the circuit shown in below figure, for an op-amp with
specified values of input offset voltage VIO  6 mV and input offset current I IO  120 nA
is_________(rounded upto two decimal places).
200 k

2 k
VI
V0
+

2 k

Question 18
For an op-amp having a slew rate of SR  2.4 V/μs , the value of maximum closed-loop voltage gain that
can be used when the input signal varies by 0.3 V in 10  sec is_________(rounded upto two decimal
places).
Question 19
The value of cutoff frequency (in kHz) of a first-order low-pass filter shown in below figure
is_________(rounded upto two decimal places).
10k 10k

2.2k V0
Vin

0.05 F
GATE ACADEMY® 5 TARGET : GATE 2025/26, DPP-06
Question 20
The value of cutoff frequency (in kHz) of a low-pass filter shown in below figure is_________(rounded
upto two decimal places).
10k 10k

20 k 20k V0
Vin

0.02 F 0.02 F

Question 21
Consider the circuit shown in below figure, the value of the sum of the lower and upper cutoff frequencies
(in kHz) of the band pass filter is_________(rounded upto two decimal places).
4.1k 4.1k 20k 20k

20k
0.05 F V0
Vin

10k 0.02 F

Question 22
Consider the circuit shown in below figure, given parameters of circuit are R1  1 k , R2  10 k ,
RA  1 M , RB  10 k , vIN  1 V , and vx  0.1 V , the value of open-loop gain of the Op-amp ‘ AO ’
is_________(rounded upto two decimal places).

R1 Vx R2

RA
VIN +–
RB VOU T
TARGET : GATE 2025/26, DPP-06 6 GATE ACADEMY®
..Common Data for Q.22 & Q.23..
A particular op-amp has parameter AO  105 and rin  1 M . If R2  19 k and R1  1 k
I in

vin Rin v rin


V0

A0v
R2

R1

Question 23
The value of closed-loop gain of the circuit is_________(rounded upto two decimal places).
Question 24
The value of input resistance (in M  ) is_________(rounded upto two decimal places).
Question 25
An op-amp has an open-loop gain of 2 104 and a dominant open-loop breakpoint at 12Hz. A non-
inverting amplifier is made with R2  270 k and R1  5.6 k where R2 is the feedback resistor. The
value of bandwidth (in kHz) of the closed-loop amplifier is_________(rounded upto two decimal places).
Question 26
Consider the circuit shown in below Figure, the output of Op-Amp is V0 when switch ‘S’ is open and the
1

output of Op-Amp is V0 , when switch ‘s’ is closed. The value of sum of voltage
2
V
01  V02  (in volt) is
________. (Rounded upto two decimal place)
R1  5k R2  50k
V1  1V

V0

R3  10k R4  10k
S

Question 27
Consider is low pass active filter shown in below figure, the value of the gain at 100 kHz is _________.
(Rounded upto two decimal place)
10 k
Vin
V0
1000 pF

100k
10k
GATE ACADEMY® 7 TARGET : GATE 2025/26, DPP-06
Question 28
Consider the circuit shown in below figure which is work as a active filter, which option is correct.
R4

C1 C2 V0

R3
R1
Vin
C3 R2

(A) Low pass filter (B) Band pass filter


(C) Band stop filter (D) All pass filter
Question 29
Consider the second-order low-pass filter circuit shown in below figure, if the filter were to have cut-off
frequency of 10 kHz, Q-factor of 0.707. The value of capacitor C 2 (in nF) is ________. (Rounded upto
two decimal place)
C1  1.126 nF

R3  20 k

R1  10 k V0
Vin
R2  20 k
C2

Question 30
The relaxation oscillator circuit shown in below figure, operates on a power supply voltage of 15 V .
Given that the op-amp has positive and negative saturation output voltage of 13 A and 13 A
respectively. The value of frequency (in kHz) of the output wave form is _________. (Rounded upto two
decimal place)
RF  10 k

V0
C  0.01 F

R2  10 k

R1  47 k
TARGET : GATE 2025/26, DPP-06 8 GATE ACADEMY®
Question 31
Given figure shown in below an Op-Amp based constant current source. The value of resistor R  in ohms 
, so that a current of 25 mA flows through the Light Amplification by stimulated emission of radiation
(LASER) diode is _______. (Rounded upto two decimal place)
15 V

15 V

2.5 V
15 V

Laser diode

Question 32
Consider the circuit shown in below figure is a low pass filter circuit. The value of cut-off frequency and
the gain value at four times the cut-off frequency are respectively.
R  10k
Vin
V0
C  1000 pF

R1  100k
R2  10 k

(A) 15.7 kHz, 8.8 dB (B) 15.9 kHz, 8.8 dB


(C) 15.1 kHz, 8.8 dB (D) 15.9 kHz, 8.9 dB
Question 33
For the comparator circuit shown in below figure, diodes D1 and D2 have forward-biased voltage drop
equal to 0.7 V each. What is the state of LED-1 and LED-2 (whether ON or OFF) when the switch SW-1
is in position-A?
SW  1
A
V R1

V V0
B
D1 D2

LED  1 LED  2

(A) LED-1 ON, LED-2 OFF (B) LED-1 ON, LED-2 ON


(C) LED-1 OFF, LED-2 ON (D) LED-1 OFF, LED-2 OFF
GATE ACADEMY® 9 TARGET : GATE 2025/26, DPP-06
Question 34
Consider the circuit shown in below figure, Given that the Op-Amp is ideal and R2 / R1  5 The
mathematical operation performed by the amplifier circuit is.
R1 R2

R2
R1

Vs1
V0
Vs 2

(A) Subtractor (B) Multiplier


(C) Adder (D) Divider
Question 35
Consider a transfer characteristics of some op-amp circuit. It could possibly be
V0

VSAT

Vi
0

VSAT

(A) an inverting comparator (B) a non-inverting comparator


(C) an inverting amplifier with hysteresis (D) a non-inverting amplifier with hysteresis
Question 36
For the Op-Amp circuit shown in below figure, the value of sum of resistance R1 and R2 (in kHz) such
that output voltage of Op-Amp is v0  5va  3vb _________. (Rounded upto two decimal place)
250 k

R1
va
R1 v0
vb

R2
TARGET : GATE 2025/26, DPP-06 10 GATE ACADEMY®
Question 37
Consider the circuit shown in below figure. The value of ratio of resistance ( R2 /R1 ) is required for
oscillation of the circuit is ________ (rounded upto one decimal place).
R2

R1

v0

C R
R C

Question 38
Consider the circuit shown in below figure, the value of output voltage V0 t  (in mV) at t  2 msec is
_________. (Rounded upto two decimal place)
1 F

R1  250 k
1 u t  V
v0 t 
1 u t V
R2  500 k

Question 39
Consider the circuit shown in below figure, the value of the current ' I L ' (in mA) is __________. (Rounded
upto two decimal place)
RF  100 k

vin  2 V RL
R1  10 k v2
IL
R2  50 k

..Common Data for Q.40 to Q.42..


For the amplifier circuit shown in below figure,

RS  50 k v0

RL  1 k
vi
GATE ACADEMY® 11 TARGET : GATE 2025/26, DPP-06
Question 40
The value of ideal closed-loop voltage gain is ________. (Rounded upto two decimal place)
Question 41
The actual value of closed-loop voltage gain if the open-loop gain is Aod  150,000 ________. (Rounded
upto two decimal place)
Question 42
The value open-loop gain such that actual closed-loop gain is within 1 percent of the ideal value
is________. (Rounded upto two decimal place)
Question 43
Consider the circuit shown in below figure. The output current of the op-amp is 1.2 mA and the transistor
current gain is   75 . The value of resistance R (in  ) is_________. (Rounded upto two decimal)
25 V

10 V +

Question 44
Consider the adjustable gain difference amplifier circuit shown in below figure. Variable resistor RV is
used to vary the gain. The value of output voltage V0 , as a function of V I1 and VI 2 , is given by
R1 R2 R2
VI1

V0
VI2
R1
RV

R2 R2

2 R2  R2  2 R2  R2 
(A) V0  1 VI  VI1 
r1  RV  2
(B) V0  1 VI  VI1 
r1  RV  2
2 R2  R2  2 R2  R2 
(C) V0  1 VI  VI2 
r1  RV  1
(D) V0  1 VI  VI2 
r1  RV  1
TARGET : GATE 2025/26, DPP-06 12 GATE ACADEMY®
Question 45
Consider the circuit shown in below figure. Assume ideal op-amp are used. The input voltage is
V 
VI  0.5sin t . The value of the ratio of the voltage  OB  is ________. (Rounded upto two decimal
 VOC 
place)
40 k

12 k

12 k
+
+
VOB

V0
30 k
Vi
12 k

12 k
+
VOC

..Common Data for Q.46 & Q.47..

Consider the circuit shown in below Figure, is a first-order low-pass active filter.

C 2  1 F

R2  10 k
R1  1 k
Vi
V0

Question 46
The value of DC voltage of the circuit is __________. (Rounded upto two decimal place)
Question 47

The value of frequency (in Hz) the magnitude of the voltage gain a factor of 2 less that the DC value is
known as 3  dB frequency is ___________. (Rounded upto two decimal place)
GATE ACADEMY® 13 TARGET : GATE 2025/26, DPP-06
..Common Data for Q.48 & Q.49..
Consider the circuit shown in below Figure, is a first-order low-pass active filter.
C2

R2
R1
Vi
V0

Question 48
The value of sum of the resistance ' R1  R2 ' (in k ) such that input resistance is 20 k and the low
frequency gain is 15 , and 3 dB frequency is 5 kHz ________. (Rounded upto two decimal place)
Question 49
The value of capacitance C 2 (in pF) such that input resistance is 20 k and the low frequency gain is
15 , and 3 dB frequency is 5 kHz ________. (Rounded upto two decimal place)
Question 50
In the circuit shown in below figure, assume that Q1 and Q2 are identical transistors. The value of output
voltage V0 (in volt) is ________. (Rounded upto two decimal place)
Q1 Q2

R1  10 k R2  20 k
V1  10 V V2  20 V

333 k

20 k

V0
20 k

333 k

..Common Data for Q.51 to Q.54..


Because of a manufacturing error, the open-loop gain of each op-amp in the circuit in Figure, is only AOL  100 .
The open-loop input and output resistance are Ri  10 k and R0  1 k , respectively.
TARGET : GATE 2025/26, DPP-06 14 GATE ACADEMY®
1 k
Rif 100 

1 k
100 Rof
V0
1 V0
2
VI

Question 51
The value of input resistance Rif (in  ) is ___________. (Rounded upto two decimal place)
Question 52
The value of Output resistance R0 f (in  ) is ___________. (Rounded upto two decimal place)
Question 53
The value of Actual closed loop gain of the circuit is ___________. (Rounded upto two decimal place)
Question 54
The value of the ratio of Actual closed loop gain to the ideal closed loop gain is ___________. (Rounded
upto two decimal place)
Question 55
An inverting amplifier has parameters R2  150 k and R1  15 k . Bias current of 2 A are leaving
each Op-Amp terminal, otherwise Op-Amp is ideal. The value of output voltage (in volt) if the input
voltage is 20 mV is _______. (Rounded upto one decimal place)

..Common Data for Q.56 to Q.57..

For the circuit shown in below figure, the Op-Amp are ideal except that the Op-Amps have bias current if
I B  3 A entering each op-amp terminal.

50 k

10 k
V02

V01

RA 20 k

VI
20 k
V03

RB
GATE ACADEMY® 15 TARGET : GATE 2025/26, DPP-06
Question 56
The value of sum of voltage ‘ V0  V0  V0 ’ (in Volt) for which input voltage VI  0 and resistance
1 2 3

RA  RB  0 is _________. (Rounded upto two decimal place)


Question 57
The values of sum of resistance  RA  RB  (in k ) for input bias current compensation is _____________.
(Rounded upto two decimal place)

..Common Data for Q.58 & Q.60..


Consider the band pass filter shown in below Figure, given that circuit parameters,
C  0.1 F, R1  85 k, R2  R3  300 , R4  3 k and R5  30 k .
R1

R1

C
C
R4 R5
Vi R2
R5

V0

Question 58
The value of magnitude of maximum voltage gain AV (max) of the circuit is _________. (Rounded upto
two decimal place)
Question 59
The value of frequency to (in kHz) at which AV (max) occurs is ________. (Rounded upto two decimal
place)
Question 60
The value of 3  dB frequency (in kHz) is ___________. (Rounded upto two decimal place)
Question 61
Consider circuit shown in below Figure, the value of cut-off frequency (in rad / sec ) of the circuit is.
R2

R1 C

V0
Vi

1 1
(A) (B)
R2C R1C
R2
(C) R1C (D)
R1
TARGET : GATE 2025/26, DPP-06 16 GATE ACADEMY®
Question 62
Consider circuit shown in below Figure, the value of cut-off frequency (in rad / sec ) of the circuit is.
C R2

R1

V0
Vi

1 1
(A) (B)
R2C R1C
R2
(C) R1C (D)
R1
Question 63
The circuit shown in below figure, is a band pass filter. If R1  10 k . The value of resistance R2 (in k
) such a that magnitude of the midband gain is 50 and the cutoff frequency are 200 Hz and 5 kHz is
___________. (Rounded upto two decimal place)
C2

R1 C1 R2
Vi
V0

Question 64
The saturated output voltage are VP for the Schmitt trigger shown in below Figure. If
VP  12 V, VREF  10 V and R3  10 k , The value of sum of resistance ‘ R1  R2 ’ (in kHz) such that
switching point is VS  5 V and the hysteresis width is 0.2 V is _________. (Rounded upto two decimal
place)
Vi
V0
R1

R2
R3

VREF

..Common Data for Q.65 & Q.66..


Consider the circuit shown in below figure, given that the reverse breakdown Zener voltage is VZ  5.6 V and the
forward diode voltage is V  0.6 V .
GATE ACADEMY® 17 TARGET : GATE 2025/26, DPP-06

V0
Vi
20 k

DZ1 DZ2
Question 65
The plot of the voltage transfer characteristics of the comparator circuit is assuming the open-loop gain in
infinite.
(A) if the saturated output voltage is VP  6.2V, then the circuit behave as a comparator.
(B) if the saturated output voltage is VP  6.2V, then the circuit behave as a comparator.
(C) if the saturated output voltage is VP  6.2V, then the output will flip to either  VP or  VP and the
input no control.
(D) if the saturated output voltage is VP  6.2V, then the output will flip to either  VP or  VP and the
input no control.
Question 66
The plot of the voltage transfer characteristics of the comparator circuit is assuming the open-loop gain in
infinite and input voltage is 2.5 V.
(A) Circuit work as a comparator as long as V01  8.7 V and V02  – 3.7 V otherwise input has no control.
(B) Circuit work as a comparator as long as V01  8.7 V and V02  – 3.7 V otherwise input has no control.
(C) Circuit work as a comparator as long as V01  8.7 V and V02  – 3.7 V otherwise input has no control.
(D) Circuit work as a comparator as long as V01  8.7 V and V02  – 3.7 V otherwise input has no control.
Question 67
Consider the circuit shown in below figure. The value of ratio of resistance ( R2 /R1 ) is required for
oscillation of the circuit is ________ (rounded upto one decimal place).
R2

R1

v0

R C
C R

..Common Data for Q.68 & Q.69..


Consider the Schmit trigger shown in below Figure. The saturated output voltage of the op-amp are VH  10 V
and VL  10 V . Assume the diode turn-on voltage is 0.7 V. The range of the input voltage is 2  VI  2 V .
TARGET : GATE 2025/26, DPP-06 18 GATE ACADEMY®
R3  75 k 
I R3
R1  25 k 
R2  20 k 
V0
VI IR 2
D1 D2

ID ID
2
1

Question 68
The value of hysteresis voltage is ________. (Rounded upto two decimal place)
Question 69
The value of sum of current ' I D  I D  I R  I R ' (in mA) if input voltage is 2 V is __________. (Rounded
1 2 2 3

upto two decimal place)


Question 70
The parameters of the transistor shown in below figure are   80 and VEB  on   0.6 V . The Zener diode
is ideal with VZ  6.8V and the op-amp is ideal. The value of load current ‘ I L ’ (in mA) is ____________.
(Rounded upto two decimal place)

V  20

R2  5 k 
+
VZ D1

Q

V0
IL
R1  10 k  RL

..Common Data for Q.71 to Q.74..


The inverting op-amp shown in below figure has parameters R1  25 k , R2  100 k and Aod  5  103 . The
input voltage is from an ideal voltage source whose value is VI  1.0000 V .
R2

R1
Vi
V0

Aod V2  V1 
GATE ACADEMY® 19 TARGET : GATE 2025/26, DPP-06
Question 71
The value of closed-loop voltage gain of the circuit is ________. (Rounded upto two decimal place)
Question 72
The value of actual output voltage (in volt) of the circuit is ________. (Rounded upto two decimal
place)
Question 73
What is the percentage difference between the actual output voltage and the ideal output voltage is
________. (Rounded upto two decimal place).
Question 74
What is the voltage (in mV) at the inverting terminal of the op-amp is ________. (Rounded upto two
decimal place).

..Common Data for Q.75 & Q.76..


An op-amp with an open-loop gain of Aod  7 103 is to be used in an inverting op-amp circuit. Let R2  100 k
and R1  10 k . If the output voltage is V0  7 V .
Question 75
The value of input voltage (in volt) is ________. (Rounded upto two decimal place).
Question 76
The voltage (in mV) at the inverting terminal of the op-amp is ________. (Rounded upto two decimal
place).

..Common Data for Q.77 & Q.78..


For the ideal inverting op-amp circuit with T-network, shown in figure, the circuit parameters are
R1  10 k, R2  R3  50 k , and R4  5 k .

R2 R3

R4

R1
Vi
V0

Question 77
The value of closed-loop voltage gain is ________. (Rounded upto two decimal place)
Question 78
The value of resistance R4 (in k ) to produce a voltage gain is -100 ________. (Rounded upto two
decimal place)

TARGET : GATE 2024/25
Analog Electronics
Topic : Current Mirror Circuit DPP : 07
Question 1
Consider a MOS current mirror circuit shown in below figure, given that parameter of MOSFET are
Vss  10 V , K n  250 A/V 2 , VTN  1 V,   0.0133 V 1 and I REF  150 A . The value of current ‘ I 0 ’ (in
mA) is _________. (Rounded upto one decimal place)

I REF I0

M1 M2

Vss

..Common Data for Q.2 & Q.3..


Consider a MOS current mirror circuit shown in below figure, given that parameter of MOSFET
VTN  1 V, K n'  25 A/V 2 , and I REF  50 A .

I REF I0

W  3 W  25
     
 L 1 1  L 2 1

15 V
Question 2
The value of the mirror ratio of the circuit when channel length modulation is zero ______. (Rounded
upto two decimal place)
TARGET : GATE 2024/25, DPP-07 2 GATE ACADEMY®
Question 3
The value of the mirror ratio of the circuit when channel length modulation is 0.02 V1 ______. (Rounded
upto two decimal place)

..Common Data for Q.4 & Q.5..


Consider a MOS current mirror circuit shown in below figure, given that parameter of MOSFET
VTN  1 V, K n'  25 A/V 2 , and I REF  50 A .
10 V

I REF
I0

W  5 W  2
     
 2 1
L  L 2 1

15 V
Question 4
The value of the mirror ratio of the circuit when channel length modulation is zero ______. (Rounded
upto two decimal place)
Question 5
The value of the mirror ratio of the circuit when channel length modulation is 0.02 V1 ______. (Rounded
upto two decimal place)

..Common Data for Q.6 & Q.7..


Consider a MOS and BJT current mirrors circuit shown in below figure, given that parameter of MOSFET and
BJT are VGS  2 V, VDS 2  10 V  VCE 2 ,   0.02 V 1 , VA  50 V , and   100 . Assume MOSFET M1 & M 2 and
both BJT Q1 & Q2 are identical.

I REF I0
I REF I0

M1 M2
Q1 Q2

Vss VEE
Question 6
The value of the mirror ratio of the MOS current mirror circuit is ________. (Rounded upto two decimal
place)
Question 7
The value of the mirror ratio of the BJT current mirror circuit is ________. (Rounded upto two decimal
place)
GATE ACADEMY® 3 TARGET : GATE 2024/25, DPP-07
..Common Data for Q.8 to Q.10..
Consider a BJT current mirror circuit shown in below figure,
Question 8 15 V

The value of mirror ratio such that VA   and    is __________.


(Rounded upto two decimal place) I REF  1 A I 0  0.5 A

Question 9
The value of mirror ratio such that VA   and   75 is
__________. (Rounded upto two decimal place) A 0.5 A
Question 10
The value of mirror ratio such that VA  60 and   75 and
VB  0.7 V is __________. (Rounded upto two decimal place)

..Common Data for Q.11 to Q.13..


Consider a BJT current mirror circuit shown in below figure,
Question 11 15 V

The value of mirror ratio such that VA   and    is __________.


I REF  2 A I0  5 A
(Rounded upto two decimal place)
Question 12
The value of mirror ratio such that VA   and   75 is __________.
(Rounded upto two decimal place)
Question 13
The value of mirror ratio such that VA  60 and   75 and VB  0.7 V
is __________. (Rounded upto two decimal place)

..Common Data for Q.14 & Q.15..


Consider the Widlar current mirror circuit shown in below figure,

I REF I0

Q1, AE1 Q2 , AE 2

Question 14
The value of resistance R (in k ) is required to set I 0  25 A if I REF  100 A and AE 2  5 AE1 is
_________. (Rounded upto one decimal place)
TARGET : GATE 2024/25, DPP-07 4 GATE ACADEMY®
Question 15
The value of output current ‘ I 0 ’ (in A ) the Widlar source if I REF  100 A, R  100  and AE 2  10 AE1
is ___________. (Rounded upto two decimal place)
Question 16
Consider the MOS current mirror circuit shown in below figure, the value of output current I 0 (in A )
such that I REF  200 A, R  2 k , and K n 2  10, K n1  250 A/V 2 is _________. (Rounded upto two
decimal place)
VDD

I REF I0

M1 M2

..Common Data for Q.17 to Q.19..


Consider the Widlar current mirror circuit shown in below figure, if R1  50 k, RE  3 k, V   5 V , and
V   5 V . The transistor parameters are   120 and VBE1  on   0.7 V .
V

IRE F R1
I0

Q1 Q2

RE

V
Question 17
The value of the current ‘ I REF ’ (in mA) is _________ (Rounded upto two decimal places).
Question 18
The value of the current ‘ I 0 ’ (in A) is _________ (Rounded upto two decimal places).
Question 19
The value of the base to emitter of transistor Q2 (in volt) is _________ (Rounded upto two decimal places).
GATE ACADEMY® 5 TARGET : GATE 2024/25, DPP-07
..Common Data for Q.20 & Q.21..
Consider the circuit shown in below figure, let I REF  200 A . The transistor parameters are

K n1  K n 2  0.2 mA/V 2 , VTN 1  VTN 2  0.5 V and 1   2  0 .

V 5V

IRE F
I0

M1 M2

RS

Question 20
The value of the current ‘ I 0 ’ (in A) such a that Rs  10 k is ________ (Rounded upto two decimal
places)
Question 21
The value of the resistance ‘ Rs ’ (in k ) such a that I 0  0.5 I REF is ________ (Rounded upto two decimal
places)

..Common Data for Q.22 to Q.24..


Consider the circuit shown in below figure, the transistor M 2 sources a bias current to a load circuit. Assume the
circuit is biased at V   5 V and V   5 V , and assume the transistor parameters are,

VTP  0.5 V, k p'  50 A/V2 , W / L 1  W / L 2  15, W / L 3  3 V

and   0 .
Question 22
M1 M2
The value of the current ‘ I REF ’ (in mA) is _________. (Rounded upto two
decimal places). IRE F

Question 23 I0
The value of the current ‘ I 0 ’ (in mA) is _________. (Rounded upto two
decimal places). M3

Question 24
The value of the voltage ‘ VSD 2 ’ (sat) (in Volt) is _________. (Rounded upto
two decimal places). V
TARGET : GATE 2024/25, DPP-07 6 GATE ACADEMY®
..Common Data for Q.25 to Q.27.
Consider the circuit shown in below figure, the transistor M 2 sources a bias current to a load circuit. Assume the
circuit is biased at V   5 V and V   5 V . The transistor parameters are
VTP  1.2 V, k p'  80 A/V2 ,   0, W / L 1  W / L 2  25 , and W / L 3  W / L 4  4 .
V

M1 M2

IRE F I0

M3

M4

V
Question 25
The value of the current ‘ I REF ’ (in mA) is _________. (Rounded upto two decimal places).
Question 26
The value of the current ‘ I 0 ’ (in mA) is _________. (Rounded upto two decimal places).
Question 27
The value of the voltage ‘ VSD 2 ’ (sat) (in Volt) is _________. (Rounded upto two decimal places).

..Common Data for Q.28 & Q.29..


A Wilson current mirror is shown in Figure, the parameters are : V   5 V,V   5 V and I REF  80 A .
The transistor parameters are : VTN  1 V, K n  80 A/V 2 and   0.02 V 1 .
V

IRE F I0
VD 3
M3

M1 M2

V
GATE ACADEMY® 7 TARGET : GATE 2024/25, DPP-07
Question 28
The value of the current I 0 (in A ) such a that VD 3  1 V is ________ (Rounded upto two decimal
places).
Question 29
The value of the current I 0 (in A ) such a that VD 3  3 V is ________ (Rounded upto two decimal
places).
Question 30
Consider the multi transistor current source shown in below figure, the V 5V

transistor parameters are VTN  0.7 V, kn'  80 A/V 2 and   0 . IRE F

Assume M 3 , M 4 and M 5 are identical. The value of the width-to-length


M5
ratio of the transistor M 1 and M 4 of the circuit such that
I REF  0.1 mA, I 01  0.2 mA and I 02  0.3 mA .
W  W  M4
(A)    5.35,    2.68
 L 1  L 4 I01 I02
W  W 
(B)    2.68,    5.35 M3 M2
L 1  L 4 M1
W  W 
(C)    6.45,    5.35
L 1  L 4
W  W 
(D)    2.68,    6.45
 L 1  L 4 V
Question 31
For the circuit shown in Figure, I REF  100 A . The transistor parameters are
VTN  0.4 V, VTP  0.4 V, kn'  100 A/V 2 , k p'  60 A/V2 , and I REF
M3 M4

n   p  0 . The transistor width-to-length ratios are I0

W / L 1  4, W / L 2  2.5, W / L 3  6 and W / L 4  4 .
M1 M2
The value of the ‘ I 0 ’ (in A ) is __________ (Rounded upto two decimal
places).


TARGET : GATE 2025/26
Analog Electronics
Topic : BJT & MOSFET Amplifier DPP : 08

..Common Data for Q.1 to Q.3..


The parameters of each transistor in the circuits shown in below figure are   120 and I CQ  0.5 mA .
V V
Ri Ri

RB  50 k

Ri RB  100 k
RC  4 k

fig. (a)
fig. (c)
fig. (b)
Question 1
The value of input resistance ‘ Ri ’ (in k ) in fig. (a) is __________ (Rounded upto two decimal places).
Question 2
The value of input resistance ‘ Ri ’ (in k ) in fig. (b) is __________ (Rounded upto two decimal places).
Question 3
The value of input resistance ‘ Ri ’ (in k ) in fig. (c) is __________ (Rounded upto two decimal places).

..Common Data for Q.4 to Q.6..


The parameters of each transistor in the circuits shown in below figure are   130, VA  80 V and I CQ  0.2 mA
V V V

RC  10 k RC  10 k
R0
R0 RB  100 k RB  50 k
R0
+
VBB + + RL  5 k
– RC  4 k VB B VBB
– –

fig. (a) fig. (b) fig. (c)


TARGET : GATE 2025/26, DPP-08 2 GATE ACADEMY®
Question 4
The value of output resistance ‘ R0 ’ (in k ) in fig. (a) is __________ (Rounded upto two decimal places).
Question 5
The value of output resistance ‘ R0 ’ (in k ) in fig. (b) is __________ (Rounded upto two decimal places).
Question 6
The value of output resistance ‘ R0 ’ (in k ) in fig. (c) is __________ (Rounded upto two decimal places).

..Common Data for Q.7 & Q.8..


The parameters of the transistor in the circuit shown in below figure are   150 and VA   .
V  5 V

R1 RC  1.2 k
CC
V0

R2 RE  0.2k

V   5 V
Question 7
The value of sum of resistance ‘ R1  R2 ’ (in k ) to obtain a bias-stable circuit with the Q-point in the
center of the load line is __________ (Rounded upto two decimal places).
Question 8
The value of the small-signal voltage gain of the circuit is __________ (Rounded upto two decimal
places).
Question 9
The signal source shown in below figure is vs  5sin t mV . The transistor parameters are   120 and
VA   . The value of small-signal voltage gain  Av  v0 / vs  such that I CQ  0.25 mA and VCEQ  3 V is
__________ (Rounded upto two decimal places)
V  5 V

RC
CC
RS  2.5 k V0

Vs RL  5 k
RE CE

V   5 V
GATE ACADEMY® 3 TARGET : GATE 2025/26, DPP-08
..Common Data for Q.10 & Q.11..
The parameters of the transistor in the circuit shown in below figure are   100
V 5V

RC

RS  100  CC V0

Vs RB  10 k
I  0.35 mA CE

V   5 V
Question 10
The value of resistance RC (in k ) such that VCEQ  3.5 V is __________ (Rounded upto two decimal).
Question 11
The value of small-signal voltage gain Av  v0 / vs of the circuit is __________ (Rounded upto two
decimal places).

..Common Data for Q.12 to Q.15..


The circuit shown in below figure, the transistor parameters are   80 and VA  80 V .
V 9 V

RE

RS  2 k CE

v0
vs CC
RC RL

V   9 V

Question 12
The value of resistance RE (in k ) such that I EQ  0.75 mA is _________ (Rounded upto two decimal
places).
Question 13
The value of resistance RC (in k ) such that VECQ  7 V is ___________ (Rounded upto two decimal
places).
TARGET : GATE 2025/26, DPP-08 4 GATE ACADEMY®
Question 14
The value of small-signal voltage gain Av  v0 / vs . Such that  RL  10 k is ________ (Rounded upto
two decimal places).
Question 15
The value of input impedance (in k ) seen by the signal source vs is ________ (Rounded upto two
decimal places).

..Common Data for Q.16 to Q.20..


For the transistor in the circuit shown in below figure, the parameters are   100 and VA   .
V   16 V

RC  6.8 k
Ris Rib
CC 2
RS  0.5 k CC1 v0
i0

vs RB  10 k RL  6.8 k
RE  3 k

V   6 V
Question 16
The value of Q-point of the circuit is
(A) 1.71 mA, 5.38 V (B) 1.71 mA, 0.53 V
(C) 5.38 mA, 1.71 V (D) 17.1 mA, 5.38 V
Question 17
The value of small-signal parameters g m , r and r0 are respectively is
(A) 45 mA/V, 0.154 k ,  (B) 65 mA/V, 1.54 k , 
(C) 6.5 mA/V, 15.4 k ,  (D) 0.65 mA/V, 154 k , 
Question 18
The value of small-signal voltage gain Av  v0 / vs of the circuit is __________ (Rounded upto two
decimal places)
Question 19
The value of small-signal current gain Ai  i0 / is of the circuit is _________ (Rounded upto two decimal
places).
Question 20
The value of input resistance Rib and Ris , (in k ) are respectively is
(A) 30.45 k, 1.02 k (B) 0.3045 k, 102 k
(C) 304.5 k, 10.2 k (D) 3.045 k, 0.102 k
GATE ACADEMY® 5 TARGET : GATE 2025/26, DPP-08
Question 21
Consider the circuit shown in below figure circuit is emitter follower. The transistor parameters are
  120 and VA   . For RE  500  . The value of current I CQ (in mA) such that the small signal voltage
gain Av  0.92 is _______. (Rounded upto two decimal places).

vi
v0

RE

Question 22
Consider the circuit shown in below figure circuit is emitter follower. The transistor parameters are   80
and VA   . The value of current I CQ (in mA) and Resistance ‘ RE ’ (in k ) are respectively such that
Rib  50 k and Av  0.95 .

vi
v0

RE

(A) 83.2 mA, 0.586 k (B) 8.32 mA, 0.586 k


(C) 0.832 mA, 5.86 k (D) 0.832 mA, 0.586 k

..Common Data for Q.23 to Q.25..


For the ac equivalent circuit shown in below Figure, Rs  1 k and the transistor parameters are   80 and
VA  50 V , I CQ  2 mA .

I CQ
R0
v0
vi
Rs R0

Question 23
The value of small signal voltage gain of the circuit is _________ (Rounded upto two decimal places).
Question 24
The value of input resistance ‘ Ri ’ (in M ) of the circuit is ________ (Rounded upto two decimal places).
Question 25
The value of output resistance ‘ R0 ’ (in  ) of the circuit is ________. (Rounded upto two decimal places).
TARGET : GATE 2025/26, DPP-08 6 GATE ACADEMY®
..Common Data for Q.26 & Q.27..
The transistor parameters for the circuit shown in below figure are   180 and VA   .
V  9 V

R1  10 k

Rib
Rs  1 k
R0
CC 1 CC 2
vs +

v0
R2  10 k
RE  500 
RL  300 

V   9 V
Question 26
The value of small-signal voltage gain of the circuit is ________ (Rounded upto two decimal places).
Question 27
The of input resistance ‘ Rib ’ and output resistance ‘ R0 ’, (in k ) are respectively
(A) 3.43, 618 (B) 0.343, 61.8 (C) 34.3, 6.18 (D) 343, 0.618

..Common Data for Q.28 to Q.30..


The transistor parameters for the circuit shown in below figure are   120 and VA   .

R1  10 k RC  1 k

Rib
Rs  1 k
R0
CC1 CC 2
vs +
– v0
R2  10 k
RE  2 k
RL  2 k

 10 V
GATE ACADEMY® 7 TARGET : GATE 2025/26, DPP-08
Question 28
The value of small-signal voltage gain of the circuit is ________ (Rounded upto two decimal places).
Question 29
The of input resistance ‘ Rib ’ and output resistance ‘ R0 ’, (in k ) are respectively
(A) 12.25, 0.32 (B) 122.5, 0.032 (C) 1.225, 3.22 (D) 3.24, 12.25

..Common Data for Q.30 to Q.32..


For the circuit shown in below Figure, let VCC  3.3 V, RL  4 k, R1  585 k, R2  135 k and RE  12 k
. The transistor parameter are   90 and VA  60 V .
VCC

RE R0
R1
v0
CC 1 Rib CC 2

is
RL
vi
R2
i0

Question 30
The value of small-signal voltage gain of the circuit is ________ (Rounded upto two decimal places).
Question 31
The of input resistance ‘ Rib ’ and output resistance ‘ R0 ’, (in k ) are respectively
(A) 0.17, 286.8 (B) 286.8, 0.17 (C) 28.68, 0.17 (D) 2.86, 1.7
Question 32
The value of small-signal current gain of the circuit is ________ (Rounded upto two decimal places).

..Common Data for Q.33 to Q.34..


Consider the emitter-follower amplifier shown in Figure. The transistor parameters are   100 and VA  100 V .
V  3 V

Rs  10 k

CC R0
vs
v0

IQ  2 mA RL

V   3 V
TARGET : GATE 2025/26, DPP-08 8 GATE ACADEMY®
Question 33
The value of output resistance R0 (in  ) such that RL  500  is __________ (Rounded upto two
decimal places).
Question 34
The value small-signal voltage gain such that RL  500  is ________ (Rounded upto two decimal
places).

..Common Data for Q.35 to Q.36..


The transistor parameters for the circuit shown in below figure are   110, VA  50 V and VEB  on   0.7 V .
V 5V

RE  3.3 k

Rib veb +

is
CC R0
vs
v0
i0

RL  1 k

V   5 V
Question 35
The value of small-signal voltage gain of the circuit is ________ (Rounded upto two decimal places).
Question 36
The value of input resistance ‘ Rib ’ and output resistance ‘ R0 ’, (in k ) are respectively
(A) 85.7, 19.8 (B) 19.8, 85.7 (C) 8.57, 1.98 (D) 0.857, 0.198

..Common Data for Q.37 to Q.40..


Consider the circuit shown in below figure is a common-base amplifier. The transistor parameters are
  120, VA   and I CQ  1 mA .
Ri R0

vi v0
Ii I0

RC  2 k

Question 37
The value of small-signal voltage gain Av  v0 / vi of the circuit is _________ (Rounded upto two decimal
places).
GATE ACADEMY® 9 TARGET : GATE 2025/26, DPP-08
Question 38
The value of small signal current gain Ai  I 0 / I i of the circuit is _________ (Rounded upto two decimal
places).
Question 39
The value of input resistance ‘ Ri ’ (in  ) of the circuit is _________ (Rounded upto two decimal places).
Question 40
The value of output resistance ‘ R0 ’ (in k ) of the circuit is _________ (Rounded upto two decimal
places).

..Common Data for Q.41 to Q.43..


Consider the circuit shown in below figure is a common-base amplifier. has parameters   80 and VA   .
Ri Roc R0
CC
vi v0
Ii I0
ICQ  2 mA
RC  1.5 k RL  2.5 k

Question 41
The value of small-signal voltage gain Av  v0 / vi of the circuit is _________ (Rounded upto two decimal
places).
Question 42
The value of small signal current gain Ai  I 0 / I i of the circuit is _________ (Rounded upto two decimal
places).
Question 43
The value of input resistance ‘ Ri ’ (in  ) of the circuit is _________ (Rounded upto two decimal places).

..Common Data for Q.44 to Q.46..


Consider the ac equivalent circuit shown in below figure. The transistor parameters are
1  120, 2  80, VA1  VA2   and I CQ1  I CQ 2  1 mA .

vi Q1

Q2
v01 v02

RE  1 k  RC  4 k 
TARGET : GATE 2025/26, DPP-08 10 GATE ACADEMY®
Question 44
The value of small-signal voltage gain Av  v01 / vi of the circuit is _________ (Rounded upto two decimal
1

places).
Question 45
The value of small-signal voltage gain Av  v02 / v01 of the circuit is _________ (Rounded upto two
2

decimal places).
Question 46
The value of small-signal voltage gain Av  v02 / vi of the circuit is _________ (Rounded upto two decimal
places).

..Common Data for Q.47 to Q.49..


Consider the ac equivalent circuit shown in below figure. The transistor parameters are
1  2  100, VA1  VA 2  , I CQ1  0.5 mA , and I CQ 2  2 mA .

RE 2  4 k
vi Q1
v02
v01
Q2

RC1  4 k

Question 47
The value of small-signal voltage gain Av  v01 / vi of the circuit is _________ (Rounded upto two decimal
1

places).
Question 48
The value of small-signal voltage gain Av  v02 / v01 of the circuit is _________ (Rounded upto two
2

decimal places).
Question 49
The value of small-signal voltage gain Av  v02 / vi of the circuit is _________ (Rounded upto two decimal
places).

..Common Data for Q.50 to Q.52..


The consider a Darlington pair configuration is shown in below Figure. The transistor parameters are
1  120, 2  80,VA1  80 V and VA 2  50 V .
GATE ACADEMY® 11 TARGET : GATE 2025/26, DPP-08
R0

I C2

Q1
Q2

AC ground
I Bias

Question 50
The value of the output resistance R0 (in k ) of the circuit such that IC 2  I Bias  1 mA is __________
(Rounded upto two decimal places).
Question 51
The value of the output resistance R0 (in k ) of the circuit such that I C 2  1 mA, I Bias  0.2 mA is
________. (Rounded upto two decimal places).
Question 52
The value of the output resistance R0 (in k ) of the circuit such that I C 2  2 mA, I Bias  0 is __________
(Rounded upto two decimal places).

..Common Data for Q.53 to Q.55..


The circuit shown in below Figure, the transistor parameters are
VTN  0.6 V, kn'   nCox  80 A/V 2 and   0.015 V 1 , VDD  5 V .
VDD

RD

iD
v0
+
vDS
+ –
vGS

vi
+
VGSQ

Question 53
The value of transistor width-to-length ratio W / L  and the resistance RD (in k ) are respectively such
that I DQ  0.5 mA, VGSQ  1.2 V .
(A) 4.0, 34.7 (B) 3.47, 4.0 (C) 4.0, 3.47 (D) 34.7, 4.0
TARGET : GATE 2025/26, DPP-08 12 GATE ACADEMY®
Question 54
The value of the transconductance g m (in mA/V) and output resistance r0 ( k ) are respectively.
(A) 1.66, 133.3 (B) 16.6, 1.333 (C) 0.166, 13.33 (D) 166, 0.1333
Question 55
The value of small-signal voltage gain Av  v0 / vi is ____________ (Rounded upto two decimal places).

..Common Data for Q.56 to Q.58..


Consider the circuit in below figure, the circuit parameters are VDD  3.3 V, RD  8 k, R1  240 k, R2  60 k
and RSi  2 k . The transistor parameters are VTN  0.4 V, kn'   nCox  100 A/V 2 , W / L  80 and   0.02 V 1
VDD

R1 RD

RSi CC 1
v0

vi
R2

Question 56
The values of the current I DQ (in mA) and voltage VDSQ (in volt) are respectively.
(A) 27.7, 11.4 (B) 2.77, 114 (C) 0.277, 1.14 (D) 1.14, 277
Question 57
The value of small-signal parameters g m (in mA/V) and r0 (in k ) are respectively.
(A) 20.78, 18.5 (B) 2.078, 185 (C) 185, 20.78 (D) 2.078, 1.85
Question 58
The value of small-signal voltage gain of the circuit is _________ (Rounded upto two decimal places).
Question 59
A common-source amplifier, such as shown in below figure, has parameters r0  100 k and RD  5 k
. The value of transconductance (in ms) of the transistor such that small-signal voltage gain in Av  10
and RSi  0 is _________ (Rounded upto thus decimal places).
VDD

R1 RD

RSi CC 1
v0

vi
R2
GATE ACADEMY® 13 TARGET : GATE 2025/26, DPP-08
..Common Data for Q.60 to Q.61..
Consider the NMOS common-source amplifier shown in below figure, the transistor parameters are :
C W
VTN  0.8 V, kn  n ox  1 mA/V 2 and   0 .
2L
The circuit parameters are : VDD  5 V, Rs  1 k, RD  4 k, R1  225 k and R2  175 k .
VDD

RD
R1 CC 2
CC1 v0

RL
vi R2 RS

Question 60
The value of small-signal voltage gain of the circuit such that load resistance RL   is __________
(Rounded upto two decimal places).
Question 61
The value of load resistance ‘ RL ’ (in k ) that will reduce the small-signal voltage gain to 75 percent of
its initial value is ___________ (Rounded upto two decimal places).
Question 62
The parameters of the circuit shown in below figure, are VDD  12 V, Rs  0.5 k, Rin  250 k and
 nCoxW
RL  10 k . The transistor parameters are VTN  1.2 V, kn   1.5 mA/V 2 and   0 . The value
2L
of small-signal voltage gain of the circuit is _________ (Rounded upto two decimal places).
VDD

RD
R1 CC 2
CC1 v0

RL
vi R2 RS
TARGET : GATE 2025/26, DPP-08 14 GATE ACADEMY®
..Common Data for Q.63 & Q.64..
The ac equivalent circuit of a common-source amplifier is shown in below figure, the small-signal parameters of
the transistor are g m  2 mA/V and r0  
v0

RD
vi
RS

Question 63
The value of resistance ‘ RD ’ (in k ) such that voltage gain of the circuit is 15 , with Rs  0  is
_______ (Rounded upto two decimal places).
Question 64
A source resistor RS is inserted. Assuming the transistor parameters do not change, the value of source
resistance ‘ RS ’ (in k ) if the voltage gain in reduced to Av  5 is ______ (Rounded upto two decimal
places).

..Common Data for Q.65 & Q.66..


The transistor in the common-source amplifier shown in below figure, has parameters
VTN  0.8 V, kn'   nCox  100 A/V 2 , W / L  50 and   0.02 V 1 .

The circuit parameters are V   5 V, V   5 V, IQ  0.5 mA and RD  6 k .


V

RD
CC 2
v0
CC1
RL

vi RG  200 k

IQ
CS

V

Question 65
The value of small-signal voltage gain of the circuit such that load resistance RL   is _________
(Rounded upto two decimal places).
Question 66
The value of small-signal voltage gain of the circuit such that load resistance RL  20 k is _________
(Rounded upto two decimal places).
GATE ACADEMY® 15 TARGET : GATE 2025/26, DPP-08
..Common Data for Q.67 & Q.69..
The parameters of the MOSFET in the circuit shown in below figure are
C W
VTN  0.8 V, kn  n ox  0.85 mA/V 2 and   0.02 V 1 .
2L
5V

RD
CC
v0

RL  40 k

vi RG CS

RS

5 V
Question 67
The value of the resistance RS and RD , (in k ) are respectively such that I DQ  0.1 mA and VDSQ  5.5 V
(A) 38.6, 6.43 (B) 3.86, 643 (C) 0.386, 64.3 (D) 386, 643
Question 68
The value of small-signal transistor parameters g m (in mA/V) and r0 (in k ) are respectively.
(A) 5.83, 50 (B) 0.583, 5.0 (C) 58.3, 0.5 (D) 0.583, 500
Question 69
The value of small-signal voltage gain of the circuit is _________ (rounded upto two decimal places).
Question 70
Consider the common-source amplifiers shown in below figure, the circuit parameters are VDD  3.3 V
and RL  10 k . I DQ  0.5 mA and VDSQ  2 V . The value small-signal voltage gain of the circuit is
________. (Rounded upto two decimal places)
VDD

RD
CC1
v0

CC 2 RL

vi +
– RG  1 M
RS
TARGET : GATE 2025/26, DPP-08 16 GATE ACADEMY®
..Common Data for Q.71 & Q.72..
Consider the PMOS common-source circuit shown in below Figure with transistor parameters VTP  2 V and
  0 and circuit parameters RD  RL  10 k .
5V

RS

CS
CC1
CC 2
v0
vi RG  100 k
RD RL

5 V
Question 71
 pCoxW
The value of process parameter K p  (in mA/V2 ) such that VSDQ  6 V and Rs  10 k .
2L
(A) 20.2 (B) 2.0 (C) 200 (D) 0.2
Question 72
The value of small-signal voltage gain ‘ Av ’ of the circuit is _________ (Rounded upto two decimal
places).

..Common Data for Q.73 & Q.75..


Consider the common-source amplifier shown in figure, the transistor parameters are
 pCoxW
VTP  1.2 V, K p   2 mA/V 2 and   0.03 V 1 . The drain resistor is RD  4 k .
2L
9V

IQ

CS
CC1
CC 2
v0
vi RG  500 k
RD RL

9 V
Question 73
The value of the current ‘ I Q ’ (in mA) such that VSDQ  5 V is ___________ (Rounded upto two decimal
places).
GATE ACADEMY® 17 TARGET : GATE 2025/26, DPP-08
Question 74
 v 
The value of small-signal voltage gain  Av  0  such that RL   is _________ (Rounded upto two
 vi 
decimal places).
Question 75
 v 
The value of small-signal voltage gain  Av  0  such that RL  8 k is _________ (Rounded upto two
 vi 
decimal places).
Question 76
The open-circuit  RL    voltage gain of the ac equivalent source- circuit shown in Figure is Av  0.98 .
When RL is set to 1 k , the voltage gain is reduced to Av  0.49 . The values of transconductance g m (in
ms) and output resistance r0 (in k ) are respectively

v0
vi
RL

(A) 9.8, 5.0 (B) 0.98, 50 (C) 98, 0.50 (D) 50, 0.98

..Common Data for Q.77 & Q.79..


Consider the source-follower circuit shown in below figure, The small-signal parameters of the transistor are
g m  2 mA/V and r0  25 k .

v0
vi
RL

Question 77
The value of open-circuit  RL    small signal voltage gain of the circuit is ________ (Rounded upto
two decimal places).
Question 78
The value of open-circuit  RL    output resistance (in k ) is __________ (Rounded upto two decimal
places).
TARGET : GATE 2025/26, DPP-08 18 GATE ACADEMY®
Question 79
If load resistance RL  2 k and the small-signal transistor parameters remain constant, the value of small
 v 
signal voltage gain  Av  0  of the circuit is __________ (Rounded upto two decimal places).
 vi 

..Common Data for Q.80 & Q.81..


Consider the source follower amplifier shown in below figure, is biased at V   1.5 V and V   1.5 V . The
transistor parameters are : VTN  0.4 V, kn'   nCox  100 A/V 2 , W / L  80 and   0.02 V 1 .
V

v0
vi
10 k

V
Question 80
The value of small-signal voltage gain of the circuit is __________ (Rounded upto two decimal places).
Question 81
The value of output resistance ‘ R0 ’ (in k ) of the circuit is _________ (Rounded upto two decimal
places).

..Common Data for Q.82 & Q.84..


Consider the circuit shown in below figure, the transistor parameters are : VTN  0.6 V, kn'   nCox  100 A/V 2
and   0 , VDSQ  1.25 V and small-signal voltage gain is 0.85
VDD  2.5 V

vi
v0

RS  0.5 k

Question 82
The value of current I DQ (in mA) flow from drain to source terminal of the circuit is __________
(Rounded upto two decimal places).
Question 83
The value of width-to-length ratio of the transistor is _________ (Rounded upto two decimal places).
GATE ACADEMY® 19 TARGET : GATE 2025/26, DPP-08
Question 84
What is the required dc value of the input voltage is ___________ (Rounded upto two decimal places).

..Common Data for Q.85 to Q.88..


The quiescent power dissipation in the circuit shown in below figure, is to be limited to 2.5 mW. The parameters
of the transistor are VTN  0.6 V, kn'   nCox  100 A/V 2 and   0.02 V 1 .
VDD  2.5 V

vi R0
v0

IQ

Question 85
The value of current I Q (in mA) is __________ (Rounded upto two decimal place).
Question 86
The value of width-to-length ratio W / L  such that the output resistance is R0  0.5 k is __________
(Rounded upto two decimal places).
Question 87
The value of small-signal voltage gain of the circuit is ________ (Rounded upto two decimal places)
Question 88
The value of output resistance (in  ) if the transistor width-to-length ratio is W / L  100 is _________
(Rounded upto two decimal places).

..Common Data for Q.89 & Q.90..


Consider the source follower circuit shown in below figure, with transistor parameters
VTN  0.8 V, kn'   nCox  100 A/V 2 , W / L  20 and I Q  5 mA .
5V

CC1
R0
CC2
v0
vi +
– RG  500 k

IQ RL  4 k

5 V
Question 89
The value of small-signal voltage gain of the circuit is __________ (Rounded upto two decimal places).
TARGET : GATE 2025/26, DPP-08 20 GATE ACADEMY®
Question 90
The value output resistance ‘ R0 ’ (in k ) is __________ (Rounded upto two decimal places).
Question 91
Consider the ac equivalent circuit of a common-gate amplifier shown in below figure. The transistor
parameters are VTN  0.4 V, kn'   nCox  100 A/V 2 and   0 . The quiescent drain current is
I DQ  0.25 mA . The value of the width to length ratio W / L  and the value of drain resistance ‘ RD ’ (in
k ) are respectively such that the small-signal voltage gain is 20 and the input resistance is Ri  500  .
Ri

vi v0

RD
VB

(A) 1, 8 (B) 10, 80 (C) 8, 1 (D) 80, 10

..Common Data for Q.92 to Q.95..


The value of transistor in the common-gate circuit shown in below figure, the transistor parameters are
VTN  0.4 V, kn'   nCox  100 A/V 2 and   0 and output resistance R0 is to be 500  and the drain-to-source
quiescent voltage is to be VDSQ  VDS sat   0.3 V .
Ri R0

vi v0

+ RD
VGSQ  1.2 V
– +
VDD  2.2 V

Question 92
The value of resistance ‘ RD ’ (in k ) is _________ (Rounded upto two decimal places)
Question 93
The value of quiescent drain current ‘ I DQ ’(in mA) is _________ (Rounded upto two decimal places).
Question 94
The value of input resistance ‘ Ri ’ (in  ) is _________ (Rounded upto two decimal places).
Question 95
The value of small-signal voltage gain  Av  v0 / vi  is _________ (Rounded upto two decimal places).

..Common Data for Q.96 & Q.97..


The small-signal parameters of the NMOS transistor in the ac equivalent common-gate circuit shown in below
figure are VTn  0.4 V, kn'   nCox  100 A/V 2 , W / L  80 and   0 . The quiescent drain current is
I DQ  0.5 mA .
GATE ACADEMY® 21 TARGET : GATE 2025/26, DPP-08
Ri
v0

vi +– 10 k 4 k

Question 96
The value of input resistance ‘ Ri ’ (in  ) is _________ (Rounded upto two decimal places).
Question 97
The value of small-signal voltage gain  Av  v0 / vi  is _________ (Rounded upto two decimal places).

..Common Data for Q.98 & Q.99..


Consider the common-gate circuit in below figure, the NMOS transistor parameters are :
C W
VTN  1 V, kn  n ox  3 mA/V 2 and   0 .
2L
CC1 CC 2
v0

vi +– RS  10 k RD  5 k RL  4 k

V   5 V V  5 V
Question 98
The value of transconductance g m (in mA/V) and output resistance ‘ r0 ’ (in k ) are respectively.
(A)  , 20.9 (B) 2.09,  (C) 0.290,  (D)  , 2.09
Question 99
The value of small-signal voltage gain  Av  v0 / vi  of the circuit is ________ (Rounded upto two decimal
places).

..Common Data for Q.100 & Q.101..


The transistor parameters of the NMOS device in the common-gate amplifier shown in below figure, are
VTN  0.4 V, kn'   nCox  100 A/V 2 and   0 .
CC
V0

Vi IQ 
RD
2 mA

V   1.8 V V   1.8 V
Question 100
The value of resistance ‘ RD ’ (in k ) such that VDSQ  VDS sat   0.25 V is ________ (Rounded upto
two decimal places).
TARGET : GATE 2025/26, DPP-08 22 GATE ACADEMY®
Question 101
The value of the width to length ratio W / L  such that the small-signal voltage gain is 6 __________
(Rounded upto two decimal places).
Question 102
The value of transistor parameters for the common-source circuit in below figure, are
VTND  0.4 V, VTPL  0.04 V, W / L  L  50,  D  0.02 V 1 ,  E  0.04 V 1, kn'  100 A/V 2 and
k p'  40 A/V2 . At the Q-point, I DQ  0.5 mA . The value of width to length ratio W / L  D such that the
V0
small-signal voltage gain is Av   40 is _________. (Rounded upto two decimal places).
Vi
V   2.5 V

VB ML

V0

Vi MD

Question 103
Consider the circuit in below Figure, the transistor parameters are :
VTPD  0.6 V, VTNL  0.4 V, kn'  nCox  100 A/V2 , k p'   pCox  40 A/V2 ,  L  0.02 V1,
 D  0.04 V 1 and W / L  L  10 .

The quiescent drain current is I DQ  0.25 mA . The value of width to length ratio W / L  D such that the
v0
small-signal voltage gain is Av   25 is __________ (Rounded upto two decimal places).
vi
V   2.5 V

vi MD

v0

VB ML
TARGET : GATE 2025/26
Analog Electronics
Topic : Frequency Response of Amplifier DPP : 09

..Common Data for Q.1 & Q.2..


 nCoxW
The transistor shown in below figure has parameters VTN  0.4 V , kn   0.4 mA/V 2 and   0 . The
2L
transistor is biased at I DQ  0.8 mA .
V   2.5 V

RD  1k 

V0

Vi
CL  1pF

Question 1
The value of maximum voltage gain of the circuit is _______. (rounded off to two decimal place)
Question 2
The value of bandwidth (in MHz) of the circuit is _______. (rounded off to two decimal place)

..Common Data for Q.3 to Q.5..


Consider the circuit shown in below figure. The transistor has parameters   120 and VA   . The circuit
bandwidth is 800 MHz and the quiescent collector-emitter voltage VCEQ  1.25 V .
VCC  2.5 V

RC

V0
Vi
CL  0.08 pF
TARGET : GATE 2025/26, DPP-09 2 GATE ACADEMY®
Question 3
The value of resistance ‘ RC ’ (in k ) is _______. (rounded off to two decimal place)
Question 4
The value of current ‘ I CQ ’ (in mA) is _______. (rounded off to two decimal place)
Question 5
The value of maximum voltage gain of the circuit is _______. (rounded off to two decimal place)

..Common Data for Q.6 & Q.7..


 n CoxW
The transistor in the circuit shown in below figure has parameters VTN  0.4 V , kn   50 A/V 2 and
2L
  0.01 V 1 .
V   2.5 V

I DQ  100  A

V0

Vi
CL  0.5pF

Question 6
The value of maximum voltage gain of the circuit is _______. (rounded off to two decimal place)
Question 7
The value of bandwidth (in kHz) of the circuit is _______. (rounded off to two decimal place)

..Common Data for Q.8 & Q.9..


For the common-emitter circuit in below figure, the transistor parameters are :   100 , VBE  on   0.7 V , and
VA   .
VCC  12 V

RC  1k 
R1  10 k 
V0
Rs  0.5 k CC  0.1 F

Vi +
– R2  1.5 k
RE  0.1k 

Question 8
The value of lower corner frequency (in Hz) of the circuit is _______. (rounded off to two decimal place)
GATE ACADEMY® 3 TARGET : GATE 2025/26, DPP-09
Question 9
The value of midband voltage gain of the circuit is _______. (rounded off to two decimal place)

..Common Data for Q.10 to Q.12..


 pCoxW
The transistor in the circuit in below figure has parameters k p   0.5 mA/V2 , VTP  2 V and   0 .
2L
9V

RS  12k 
R0

v0
CC
RL  10 k

vi +– RG  50 k 

9 V

Question 10
The value of resistance ‘ R0 ’ (in k ) is _______. (rounded off to two decimal place)
Question 11
The value of time constant of the circuit (in ms) is _______. (rounded off to two decimal place)
Question 12
The value of capacitance ‘ CC ’ (in F) such that the lower 3 dB frequency is 20 Hz is _______. (rounded
off to two decimal place)

..Common Data for Q.13 & Q.14..


The parameters of the transistor in the circuit shown in below figure are :   100 , VBE  on   0.7 V and VA   .
Neglect the capacitance effects of the transistor
V   12 V

RC  5.1k
RB  1M 
v0
RS  1k
RL  500 k CL  10 pF
CC  10 F
vi +

Question 13
The value of lower corner frequency ‘ f L ’ (in Hz) of the circuit is _______. (rounded off to two decimal
place)
Question 14
The value of upper corner frequency ‘ f H ’ (in MHz) of the circuit is _______. (rounded off to two decimal
place)
TARGET : GATE 2025/26, DPP-09 4 GATE ACADEMY®
..Common Data for Q.15 & Q.16..
Consider the circuit shown in below figure.
rb  200  C  0.8pF

+
Vi +– r  2.5k  V C  10 pF 0.04V RL  2.5 k

Zin

Question 15
The value of magnitude of input impedance (in k ) seen by the signal source Vi at f  1 kHz is _______.
(rounded off to two decimal place)
Question 16
The value of magnitude of input impedance (in k ) seen by the signal source Vi at f  1 MHz is
_______. (rounded off to two decimal place)
Question 17
The parameters of an n-channel MOSFET are kn'   nCox  80 A/V 2 , W  4 m , L  0.8 m ,
Cgs  50 fF , and Css  10 fF . The transistor is biased at I DQ  0.6 mA .

The value of unity gain frequency ‘ fT ’ (in GHz) is _______. (rounded off to two decimal place).
Question 18
A common-source equivalent circuit is shown in below figure. The transistor transconductance is
g m  3 mA/V .

rb  200  C  0.8 pF
V0

+
Vi +– V Cgs  80 pF g mVgs r0  120 k  RD  10 k 

The value of upper corner frequency ‘ f H ’ (in MHz) of the circuit is _______. (rounded off to two decimal
place)

..Common Data for Q.19 & Q.20..


 nCoxW
Consider the circuit shown in below figure, the transistor parameters are: kn   1 mA/V 2 , VTN  2 V ,
2L
  0 , Cgs  50 fF and Cgd  8 fF .
GATE ACADEMY® 5 TARGET : GATE 2025/26, DPP-09
VDD  10 V

RD  5 k
R1  500 k
v0
CC  10 F

Ri  1 k
vi R2  225 k

Question 19
The value of upper corner frequency (in GHz) of the circuit is _______. (rounded off to two decimal place)
Question 20
The value of midband voltage gain of the circuit is _______. (rounded off to two decimal place)

..Common Data for Q.21 & Q.22..


 pCoxW
The parameters of the transistor in the common-source circuit in below figure are : k p   2 mA/V 2 ,
2L
1
VTP  2 V ,   0.01 V , Cgs  10 pF , and Cgd  1 pF .
9V

RS  1.2 k 

Ri  2 k
CS
v0
vi RG  100 k 

RD  1 k

9 V
Question 21
The value of upper corner frequency (in MHz) of the circuit is _______. (rounded off to two decimal
place)
Question 22
The value of midband voltage gain of the circuit is _______. (rounded off to two decimal place)


TARGET : GATE 2025/26
Analog Electronics
Topic : Series Shunt Feedback Amplifier DPP : 10
Bottom Line :
Advantages of Negative Feedback :
1. Gain sensitivity : Variations in the circuit transfer function (gain) as a result of changes in transistor
parameters are reduced by feedback. This reduction in sensitivity is one of the most attractive features of
negative feedback.
2. Bandwidth extension : The bandwidth of a circuit that incorporates negative feedback is larger than that
of the basic amplifier.
3. Noise sensitivity : Negative feedback may increase the signal-to-noise ratio if noise is generated within
the feedback loop.
4. Reduction of nonlinear distortion : Since transistors have nonlinear characteristics, distortion may
appear in the output signals, especially at large signal levels. Negative feedback reduces this distortion.
5. Control of impedance levels : The input and output impedances can be increased or decreased with the
proper type of negative feedback circuit.
Disadvantages of Negative Feedback :
1. Circuit gain : The overall amplifier gain, with negative feedback, is reduced compared to the basic
amplifier used in the circuit.
2. Stability : There is a possibility that the feedback circuit may become unstable (oscillate) at high
frequencies.
RS
+
Av V0 RL Ii RS Ai

I0
Vi
RL

v
i

Series-shunt
Shunt-Series
TARGET : GATE 2025/26, DPP-10 2 GATE ACADEMY®
RS

Ag +
Ii RS Az V0 RL
I0 –

Vi RL

tc tr

Series-series Shunt-shunt
Summary Results of Feedback Amplifier Functions for the Ideal Feedback Circuit :
Feedback Source Output Input Output
Transfer function
amplifier signal signal resistance resistance
Series-shunt
V0 A R0
Voltage Voltage Avf   Ri 1  v Av 
Vi 1  v Av  1  v Av 
(Voltage
amplifier)
Shunt-series I0 Ai Ri
Aif   R0 1 i Ai 
I i 1  i Ai  1  i Ai 
(Current Current Current
amplifier)
Series-series Ag
I0
(transconductance Voltage Current Gmf   Ri 1  tcGm  R0 1  tcGm 
Ii 1  tcGm 
amplifier)
Shunt-shunt V0 Az Ri R0
(Transresistance Current Voltage Rmf  
I i 1  tr Rm  1  tr Rm  1  tr Rm 
amplifier)

Question 1
A series-shunt feedback amplifier in which the open-loop gain is AV  105 and the closed loop gain is
Avf  50 . Where, the input and output resistances of the basic amplifier are Ri  10 kΩ and R0  20 kΩ ,
respectively. The input resistance of a series input connection and the output resistance of a shunt output
connection for an ideal feedback voltage amplifier respectively, are
(A) 20 M , 10  (B) 10 M , 20  (C) 20  , 10 M (D) 10  , 20 M
Question 2
A shunt-series feedback amplifier in which the open-loop gain is Ai  105 and the closed-loop gain is
Aif  50 . Where, the input and output resistances of the basic amplifier are Ri  10 kΩ and R0  20 kΩ ,
respectively. The value of input resistance of a shunt input connection and the output resistance of a series
output connection, for a feedback current amplifier respectively, are
(A) 5  , 40 M (B) 40 M , 5  (C) 40  , 5 M (D) 5 M , 40 
Question 3
Consider the noninverting Op-amp in given figure, with parameters Ri  50 k , R1  10 kΩ , R2  90 kΩ
and Av  104 . The expected input resistance of the noninverting op-amp circuit is ______ M . (in
integer)
GATE ACADEMY® 3 TARGET : GATE 2025/26, DPP-10

..Common Data for Q.4 & Q.5..


v0
Two feedback configurations are shown in figures (a) and (b). The closed-loop gain in each case is Avf   50
vi

Fig. (a)

Fig. (b)
Question 4
The value of 1 and 2 for the figure (a) and (b) respectively are
(A) 0.0966 and 0.0195 (B) 0.0195 and 0.0966
(C) 0.0264 and 0.03966 (D) 0.0348 and 0.0596
Question 5
The gain A2 decreases by 10% in both circuit then the percent change in closed-loop gain for each circuit
(a) and (b) are
(A) – 5.43% and – 0.28% (B) – 6.43% and – 0.39%
(C) – 0.28% and – 5.43% (D) – 0.39% and – 6.43%

..Common Data for Q.6 & Q.7..


Three voltage amplifiers are in cascade as shown in figure with various amplification factors. The 180 degree
phase shift for negative feedback actually occurs in the basic amplifier itself.
TARGET : GATE 2025/26, DPP-10 4 GATE ACADEMY®

Question 6
V0
The value of  such that the closed loop voltage gain is Avf   120 is ______. (rounded upto three
Vs
decimal places)
Question 7
The percentage change in Avf if each individual amplifier gain decreases by 10% is ______ %. (rounded
upto two decimal places)

..Common Data for Q.8 & Q.9..


The open-loop low-frequency voltage gain of an amplifier is Av  5 104 and the open-loop 3 dB frequency is
f H  10 Hz . If the closed loop low - frequency gain is Avf  25 .
Question 8
The minimum closed loop bandwidth of a feedback amplifier is _______ kHz. (in integer)
Question 9
The open loop low frequency voltage gain is Av  105 and the open loop 3 dB frequency is f H  8 Hz ,
then the maximum closed loop voltage gain is ______. (in integer)



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