MODULE 1

ECT 304 VLSI CIRCUIT DESIGN

History of Micro Electronics Development
 Moore’s Law

► Gorden Moore was one of the early integrated circuit

pioneers and founders of Intel.
► In 1965,he saw the future and predicted ,now popularly
known as Moore’s Law.
► This law states that that the number of transistors on a
chip doubles about every two years.
► It is interesting to note that IC complexity has advanced from
SSI to MSI,to LSI and finally VLSI which has millions of
components per chip.
 ASIC
► ASIC [“a-sick”] is an acronym for Application Specific Integrated
Circuit.
► As the name indicates, ASIC is a non-standard integrated circuit
that is designed for a specific use or application.
► Generally an ASIC design will be undertaken for a product that will
have a large production run , and the ASIC may contain a very large
part of the electronics needed on a single integrated circuit.
► ASIC is a combination of analog function
(clock,amplification,registers,noise,suppressing) digital
function (adder,mux,registers,CPU) programmable logic,
different types of memory,power management in a single chip.
Examples

► Examples for ASIC ICs are :

► a chip for a toy bear that talks;

► a chip for a satellite;

► a chip designed to handle the interface between memory
and a microprocessor for a workstation CPU
► and a chip containing a microprocessor as a cell together
with other logic.
► Two ICs that might or might not be considered as ASICs are, a
controller chip for a PC and a chip for a modem.
► Both of these examples are specific to an application (shades
of an ASIC) but are sold to many different system vendors
(shades of a standard part).
► ASICs such as these are sometimes called application-specific
standard products ( ASSPs ).
Example: ADS1263
ACTIVE

32-bit 38-kSPS 10-ch delta-sigma ADC with PGA, VREF and auxiliary ADC for
factory automation
Types of ASICs (VLSI Design styles)
Types of ASICs (VLSI Design styles)

► ASICs are broadly classified into three types.

► I. Full-Custom ASICs
► II. Semi-custom ASICs
► III. Programmable ASICs
Full-Custom ASICs
► A Full custom ASIC is one which includes all logic cells that are
customized and all mask layers that are customized.
► A microprocessor is an example of a full-custom IC .
► Designers spend many hours squeezing the most out of every last
square micron of microprocessor chip space by hand.
► Customizing all of the IC features in this way allows designers to
include analog circuits, optimized memory cells, or mechanical
structures on an IC.
► Full-custom ICs are the most expensive to manufacture and to
design.
► These are usually intended for high-level applications. Maximum
performance, minimized area and highest degree of flexibility are major
features of Full custom design.
Full-Custom ASICs

► The manufacturing lead time (the time required just to make an

IC not including design time) is typically eight weeks for a
full-custom IC.
► In a full-custom ASIC an engineer designs some or all of the
logic cells, circuits, or layout specifically for one ASIC. This
means the designer avoids using pretested and pre
characterized cells for all or part of that design.

► This might be because existing cell libraries are not fast enough,
or the logic cells are not small enough or consume too much
power.
► One has to use full-custom design if:
► the ASIC technology is new or so specialized that there are
no existing cell libraries
► or because the ASIC is so specialized that some circuits must
be custom designed.
► Fewer and fewer full-custom ICs are being designed because of
the problems with these special parts of the ASIC.
► The growing member of this family, now a days is the mixed
analog/digital ASIC.
 Semi-custom ASICs

► ASICs , for which all of the logic cells are predesigned and
some (possibly all) of the mask layers are customized are
called semi custom ASICs.
► Using the predesigned cells from a cell library makes the
design , much easier.
► There are two types of semi-custom ASICs
► (i) Standard-cell–based ASICs (ii)Gate-array–based ASICs
(i)Standard-Cell Based ASICs
►A cell-based ASIC (cell-based IC, or CBIC pronounced sea-bick) uses
predesigned logic cells known as standard cells.
► Standard cells are also called poly cells.
► Examples of standard cells are AND gates, OR gates, multiplexers,
and flip-flops.
► These cells are initially developed and stored in the library.
► Designer defines only the placement of standard cells and
interconnections between them.

The standard-cell areas (also called flexible blocks) in a CBIC are built of
rows of standard cells like a wall built of bricks.
► The ASIC designer defines only the placement of the
standard cells and the interconnect in a CBIC. However, the
standard cells can be placed anywhere on the silicon; this
means that all the mask layers of a CBIC are customized
and are unique to a particular customer.
► The advantage of CBICs is that designers save time,
money, and reduce risk by using a predesigned,
pretested, and pre characterized standard-cell library.
► In addition each standard cell can be optimized
individually.
► During the design of the cell library, each and every transistor
in every standard cell can be chosen to maximize speed or
minimize area .
► The disadvantages are the time or expense of designing
or buying the standard-cell library and the time needed
to fabricate all layers of the ASIC for each new design.
(ii)Gate-Array Based ASIC design

► Fabrication of gate array based ASICs consists of two phases:

Phase 1:
► In a gate array based ASIC, the transistors (gates) are
predefined on the silicon wafer. (Generic (standard) masks
can be used for this purpose)
► This predefined pattern of transistors on a gate array is the
base array.
 Phase 2:
► The top few layers of metal, which define the interconnect between
transistors, are defined by the designer and fabricated using
custom masks.

► To distinguish this type of gate array from other types of gate array,
it is often called a masked gate array ( MGA ).
► The designer chooses from a gate-array library of predesigned and
pre-characterized logic cells
► The logic cells in a gate-array library are often called macros .
► The reason for this is that the base-cell layout is the same for
each logic cell, and only the interconnect (inside cells and
between cells) is customized, which is similar to a software
macro.
Types of MGA or Gate-array based ASICs
► There are three types of Gate Array based ASICs.
► Channeled gate arrays.
► Channelless gate arrays.
► Structured gate arrays.

Channeled, channel less and structured gate arrays

Channeled gate arrays

► In a channeled gate array space is left between the rows of

transistors for wiring (interconnection of cells).
Features of channeled MGA

► Only the interconnect is customized.

► The interconnect uses predefined spaces between rows of
base cells.
► Manufacturing lead time is between two days and two
weeks.
Channel less Gate Array (Sea of Gates(SoG))

► In channel- less gate array, as name indicates, there is no gap between

rows. Transistors are continuously defined.This architecture is also
called Sea of Gates(SoG).
► Channel less gate array uses rows of unused transistors for
interconnection between cells (ROUTING).

► The key difference between a channel less gate array and channeled gate
array is that there are no predefined areas set aside for routing between
cells on a channel less gate array.
► Instead we route over the top of the gate-array devices. We can do this
because we customize the contact layer that defines the connections
between metal 1, the first layer of metal, and the transistors.
Structured gate arrays

► Structured gate arrays can be either channelled or

channel-less, but they also involve custom blocks.
Programmable ASIC

This category include programmable devices like Field

Programmable Gate Arrays and Programmable Logic Devices (PLDs)

Programmable Logic Devices (PLDs) are the components which

do not have a specific function associated with them. These can be
configured to perform a certain function by the user, on a need
basis and can further be changed to perform some other function at
the later point of time, i.e. these are re-configurable.
FPGA

FPGAs are the newest member of the ASIC family and are rapidly growing
in , replacing TTL in microelectronic systems.
• The first FPGA was introduced by Xilinx in 1985.
• There is very little difference between an FPGA and a PLD.
• An FPGA is usually just larger and more complex than a PLD.
• In fact, some vendors that manufacture programmable ASICs call their
products as FPGAs and some call them as complex PLDs
A typical field programmable gate array (FPGA) chip consists of:
► I/O buffers,
► an array of configurable logic blocks (CLBs),
► programmable interconnect structures.
• The programming of the interconnects is implemented by programming of
RAM cells whose output terminals are connected to the gates of MOS pass
transistors.
• The signal routing between the CLBs and the I/O blocks is accomplished by
setting the configurable switch matrices accordingly
Configurable Logic Block (CLB)
CLB of Xilinx XC2000 consists of:
► four signal input terminals (A, B, C, D)
► a clock signal terminal
► user programmable multiplexers
► an SR-latch
► and a look-up table (LUT).
• A lookup table (LUT) stores a predefined list of logic outputs for
any combination of inputs: LUTs with four to six input bits are widely
used.
• The LUT can generate any function of up to four variables or any
two functions of three variables.
• The CLB is configured such that many different logic functions
can be realized by programming its array.
FPGA Design Flow
► Algorithm: ALGORITHM of the design is described in this step.
► HDL design entry : the design description is written using HDL
such as VHDL or Verilog.
► Logic synthesis : Design is converted in terms of logic cells in the
FPGA architecture.(Synthesis is the process of transforming an RTL-specified
design into a gate-level representation)

► Technology netlist : the optimized/synthesized netlist is

transformed into the technology dependent net-list(LUTs).A netlist
is nothing but textual description of a circuit made of components in
VLSI design
► Mapping,Placing,and Routing- Arrange the blocks;place the cells
on the chip with connections.
► Bit stream : The synthesized, verified timing constrains
netlist is converted into bit streams to transform onto chip.
The final streams are programmed on to target device.
Characteristics of FPGA

► None of mask layer customised.

► Matrix for programmable interconnect surround basic logic
cells.
► Programmable I/O cells surround the core.
VLSI design flow - General procedure

The design process at various levels is evolutionary in nature:

It starts with a given set of requirements
Initial design is developed and tested
If the design doesn’t meet the required conditions:
-1.design will be improved
2. if improvement is not possible, specifications(requirements) are
re-defined
ASIC design flow
ASIC design
flow (steps 1
to 5)
ASIC design flow
(steps 6 to 9)
 System On Chip

► A System on Chip (SoC) is an integrated circuit that implements

most or all of the function of a complete electronic or computer
system.
► SoC generally looks to incorporate within itself include a central processing
unit, input and output ports, internal memory, as well as analog input and
output blocks
SoC
SoC building blocks
► A system on chip must have a processor at its core which will
define its functions. Normally, an SoC has multiple processor cores.
It can be a microcontroller, a microprocessor, a digital signal
processor, or an application specific instruction set processor.
► Secondly, the chip must have its memories which will allow it to
perform computation. It may have RAM, ROM, EEPROM, or even a
flash memory.
► The next thing an SoC must possess are external interfaces which
will help it comply with industry standard communication protocols
such as USB, Ethernet, and HDMI. It can also incorporate wireless
technology and involve protocols pertaining to WiFi and Bluetooth.
SoC building blocks (contd.)

► It will also need a GPU or a Graphical Processing Unit in order

to help visualize the interface.
► Other stuff that an SoC may have includes voltage regulators,
phase lock loop control systems and oscillators, clocks and
timers, analog to digital and digital to analog converters, etc.
► Internal interface bus or a network to connect all the individual
blocks
Advantages of SoC

● Essentially the great benefits of using an SoC are: power

saving, space saving and cost reduction
a. SoCs are efficient as systems as their performance is
maximized per watt
b. Systems on chip also tend to minimize the latency provided
the various elements are strategically placed on the
motherboard in order to minimize interference and
interconnection delays as well as speed up the data
transmission process
Evolution of Microelectronics: the SoC
Paradigm
Migration from ASICs to SoCs

► An SoC is an IC designed by stitching together multiple stand-

alone VLSI designs to provide full functionality for an
application.
► An SoC compose of predesigned models of complex functions
known as cores (terms such as intellectual property block,
virtual components, and macros) that serve a variety of
applications
Three forms of SoC design

1. ASIC vendor design: This refers to the design in which all the
components in the chip are designed as well as fabricated by an ASIC
vendor.
2. Integrated design: This refers to the design by an ASIC vendor in
which all components are not designed by that vendor. It implies the
use of cores obtained from some other source such as a core/IP
vendor or a foundry.
3. Desktop design: This refers to the design by a fabless company
that uses cores which for the most part have been obtained from
other source such as IP companies, EDA companies, design services
companies, or a foundry
 SoCs vs. ASICs

► SoC is not just a large ASIC

► It is an architectural approach involving significant design reuse
addresses the cost and time-to-market problems
► SoC methodology is an incremental step over ASIC methodology
► SoC design is significantly more complex
► Need cross-domain optimizations
► IP reuse and Platform-based design increase productivity
► Even with extensive IP reuse, many of the ASICs design problems
remain
► Productivity increase far from closing design gap
 Architecture Design

► The major challenges to design a digital system are that it must

execute the desired function and meet the area,performance and
timing constraints.
► During the design process, modeling is an important aspects to
meet the required specifications.
► The HDLs allow designing any digital system using RTL at
various levels of abstraction.
► The two major approaches followed in the process of design flow
are top-down approach and bottom-up approach.
TOP-DOWN DESIGN

► This is one of the approaches to design any digital system from

simple to complex design.
► The design starts at the highest at the highest level of a design
concept as specifications ,algorithm,and implementation using
HDL and proceeds towards the lowest level,that is gate level
netlist.
► The top-down design methodology takes the HDL model of
hardware as an abstract level input.
► The design steps down until gate or transistor level of the circuit.
 System
specification

Algorithm

HDL Design
Entry

Simulation of
circuit

Back-end
process
► The first level is the system specifications followed by algorithm and
architecture specifications.
► The step followed by the architecture is HDL model,which is hardware
model of the design represented in RTL(register-transfer level).
► The RTL model is synthesized to gate-level netlist and then to
transistor level netlist.
► This approach is best suitable to design complex designs,such as very
large integrated circuits.
Advantages of top down design

► Ease of design modifications

► Verification can be done at every stage.
► Validation of the design takes place at every stage of design,such
as RTL level,gate-level,layout level, and placement and route,to
meet the design requirements.
Bottom-Up Design

► This approach is a traditional method of electronic design.

► Each design is performed at gate level using standard gates.
► The basic logic units, such as primitive gates, adders, and
registers, are designed as a first step in the design process.
► These are combined to create designs that are more complex.
► This approach is best suitable for small projects, such as
arithmetic logic unit,parallel adder,and Wallace tree multiplier.
► As the complexity of circuit increases , this approach is not
suitable.
► For example , 64-bit microprocessor is difficult to design using
bottom-up design approach, as there are large numbers of
complex designs tobe designed using existing logical
components.
Advantages and disadvantages of
bottom-up approach
1. Easy to design small circuits
2. Easy to understand the flow of logic components.
3. Difficult to implement for large designs,such as microprocessors.

• Nowadays , a combination of both top-down and bottom –up

design approaches is followed to design complex circuits.
Logic design
► Logic design for an ASIC begins with the design team
analyzing the functional specification
► Second step is creation of a logic design architecture,
which includes a block diagram that provides details about
functional relationships between digital logic such as, finite
state machines, combinational logic, sequential logic,
processors, memories, data path design, communication
buses, and the connections between them.
► The next step is to describe detailed functionality of the
blocks and the connection between the respective functional
blocks using HDL codes or schematics
Logic design
► Next, Register Transfer Level(RTL) code is developed by the
EDA tool.
► Verification: The logical design is verified for matching of
original design intent and implementation at several stages
throughout the design process to ensure an accurate
successful ASIC outcome.
► Design synthesis is the process of translating the logical
design into a gate- level netlist that can then be
implemented as a physical silicon structure.
Physical Design

Physical design (also known as back-end design) is the process of

converting the gate-level netlist produced at synthesis into
functional ASIC hardware.
Physical Design

Physical design steps include:

► floor planning
► power planning
► partitioning
► placement
► routing
► clock tree synthesis
► final verification
► and export as a GDSII (Geometrical database standard for
Information Interchange) file to the fabrication facility for
construction.
Physical Design - Floor-planning

Floorplanning is the process of placing functional blocks in

the chip area so as to allocate routing areas between them,
plan for critical power and ground connections, and
determine Input / Output (IO) pad locations.
Physical Design - Logical partitioning

Partitioning (logical partitioning) is the process of dividing the

chip into small blocks.
The objective of partitioning is to make the functional block
easier for placement and routing.
This step can be done in the logical design phase when the design
team divides the entire design into sub-blocks for development, or
at the physical design (back-end) phase to aid in place and route
activities
Physical Design - Power planning

Power planning takes into account the energy usage

of each block, individual voltage supplies, ground
paths, and interaction between them.
Physical Design - Placement

Placement is the process of dividing the chip into smaller blocks

by placing the correct position to standard cells with none
overlapping on the chip
Physical Design - Clock Tree Synthesis

Clock tree synthesis is the process of ensuring that clock signals are
distributed evenly to all sequential elements in a design with the primary
objective of preventing clock timing-related errors.
This timing error is called clock skew
Clock tree synthesis performed during the physical design process
considers the effects of place and route, channel impedance, parasitic
loads, etc.
Then through the insertion of buffers or inverters along the clock paths to
minimize or balance skew of important clock signal chains, build a clock
tree that achieves proper timing across the entire design.
Physical Design - Routing

Routing is the process of connecting macros, standard cells, I/O ports,

power, and the clock physically with metal traces.
Physical Design - Design for Manufacture
(DFM)
DFM is the step that take into account process and use constraints of the
manufacturer
This step is intended to increase yield, decrease test time, and other
processing concerns.
DFM can often be the difference between a successful ASIC project that
meets cost, reliability, and production goals versus one that falls short.